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qeth: Fix IP version detection for VLAN traffic
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
74cfb2e1 4 Copyright(c) 2007-2014 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
74cfb2e1 16 this program; if not, see <http://www.gnu.org/licenses/>.
9d5c8243
AK		 17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
876d2d6f
JK		 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28
9d5c8243
AK		 29#include <linux/module.h>
30#include <linux/types.h>
31#include <linux/init.h>
b2cb09b1 32#include <linux/bitops.h>
9d5c8243
AK		 33#include <linux/vmalloc.h>
34#include <linux/pagemap.h>
35#include <linux/netdevice.h>
9d5c8243 36#include <linux/ipv6.h>
5a0e3ad6 37#include <linux/slab.h>
9d5c8243
AK		 38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
c6cb090b 40#include <linux/net_tstamp.h>
9d5c8243
AK		 41#include <linux/mii.h>
42#include <linux/ethtool.h>
01789349 43#include <linux/if.h>
9d5c8243
AK		 44#include <linux/if_vlan.h>
45#include <linux/pci.h>
c54106bb 46#include <linux/pci-aspm.h>
9d5c8243
AK		 47#include <linux/delay.h>
48#include <linux/interrupt.h>
7d13a7d0
AD		 49#include <linux/ip.h>
50#include <linux/tcp.h>
51#include <linux/sctp.h>
9d5c8243 52#include <linux/if_ether.h>
40a914fa 53#include <linux/aer.h>
70c71606 54#include <linux/prefetch.h>
749ab2cd 55#include <linux/pm_runtime.h>
421e02f0 56#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 57#include <linux/dca.h>
58#endif
441fc6fd 59#include <linux/i2c.h>
9d5c8243
AK		 60#include "igb.h"
61
67b1b903
CW		 62#define MAJ 5
63#define MIN 0
66f40b8a 64#define BUILD 5
0d1fe82d 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 66__stringify(BUILD) "-k"
9d5c8243
AK		 67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 71static const char igb_copyright[] =
74cfb2e1 72 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 73
9d5c8243
AK		 74static const struct e1000_info *igb_info_tbl[] = {
75 [board_82575] = &e1000_82575_info,
76};
77
a3aa1884 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
114 /* required last entry */
115 {0, }
116};
117
118MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
119
120void igb_reset(struct igb_adapter *);
121static int igb_setup_all_tx_resources(struct igb_adapter *);
122static int igb_setup_all_rx_resources(struct igb_adapter *);
123static void igb_free_all_tx_resources(struct igb_adapter *);
124static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 125static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 126static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 127static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 128static int igb_sw_init(struct igb_adapter *);
129static int igb_open(struct net_device *);
130static int igb_close(struct net_device *);
53c7d064 131static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 132static void igb_configure_tx(struct igb_adapter *);
133static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 134static void igb_clean_all_tx_rings(struct igb_adapter *);
135static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 136static void igb_clean_tx_ring(struct igb_ring *);
137static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 138static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 139static void igb_update_phy_info(unsigned long);
140static void igb_watchdog(unsigned long);
141static void igb_watchdog_task(struct work_struct *);
cd392f5c 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
144 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 145static int igb_change_mtu(struct net_device *, int);
146static int igb_set_mac(struct net_device *, void *);
68d480c4 147static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 148static irqreturn_t igb_intr(int irq, void *);
149static irqreturn_t igb_intr_msi(int irq, void *);
150static irqreturn_t igb_msix_other(int irq, void *);
047e0030 151static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 152#ifdef CONFIG_IGB_DCA
047e0030 153static void igb_update_dca(struct igb_q_vector *);
fe4506b6 154static void igb_setup_dca(struct igb_adapter *);
421e02f0 155#endif /* CONFIG_IGB_DCA */
661086df 156static int igb_poll(struct napi_struct *, int);
13fde97a 157static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 158static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
160static void igb_tx_timeout(struct net_device *);
161static void igb_reset_task(struct work_struct *);
c8f44aff 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 165static void igb_restore_vlan(struct igb_adapter *);
26ad9178 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 167static void igb_ping_all_vfs(struct igb_adapter *);
168static void igb_msg_task(struct igb_adapter *);
4ae196df 169static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
173static int igb_ndo_set_vf_vlan(struct net_device *netdev,
174 int vf, u16 vlan, u8 qos);
175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
177 bool setting);
8151d294
WM		 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
179 struct ifla_vf_info *ivi);
17dc566c 180static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 181
182#ifdef CONFIG_PCI_IOV
0224d663 183static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 185#endif
9d5c8243 186
9d5c8243 187#ifdef CONFIG_PM
d9dd966d 188#ifdef CONFIG_PM_SLEEP
749ab2cd 189static int igb_suspend(struct device *);
d9dd966d 190#endif
749ab2cd
YZ		 191static int igb_resume(struct device *);
192#ifdef CONFIG_PM_RUNTIME
193static int igb_runtime_suspend(struct device *dev);
194static int igb_runtime_resume(struct device *dev);
195static int igb_runtime_idle(struct device *dev);
196#endif
197static const struct dev_pm_ops igb_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 igb_runtime_idle)
201};
9d5c8243
AK		 202#endif
203static void igb_shutdown(struct pci_dev *);
fa44f2f1 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 205#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
207static struct notifier_block dca_notifier = {
208 .notifier_call = igb_notify_dca,
209 .next = NULL,
210 .priority = 0
211};
212#endif
9d5c8243
AK		 213#ifdef CONFIG_NET_POLL_CONTROLLER
214/* for netdump / net console */
215static void igb_netpoll(struct net_device *);
216#endif
37680117 217#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 218static unsigned int max_vfs = 0;
219module_param(max_vfs, uint, 0);
220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
221 "per physical function");
222#endif /* CONFIG_PCI_IOV */
223
9d5c8243
AK		 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
225 pci_channel_state_t);
226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
227static void igb_io_resume(struct pci_dev *);
228
3646f0e5 229static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 230 .error_detected = igb_io_error_detected,
231 .slot_reset = igb_io_slot_reset,
232 .resume = igb_io_resume,
233};
234
b6e0c419 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 236
237static struct pci_driver igb_driver = {
238 .name = igb_driver_name,
239 .id_table = igb_pci_tbl,
240 .probe = igb_probe,
9f9a12f8 241 .remove = igb_remove,
9d5c8243 242#ifdef CONFIG_PM
749ab2cd 243 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 244#endif
245 .shutdown = igb_shutdown,
fa44f2f1 246 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 247 .err_handler = &igb_err_handler
248};
249
250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
252MODULE_LICENSE("GPL");
253MODULE_VERSION(DRV_VERSION);
254
b3f4d599 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
256static int debug = -1;
257module_param(debug, int, 0);
258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
259
c97ec42a
TI		 260struct igb_reg_info {
261 u32 ofs;
262 char *name;
263};
264
265static const struct igb_reg_info igb_reg_info_tbl[] = {
266
267 /* General Registers */
268 {E1000_CTRL, "CTRL"},
269 {E1000_STATUS, "STATUS"},
270 {E1000_CTRL_EXT, "CTRL_EXT"},
271
272 /* Interrupt Registers */
273 {E1000_ICR, "ICR"},
274
275 /* RX Registers */
276 {E1000_RCTL, "RCTL"},
277 {E1000_RDLEN(0), "RDLEN"},
278 {E1000_RDH(0), "RDH"},
279 {E1000_RDT(0), "RDT"},
280 {E1000_RXDCTL(0), "RXDCTL"},
281 {E1000_RDBAL(0), "RDBAL"},
282 {E1000_RDBAH(0), "RDBAH"},
283
284 /* TX Registers */
285 {E1000_TCTL, "TCTL"},
286 {E1000_TDBAL(0), "TDBAL"},
287 {E1000_TDBAH(0), "TDBAH"},
288 {E1000_TDLEN(0), "TDLEN"},
289 {E1000_TDH(0), "TDH"},
290 {E1000_TDT(0), "TDT"},
291 {E1000_TXDCTL(0), "TXDCTL"},
292 {E1000_TDFH, "TDFH"},
293 {E1000_TDFT, "TDFT"},
294 {E1000_TDFHS, "TDFHS"},
295 {E1000_TDFPC, "TDFPC"},
296
297 /* List Terminator */
298 {}
299};
300
b980ac18 301/* igb_regdump - register printout routine */
c97ec42a
TI		 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
303{
304 int n = 0;
305 char rname[16];
306 u32 regs[8];
307
308 switch (reginfo->ofs) {
309 case E1000_RDLEN(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDLEN(n));
312 break;
313 case E1000_RDH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDH(n));
316 break;
317 case E1000_RDT(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDT(n));
320 break;
321 case E1000_RXDCTL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RXDCTL(n));
324 break;
325 case E1000_RDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_RDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAH(n));
332 break;
333 case E1000_TDBAL(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_RDBAL(n));
336 break;
337 case E1000_TDBAH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDBAH(n));
340 break;
341 case E1000_TDLEN(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDLEN(n));
344 break;
345 case E1000_TDH(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDH(n));
348 break;
349 case E1000_TDT(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TDT(n));
352 break;
353 case E1000_TXDCTL(0):
354 for (n = 0; n < 4; n++)
355 regs[n] = rd32(E1000_TXDCTL(n));
356 break;
357 default:
876d2d6f 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 359 return;
360 }
361
362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 regs[2], regs[3]);
c97ec42a
TI		 365}
366
b980ac18 367/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 368static void igb_dump(struct igb_adapter *adapter)
369{
370 struct net_device *netdev = adapter->netdev;
371 struct e1000_hw *hw = &adapter->hw;
372 struct igb_reg_info *reginfo;
c97ec42a
TI		 373 struct igb_ring *tx_ring;
374 union e1000_adv_tx_desc *tx_desc;
375 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 376 struct igb_ring *rx_ring;
377 union e1000_adv_rx_desc *rx_desc;
378 u32 staterr;
6ad4edfc 379 u16 i, n;
c97ec42a
TI		 380
381 if (!netif_msg_hw(adapter))
382 return;
383
384 /* Print netdevice Info */
385 if (netdev) {
386 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 387 pr_info("Device Name state trans_start "
388 "last_rx\n");
389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
390 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 391 }
392
393 /* Print Registers */
394 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 395 pr_info(" Register Name Value\n");
c97ec42a
TI		 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
397 reginfo->name; reginfo++) {
398 igb_regdump(hw, reginfo);
399 }
400
401 /* Print TX Ring Summary */
402 if (!netdev || !netif_running(netdev))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 407 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 408 struct igb_tx_buffer *buffer_info;
c97ec42a 409 tx_ring = adapter->tx_ring[n];
06034649 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
412 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 413 (u64)dma_unmap_addr(buffer_info, dma),
414 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 415 buffer_info->next_to_watch,
416 (u64)buffer_info->time_stamp);
c97ec42a
TI		 417 }
418
419 /* Print TX Rings */
420 if (!netif_msg_tx_done(adapter))
421 goto rx_ring_summary;
422
423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
424
425 /* Transmit Descriptor Formats
426 *
427 * Advanced Transmit Descriptor
428 * +--------------------------------------------------------------+
429 * 0 | Buffer Address [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
432 * +--------------------------------------------------------------+
433 * 63 46 45 40 39 38 36 35 32 31 24 15 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
442 "[bi->dma ] leng ntw timestamp "
443 "bi->skb\n");
c97ec42a
TI		 444
445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 446 const char *next_desc;
06034649 447 struct igb_tx_buffer *buffer_info;
60136906 448 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 449 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 450 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 451 if (i == tx_ring->next_to_use &&
452 i == tx_ring->next_to_clean)
453 next_desc = " NTC/U";
454 else if (i == tx_ring->next_to_use)
455 next_desc = " NTU";
456 else if (i == tx_ring->next_to_clean)
457 next_desc = " NTC";
458 else
459 next_desc = "";
460
461 pr_info("T [0x%03X] %016llX %016llX %016llX"
462 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
c9f14bf3
AD		 465 (u64)dma_unmap_addr(buffer_info, dma),
466 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 467 buffer_info->next_to_watch,
468 (u64)buffer_info->time_stamp,
876d2d6f 469 buffer_info->skb, next_desc);
c97ec42a 470
b669588a 471 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS,
b669588a 474 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 475 dma_unmap_len(buffer_info, len),
476 true);
c97ec42a
TI		 477 }
478 }
479
480 /* Print RX Rings Summary */
481rx_ring_summary:
482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 483 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 486 pr_info(" %5d %5X %5X\n",
487 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 488 }
489
490 /* Print RX Rings */
491 if (!netif_msg_rx_status(adapter))
492 goto exit;
493
494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
495
496 /* Advanced Receive Descriptor (Read) Format
497 * 63 1 0
498 * +-----------------------------------------------------+
499 * 0 | Packet Buffer Address [63:1] |A0/NSE|
500 * +----------------------------------------------+------+
501 * 8 | Header Buffer Address [63:1] | DD |
502 * +-----------------------------------------------------+
503 *
504 *
505 * Advanced Receive Descriptor (Write-Back) Format
506 *
507 * 63 48 47 32 31 30 21 20 17 16 4 3 0
508 * +------------------------------------------------------+
509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
510 * | Checksum Ident | | | | Type | Type |
511 * +------------------------------------------------------+
512 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
513 * +------------------------------------------------------+
514 * 63 48 47 32 31 20 19 0
515 */
516
517 for (n = 0; n < adapter->num_rx_queues; n++) {
518 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 519 pr_info("------------------------------------\n");
520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 526
527 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 528 const char *next_desc;
06034649
AD		 529 struct igb_rx_buffer *buffer_info;
530 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 531 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 532 u0 = (struct my_u0 *)rx_desc;
533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 534
535 if (i == rx_ring->next_to_use)
536 next_desc = " NTU";
537 else if (i == rx_ring->next_to_clean)
538 next_desc = " NTC";
539 else
540 next_desc = "";
541
c97ec42a
TI		 542 if (staterr & E1000_RXD_STAT_DD) {
543 /* Descriptor Done */
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
545 "RWB", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
1a1c225b 548 next_desc);
c97ec42a 549 } else {
1a1c225b
AD		 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
551 "R ", i,
c97ec42a
TI		 552 le64_to_cpu(u0->a),
553 le64_to_cpu(u0->b),
554 (u64)buffer_info->dma,
1a1c225b 555 next_desc);
c97ec42a 556
b669588a 557 if (netif_msg_pktdata(adapter) &&
1a1c225b 558 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 559 print_hex_dump(KERN_INFO, "",
560 DUMP_PREFIX_ADDRESS,
561 16, 1,
b669588a
ET		 562 page_address(buffer_info->page) +
563 buffer_info->page_offset,
de78d1f9 564 IGB_RX_BUFSZ, true);
c97ec42a
TI		 565 }
566 }
c97ec42a
TI		 567 }
568 }
569
570exit:
571 return;
572}
573
b980ac18
JK		 574/**
575 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 576 * @hw: pointer to hardware structure
577 * @i2cctl: Current value of I2CCTL register
578 *
579 * Returns the I2C data bit value
b980ac18 580 **/
441fc6fd
CW		 581static int igb_get_i2c_data(void *data)
582{
583 struct igb_adapter *adapter = (struct igb_adapter *)data;
584 struct e1000_hw *hw = &adapter->hw;
585 s32 i2cctl = rd32(E1000_I2CPARAMS);
586
587 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
588}
589
b980ac18
JK		 590/**
591 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 592 * @data: pointer to hardware structure
593 * @state: I2C data value (0 or 1) to set
594 *
595 * Sets the I2C data bit
b980ac18 596 **/
441fc6fd
CW		 597static void igb_set_i2c_data(void *data, int state)
598{
599 struct igb_adapter *adapter = (struct igb_adapter *)data;
600 struct e1000_hw *hw = &adapter->hw;
601 s32 i2cctl = rd32(E1000_I2CPARAMS);
602
603 if (state)
604 i2cctl |= E1000_I2C_DATA_OUT;
605 else
606 i2cctl &= ~E1000_I2C_DATA_OUT;
607
608 i2cctl &= ~E1000_I2C_DATA_OE_N;
609 i2cctl |= E1000_I2C_CLK_OE_N;
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612
613}
614
b980ac18
JK		 615/**
616 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 617 * @data: pointer to hardware structure
618 * @state: state to set clock
619 *
620 * Sets the I2C clock line to state
b980ac18 621 **/
441fc6fd
CW		 622static void igb_set_i2c_clk(void *data, int state)
623{
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 if (state) {
629 i2cctl |= E1000_I2C_CLK_OUT;
630 i2cctl &= ~E1000_I2C_CLK_OE_N;
631 } else {
632 i2cctl &= ~E1000_I2C_CLK_OUT;
633 i2cctl &= ~E1000_I2C_CLK_OE_N;
634 }
635 wr32(E1000_I2CPARAMS, i2cctl);
636 wrfl();
637}
638
b980ac18
JK		 639/**
640 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 641 * @data: pointer to hardware structure
642 *
643 * Gets the I2C clock state
b980ac18 644 **/
441fc6fd
CW		 645static int igb_get_i2c_clk(void *data)
646{
647 struct igb_adapter *adapter = (struct igb_adapter *)data;
648 struct e1000_hw *hw = &adapter->hw;
649 s32 i2cctl = rd32(E1000_I2CPARAMS);
650
651 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
652}
653
654static const struct i2c_algo_bit_data igb_i2c_algo = {
655 .setsda = igb_set_i2c_data,
656 .setscl = igb_set_i2c_clk,
657 .getsda = igb_get_i2c_data,
658 .getscl = igb_get_i2c_clk,
659 .udelay = 5,
660 .timeout = 20,
661};
662
9d5c8243 663/**
b980ac18
JK		 664 * igb_get_hw_dev - return device
665 * @hw: pointer to hardware structure
666 *
667 * used by hardware layer to print debugging information
9d5c8243 668 **/
c041076a 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 670{
671 struct igb_adapter *adapter = hw->back;
c041076a 672 return adapter->netdev;
9d5c8243 673}
38c845c7 674
9d5c8243 675/**
b980ac18 676 * igb_init_module - Driver Registration Routine
9d5c8243 677 *
b980ac18
JK		 678 * igb_init_module is the first routine called when the driver is
679 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 680 **/
681static int __init igb_init_module(void)
682{
683 int ret;
876d2d6f 684 pr_info("%s - version %s\n",
9d5c8243
AK		 685 igb_driver_string, igb_driver_version);
686
876d2d6f 687 pr_info("%s\n", igb_copyright);
9d5c8243 688
421e02f0 689#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 690 dca_register_notify(&dca_notifier);
691#endif
bbd98fe4 692 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 693 return ret;
694}
695
696module_init(igb_init_module);
697
698/**
b980ac18 699 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 700 *
b980ac18
JK		 701 * igb_exit_module is called just before the driver is removed
702 * from memory.
9d5c8243
AK		 703 **/
704static void __exit igb_exit_module(void)
705{
421e02f0 706#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 707 dca_unregister_notify(&dca_notifier);
708#endif
9d5c8243
AK		 709 pci_unregister_driver(&igb_driver);
710}
711
712module_exit(igb_exit_module);
713
26bc19ec
AD		 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
715/**
b980ac18
JK		 716 * igb_cache_ring_register - Descriptor ring to register mapping
717 * @adapter: board private structure to initialize
26bc19ec 718 *
b980ac18
JK		 719 * Once we know the feature-set enabled for the device, we'll cache
720 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 721 **/
722static void igb_cache_ring_register(struct igb_adapter *adapter)
723{
ee1b9f06 724 int i = 0, j = 0;
047e0030 725 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 726
727 switch (adapter->hw.mac.type) {
728 case e1000_82576:
729 /* The queues are allocated for virtualization such that VF 0
730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
731 * In order to avoid collision we start at the first free queue
732 * and continue consuming queues in the same sequence
733 */
ee1b9f06 734 if (adapter->vfs_allocated_count) {
a99955fc 735 for (; i < adapter->rss_queues; i++)
3025a446 736 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 737 Q_IDX_82576(i);
ee1b9f06 738 }
26bc19ec 739 case e1000_82575:
55cac248 740 case e1000_82580:
d2ba2ed8 741 case e1000_i350:
ceb5f13b 742 case e1000_i354:
f96a8a0b
CW		 743 case e1000_i210:
744 case e1000_i211:
26bc19ec 745 default:
ee1b9f06 746 for (; i < adapter->num_rx_queues; i++)
3025a446 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 748 for (; j < adapter->num_tx_queues; j++)
3025a446 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 750 break;
751 }
752}
753
4be000c8
AD		 754/**
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
760 *
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
765 **/
766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
768{
769 u32 ivar = array_rd32(E1000_IVAR0, index);
770
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
773
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
776
777 array_wr32(E1000_IVAR0, index, ivar);
778}
779
9d5c8243 780#define IGB_N0_QUEUE -1
047e0030 781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 782{
047e0030 783 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 784 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
4be000c8 787 u32 msixbm = 0;
047e0030 788
0ba82994
AD		 789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 793
794 switch (hw->mac.type) {
795 case e1000_82575:
9d5c8243 796 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
800 */
047e0030 801 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 803 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 806 msixbm |= E1000_EIMS_OTHER;
9d5c8243 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 808 q_vector->eims_value = msixbm;
2d064c06
AD		 809 break;
810 case e1000_82576:
b980ac18 811 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
814 * column offset.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 rx_queue & 0x7,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
822 tx_queue & 0x7,
823 ((tx_queue & 0x8) << 1) + 8);
047e0030 824 q_vector->eims_value = 1 << msix_vector;
2d064c06 825 break;
55cac248 826 case e1000_82580:
d2ba2ed8 827 case e1000_i350:
ceb5f13b 828 case e1000_i354:
f96a8a0b
CW		 829 case e1000_i210:
830 case e1000_i211:
b980ac18 831 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
835 * row index.
836 */
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
839 rx_queue >> 1,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
843 tx_queue >> 1,
844 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 845 q_vector->eims_value = 1 << msix_vector;
846 break;
2d064c06
AD		 847 default:
848 BUG();
849 break;
850 }
26b39276
AD		 851
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
854
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
9d5c8243
AK		 857}
858
859/**
b980ac18
JK		 860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
9d5c8243 862 *
b980ac18
JK		 863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
9d5c8243
AK		 865 **/
866static void igb_configure_msix(struct igb_adapter *adapter)
867{
868 u32 tmp;
869 int i, vector = 0;
870 struct e1000_hw *hw = &adapter->hw;
871
872 adapter->eims_enable_mask = 0;
9d5c8243
AK		 873
874 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 875 switch (hw->mac.type) {
876 case e1000_82575:
9d5c8243
AK		 877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
880
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
884
885 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 886
887 /* enable msix_other interrupt */
b980ac18 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 889 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 890
2d064c06
AD		 891 break;
892
893 case e1000_82576:
55cac248 894 case e1000_82580:
d2ba2ed8 895 case e1000_i350:
ceb5f13b 896 case e1000_i354:
f96a8a0b
CW		 897 case e1000_i210:
898 case e1000_i211:
047e0030 899 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 900 * won't stick. And it will take days to debug.
901 */
047e0030 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
904 E1000_GPIE_NSICR);
047e0030
AD		 905
906 /* enable msix_other interrupt */
907 adapter->eims_other = 1 << vector;
2d064c06 908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 909
047e0030 910 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 911 break;
912 default:
913 /* do nothing, since nothing else supports MSI-X */
914 break;
915 } /* switch (hw->mac.type) */
047e0030
AD		 916
917 adapter->eims_enable_mask |= adapter->eims_other;
918
26b39276
AD		 919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 921
9d5c8243
AK		 922 wrfl();
923}
924
925/**
b980ac18
JK		 926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
9d5c8243 928 *
b980ac18
JK		 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
930 * kernel.
9d5c8243
AK		 931 **/
932static int igb_request_msix(struct igb_adapter *adapter)
933{
934 struct net_device *netdev = adapter->netdev;
047e0030 935 struct e1000_hw *hw = &adapter->hw;
52285b76 936 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 937
047e0030 938 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 939 igb_msix_other, 0, netdev->name, adapter);
047e0030 940 if (err)
52285b76 941 goto err_out;
047e0030
AD		 942
943 for (i = 0; i < adapter->num_q_vectors; i++) {
944 struct igb_q_vector *q_vector = adapter->q_vector[i];
945
52285b76
SA		 946 vector++;
947
047e0030
AD		 948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
949
0ba82994 950 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 952 q_vector->rx.ring->queue_index);
953 else if (q_vector->tx.ring)
047e0030 954 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 955 q_vector->tx.ring->queue_index);
956 else if (q_vector->rx.ring)
047e0030 957 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 958 q_vector->rx.ring->queue_index);
9d5c8243 959 else
047e0030
AD		 960 sprintf(q_vector->name, "%s-unused", netdev->name);
961
9d5c8243 962 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 963 igb_msix_ring, 0, q_vector->name,
964 q_vector);
9d5c8243 965 if (err)
52285b76 966 goto err_free;
9d5c8243
AK		 967 }
968
9d5c8243
AK		 969 igb_configure_msix(adapter);
970 return 0;
52285b76
SA		 971
972err_free:
973 /* free already assigned IRQs */
974 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
975
976 vector--;
977 for (i = 0; i < vector; i++) {
978 free_irq(adapter->msix_entries[free_vector++].vector,
979 adapter->q_vector[i]);
980 }
981err_out:
9d5c8243
AK		 982 return err;
983}
984
5536d210 985/**
b980ac18
JK		 986 * igb_free_q_vector - Free memory allocated for specific interrupt vector
987 * @adapter: board private structure to initialize
988 * @v_idx: Index of vector to be freed
5536d210 989 *
02ef6e1d 990 * This function frees the memory allocated to the q_vector.
5536d210
AD		 991 **/
992static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
993{
994 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
995
02ef6e1d
CW		 996 adapter->q_vector[v_idx] = NULL;
997
998 /* igb_get_stats64() might access the rings on this vector,
999 * we must wait a grace period before freeing it.
1000 */
1001 kfree_rcu(q_vector, rcu);
1002}
1003
1004/**
1005 * igb_reset_q_vector - Reset config for interrupt vector
1006 * @adapter: board private structure to initialize
1007 * @v_idx: Index of vector to be reset
1008 *
1009 * If NAPI is enabled it will delete any references to the
1010 * NAPI struct. This is preparation for igb_free_q_vector.
1011 **/
1012static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1013{
1014 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1015
5536d210
AD		 1016 if (q_vector->tx.ring)
1017 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1018
1019 if (q_vector->rx.ring)
1020 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1021
5536d210
AD		 1022 netif_napi_del(&q_vector->napi);
1023
02ef6e1d
CW		 1024}
1025
1026static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1027{
1028 int v_idx = adapter->num_q_vectors;
1029
cd14ef54 1030 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1031 pci_disable_msix(adapter->pdev);
cd14ef54 1032 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1033 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1034
1035 while (v_idx--)
1036 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1037}
1038
047e0030 1039/**
b980ac18
JK		 1040 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1041 * @adapter: board private structure to initialize
047e0030 1042 *
b980ac18
JK		 1043 * This function frees the memory allocated to the q_vectors. In addition if
1044 * NAPI is enabled it will delete any references to the NAPI struct prior
1045 * to freeing the q_vector.
047e0030
AD		 1046 **/
1047static void igb_free_q_vectors(struct igb_adapter *adapter)
1048{
5536d210
AD		 1049 int v_idx = adapter->num_q_vectors;
1050
1051 adapter->num_tx_queues = 0;
1052 adapter->num_rx_queues = 0;
047e0030 1053 adapter->num_q_vectors = 0;
5536d210 1054
02ef6e1d
CW		 1055 while (v_idx--) {
1056 igb_reset_q_vector(adapter, v_idx);
5536d210 1057 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1058 }
047e0030
AD		 1059}
1060
1061/**
b980ac18
JK		 1062 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1063 * @adapter: board private structure to initialize
047e0030 1064 *
b980ac18
JK		 1065 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1066 * MSI-X interrupts allocated.
047e0030
AD		 1067 */
1068static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1069{
047e0030
AD		 1070 igb_free_q_vectors(adapter);
1071 igb_reset_interrupt_capability(adapter);
1072}
9d5c8243
AK		 1073
1074/**
b980ac18
JK		 1075 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1076 * @adapter: board private structure to initialize
1077 * @msix: boolean value of MSIX capability
9d5c8243 1078 *
b980ac18
JK		 1079 * Attempt to configure interrupts using the best available
1080 * capabilities of the hardware and kernel.
9d5c8243 1081 **/
53c7d064 1082static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1083{
1084 int err;
1085 int numvecs, i;
1086
53c7d064
SA		 1087 if (!msix)
1088 goto msi_only;
cd14ef54 1089 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1090
83b7180d 1091 /* Number of supported queues. */
a99955fc 1092 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1093 if (adapter->vfs_allocated_count)
1094 adapter->num_tx_queues = 1;
1095 else
1096 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1097
b980ac18 1098 /* start with one vector for every Rx queue */
047e0030
AD		 1099 numvecs = adapter->num_rx_queues;
1100
b980ac18 1101 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1102 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1103 numvecs += adapter->num_tx_queues;
047e0030
AD		 1104
1105 /* store the number of vectors reserved for queues */
1106 adapter->num_q_vectors = numvecs;
1107
1108 /* add 1 vector for link status interrupts */
1109 numvecs++;
9d5c8243
AK		 1110 for (i = 0; i < numvecs; i++)
1111 adapter->msix_entries[i].entry = i;
1112
479d02df
AG		 1113 err = pci_enable_msix_range(adapter->pdev,
1114 adapter->msix_entries,
1115 numvecs,
1116 numvecs);
1117 if (err > 0)
0c2cc02e 1118 return;
9d5c8243
AK		 1119
1120 igb_reset_interrupt_capability(adapter);
1121
1122 /* If we can't do MSI-X, try MSI */
1123msi_only:
2a3abf6d
AD		 1124#ifdef CONFIG_PCI_IOV
1125 /* disable SR-IOV for non MSI-X configurations */
1126 if (adapter->vf_data) {
1127 struct e1000_hw *hw = &adapter->hw;
1128 /* disable iov and allow time for transactions to clear */
1129 pci_disable_sriov(adapter->pdev);
1130 msleep(500);
1131
1132 kfree(adapter->vf_data);
1133 adapter->vf_data = NULL;
1134 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1135 wrfl();
2a3abf6d
AD		 1136 msleep(100);
1137 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1138 }
1139#endif
4fc82adf 1140 adapter->vfs_allocated_count = 0;
a99955fc 1141 adapter->rss_queues = 1;
4fc82adf 1142 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1143 adapter->num_rx_queues = 1;
661086df 1144 adapter->num_tx_queues = 1;
047e0030 1145 adapter->num_q_vectors = 1;
9d5c8243 1146 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1147 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1148}
1149
5536d210
AD		 1150static void igb_add_ring(struct igb_ring *ring,
1151 struct igb_ring_container *head)
1152{
1153 head->ring = ring;
1154 head->count++;
1155}
1156
047e0030 1157/**
b980ac18
JK		 1158 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1159 * @adapter: board private structure to initialize
1160 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1161 * @v_idx: index of vector in adapter struct
1162 * @txr_count: total number of Tx rings to allocate
1163 * @txr_idx: index of first Tx ring to allocate
1164 * @rxr_count: total number of Rx rings to allocate
1165 * @rxr_idx: index of first Rx ring to allocate
047e0030 1166 *
b980ac18 1167 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1168 **/
5536d210
AD		 1169static int igb_alloc_q_vector(struct igb_adapter *adapter,
1170 int v_count, int v_idx,
1171 int txr_count, int txr_idx,
1172 int rxr_count, int rxr_idx)
047e0030
AD		 1173{
1174 struct igb_q_vector *q_vector;
5536d210
AD		 1175 struct igb_ring *ring;
1176 int ring_count, size;
047e0030 1177
5536d210
AD		 1178 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1179 if (txr_count > 1 || rxr_count > 1)
1180 return -ENOMEM;
1181
1182 ring_count = txr_count + rxr_count;
1183 size = sizeof(struct igb_q_vector) +
1184 (sizeof(struct igb_ring) * ring_count);
1185
1186 /* allocate q_vector and rings */
02ef6e1d
CW		 1187 q_vector = adapter->q_vector[v_idx];
1188 if (!q_vector)
1189 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1190 if (!q_vector)
1191 return -ENOMEM;
1192
1193 /* initialize NAPI */
1194 netif_napi_add(adapter->netdev, &q_vector->napi,
1195 igb_poll, 64);
1196
1197 /* tie q_vector and adapter together */
1198 adapter->q_vector[v_idx] = q_vector;
1199 q_vector->adapter = adapter;
1200
1201 /* initialize work limits */
1202 q_vector->tx.work_limit = adapter->tx_work_limit;
1203
1204 /* initialize ITR configuration */
1205 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1206 q_vector->itr_val = IGB_START_ITR;
1207
1208 /* initialize pointer to rings */
1209 ring = q_vector->ring;
1210
4e227667
AD		 1211 /* intialize ITR */
1212 if (rxr_count) {
1213 /* rx or rx/tx vector */
1214 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1215 q_vector->itr_val = adapter->rx_itr_setting;
1216 } else {
1217 /* tx only vector */
1218 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1219 q_vector->itr_val = adapter->tx_itr_setting;
1220 }
1221
5536d210
AD		 1222 if (txr_count) {
1223 /* assign generic ring traits */
1224 ring->dev = &adapter->pdev->dev;
1225 ring->netdev = adapter->netdev;
1226
1227 /* configure backlink on ring */
1228 ring->q_vector = q_vector;
1229
1230 /* update q_vector Tx values */
1231 igb_add_ring(ring, &q_vector->tx);
1232
1233 /* For 82575, context index must be unique per ring. */
1234 if (adapter->hw.mac.type == e1000_82575)
1235 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1236
1237 /* apply Tx specific ring traits */
1238 ring->count = adapter->tx_ring_count;
1239 ring->queue_index = txr_idx;
1240
827da44c
JS		 1241 u64_stats_init(&ring->tx_syncp);
1242 u64_stats_init(&ring->tx_syncp2);
1243
5536d210
AD		 1244 /* assign ring to adapter */
1245 adapter->tx_ring[txr_idx] = ring;
1246
1247 /* push pointer to next ring */
1248 ring++;
047e0030 1249 }
81c2fc22 1250
5536d210
AD		 1251 if (rxr_count) {
1252 /* assign generic ring traits */
1253 ring->dev = &adapter->pdev->dev;
1254 ring->netdev = adapter->netdev;
047e0030 1255
5536d210
AD		 1256 /* configure backlink on ring */
1257 ring->q_vector = q_vector;
047e0030 1258
5536d210
AD		 1259 /* update q_vector Rx values */
1260 igb_add_ring(ring, &q_vector->rx);
047e0030 1261
5536d210
AD		 1262 /* set flag indicating ring supports SCTP checksum offload */
1263 if (adapter->hw.mac.type >= e1000_82576)
1264 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1265
ceb5f13b
CW		 1266 /*
1267 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1268 * have the tag byte-swapped.
b980ac18 1269 */
5536d210
AD		 1270 if (adapter->hw.mac.type >= e1000_i350)
1271 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1272
5536d210
AD		 1273 /* apply Rx specific ring traits */
1274 ring->count = adapter->rx_ring_count;
1275 ring->queue_index = rxr_idx;
1276
827da44c
JS		 1277 u64_stats_init(&ring->rx_syncp);
1278
5536d210
AD		 1279 /* assign ring to adapter */
1280 adapter->rx_ring[rxr_idx] = ring;
1281 }
1282
1283 return 0;
047e0030
AD		 1284}
1285
5536d210 1286
047e0030 1287/**
b980ac18
JK		 1288 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1289 * @adapter: board private structure to initialize
047e0030 1290 *
b980ac18
JK		 1291 * We allocate one q_vector per queue interrupt. If allocation fails we
1292 * return -ENOMEM.
047e0030 1293 **/
5536d210 1294static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1295{
5536d210
AD		 1296 int q_vectors = adapter->num_q_vectors;
1297 int rxr_remaining = adapter->num_rx_queues;
1298 int txr_remaining = adapter->num_tx_queues;
1299 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1300 int err;
047e0030 1301
5536d210
AD		 1302 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1303 for (; rxr_remaining; v_idx++) {
1304 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1305 0, 0, 1, rxr_idx);
047e0030 1306
5536d210
AD		 1307 if (err)
1308 goto err_out;
1309
1310 /* update counts and index */
1311 rxr_remaining--;
1312 rxr_idx++;
047e0030 1313 }
047e0030 1314 }
5536d210
AD		 1315
1316 for (; v_idx < q_vectors; v_idx++) {
1317 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1318 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1319 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1320 tqpv, txr_idx, rqpv, rxr_idx);
1321
1322 if (err)
1323 goto err_out;
1324
1325 /* update counts and index */
1326 rxr_remaining -= rqpv;
1327 txr_remaining -= tqpv;
1328 rxr_idx++;
1329 txr_idx++;
1330 }
1331
047e0030 1332 return 0;
5536d210
AD		 1333
1334err_out:
1335 adapter->num_tx_queues = 0;
1336 adapter->num_rx_queues = 0;
1337 adapter->num_q_vectors = 0;
1338
1339 while (v_idx--)
1340 igb_free_q_vector(adapter, v_idx);
1341
1342 return -ENOMEM;
047e0030
AD		 1343}
1344
1345/**
b980ac18
JK		 1346 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1347 * @adapter: board private structure to initialize
1348 * @msix: boolean value of MSIX capability
047e0030 1349 *
b980ac18 1350 * This function initializes the interrupts and allocates all of the queues.
047e0030 1351 **/
53c7d064 1352static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1353{
1354 struct pci_dev *pdev = adapter->pdev;
1355 int err;
1356
53c7d064 1357 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1358
1359 err = igb_alloc_q_vectors(adapter);
1360 if (err) {
1361 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1362 goto err_alloc_q_vectors;
1363 }
1364
5536d210 1365 igb_cache_ring_register(adapter);
047e0030
AD		 1366
1367 return 0;
5536d210 1368
047e0030
AD		 1369err_alloc_q_vectors:
1370 igb_reset_interrupt_capability(adapter);
1371 return err;
1372}
1373
9d5c8243 1374/**
b980ac18
JK		 1375 * igb_request_irq - initialize interrupts
1376 * @adapter: board private structure to initialize
9d5c8243 1377 *
b980ac18
JK		 1378 * Attempts to configure interrupts using the best available
1379 * capabilities of the hardware and kernel.
9d5c8243
AK		 1380 **/
1381static int igb_request_irq(struct igb_adapter *adapter)
1382{
1383 struct net_device *netdev = adapter->netdev;
047e0030 1384 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1385 int err = 0;
1386
cd14ef54 1387 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1388 err = igb_request_msix(adapter);
844290e5 1389 if (!err)
9d5c8243 1390 goto request_done;
9d5c8243 1391 /* fall back to MSI */
5536d210
AD		 1392 igb_free_all_tx_resources(adapter);
1393 igb_free_all_rx_resources(adapter);
53c7d064 1394
047e0030 1395 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1396 err = igb_init_interrupt_scheme(adapter, false);
1397 if (err)
047e0030 1398 goto request_done;
53c7d064 1399
047e0030
AD		 1400 igb_setup_all_tx_resources(adapter);
1401 igb_setup_all_rx_resources(adapter);
53c7d064 1402 igb_configure(adapter);
9d5c8243 1403 }
844290e5 1404
c74d588e
AD		 1405 igb_assign_vector(adapter->q_vector[0], 0);
1406
7dfc16fa 1407 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1408 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1409 netdev->name, adapter);
9d5c8243
AK		 1410 if (!err)
1411 goto request_done;
047e0030 1412
9d5c8243
AK		 1413 /* fall back to legacy interrupts */
1414 igb_reset_interrupt_capability(adapter);
7dfc16fa 1415 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1416 }
1417
c74d588e 1418 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1419 netdev->name, adapter);
9d5c8243 1420
6cb5e577 1421 if (err)
c74d588e 1422 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1423 err);
9d5c8243
AK		 1424
1425request_done:
1426 return err;
1427}
1428
1429static void igb_free_irq(struct igb_adapter *adapter)
1430{
cd14ef54 1431 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1432 int vector = 0, i;
1433
047e0030 1434 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1435
0d1ae7f4 1436 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1437 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1438 adapter->q_vector[i]);
047e0030
AD		 1439 } else {
1440 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1441 }
9d5c8243
AK		 1442}
1443
1444/**
b980ac18
JK		 1445 * igb_irq_disable - Mask off interrupt generation on the NIC
1446 * @adapter: board private structure
9d5c8243
AK		 1447 **/
1448static void igb_irq_disable(struct igb_adapter *adapter)
1449{
1450 struct e1000_hw *hw = &adapter->hw;
1451
b980ac18 1452 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1453 * mapped into these registers and so clearing the bits can cause
1454 * issues on the VF drivers so we only need to clear what we set
1455 */
cd14ef54 1456 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212
AD		 1457 u32 regval = rd32(E1000_EIAM);
1458 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1459 wr32(E1000_EIMC, adapter->eims_enable_mask);
1460 regval = rd32(E1000_EIAC);
1461 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1462 }
844290e5
PW		 1463
1464 wr32(E1000_IAM, 0);
9d5c8243
AK		 1465 wr32(E1000_IMC, ~0);
1466 wrfl();
cd14ef54 1467 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859
ET		 1468 int i;
1469 for (i = 0; i < adapter->num_q_vectors; i++)
1470 synchronize_irq(adapter->msix_entries[i].vector);
1471 } else {
1472 synchronize_irq(adapter->pdev->irq);
1473 }
9d5c8243
AK		 1474}
1475
1476/**
b980ac18
JK		 1477 * igb_irq_enable - Enable default interrupt generation settings
1478 * @adapter: board private structure
9d5c8243
AK		 1479 **/
1480static void igb_irq_enable(struct igb_adapter *adapter)
1481{
1482 struct e1000_hw *hw = &adapter->hw;
1483
cd14ef54 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1485 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1486 u32 regval = rd32(E1000_EIAC);
1487 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAM);
1489 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1490 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1491 if (adapter->vfs_allocated_count) {
4ae196df 1492 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1493 ims |= E1000_IMS_VMMB;
1494 }
1495 wr32(E1000_IMS, ims);
844290e5 1496 } else {
55cac248
AD		 1497 wr32(E1000_IMS, IMS_ENABLE_MASK |
1498 E1000_IMS_DRSTA);
1499 wr32(E1000_IAM, IMS_ENABLE_MASK |
1500 E1000_IMS_DRSTA);
844290e5 1501 }
9d5c8243
AK		 1502}
1503
1504static void igb_update_mng_vlan(struct igb_adapter *adapter)
1505{
51466239 1506 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1507 u16 vid = adapter->hw.mng_cookie.vlan_id;
1508 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1509
1510 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1511 /* add VID to filter table */
1512 igb_vfta_set(hw, vid, true);
1513 adapter->mng_vlan_id = vid;
1514 } else {
1515 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1516 }
1517
1518 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1519 (vid != old_vid) &&
b2cb09b1 1520 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1521 /* remove VID from filter table */
1522 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1523 }
1524}
1525
1526/**
b980ac18
JK		 1527 * igb_release_hw_control - release control of the h/w to f/w
1528 * @adapter: address of board private structure
9d5c8243 1529 *
b980ac18
JK		 1530 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1531 * For ASF and Pass Through versions of f/w this means that the
1532 * driver is no longer loaded.
9d5c8243
AK		 1533 **/
1534static void igb_release_hw_control(struct igb_adapter *adapter)
1535{
1536 struct e1000_hw *hw = &adapter->hw;
1537 u32 ctrl_ext;
1538
1539 /* Let firmware take over control of h/w */
1540 ctrl_ext = rd32(E1000_CTRL_EXT);
1541 wr32(E1000_CTRL_EXT,
1542 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1543}
1544
9d5c8243 1545/**
b980ac18
JK		 1546 * igb_get_hw_control - get control of the h/w from f/w
1547 * @adapter: address of board private structure
9d5c8243 1548 *
b980ac18
JK		 1549 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1550 * For ASF and Pass Through versions of f/w this means that
1551 * the driver is loaded.
9d5c8243
AK		 1552 **/
1553static void igb_get_hw_control(struct igb_adapter *adapter)
1554{
1555 struct e1000_hw *hw = &adapter->hw;
1556 u32 ctrl_ext;
1557
1558 /* Let firmware know the driver has taken over */
1559 ctrl_ext = rd32(E1000_CTRL_EXT);
1560 wr32(E1000_CTRL_EXT,
1561 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1562}
1563
9d5c8243 1564/**
b980ac18
JK		 1565 * igb_configure - configure the hardware for RX and TX
1566 * @adapter: private board structure
9d5c8243
AK		 1567 **/
1568static void igb_configure(struct igb_adapter *adapter)
1569{
1570 struct net_device *netdev = adapter->netdev;
1571 int i;
1572
1573 igb_get_hw_control(adapter);
ff41f8dc 1574 igb_set_rx_mode(netdev);
9d5c8243
AK		 1575
1576 igb_restore_vlan(adapter);
9d5c8243 1577
85b430b4 1578 igb_setup_tctl(adapter);
06cf2666 1579 igb_setup_mrqc(adapter);
9d5c8243 1580 igb_setup_rctl(adapter);
85b430b4
AD		 1581
1582 igb_configure_tx(adapter);
9d5c8243 1583 igb_configure_rx(adapter);
662d7205
AD		 1584
1585 igb_rx_fifo_flush_82575(&adapter->hw);
1586
c493ea45 1587 /* call igb_desc_unused which always leaves
9d5c8243 1588 * at least 1 descriptor unused to make sure
b980ac18
JK		 1589 * next_to_use != next_to_clean
1590 */
9d5c8243 1591 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1592 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1593 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1594 }
9d5c8243
AK		 1595}
1596
88a268c1 1597/**
b980ac18
JK		 1598 * igb_power_up_link - Power up the phy/serdes link
1599 * @adapter: address of board private structure
88a268c1
NN		 1600 **/
1601void igb_power_up_link(struct igb_adapter *adapter)
1602{
76886596
AA		 1603 igb_reset_phy(&adapter->hw);
1604
88a268c1
NN		 1605 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1606 igb_power_up_phy_copper(&adapter->hw);
1607 else
1608 igb_power_up_serdes_link_82575(&adapter->hw);
1609}
1610
1611/**
b980ac18
JK		 1612 * igb_power_down_link - Power down the phy/serdes link
1613 * @adapter: address of board private structure
88a268c1
NN		 1614 */
1615static void igb_power_down_link(struct igb_adapter *adapter)
1616{
1617 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1618 igb_power_down_phy_copper_82575(&adapter->hw);
1619 else
1620 igb_shutdown_serdes_link_82575(&adapter->hw);
1621}
9d5c8243 1622
56cec249
CW		 1623/**
1624 * Detect and switch function for Media Auto Sense
1625 * @adapter: address of the board private structure
1626 **/
1627static void igb_check_swap_media(struct igb_adapter *adapter)
1628{
1629 struct e1000_hw *hw = &adapter->hw;
1630 u32 ctrl_ext, connsw;
1631 bool swap_now = false;
1632
1633 ctrl_ext = rd32(E1000_CTRL_EXT);
1634 connsw = rd32(E1000_CONNSW);
1635
1636 /* need to live swap if current media is copper and we have fiber/serdes
1637 * to go to.
1638 */
1639
1640 if ((hw->phy.media_type == e1000_media_type_copper) &&
1641 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1642 swap_now = true;
1643 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1644 /* copper signal takes time to appear */
1645 if (adapter->copper_tries < 4) {
1646 adapter->copper_tries++;
1647 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1648 wr32(E1000_CONNSW, connsw);
1649 return;
1650 } else {
1651 adapter->copper_tries = 0;
1652 if ((connsw & E1000_CONNSW_PHYSD) &&
1653 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1654 swap_now = true;
1655 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1656 wr32(E1000_CONNSW, connsw);
1657 }
1658 }
1659 }
1660
1661 if (!swap_now)
1662 return;
1663
1664 switch (hw->phy.media_type) {
1665 case e1000_media_type_copper:
1666 netdev_info(adapter->netdev,
1667 "MAS: changing media to fiber/serdes\n");
1668 ctrl_ext |=
1669 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1670 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1671 adapter->copper_tries = 0;
1672 break;
1673 case e1000_media_type_internal_serdes:
1674 case e1000_media_type_fiber:
1675 netdev_info(adapter->netdev,
1676 "MAS: changing media to copper\n");
1677 ctrl_ext &=
1678 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1679 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1680 break;
1681 default:
1682 /* shouldn't get here during regular operation */
1683 netdev_err(adapter->netdev,
1684 "AMS: Invalid media type found, returning\n");
1685 break;
1686 }
1687 wr32(E1000_CTRL_EXT, ctrl_ext);
1688}
1689
9d5c8243 1690/**
b980ac18
JK		 1691 * igb_up - Open the interface and prepare it to handle traffic
1692 * @adapter: board private structure
9d5c8243 1693 **/
9d5c8243
AK		 1694int igb_up(struct igb_adapter *adapter)
1695{
1696 struct e1000_hw *hw = &adapter->hw;
1697 int i;
1698
1699 /* hardware has been reset, we need to reload some things */
1700 igb_configure(adapter);
1701
1702 clear_bit(__IGB_DOWN, &adapter->state);
1703
0d1ae7f4
AD		 1704 for (i = 0; i < adapter->num_q_vectors; i++)
1705 napi_enable(&(adapter->q_vector[i]->napi));
1706
cd14ef54 1707 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1708 igb_configure_msix(adapter);
feeb2721
AD		 1709 else
1710 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1711
1712 /* Clear any pending interrupts. */
1713 rd32(E1000_ICR);
1714 igb_irq_enable(adapter);
1715
d4960307
AD		 1716 /* notify VFs that reset has been completed */
1717 if (adapter->vfs_allocated_count) {
1718 u32 reg_data = rd32(E1000_CTRL_EXT);
1719 reg_data |= E1000_CTRL_EXT_PFRSTD;
1720 wr32(E1000_CTRL_EXT, reg_data);
1721 }
1722
4cb9be7a
JB		 1723 netif_tx_start_all_queues(adapter->netdev);
1724
25568a53
AD		 1725 /* start the watchdog. */
1726 hw->mac.get_link_status = 1;
1727 schedule_work(&adapter->watchdog_task);
1728
f4c01e96
CW		 1729 if ((adapter->flags & IGB_FLAG_EEE) &&
1730 (!hw->dev_spec._82575.eee_disable))
1731 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1732
9d5c8243
AK		 1733 return 0;
1734}
1735
1736void igb_down(struct igb_adapter *adapter)
1737{
9d5c8243 1738 struct net_device *netdev = adapter->netdev;
330a6d6a 1739 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1740 u32 tctl, rctl;
1741 int i;
1742
1743 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1744 * reschedule our watchdog timer
1745 */
9d5c8243
AK		 1746 set_bit(__IGB_DOWN, &adapter->state);
1747
1748 /* disable receives in the hardware */
1749 rctl = rd32(E1000_RCTL);
1750 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1751 /* flush and sleep below */
1752
fd2ea0a7 1753 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1754
1755 /* disable transmits in the hardware */
1756 tctl = rd32(E1000_TCTL);
1757 tctl &= ~E1000_TCTL_EN;
1758 wr32(E1000_TCTL, tctl);
1759 /* flush both disables and wait for them to finish */
1760 wrfl();
1761 msleep(10);
1762
41f149a2
CW		 1763 igb_irq_disable(adapter);
1764
aa9b8cc4
AA		 1765 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1766
41f149a2
CW		 1767 for (i = 0; i < adapter->num_q_vectors; i++) {
1768 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1769 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1770 }
9d5c8243 1771
9d5c8243
AK		 1772
1773 del_timer_sync(&adapter->watchdog_timer);
1774 del_timer_sync(&adapter->phy_info_timer);
1775
9d5c8243 1776 netif_carrier_off(netdev);
04fe6358
AD		 1777
1778 /* record the stats before reset*/
12dcd86b
ED		 1779 spin_lock(&adapter->stats64_lock);
1780 igb_update_stats(adapter, &adapter->stats64);
1781 spin_unlock(&adapter->stats64_lock);
04fe6358 1782
9d5c8243
AK		 1783 adapter->link_speed = 0;
1784 adapter->link_duplex = 0;
1785
3023682e
JK		 1786 if (!pci_channel_offline(adapter->pdev))
1787 igb_reset(adapter);
9d5c8243
AK		 1788 igb_clean_all_tx_rings(adapter);
1789 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1790#ifdef CONFIG_IGB_DCA
1791
1792 /* since we reset the hardware DCA settings were cleared */
1793 igb_setup_dca(adapter);
1794#endif
9d5c8243
AK		 1795}
1796
1797void igb_reinit_locked(struct igb_adapter *adapter)
1798{
1799 WARN_ON(in_interrupt());
1800 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1801 msleep(1);
1802 igb_down(adapter);
1803 igb_up(adapter);
1804 clear_bit(__IGB_RESETTING, &adapter->state);
1805}
1806
56cec249
CW		 1807/** igb_enable_mas - Media Autosense re-enable after swap
1808 *
1809 * @adapter: adapter struct
1810 **/
1811static s32 igb_enable_mas(struct igb_adapter *adapter)
1812{
1813 struct e1000_hw *hw = &adapter->hw;
1814 u32 connsw;
1815 s32 ret_val = 0;
1816
1817 connsw = rd32(E1000_CONNSW);
1818 if (!(hw->phy.media_type == e1000_media_type_copper))
1819 return ret_val;
1820
1821 /* configure for SerDes media detect */
1822 if (!(connsw & E1000_CONNSW_SERDESD)) {
1823 connsw |= E1000_CONNSW_ENRGSRC;
1824 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1825 wr32(E1000_CONNSW, connsw);
1826 wrfl();
1827 } else if (connsw & E1000_CONNSW_SERDESD) {
1828 /* already SerDes, no need to enable anything */
1829 return ret_val;
1830 } else {
1831 netdev_info(adapter->netdev,
1832 "MAS: Unable to configure feature, disabling..\n");
1833 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1834 }
1835 return ret_val;
1836}
1837
9d5c8243
AK		 1838void igb_reset(struct igb_adapter *adapter)
1839{
090b1795 1840 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1841 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1842 struct e1000_mac_info *mac = &hw->mac;
1843 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1844 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1845
1846 /* Repartition Pba for greater than 9k mtu
1847 * To take effect CTRL.RST is required.
1848 */
fa4dfae0 1849 switch (mac->type) {
d2ba2ed8 1850 case e1000_i350:
ceb5f13b 1851 case e1000_i354:
55cac248
AD		 1852 case e1000_82580:
1853 pba = rd32(E1000_RXPBS);
1854 pba = igb_rxpbs_adjust_82580(pba);
1855 break;
fa4dfae0 1856 case e1000_82576:
d249be54
AD		 1857 pba = rd32(E1000_RXPBS);
1858 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1859 break;
1860 case e1000_82575:
f96a8a0b
CW		 1861 case e1000_i210:
1862 case e1000_i211:
fa4dfae0
AD		 1863 default:
1864 pba = E1000_PBA_34K;
1865 break;
2d064c06 1866 }
9d5c8243 1867
2d064c06
AD		 1868 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1869 (mac->type < e1000_82576)) {
9d5c8243
AK		 1870 /* adjust PBA for jumbo frames */
1871 wr32(E1000_PBA, pba);
1872
1873 /* To maintain wire speed transmits, the Tx FIFO should be
1874 * large enough to accommodate two full transmit packets,
1875 * rounded up to the next 1KB and expressed in KB. Likewise,
1876 * the Rx FIFO should be large enough to accommodate at least
1877 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1878 * expressed in KB.
1879 */
9d5c8243
AK		 1880 pba = rd32(E1000_PBA);
1881 /* upper 16 bits has Tx packet buffer allocation size in KB */
1882 tx_space = pba >> 16;
1883 /* lower 16 bits has Rx packet buffer allocation size in KB */
1884 pba &= 0xffff;
b980ac18
JK		 1885 /* the Tx fifo also stores 16 bytes of information about the Tx
1886 * but don't include ethernet FCS because hardware appends it
1887 */
9d5c8243 1888 min_tx_space = (adapter->max_frame_size +
85e8d004 1889 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1890 ETH_FCS_LEN) * 2;
1891 min_tx_space = ALIGN(min_tx_space, 1024);
1892 min_tx_space >>= 10;
1893 /* software strips receive CRC, so leave room for it */
1894 min_rx_space = adapter->max_frame_size;
1895 min_rx_space = ALIGN(min_rx_space, 1024);
1896 min_rx_space >>= 10;
1897
1898 /* If current Tx allocation is less than the min Tx FIFO size,
1899 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1900 * allocation, take space away from current Rx allocation
1901 */
9d5c8243
AK		 1902 if (tx_space < min_tx_space &&
1903 ((min_tx_space - tx_space) < pba)) {
1904 pba = pba - (min_tx_space - tx_space);
1905
b980ac18
JK		 1906 /* if short on Rx space, Rx wins and must trump Tx
1907 * adjustment
1908 */
9d5c8243
AK		 1909 if (pba < min_rx_space)
1910 pba = min_rx_space;
1911 }
2d064c06 1912 wr32(E1000_PBA, pba);
9d5c8243 1913 }
9d5c8243
AK		 1914
1915 /* flow control settings */
1916 /* The high water mark must be low enough to fit one full frame
1917 * (or the size used for early receive) above it in the Rx FIFO.
1918 * Set it to the lower of:
1919 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1920 * - the full Rx FIFO size minus one full frame
1921 */
9d5c8243 1922 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1923 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1924
d48507fe 1925 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1926 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1927 fc->pause_time = 0xFFFF;
1928 fc->send_xon = 1;
0cce119a 1929 fc->current_mode = fc->requested_mode;
9d5c8243 1930
4ae196df
AD		 1931 /* disable receive for all VFs and wait one second */
1932 if (adapter->vfs_allocated_count) {
1933 int i;
1934 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1935 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1936
1937 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1938 igb_ping_all_vfs(adapter);
4ae196df
AD		 1939
1940 /* disable transmits and receives */
1941 wr32(E1000_VFRE, 0);
1942 wr32(E1000_VFTE, 0);
1943 }
1944
9d5c8243 1945 /* Allow time for pending master requests to run */
330a6d6a 1946 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1947 wr32(E1000_WUC, 0);
1948
56cec249
CW		 1949 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1950 /* need to resetup here after media swap */
1951 adapter->ei.get_invariants(hw);
1952 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1953 }
1954 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1955 if (igb_enable_mas(adapter))
1956 dev_err(&pdev->dev,
1957 "Error enabling Media Auto Sense\n");
1958 }
330a6d6a 1959 if (hw->mac.ops.init_hw(hw))
090b1795 1960 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1961
b980ac18 1962 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1963 * control is off when forcing speed.
1964 */
1965 if (!hw->mac.autoneg)
1966 igb_force_mac_fc(hw);
1967
b6e0c419 1968 igb_init_dmac(adapter, pba);
e428893b
CW		 1969#ifdef CONFIG_IGB_HWMON
1970 /* Re-initialize the thermal sensor on i350 devices. */
1971 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1972 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1973 /* If present, re-initialize the external thermal sensor
1974 * interface.
1975 */
1976 if (adapter->ets)
1977 mac->ops.init_thermal_sensor_thresh(hw);
1978 }
1979 }
1980#endif
b936136d 1981 /* Re-establish EEE setting */
f4c01e96
CW		 1982 if (hw->phy.media_type == e1000_media_type_copper) {
1983 switch (mac->type) {
1984 case e1000_i350:
1985 case e1000_i210:
1986 case e1000_i211:
1987 igb_set_eee_i350(hw);
1988 break;
1989 case e1000_i354:
1990 igb_set_eee_i354(hw);
1991 break;
1992 default:
1993 break;
1994 }
1995 }
88a268c1
NN		 1996 if (!netif_running(adapter->netdev))
1997 igb_power_down_link(adapter);
1998
9d5c8243
AK		 1999 igb_update_mng_vlan(adapter);
2000
2001 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2002 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2003
1f6e8178
MV		 2004 /* Re-enable PTP, where applicable. */
2005 igb_ptp_reset(adapter);
1f6e8178 2006
330a6d6a 2007 igb_get_phy_info(hw);
9d5c8243
AK		 2008}
2009
c8f44aff
MM		 2010static netdev_features_t igb_fix_features(struct net_device *netdev,
2011 netdev_features_t features)
b2cb09b1 2012{
b980ac18
JK		 2013 /* Since there is no support for separate Rx/Tx vlan accel
2014 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2015 */
f646968f
PM		 2016 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2017 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2018 else
f646968f 2019 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2020
2021 return features;
2022}
2023
c8f44aff
MM		 2024static int igb_set_features(struct net_device *netdev,
2025 netdev_features_t features)
ac52caa3 2026{
c8f44aff 2027 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2028 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2029
f646968f 2030 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2031 igb_vlan_mode(netdev, features);
2032
89eaefb6
BG		 2033 if (!(changed & NETIF_F_RXALL))
2034 return 0;
2035
2036 netdev->features = features;
2037
2038 if (netif_running(netdev))
2039 igb_reinit_locked(adapter);
2040 else
2041 igb_reset(adapter);
2042
ac52caa3
MM		 2043 return 0;
2044}
2045
2e5c6922 2046static const struct net_device_ops igb_netdev_ops = {
559e9c49 2047 .ndo_open = igb_open,
2e5c6922 2048 .ndo_stop = igb_close,
cd392f5c 2049 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2050 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2051 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2052 .ndo_set_mac_address = igb_set_mac,
2053 .ndo_change_mtu = igb_change_mtu,
2054 .ndo_do_ioctl = igb_ioctl,
2055 .ndo_tx_timeout = igb_tx_timeout,
2056 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2057 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2058 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2059 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2060 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2061 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 2062 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2063 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2064#ifdef CONFIG_NET_POLL_CONTROLLER
2065 .ndo_poll_controller = igb_netpoll,
2066#endif
b2cb09b1
JP		 2067 .ndo_fix_features = igb_fix_features,
2068 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2069};
2070
d67974f0
CW		 2071/**
2072 * igb_set_fw_version - Configure version string for ethtool
2073 * @adapter: adapter struct
d67974f0
CW		 2074 **/
2075void igb_set_fw_version(struct igb_adapter *adapter)
2076{
2077 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2078 struct e1000_fw_version fw;
2079
2080 igb_get_fw_version(hw, &fw);
2081
2082 switch (hw->mac.type) {
7dc98a62 2083 case e1000_i210:
0b1a6f2e 2084 case e1000_i211:
7dc98a62
CW		 2085 if (!(igb_get_flash_presence_i210(hw))) {
2086 snprintf(adapter->fw_version,
2087 sizeof(adapter->fw_version),
2088 "%2d.%2d-%d",
2089 fw.invm_major, fw.invm_minor,
2090 fw.invm_img_type);
2091 break;
2092 }
2093 /* fall through */
0b1a6f2e
CW		 2094 default:
2095 /* if option is rom valid, display its version too */
2096 if (fw.or_valid) {
2097 snprintf(adapter->fw_version,
2098 sizeof(adapter->fw_version),
2099 "%d.%d, 0x%08x, %d.%d.%d",
2100 fw.eep_major, fw.eep_minor, fw.etrack_id,
2101 fw.or_major, fw.or_build, fw.or_patch);
2102 /* no option rom */
7dc98a62 2103 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2104 snprintf(adapter->fw_version,
7dc98a62
CW		 2105 sizeof(adapter->fw_version),
2106 "%d.%d, 0x%08x",
2107 fw.eep_major, fw.eep_minor, fw.etrack_id);
2108 } else {
2109 snprintf(adapter->fw_version,
2110 sizeof(adapter->fw_version),
2111 "%d.%d.%d",
2112 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2113 }
2114 break;
d67974f0 2115 }
d67974f0
CW		 2116 return;
2117}
2118
56cec249
CW		 2119/**
2120 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2121 *
2122 * @adapter: adapter struct
2123 **/
2124static void igb_init_mas(struct igb_adapter *adapter)
2125{
2126 struct e1000_hw *hw = &adapter->hw;
2127 u16 eeprom_data;
2128
2129 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2130 switch (hw->bus.func) {
2131 case E1000_FUNC_0:
2132 if (eeprom_data & IGB_MAS_ENABLE_0) {
2133 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2134 netdev_info(adapter->netdev,
2135 "MAS: Enabling Media Autosense for port %d\n",
2136 hw->bus.func);
2137 }
2138 break;
2139 case E1000_FUNC_1:
2140 if (eeprom_data & IGB_MAS_ENABLE_1) {
2141 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2142 netdev_info(adapter->netdev,
2143 "MAS: Enabling Media Autosense for port %d\n",
2144 hw->bus.func);
2145 }
2146 break;
2147 case E1000_FUNC_2:
2148 if (eeprom_data & IGB_MAS_ENABLE_2) {
2149 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2150 netdev_info(adapter->netdev,
2151 "MAS: Enabling Media Autosense for port %d\n",
2152 hw->bus.func);
2153 }
2154 break;
2155 case E1000_FUNC_3:
2156 if (eeprom_data & IGB_MAS_ENABLE_3) {
2157 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2158 netdev_info(adapter->netdev,
2159 "MAS: Enabling Media Autosense for port %d\n",
2160 hw->bus.func);
2161 }
2162 break;
2163 default:
2164 /* Shouldn't get here */
2165 netdev_err(adapter->netdev,
2166 "MAS: Invalid port configuration, returning\n");
2167 break;
2168 }
2169}
2170
b980ac18
JK		 2171/**
2172 * igb_init_i2c - Init I2C interface
441fc6fd 2173 * @adapter: pointer to adapter structure
b980ac18 2174 **/
441fc6fd
CW		 2175static s32 igb_init_i2c(struct igb_adapter *adapter)
2176{
2177 s32 status = E1000_SUCCESS;
2178
2179 /* I2C interface supported on i350 devices */
2180 if (adapter->hw.mac.type != e1000_i350)
2181 return E1000_SUCCESS;
2182
2183 /* Initialize the i2c bus which is controlled by the registers.
2184 * This bus will use the i2c_algo_bit structue that implements
2185 * the protocol through toggling of the 4 bits in the register.
2186 */
2187 adapter->i2c_adap.owner = THIS_MODULE;
2188 adapter->i2c_algo = igb_i2c_algo;
2189 adapter->i2c_algo.data = adapter;
2190 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2191 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2192 strlcpy(adapter->i2c_adap.name, "igb BB",
2193 sizeof(adapter->i2c_adap.name));
2194 status = i2c_bit_add_bus(&adapter->i2c_adap);
2195 return status;
2196}
2197
9d5c8243 2198/**
b980ac18
JK		 2199 * igb_probe - Device Initialization Routine
2200 * @pdev: PCI device information struct
2201 * @ent: entry in igb_pci_tbl
9d5c8243 2202 *
b980ac18 2203 * Returns 0 on success, negative on failure
9d5c8243 2204 *
b980ac18
JK		 2205 * igb_probe initializes an adapter identified by a pci_dev structure.
2206 * The OS initialization, configuring of the adapter private structure,
2207 * and a hardware reset occur.
9d5c8243 2208 **/
1dd06ae8 2209static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2210{
2211 struct net_device *netdev;
2212 struct igb_adapter *adapter;
2213 struct e1000_hw *hw;
4337e993 2214 u16 eeprom_data = 0;
9835fd73 2215 s32 ret_val;
4337e993 2216 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2217 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2218 int err, pci_using_dac;
9835fd73 2219 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2220
bded64a7
AG		 2221 /* Catch broken hardware that put the wrong VF device ID in
2222 * the PCIe SR-IOV capability.
2223 */
2224 if (pdev->is_virtfn) {
2225 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2226 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2227 return -EINVAL;
2228 }
2229
aed5dec3 2230 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2231 if (err)
2232 return err;
2233
2234 pci_using_dac = 0;
dc4ff9bb 2235 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2236 if (!err) {
dc4ff9bb 2237 pci_using_dac = 1;
9d5c8243 2238 } else {
dc4ff9bb 2239 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2240 if (err) {
dc4ff9bb
RK		 2241 dev_err(&pdev->dev,
2242 "No usable DMA configuration, aborting\n");
2243 goto err_dma;
9d5c8243
AK		 2244 }
2245 }
2246
aed5dec3 2247 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2248 IORESOURCE_MEM),
2249 igb_driver_name);
9d5c8243
AK		 2250 if (err)
2251 goto err_pci_reg;
2252
19d5afd4 2253 pci_enable_pcie_error_reporting(pdev);
40a914fa 2254
9d5c8243 2255 pci_set_master(pdev);
c682fc23 2256 pci_save_state(pdev);
9d5c8243
AK		 2257
2258 err = -ENOMEM;
1bfaf07b 2259 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2260 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2261 if (!netdev)
2262 goto err_alloc_etherdev;
2263
2264 SET_NETDEV_DEV(netdev, &pdev->dev);
2265
2266 pci_set_drvdata(pdev, netdev);
2267 adapter = netdev_priv(netdev);
2268 adapter->netdev = netdev;
2269 adapter->pdev = pdev;
2270 hw = &adapter->hw;
2271 hw->back = adapter;
b3f4d599 2272 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2273
9d5c8243 2274 err = -EIO;
89dbefb2 2275 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2276 if (!hw->hw_addr)
9d5c8243
AK		 2277 goto err_ioremap;
2278
2e5c6922 2279 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2280 igb_set_ethtool_ops(netdev);
9d5c8243 2281 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2282
2283 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2284
89dbefb2
AS		 2285 netdev->mem_start = pci_resource_start(pdev, 0);
2286 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2287
9d5c8243
AK		 2288 /* PCI config space info */
2289 hw->vendor_id = pdev->vendor;
2290 hw->device_id = pdev->device;
2291 hw->revision_id = pdev->revision;
2292 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2293 hw->subsystem_device_id = pdev->subsystem_device;
2294
9d5c8243
AK		 2295 /* Copy the default MAC, PHY and NVM function pointers */
2296 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2297 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2298 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2299 /* Initialize skew-specific constants */
2300 err = ei->get_invariants(hw);
2301 if (err)
450c87c8 2302 goto err_sw_init;
9d5c8243 2303
450c87c8 2304 /* setup the private structure */
9d5c8243
AK		 2305 err = igb_sw_init(adapter);
2306 if (err)
2307 goto err_sw_init;
2308
2309 igb_get_bus_info_pcie(hw);
2310
2311 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2312
2313 /* Copper options */
2314 if (hw->phy.media_type == e1000_media_type_copper) {
2315 hw->phy.mdix = AUTO_ALL_MODES;
2316 hw->phy.disable_polarity_correction = false;
2317 hw->phy.ms_type = e1000_ms_hw_default;
2318 }
2319
2320 if (igb_check_reset_block(hw))
2321 dev_info(&pdev->dev,
2322 "PHY reset is blocked due to SOL/IDER session.\n");
2323
b980ac18 2324 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2325 * set by igb_sw_init so we should use an or instead of an
2326 * assignment.
2327 */
2328 netdev->features |= NETIF_F_SG |
2329 NETIF_F_IP_CSUM |
2330 NETIF_F_IPV6_CSUM |
2331 NETIF_F_TSO |
2332 NETIF_F_TSO6 |
2333 NETIF_F_RXHASH |
2334 NETIF_F_RXCSUM |
f646968f
PM		 2335 NETIF_F_HW_VLAN_CTAG_RX |
2336 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2337
2338 /* copy netdev features into list of user selectable features */
2339 netdev->hw_features |= netdev->features;
89eaefb6 2340 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2341
2342 /* set this bit last since it cannot be part of hw_features */
f646968f 2343 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2344
2345 netdev->vlan_features |= NETIF_F_TSO |
2346 NETIF_F_TSO6 |
2347 NETIF_F_IP_CSUM |
2348 NETIF_F_IPV6_CSUM |
2349 NETIF_F_SG;
48f29ffc 2350
6b8f0922
BG		 2351 netdev->priv_flags |= IFF_SUPP_NOFCS;
2352
7b872a55 2353 if (pci_using_dac) {
9d5c8243 2354 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2355 netdev->vlan_features |= NETIF_F_HIGHDMA;
2356 }
9d5c8243 2357
ac52caa3
MM		 2358 if (hw->mac.type >= e1000_82576) {
2359 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2360 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2361 }
b9473560 2362
01789349
JP		 2363 netdev->priv_flags |= IFF_UNICAST_FLT;
2364
330a6d6a 2365 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2366
2367 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2368 * known good starting state
2369 */
9d5c8243
AK		 2370 hw->mac.ops.reset_hw(hw);
2371
ef3a0092
CW		 2372 /* make sure the NVM is good , i211/i210 parts can have special NVM
2373 * that doesn't contain a checksum
f96a8a0b 2374 */
ef3a0092
CW		 2375 switch (hw->mac.type) {
2376 case e1000_i210:
2377 case e1000_i211:
2378 if (igb_get_flash_presence_i210(hw)) {
2379 if (hw->nvm.ops.validate(hw) < 0) {
2380 dev_err(&pdev->dev,
2381 "The NVM Checksum Is Not Valid\n");
2382 err = -EIO;
2383 goto err_eeprom;
2384 }
2385 }
2386 break;
2387 default:
f96a8a0b
CW		 2388 if (hw->nvm.ops.validate(hw) < 0) {
2389 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2390 err = -EIO;
2391 goto err_eeprom;
2392 }
ef3a0092 2393 break;
9d5c8243
AK		 2394 }
2395
2396 /* copy the MAC address out of the NVM */
2397 if (hw->mac.ops.read_mac_addr(hw))
2398 dev_err(&pdev->dev, "NVM Read Error\n");
2399
2400 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2401
aaeb6cdf 2402 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2403 dev_err(&pdev->dev, "Invalid MAC Address\n");
2404 err = -EIO;
2405 goto err_eeprom;
2406 }
2407
d67974f0
CW		 2408 /* get firmware version for ethtool -i */
2409 igb_set_fw_version(adapter);
2410
c061b18d 2411 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2412 (unsigned long) adapter);
c061b18d 2413 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2414 (unsigned long) adapter);
9d5c8243
AK		 2415
2416 INIT_WORK(&adapter->reset_task, igb_reset_task);
2417 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2418
450c87c8 2419 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2420 adapter->fc_autoneg = true;
2421 hw->mac.autoneg = true;
2422 hw->phy.autoneg_advertised = 0x2f;
2423
0cce119a
AD		 2424 hw->fc.requested_mode = e1000_fc_default;
2425 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2426
9d5c8243
AK		 2427 igb_validate_mdi_setting(hw);
2428
63d4a8f9 2429 /* By default, support wake on port A */
a2cf8b6c 2430 if (hw->bus.func == 0)
63d4a8f9
MV		 2431 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2432
2433 /* Check the NVM for wake support on non-port A ports */
2434 if (hw->mac.type >= e1000_82580)
55cac248 2435 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2436 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2437 &eeprom_data);
a2cf8b6c
AD		 2438 else if (hw->bus.func == 1)
2439 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2440
63d4a8f9
MV		 2441 if (eeprom_data & IGB_EEPROM_APME)
2442 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2443
2444 /* now that we have the eeprom settings, apply the special cases where
2445 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2446 * lan on a particular port
2447 */
9d5c8243
AK		 2448 switch (pdev->device) {
2449 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2450 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2451 break;
2452 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2453 case E1000_DEV_ID_82576_FIBER:
2454 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2455 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2456 * regardless of eeprom setting
2457 */
9d5c8243 2458 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2459 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2460 break;
c8ea5ea9 2461 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2462 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2463 /* if quad port adapter, disable WoL on all but port A */
2464 if (global_quad_port_a != 0)
63d4a8f9 2465 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2466 else
2467 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2468 /* Reset for multiple quad port adapters */
2469 if (++global_quad_port_a == 4)
2470 global_quad_port_a = 0;
2471 break;
63d4a8f9
MV		 2472 default:
2473 /* If the device can't wake, don't set software support */
2474 if (!device_can_wakeup(&adapter->pdev->dev))
2475 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2476 }
2477
2478 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2479 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2480 adapter->wol |= E1000_WUFC_MAG;
2481
2482 /* Some vendors want WoL disabled by default, but still supported */
2483 if ((hw->mac.type == e1000_i350) &&
2484 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2485 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2486 adapter->wol = 0;
2487 }
2488
2489 device_set_wakeup_enable(&adapter->pdev->dev,
2490 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2491
2492 /* reset the hardware with the new settings */
2493 igb_reset(adapter);
2494
441fc6fd
CW		 2495 /* Init the I2C interface */
2496 err = igb_init_i2c(adapter);
2497 if (err) {
2498 dev_err(&pdev->dev, "failed to init i2c interface\n");
2499 goto err_eeprom;
2500 }
2501
9d5c8243
AK		 2502 /* let the f/w know that the h/w is now under the control of the
2503 * driver. */
2504 igb_get_hw_control(adapter);
2505
9d5c8243
AK		 2506 strcpy(netdev->name, "eth%d");
2507 err = register_netdev(netdev);
2508 if (err)
2509 goto err_register;
2510
b168dfc5
JB		 2511 /* carrier off reporting is important to ethtool even BEFORE open */
2512 netif_carrier_off(netdev);
2513
421e02f0 2514#ifdef CONFIG_IGB_DCA
bbd98fe4 2515 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2516 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2517 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2518 igb_setup_dca(adapter);
2519 }
fe4506b6 2520
38c845c7 2521#endif
e428893b
CW		 2522#ifdef CONFIG_IGB_HWMON
2523 /* Initialize the thermal sensor on i350 devices. */
2524 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2525 u16 ets_word;
3c89f6d0 2526
b980ac18 2527 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2528 * external thermal sensor.
2529 */
2530 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2531 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2532 adapter->ets = true;
2533 else
2534 adapter->ets = false;
2535 if (igb_sysfs_init(adapter))
2536 dev_err(&pdev->dev,
2537 "failed to allocate sysfs resources\n");
2538 } else {
2539 adapter->ets = false;
2540 }
2541#endif
56cec249
CW		 2542 /* Check if Media Autosense is enabled */
2543 adapter->ei = *ei;
2544 if (hw->dev_spec._82575.mas_capable)
2545 igb_init_mas(adapter);
2546
673b8b70 2547 /* do hw tstamp init after resetting */
7ebae817 2548 igb_ptp_init(adapter);
673b8b70 2549
9d5c8243 2550 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2551 /* print bus type/speed/width info, not applicable to i354 */
2552 if (hw->mac.type != e1000_i354) {
2553 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2554 netdev->name,
2555 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2556 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2557 "unknown"),
2558 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2559 "Width x4" :
2560 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2561 "Width x2" :
2562 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2563 "Width x1" : "unknown"), netdev->dev_addr);
2564 }
9d5c8243 2565
53ea6c7e
TF		 2566 if ((hw->mac.type >= e1000_i210 ||
2567 igb_get_flash_presence_i210(hw))) {
2568 ret_val = igb_read_part_string(hw, part_str,
2569 E1000_PBANUM_LENGTH);
2570 } else {
2571 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2572 }
2573
9835fd73
CW		 2574 if (ret_val)
2575 strcpy(part_str, "Unknown");
2576 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2577 dev_info(&pdev->dev,
2578 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2579 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2580 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2581 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2582 if (hw->phy.media_type == e1000_media_type_copper) {
2583 switch (hw->mac.type) {
2584 case e1000_i350:
2585 case e1000_i210:
2586 case e1000_i211:
2587 /* Enable EEE for internal copper PHY devices */
2588 err = igb_set_eee_i350(hw);
2589 if ((!err) &&
2590 (!hw->dev_spec._82575.eee_disable)) {
2591 adapter->eee_advert =
2592 MDIO_EEE_100TX | MDIO_EEE_1000T;
2593 adapter->flags |= IGB_FLAG_EEE;
2594 }
2595 break;
2596 case e1000_i354:
ceb5f13b 2597 if ((rd32(E1000_CTRL_EXT) &
f4c01e96
CW		 2598 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2599 err = igb_set_eee_i354(hw);
2600 if ((!err) &&
2601 (!hw->dev_spec._82575.eee_disable)) {
2602 adapter->eee_advert =
2603 MDIO_EEE_100TX | MDIO_EEE_1000T;
2604 adapter->flags |= IGB_FLAG_EEE;
2605 }
2606 }
2607 break;
2608 default:
2609 break;
ceb5f13b 2610 }
09b068d4 2611 }
749ab2cd 2612 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2613 return 0;
2614
2615err_register:
2616 igb_release_hw_control(adapter);
441fc6fd 2617 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2618err_eeprom:
2619 if (!igb_check_reset_block(hw))
f5f4cf08 2620 igb_reset_phy(hw);
9d5c8243
AK		 2621
2622 if (hw->flash_address)
2623 iounmap(hw->flash_address);
9d5c8243 2624err_sw_init:
047e0030 2625 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2626 iounmap(hw->hw_addr);
2627err_ioremap:
2628 free_netdev(netdev);
2629err_alloc_etherdev:
559e9c49 2630 pci_release_selected_regions(pdev,
b980ac18 2631 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2632err_pci_reg:
2633err_dma:
2634 pci_disable_device(pdev);
2635 return err;
2636}
2637
fa44f2f1 2638#ifdef CONFIG_PCI_IOV
781798a1 2639static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2640{
2641 struct net_device *netdev = pci_get_drvdata(pdev);
2642 struct igb_adapter *adapter = netdev_priv(netdev);
2643 struct e1000_hw *hw = &adapter->hw;
2644
2645 /* reclaim resources allocated to VFs */
2646 if (adapter->vf_data) {
2647 /* disable iov and allow time for transactions to clear */
b09186d2 2648 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2649 dev_warn(&pdev->dev,
2650 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2651 return -EPERM;
2652 } else {
2653 pci_disable_sriov(pdev);
2654 msleep(500);
2655 }
2656
2657 kfree(adapter->vf_data);
2658 adapter->vf_data = NULL;
2659 adapter->vfs_allocated_count = 0;
2660 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2661 wrfl();
2662 msleep(100);
2663 dev_info(&pdev->dev, "IOV Disabled\n");
2664
2665 /* Re-enable DMA Coalescing flag since IOV is turned off */
2666 adapter->flags |= IGB_FLAG_DMAC;
2667 }
2668
2669 return 0;
2670}
2671
2672static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2673{
2674 struct net_device *netdev = pci_get_drvdata(pdev);
2675 struct igb_adapter *adapter = netdev_priv(netdev);
2676 int old_vfs = pci_num_vf(pdev);
2677 int err = 0;
2678 int i;
2679
cd14ef54 2680 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2681 err = -EPERM;
2682 goto out;
2683 }
fa44f2f1
GR		 2684 if (!num_vfs)
2685 goto out;
fa44f2f1 2686
781798a1
SA		 2687 if (old_vfs) {
2688 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2689 old_vfs, max_vfs);
2690 adapter->vfs_allocated_count = old_vfs;
2691 } else
2692 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2693
2694 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2695 sizeof(struct vf_data_storage), GFP_KERNEL);
2696
2697 /* if allocation failed then we do not support SR-IOV */
2698 if (!adapter->vf_data) {
2699 adapter->vfs_allocated_count = 0;
2700 dev_err(&pdev->dev,
2701 "Unable to allocate memory for VF Data Storage\n");
2702 err = -ENOMEM;
2703 goto out;
2704 }
2705
781798a1
SA		 2706 /* only call pci_enable_sriov() if no VFs are allocated already */
2707 if (!old_vfs) {
2708 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2709 if (err)
2710 goto err_out;
2711 }
fa44f2f1
GR		 2712 dev_info(&pdev->dev, "%d VFs allocated\n",
2713 adapter->vfs_allocated_count);
2714 for (i = 0; i < adapter->vfs_allocated_count; i++)
2715 igb_vf_configure(adapter, i);
2716
2717 /* DMA Coalescing is not supported in IOV mode. */
2718 adapter->flags &= ~IGB_FLAG_DMAC;
2719 goto out;
2720
2721err_out:
2722 kfree(adapter->vf_data);
2723 adapter->vf_data = NULL;
2724 adapter->vfs_allocated_count = 0;
2725out:
2726 return err;
2727}
2728
2729#endif
b980ac18 2730/**
441fc6fd
CW		 2731 * igb_remove_i2c - Cleanup I2C interface
2732 * @adapter: pointer to adapter structure
b980ac18 2733 **/
441fc6fd
CW		 2734static void igb_remove_i2c(struct igb_adapter *adapter)
2735{
441fc6fd
CW		 2736 /* free the adapter bus structure */
2737 i2c_del_adapter(&adapter->i2c_adap);
2738}
2739
9d5c8243 2740/**
b980ac18
JK		 2741 * igb_remove - Device Removal Routine
2742 * @pdev: PCI device information struct
9d5c8243 2743 *
b980ac18
JK		 2744 * igb_remove is called by the PCI subsystem to alert the driver
2745 * that it should release a PCI device. The could be caused by a
2746 * Hot-Plug event, or because the driver is going to be removed from
2747 * memory.
9d5c8243 2748 **/
9f9a12f8 2749static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2750{
2751 struct net_device *netdev = pci_get_drvdata(pdev);
2752 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2753 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2754
749ab2cd 2755 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2756#ifdef CONFIG_IGB_HWMON
2757 igb_sysfs_exit(adapter);
2758#endif
441fc6fd 2759 igb_remove_i2c(adapter);
a79f4f88 2760 igb_ptp_stop(adapter);
b980ac18 2761 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2762 * disable watchdog from being rescheduled.
2763 */
9d5c8243
AK		 2764 set_bit(__IGB_DOWN, &adapter->state);
2765 del_timer_sync(&adapter->watchdog_timer);
2766 del_timer_sync(&adapter->phy_info_timer);
2767
760141a5
TH		 2768 cancel_work_sync(&adapter->reset_task);
2769 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2770
421e02f0 2771#ifdef CONFIG_IGB_DCA
7dfc16fa 2772 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2773 dev_info(&pdev->dev, "DCA disabled\n");
2774 dca_remove_requester(&pdev->dev);
7dfc16fa 2775 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2776 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2777 }
2778#endif
2779
9d5c8243 2780 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2781 * would have already happened in close and is redundant.
2782 */
9d5c8243
AK		 2783 igb_release_hw_control(adapter);
2784
2785 unregister_netdev(netdev);
2786
047e0030 2787 igb_clear_interrupt_scheme(adapter);
9d5c8243 2788
37680117 2789#ifdef CONFIG_PCI_IOV
fa44f2f1 2790 igb_disable_sriov(pdev);
37680117 2791#endif
559e9c49 2792
28b0759c
AD		 2793 iounmap(hw->hw_addr);
2794 if (hw->flash_address)
2795 iounmap(hw->flash_address);
559e9c49 2796 pci_release_selected_regions(pdev,
b980ac18 2797 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2798
1128c756 2799 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2800 free_netdev(netdev);
2801
19d5afd4 2802 pci_disable_pcie_error_reporting(pdev);
40a914fa 2803
9d5c8243
AK		 2804 pci_disable_device(pdev);
2805}
2806
a6b623e0 2807/**
b980ac18
JK		 2808 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2809 * @adapter: board private structure to initialize
a6b623e0 2810 *
b980ac18
JK		 2811 * This function initializes the vf specific data storage and then attempts to
2812 * allocate the VFs. The reason for ordering it this way is because it is much
2813 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2814 * the memory for the VFs.
a6b623e0 2815 **/
9f9a12f8 2816static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2817{
2818#ifdef CONFIG_PCI_IOV
2819 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2820 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2821
f96a8a0b
CW		 2822 /* Virtualization features not supported on i210 family. */
2823 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2824 return;
2825
fa44f2f1 2826 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2827 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2828
a6b623e0
AD		 2829#endif /* CONFIG_PCI_IOV */
2830}
2831
fa44f2f1 2832static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2833{
2834 struct e1000_hw *hw = &adapter->hw;
374a542d 2835 u32 max_rss_queues;
9d5c8243 2836
374a542d 2837 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2838 switch (hw->mac.type) {
374a542d
MV		 2839 case e1000_i211:
2840 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2841 break;
2842 case e1000_82575:
f96a8a0b 2843 case e1000_i210:
374a542d
MV		 2844 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2845 break;
2846 case e1000_i350:
2847 /* I350 cannot do RSS and SR-IOV at the same time */
2848 if (!!adapter->vfs_allocated_count) {
2849 max_rss_queues = 1;
2850 break;
2851 }
2852 /* fall through */
2853 case e1000_82576:
2854 if (!!adapter->vfs_allocated_count) {
2855 max_rss_queues = 2;
2856 break;
2857 }
2858 /* fall through */
2859 case e1000_82580:
ceb5f13b 2860 case e1000_i354:
374a542d
MV		 2861 default:
2862 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2863 break;
374a542d
MV		 2864 }
2865
2866 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2867
2868 /* Determine if we need to pair queues. */
2869 switch (hw->mac.type) {
2870 case e1000_82575:
f96a8a0b 2871 case e1000_i211:
374a542d 2872 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2873 break;
374a542d 2874 case e1000_82576:
b980ac18 2875 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2876 * should pair the queues in order to conserve interrupts due
2877 * to limited supply.
2878 */
2879 if ((adapter->rss_queues > 1) &&
2880 (adapter->vfs_allocated_count > 6))
2881 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2882 /* fall through */
2883 case e1000_82580:
2884 case e1000_i350:
ceb5f13b 2885 case e1000_i354:
374a542d 2886 case e1000_i210:
f96a8a0b 2887 default:
b980ac18 2888 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2889 * order to conserve interrupts due to limited supply.
2890 */
2891 if (adapter->rss_queues > (max_rss_queues / 2))
2892 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2893 break;
2894 }
fa44f2f1
GR		 2895}
2896
2897/**
b980ac18
JK		 2898 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2899 * @adapter: board private structure to initialize
fa44f2f1 2900 *
b980ac18
JK		 2901 * igb_sw_init initializes the Adapter private data structure.
2902 * Fields are initialized based on PCI device information and
2903 * OS network device settings (MTU size).
fa44f2f1
GR		 2904 **/
2905static int igb_sw_init(struct igb_adapter *adapter)
2906{
2907 struct e1000_hw *hw = &adapter->hw;
2908 struct net_device *netdev = adapter->netdev;
2909 struct pci_dev *pdev = adapter->pdev;
2910
2911 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2912
2913 /* set default ring sizes */
2914 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2915 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2916
2917 /* set default ITR values */
2918 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2919 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2920
2921 /* set default work limits */
2922 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2923
2924 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2925 VLAN_HLEN;
2926 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2927
2928 spin_lock_init(&adapter->stats64_lock);
2929#ifdef CONFIG_PCI_IOV
2930 switch (hw->mac.type) {
2931 case e1000_82576:
2932 case e1000_i350:
2933 if (max_vfs > 7) {
2934 dev_warn(&pdev->dev,
2935 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2936 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2937 } else
2938 adapter->vfs_allocated_count = max_vfs;
2939 if (adapter->vfs_allocated_count)
2940 dev_warn(&pdev->dev,
2941 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2942 break;
2943 default:
2944 break;
2945 }
2946#endif /* CONFIG_PCI_IOV */
2947
2948 igb_init_queue_configuration(adapter);
a99955fc 2949
1128c756 2950 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2951 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2952 GFP_ATOMIC);
1128c756 2953
a6b623e0 2954 /* This call may decrease the number of queues */
53c7d064 2955 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2956 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2957 return -ENOMEM;
2958 }
2959
a6b623e0
AD		 2960 igb_probe_vfs(adapter);
2961
9d5c8243
AK		 2962 /* Explicitly disable IRQ since the NIC can be in any state. */
2963 igb_irq_disable(adapter);
2964
f96a8a0b 2965 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2966 adapter->flags &= ~IGB_FLAG_DMAC;
2967
9d5c8243
AK		 2968 set_bit(__IGB_DOWN, &adapter->state);
2969 return 0;
2970}
2971
2972/**
b980ac18
JK		 2973 * igb_open - Called when a network interface is made active
2974 * @netdev: network interface device structure
9d5c8243 2975 *
b980ac18 2976 * Returns 0 on success, negative value on failure
9d5c8243 2977 *
b980ac18
JK		 2978 * The open entry point is called when a network interface is made
2979 * active by the system (IFF_UP). At this point all resources needed
2980 * for transmit and receive operations are allocated, the interrupt
2981 * handler is registered with the OS, the watchdog timer is started,
2982 * and the stack is notified that the interface is ready.
9d5c8243 2983 **/
749ab2cd 2984static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2985{
2986 struct igb_adapter *adapter = netdev_priv(netdev);
2987 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2988 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2989 int err;
2990 int i;
2991
2992 /* disallow open during test */
749ab2cd
YZ		 2993 if (test_bit(__IGB_TESTING, &adapter->state)) {
2994 WARN_ON(resuming);
9d5c8243 2995 return -EBUSY;
749ab2cd
YZ		 2996 }
2997
2998 if (!resuming)
2999 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3000
b168dfc5
JB		 3001 netif_carrier_off(netdev);
3002
9d5c8243
AK		 3003 /* allocate transmit descriptors */
3004 err = igb_setup_all_tx_resources(adapter);
3005 if (err)
3006 goto err_setup_tx;
3007
3008 /* allocate receive descriptors */
3009 err = igb_setup_all_rx_resources(adapter);
3010 if (err)
3011 goto err_setup_rx;
3012
88a268c1 3013 igb_power_up_link(adapter);
9d5c8243 3014
9d5c8243
AK		 3015 /* before we allocate an interrupt, we must be ready to handle it.
3016 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3017 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3018 * clean_rx handler before we do so.
3019 */
9d5c8243
AK		 3020 igb_configure(adapter);
3021
3022 err = igb_request_irq(adapter);
3023 if (err)
3024 goto err_req_irq;
3025
0c2cc02e
AD		 3026 /* Notify the stack of the actual queue counts. */
3027 err = netif_set_real_num_tx_queues(adapter->netdev,
3028 adapter->num_tx_queues);
3029 if (err)
3030 goto err_set_queues;
3031
3032 err = netif_set_real_num_rx_queues(adapter->netdev,
3033 adapter->num_rx_queues);
3034 if (err)
3035 goto err_set_queues;
3036
9d5c8243
AK		 3037 /* From here on the code is the same as igb_up() */
3038 clear_bit(__IGB_DOWN, &adapter->state);
3039
0d1ae7f4
AD		 3040 for (i = 0; i < adapter->num_q_vectors; i++)
3041 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3042
3043 /* Clear any pending interrupts. */
3044 rd32(E1000_ICR);
844290e5
PW		 3045
3046 igb_irq_enable(adapter);
3047
d4960307
AD		 3048 /* notify VFs that reset has been completed */
3049 if (adapter->vfs_allocated_count) {
3050 u32 reg_data = rd32(E1000_CTRL_EXT);
3051 reg_data |= E1000_CTRL_EXT_PFRSTD;
3052 wr32(E1000_CTRL_EXT, reg_data);
3053 }
3054
d55b53ff
JK		 3055 netif_tx_start_all_queues(netdev);
3056
749ab2cd
YZ		 3057 if (!resuming)
3058 pm_runtime_put(&pdev->dev);
3059
25568a53
AD		 3060 /* start the watchdog. */
3061 hw->mac.get_link_status = 1;
3062 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3063
3064 return 0;
3065
0c2cc02e
AD		 3066err_set_queues:
3067 igb_free_irq(adapter);
9d5c8243
AK		 3068err_req_irq:
3069 igb_release_hw_control(adapter);
88a268c1 3070 igb_power_down_link(adapter);
9d5c8243
AK		 3071 igb_free_all_rx_resources(adapter);
3072err_setup_rx:
3073 igb_free_all_tx_resources(adapter);
3074err_setup_tx:
3075 igb_reset(adapter);
749ab2cd
YZ		 3076 if (!resuming)
3077 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3078
3079 return err;
3080}
3081
749ab2cd
YZ		 3082static int igb_open(struct net_device *netdev)
3083{
3084 return __igb_open(netdev, false);
3085}
3086
9d5c8243 3087/**
b980ac18
JK		 3088 * igb_close - Disables a network interface
3089 * @netdev: network interface device structure
9d5c8243 3090 *
b980ac18 3091 * Returns 0, this is not allowed to fail
9d5c8243 3092 *
b980ac18
JK		 3093 * The close entry point is called when an interface is de-activated
3094 * by the OS. The hardware is still under the driver's control, but
3095 * needs to be disabled. A global MAC reset is issued to stop the
3096 * hardware, and all transmit and receive resources are freed.
9d5c8243 3097 **/
749ab2cd 3098static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3099{
3100 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3101 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3102
3103 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3104
749ab2cd
YZ		 3105 if (!suspending)
3106 pm_runtime_get_sync(&pdev->dev);
3107
3108 igb_down(adapter);
9d5c8243
AK		 3109 igb_free_irq(adapter);
3110
3111 igb_free_all_tx_resources(adapter);
3112 igb_free_all_rx_resources(adapter);
3113
749ab2cd
YZ		 3114 if (!suspending)
3115 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3116 return 0;
3117}
3118
749ab2cd
YZ		 3119static int igb_close(struct net_device *netdev)
3120{
3121 return __igb_close(netdev, false);
3122}
3123
9d5c8243 3124/**
b980ac18
JK		 3125 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3126 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3127 *
b980ac18 3128 * Return 0 on success, negative on failure
9d5c8243 3129 **/
80785298 3130int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3131{
59d71989 3132 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3133 int size;
3134
06034649 3135 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3136
3137 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3138 if (!tx_ring->tx_buffer_info)
9d5c8243 3139 goto err;
9d5c8243
AK		 3140
3141 /* round up to nearest 4K */
85e8d004 3142 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3143 tx_ring->size = ALIGN(tx_ring->size, 4096);
3144
5536d210
AD		 3145 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3146 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3147 if (!tx_ring->desc)
3148 goto err;
3149
9d5c8243
AK		 3150 tx_ring->next_to_use = 0;
3151 tx_ring->next_to_clean = 0;
81c2fc22 3152
9d5c8243
AK		 3153 return 0;
3154
3155err:
06034649 3156 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3157 tx_ring->tx_buffer_info = NULL;
3158 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3159 return -ENOMEM;
3160}
3161
3162/**
b980ac18
JK		 3163 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3164 * (Descriptors) for all queues
3165 * @adapter: board private structure
9d5c8243 3166 *
b980ac18 3167 * Return 0 on success, negative on failure
9d5c8243
AK		 3168 **/
3169static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3170{
439705e1 3171 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3172 int i, err = 0;
3173
3174 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3175 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3176 if (err) {
439705e1 3177 dev_err(&pdev->dev,
9d5c8243
AK		 3178 "Allocation for Tx Queue %u failed\n", i);
3179 for (i--; i >= 0; i--)
3025a446 3180 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3181 break;
3182 }
3183 }
3184
3185 return err;
3186}
3187
3188/**
b980ac18
JK		 3189 * igb_setup_tctl - configure the transmit control registers
3190 * @adapter: Board private structure
9d5c8243 3191 **/
d7ee5b3a 3192void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3193{
9d5c8243
AK		 3194 struct e1000_hw *hw = &adapter->hw;
3195 u32 tctl;
9d5c8243 3196
85b430b4
AD		 3197 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3198 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3199
3200 /* Program the Transmit Control Register */
9d5c8243
AK		 3201 tctl = rd32(E1000_TCTL);
3202 tctl &= ~E1000_TCTL_CT;
3203 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3204 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3205
3206 igb_config_collision_dist(hw);
3207
9d5c8243
AK		 3208 /* Enable transmits */
3209 tctl |= E1000_TCTL_EN;
3210
3211 wr32(E1000_TCTL, tctl);
3212}
3213
85b430b4 3214/**
b980ac18
JK		 3215 * igb_configure_tx_ring - Configure transmit ring after Reset
3216 * @adapter: board private structure
3217 * @ring: tx ring to configure
85b430b4 3218 *
b980ac18 3219 * Configure a transmit ring after a reset.
85b430b4 3220 **/
d7ee5b3a
AD		 3221void igb_configure_tx_ring(struct igb_adapter *adapter,
3222 struct igb_ring *ring)
85b430b4
AD		 3223{
3224 struct e1000_hw *hw = &adapter->hw;
a74420e0 3225 u32 txdctl = 0;
85b430b4
AD		 3226 u64 tdba = ring->dma;
3227 int reg_idx = ring->reg_idx;
3228
3229 /* disable the queue */
a74420e0 3230 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3231 wrfl();
3232 mdelay(10);
3233
3234 wr32(E1000_TDLEN(reg_idx),
b980ac18 3235 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3236 wr32(E1000_TDBAL(reg_idx),
b980ac18 3237 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3238 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3239
fce99e34 3240 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3241 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3242 writel(0, ring->tail);
85b430b4
AD		 3243
3244 txdctl |= IGB_TX_PTHRESH;
3245 txdctl |= IGB_TX_HTHRESH << 8;
3246 txdctl |= IGB_TX_WTHRESH << 16;
3247
3248 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3249 wr32(E1000_TXDCTL(reg_idx), txdctl);
3250}
3251
3252/**
b980ac18
JK		 3253 * igb_configure_tx - Configure transmit Unit after Reset
3254 * @adapter: board private structure
85b430b4 3255 *
b980ac18 3256 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3257 **/
3258static void igb_configure_tx(struct igb_adapter *adapter)
3259{
3260 int i;
3261
3262 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3263 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3264}
3265
9d5c8243 3266/**
b980ac18
JK		 3267 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3268 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3269 *
b980ac18 3270 * Returns 0 on success, negative on failure
9d5c8243 3271 **/
80785298 3272int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3273{
59d71989 3274 struct device *dev = rx_ring->dev;
f33005a6 3275 int size;
9d5c8243 3276
06034649 3277 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3278
3279 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3280 if (!rx_ring->rx_buffer_info)
9d5c8243 3281 goto err;
9d5c8243 3282
9d5c8243 3283 /* Round up to nearest 4K */
f33005a6 3284 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3285 rx_ring->size = ALIGN(rx_ring->size, 4096);
3286
5536d210
AD		 3287 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3288 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3289 if (!rx_ring->desc)
3290 goto err;
3291
cbc8e55f 3292 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3293 rx_ring->next_to_clean = 0;
3294 rx_ring->next_to_use = 0;
9d5c8243 3295
9d5c8243
AK		 3296 return 0;
3297
3298err:
06034649
AD		 3299 vfree(rx_ring->rx_buffer_info);
3300 rx_ring->rx_buffer_info = NULL;
f33005a6 3301 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3302 return -ENOMEM;
3303}
3304
3305/**
b980ac18
JK		 3306 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3307 * (Descriptors) for all queues
3308 * @adapter: board private structure
9d5c8243 3309 *
b980ac18 3310 * Return 0 on success, negative on failure
9d5c8243
AK		 3311 **/
3312static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3313{
439705e1 3314 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3315 int i, err = 0;
3316
3317 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3318 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3319 if (err) {
439705e1 3320 dev_err(&pdev->dev,
9d5c8243
AK		 3321 "Allocation for Rx Queue %u failed\n", i);
3322 for (i--; i >= 0; i--)
3025a446 3323 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3324 break;
3325 }
3326 }
3327
3328 return err;
3329}
3330
06cf2666 3331/**
b980ac18
JK		 3332 * igb_setup_mrqc - configure the multiple receive queue control registers
3333 * @adapter: Board private structure
06cf2666
AD		 3334 **/
3335static void igb_setup_mrqc(struct igb_adapter *adapter)
3336{
3337 struct e1000_hw *hw = &adapter->hw;
3338 u32 mrqc, rxcsum;
ed12cc9a 3339 u32 j, num_rx_queues;
a57fe23e
AD		 3340 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3341 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3342 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3343 0xFA01ACBE };
06cf2666
AD		 3344
3345 /* Fill out hash function seeds */
a57fe23e
AD		 3346 for (j = 0; j < 10; j++)
3347 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3348
a99955fc 3349 num_rx_queues = adapter->rss_queues;
06cf2666 3350
797fd4be 3351 switch (hw->mac.type) {
797fd4be
AD		 3352 case e1000_82576:
3353 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3354 if (adapter->vfs_allocated_count)
06cf2666 3355 num_rx_queues = 2;
797fd4be
AD		 3356 break;
3357 default:
3358 break;
06cf2666
AD		 3359 }
3360
ed12cc9a
LMV		 3361 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3362 for (j = 0; j < IGB_RETA_SIZE; j++)
3363 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3364 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3365 }
ed12cc9a 3366 igb_write_rss_indir_tbl(adapter);
06cf2666 3367
b980ac18 3368 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3369 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3370 * offloads as they are enabled by default
3371 */
3372 rxcsum = rd32(E1000_RXCSUM);
3373 rxcsum |= E1000_RXCSUM_PCSD;
3374
3375 if (adapter->hw.mac.type >= e1000_82576)
3376 /* Enable Receive Checksum Offload for SCTP */
3377 rxcsum |= E1000_RXCSUM_CRCOFL;
3378
3379 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3380 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3381
039454a8
AA		 3382 /* Generate RSS hash based on packet types, TCP/UDP
3383 * port numbers and/or IPv4/v6 src and dst addresses
3384 */
f96a8a0b
CW		 3385 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3386 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3387 E1000_MRQC_RSS_FIELD_IPV6 |
3388 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3389 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3390
039454a8
AA		 3391 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3392 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3393 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3394 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3395
06cf2666
AD		 3396 /* If VMDq is enabled then we set the appropriate mode for that, else
3397 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3398 * if we are only using one queue
3399 */
06cf2666
AD		 3400 if (adapter->vfs_allocated_count) {
3401 if (hw->mac.type > e1000_82575) {
3402 /* Set the default pool for the PF's first queue */
3403 u32 vtctl = rd32(E1000_VT_CTL);
3404 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3405 E1000_VT_CTL_DISABLE_DEF_POOL);
3406 vtctl |= adapter->vfs_allocated_count <<
3407 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3408 wr32(E1000_VT_CTL, vtctl);
3409 }
a99955fc 3410 if (adapter->rss_queues > 1)
f96a8a0b 3411 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3412 else
f96a8a0b 3413 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3414 } else {
f96a8a0b
CW		 3415 if (hw->mac.type != e1000_i211)
3416 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3417 }
3418 igb_vmm_control(adapter);
3419
06cf2666
AD		 3420 wr32(E1000_MRQC, mrqc);
3421}
3422
9d5c8243 3423/**
b980ac18
JK		 3424 * igb_setup_rctl - configure the receive control registers
3425 * @adapter: Board private structure
9d5c8243 3426 **/
d7ee5b3a 3427void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3428{
3429 struct e1000_hw *hw = &adapter->hw;
3430 u32 rctl;
9d5c8243
AK		 3431
3432 rctl = rd32(E1000_RCTL);
3433
3434 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3435 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3436
69d728ba 3437 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3438 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3439
b980ac18 3440 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3441 * redirection as it did with e1000. Newer features require
3442 * that the HW strips the CRC.
73cd78f1 3443 */
87cb7e8c 3444 rctl |= E1000_RCTL_SECRC;
9d5c8243 3445
559e9c49 3446 /* disable store bad packets and clear size bits. */
ec54d7d6 3447 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3448
6ec43fe6
AD		 3449 /* enable LPE to prevent packets larger than max_frame_size */
3450 rctl |= E1000_RCTL_LPE;
9d5c8243 3451
952f72a8
AD		 3452 /* disable queue 0 to prevent tail write w/o re-config */
3453 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3454
e1739522
AD		 3455 /* Attention!!! For SR-IOV PF driver operations you must enable
3456 * queue drop for all VF and PF queues to prevent head of line blocking
3457 * if an un-trusted VF does not provide descriptors to hardware.
3458 */
3459 if (adapter->vfs_allocated_count) {
e1739522
AD		 3460 /* set all queue drop enable bits */
3461 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3462 }
3463
89eaefb6
BG		 3464 /* This is useful for sniffing bad packets. */
3465 if (adapter->netdev->features & NETIF_F_RXALL) {
3466 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3467 * in e1000e_set_rx_mode
3468 */
89eaefb6
BG		 3469 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3470 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3471 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3472
3473 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3474 E1000_RCTL_DPF | /* Allow filtered pause */
3475 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3476 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3477 * and that breaks VLANs.
3478 */
3479 }
3480
9d5c8243
AK		 3481 wr32(E1000_RCTL, rctl);
3482}
3483
7d5753f0
AD		 3484static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3485 int vfn)
3486{
3487 struct e1000_hw *hw = &adapter->hw;
3488 u32 vmolr;
3489
3490 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3491 * increase the size to support vlan tags
3492 */
7d5753f0
AD		 3493 if (vfn < adapter->vfs_allocated_count &&
3494 adapter->vf_data[vfn].vlans_enabled)
3495 size += VLAN_TAG_SIZE;
3496
3497 vmolr = rd32(E1000_VMOLR(vfn));
3498 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3499 vmolr |= size | E1000_VMOLR_LPE;
3500 wr32(E1000_VMOLR(vfn), vmolr);
3501
3502 return 0;
3503}
3504
e1739522 3505/**
b980ac18
JK		 3506 * igb_rlpml_set - set maximum receive packet size
3507 * @adapter: board private structure
e1739522 3508 *
b980ac18 3509 * Configure maximum receivable packet size.
e1739522
AD		 3510 **/
3511static void igb_rlpml_set(struct igb_adapter *adapter)
3512{
153285f9 3513 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3514 struct e1000_hw *hw = &adapter->hw;
3515 u16 pf_id = adapter->vfs_allocated_count;
3516
e1739522
AD		 3517 if (pf_id) {
3518 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3519 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3520 * to our max jumbo frame size, in case we need to enable
3521 * jumbo frames on one of the rings later.
3522 * This will not pass over-length frames into the default
3523 * queue because it's gated by the VMOLR.RLPML.
3524 */
7d5753f0 3525 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3526 }
3527
3528 wr32(E1000_RLPML, max_frame_size);
3529}
3530
8151d294
WM		 3531static inline void igb_set_vmolr(struct igb_adapter *adapter,
3532 int vfn, bool aupe)
7d5753f0
AD		 3533{
3534 struct e1000_hw *hw = &adapter->hw;
3535 u32 vmolr;
3536
b980ac18 3537 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3538 * we should exit and do nothing
3539 */
3540 if (hw->mac.type < e1000_82576)
3541 return;
3542
3543 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3544 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3545 if (aupe)
b980ac18 3546 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3547 else
3548 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3549
3550 /* clear all bits that might not be set */
3551 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3552
a99955fc 3553 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3554 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3555 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3556 * multicast packets
3557 */
3558 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3559 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3560
3561 wr32(E1000_VMOLR(vfn), vmolr);
3562}
3563
85b430b4 3564/**
b980ac18
JK		 3565 * igb_configure_rx_ring - Configure a receive ring after Reset
3566 * @adapter: board private structure
3567 * @ring: receive ring to be configured
85b430b4 3568 *
b980ac18 3569 * Configure the Rx unit of the MAC after a reset.
85b430b4 3570 **/
d7ee5b3a 3571void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3572 struct igb_ring *ring)
85b430b4
AD		 3573{
3574 struct e1000_hw *hw = &adapter->hw;
3575 u64 rdba = ring->dma;
3576 int reg_idx = ring->reg_idx;
a74420e0 3577 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3578
3579 /* disable the queue */
a74420e0 3580 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3581
3582 /* Set DMA base address registers */
3583 wr32(E1000_RDBAL(reg_idx),
3584 rdba & 0x00000000ffffffffULL);
3585 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3586 wr32(E1000_RDLEN(reg_idx),
b980ac18 3587 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3588
3589 /* initialize head and tail */
fce99e34 3590 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3591 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3592 writel(0, ring->tail);
85b430b4 3593
952f72a8 3594 /* set descriptor configuration */
44390ca6 3595 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3596 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3597 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3598 if (hw->mac.type >= e1000_82580)
757b77e2 3599 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3600 /* Only set Drop Enable if we are supporting multiple queues */
3601 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3602 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3603
3604 wr32(E1000_SRRCTL(reg_idx), srrctl);
3605
7d5753f0 3606 /* set filtering for VMDQ pools */
8151d294 3607 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3608
85b430b4
AD		 3609 rxdctl |= IGB_RX_PTHRESH;
3610 rxdctl |= IGB_RX_HTHRESH << 8;
3611 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3612
3613 /* enable receive descriptor fetching */
3614 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3615 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3616}
3617
9d5c8243 3618/**
b980ac18
JK		 3619 * igb_configure_rx - Configure receive Unit after Reset
3620 * @adapter: board private structure
9d5c8243 3621 *
b980ac18 3622 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3623 **/
3624static void igb_configure_rx(struct igb_adapter *adapter)
3625{
9107584e 3626 int i;
9d5c8243 3627
68d480c4
AD		 3628 /* set UTA to appropriate mode */
3629 igb_set_uta(adapter);
3630
26ad9178
AD		 3631 /* set the correct pool for the PF default MAC address in entry 0 */
3632 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3633 adapter->vfs_allocated_count);
26ad9178 3634
06cf2666 3635 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3636 * the Base and Length of the Rx Descriptor Ring
3637 */
f9d40f6a
AD		 3638 for (i = 0; i < adapter->num_rx_queues; i++)
3639 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3640}
3641
3642/**
b980ac18
JK		 3643 * igb_free_tx_resources - Free Tx Resources per Queue
3644 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3645 *
b980ac18 3646 * Free all transmit software resources
9d5c8243 3647 **/
68fd9910 3648void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3649{
3b644cf6 3650 igb_clean_tx_ring(tx_ring);
9d5c8243 3651
06034649
AD		 3652 vfree(tx_ring->tx_buffer_info);
3653 tx_ring->tx_buffer_info = NULL;
9d5c8243 3654
439705e1
AD		 3655 /* if not set, then don't free */
3656 if (!tx_ring->desc)
3657 return;
3658
59d71989
AD		 3659 dma_free_coherent(tx_ring->dev, tx_ring->size,
3660 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3661
3662 tx_ring->desc = NULL;
3663}
3664
3665/**
b980ac18
JK		 3666 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3667 * @adapter: board private structure
9d5c8243 3668 *
b980ac18 3669 * Free all transmit software resources
9d5c8243
AK		 3670 **/
3671static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3672{
3673 int i;
3674
3675 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3676 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3677}
3678
ebe42d16
AD		 3679void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3680 struct igb_tx_buffer *tx_buffer)
3681{
3682 if (tx_buffer->skb) {
3683 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3684 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3685 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3686 dma_unmap_addr(tx_buffer, dma),
3687 dma_unmap_len(tx_buffer, len),
ebe42d16 3688 DMA_TO_DEVICE);
c9f14bf3 3689 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3690 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3691 dma_unmap_addr(tx_buffer, dma),
3692 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3693 DMA_TO_DEVICE);
3694 }
3695 tx_buffer->next_to_watch = NULL;
3696 tx_buffer->skb = NULL;
c9f14bf3 3697 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3698 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3699}
3700
3701/**
b980ac18
JK		 3702 * igb_clean_tx_ring - Free Tx Buffers
3703 * @tx_ring: ring to be cleaned
9d5c8243 3704 **/
3b644cf6 3705static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3706{
06034649 3707 struct igb_tx_buffer *buffer_info;
9d5c8243 3708 unsigned long size;
6ad4edfc 3709 u16 i;
9d5c8243 3710
06034649 3711 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3712 return;
3713 /* Free all the Tx ring sk_buffs */
3714
3715 for (i = 0; i < tx_ring->count; i++) {
06034649 3716 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3717 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3718 }
3719
dad8a3b3
JF		 3720 netdev_tx_reset_queue(txring_txq(tx_ring));
3721
06034649
AD		 3722 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3723 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3724
3725 /* Zero out the descriptor ring */
9d5c8243
AK		 3726 memset(tx_ring->desc, 0, tx_ring->size);
3727
3728 tx_ring->next_to_use = 0;
3729 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3730}
3731
3732/**
b980ac18
JK		 3733 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3734 * @adapter: board private structure
9d5c8243
AK		 3735 **/
3736static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3737{
3738 int i;
3739
3740 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3741 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3742}
3743
3744/**
b980ac18
JK		 3745 * igb_free_rx_resources - Free Rx Resources
3746 * @rx_ring: ring to clean the resources from
9d5c8243 3747 *
b980ac18 3748 * Free all receive software resources
9d5c8243 3749 **/
68fd9910 3750void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3751{
3b644cf6 3752 igb_clean_rx_ring(rx_ring);
9d5c8243 3753
06034649
AD		 3754 vfree(rx_ring->rx_buffer_info);
3755 rx_ring->rx_buffer_info = NULL;
9d5c8243 3756
439705e1
AD		 3757 /* if not set, then don't free */
3758 if (!rx_ring->desc)
3759 return;
3760
59d71989
AD		 3761 dma_free_coherent(rx_ring->dev, rx_ring->size,
3762 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3763
3764 rx_ring->desc = NULL;
3765}
3766
3767/**
b980ac18
JK		 3768 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3769 * @adapter: board private structure
9d5c8243 3770 *
b980ac18 3771 * Free all receive software resources
9d5c8243
AK		 3772 **/
3773static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3774{
3775 int i;
3776
3777 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3778 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3779}
3780
3781/**
b980ac18
JK		 3782 * igb_clean_rx_ring - Free Rx Buffers per Queue
3783 * @rx_ring: ring to free buffers from
9d5c8243 3784 **/
3b644cf6 3785static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3786{
9d5c8243 3787 unsigned long size;
c023cd88 3788 u16 i;
9d5c8243 3789
1a1c225b
AD		 3790 if (rx_ring->skb)
3791 dev_kfree_skb(rx_ring->skb);
3792 rx_ring->skb = NULL;
3793
06034649 3794 if (!rx_ring->rx_buffer_info)
9d5c8243 3795 return;
439705e1 3796
9d5c8243
AK		 3797 /* Free all the Rx ring sk_buffs */
3798 for (i = 0; i < rx_ring->count; i++) {
06034649 3799 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3800
cbc8e55f
AD		 3801 if (!buffer_info->page)
3802 continue;
3803
3804 dma_unmap_page(rx_ring->dev,
3805 buffer_info->dma,
3806 PAGE_SIZE,
3807 DMA_FROM_DEVICE);
3808 __free_page(buffer_info->page);
3809
1a1c225b 3810 buffer_info->page = NULL;
9d5c8243
AK		 3811 }
3812
06034649
AD		 3813 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3814 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3815
3816 /* Zero out the descriptor ring */
3817 memset(rx_ring->desc, 0, rx_ring->size);
3818
cbc8e55f 3819 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3820 rx_ring->next_to_clean = 0;
3821 rx_ring->next_to_use = 0;
9d5c8243
AK		 3822}
3823
3824/**
b980ac18
JK		 3825 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3826 * @adapter: board private structure
9d5c8243
AK		 3827 **/
3828static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3829{
3830 int i;
3831
3832 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3833 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3834}
3835
3836/**
b980ac18
JK		 3837 * igb_set_mac - Change the Ethernet Address of the NIC
3838 * @netdev: network interface device structure
3839 * @p: pointer to an address structure
9d5c8243 3840 *
b980ac18 3841 * Returns 0 on success, negative on failure
9d5c8243
AK		 3842 **/
3843static int igb_set_mac(struct net_device *netdev, void *p)
3844{
3845 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3846 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3847 struct sockaddr *addr = p;
3848
3849 if (!is_valid_ether_addr(addr->sa_data))
3850 return -EADDRNOTAVAIL;
3851
3852 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3853 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3854
26ad9178
AD		 3855 /* set the correct pool for the new PF MAC address in entry 0 */
3856 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3857 adapter->vfs_allocated_count);
e1739522 3858
9d5c8243
AK		 3859 return 0;
3860}
3861
3862/**
b980ac18
JK		 3863 * igb_write_mc_addr_list - write multicast addresses to MTA
3864 * @netdev: network interface device structure
9d5c8243 3865 *
b980ac18
JK		 3866 * Writes multicast address list to the MTA hash table.
3867 * Returns: -ENOMEM on failure
3868 * 0 on no addresses written
3869 * X on writing X addresses to MTA
9d5c8243 3870 **/
68d480c4 3871static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3872{
3873 struct igb_adapter *adapter = netdev_priv(netdev);
3874 struct e1000_hw *hw = &adapter->hw;
22bedad3 3875 struct netdev_hw_addr *ha;
68d480c4 3876 u8 *mta_list;
9d5c8243
AK		 3877 int i;
3878
4cd24eaf 3879 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3880 /* nothing to program, so clear mc list */
3881 igb_update_mc_addr_list(hw, NULL, 0);
3882 igb_restore_vf_multicasts(adapter);
3883 return 0;
3884 }
9d5c8243 3885
4cd24eaf 3886 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3887 if (!mta_list)
3888 return -ENOMEM;
ff41f8dc 3889
68d480c4 3890 /* The shared function expects a packed array of only addresses. */
48e2f183 3891 i = 0;
22bedad3
JP		 3892 netdev_for_each_mc_addr(ha, netdev)
3893 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3894
68d480c4
AD		 3895 igb_update_mc_addr_list(hw, mta_list, i);
3896 kfree(mta_list);
3897
4cd24eaf 3898 return netdev_mc_count(netdev);
68d480c4
AD		 3899}
3900
3901/**
b980ac18
JK		 3902 * igb_write_uc_addr_list - write unicast addresses to RAR table
3903 * @netdev: network interface device structure
68d480c4 3904 *
b980ac18
JK		 3905 * Writes unicast address list to the RAR table.
3906 * Returns: -ENOMEM on failure/insufficient address space
3907 * 0 on no addresses written
3908 * X on writing X addresses to the RAR table
68d480c4
AD		 3909 **/
3910static int igb_write_uc_addr_list(struct net_device *netdev)
3911{
3912 struct igb_adapter *adapter = netdev_priv(netdev);
3913 struct e1000_hw *hw = &adapter->hw;
3914 unsigned int vfn = adapter->vfs_allocated_count;
3915 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3916 int count = 0;
3917
3918 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3919 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3920 return -ENOMEM;
9d5c8243 3921
32e7bfc4 3922 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3923 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3924
3925 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3926 if (!rar_entries)
3927 break;
26ad9178 3928 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3929 rar_entries--,
3930 vfn);
68d480c4 3931 count++;
ff41f8dc
AD		 3932 }
3933 }
3934 /* write the addresses in reverse order to avoid write combining */
3935 for (; rar_entries > 0 ; rar_entries--) {
3936 wr32(E1000_RAH(rar_entries), 0);
3937 wr32(E1000_RAL(rar_entries), 0);
3938 }
3939 wrfl();
3940
68d480c4
AD		 3941 return count;
3942}
3943
3944/**
b980ac18
JK		 3945 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3946 * @netdev: network interface device structure
68d480c4 3947 *
b980ac18
JK		 3948 * The set_rx_mode entry point is called whenever the unicast or multicast
3949 * address lists or the network interface flags are updated. This routine is
3950 * responsible for configuring the hardware for proper unicast, multicast,
3951 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3952 **/
3953static void igb_set_rx_mode(struct net_device *netdev)
3954{
3955 struct igb_adapter *adapter = netdev_priv(netdev);
3956 struct e1000_hw *hw = &adapter->hw;
3957 unsigned int vfn = adapter->vfs_allocated_count;
3958 u32 rctl, vmolr = 0;
3959 int count;
3960
3961 /* Check for Promiscuous and All Multicast modes */
3962 rctl = rd32(E1000_RCTL);
3963
3964 /* clear the effected bits */
3965 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3966
3967 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3968 /* retain VLAN HW filtering if in VT mode */
7e44892c 3969 if (adapter->vfs_allocated_count)
6f3dc319 3970 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3971 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3972 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3973 } else {
3974 if (netdev->flags & IFF_ALLMULTI) {
3975 rctl |= E1000_RCTL_MPE;
3976 vmolr |= E1000_VMOLR_MPME;
3977 } else {
b980ac18 3978 /* Write addresses to the MTA, if the attempt fails
25985edc 3979 * then we should just turn on promiscuous mode so
68d480c4
AD		 3980 * that we can at least receive multicast traffic
3981 */
3982 count = igb_write_mc_addr_list(netdev);
3983 if (count < 0) {
3984 rctl |= E1000_RCTL_MPE;
3985 vmolr |= E1000_VMOLR_MPME;
3986 } else if (count) {
3987 vmolr |= E1000_VMOLR_ROMPE;
3988 }
3989 }
b980ac18 3990 /* Write addresses to available RAR registers, if there is not
68d480c4 3991 * sufficient space to store all the addresses then enable
25985edc 3992 * unicast promiscuous mode
68d480c4
AD		 3993 */
3994 count = igb_write_uc_addr_list(netdev);
3995 if (count < 0) {
3996 rctl |= E1000_RCTL_UPE;
3997 vmolr |= E1000_VMOLR_ROPE;
3998 }
3999 rctl |= E1000_RCTL_VFE;
28fc06f5 4000 }
68d480c4 4001 wr32(E1000_RCTL, rctl);
28fc06f5 4002
b980ac18 4003 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4004 * the VMOLR to enable the appropriate modes. Without this workaround
4005 * we will have issues with VLAN tag stripping not being done for frames
4006 * that are only arriving because we are the default pool
4007 */
f96a8a0b 4008 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4009 return;
9d5c8243 4010
68d480c4 4011 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4012 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4013 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4014 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4015}
4016
13800469
GR		 4017static void igb_check_wvbr(struct igb_adapter *adapter)
4018{
4019 struct e1000_hw *hw = &adapter->hw;
4020 u32 wvbr = 0;
4021
4022 switch (hw->mac.type) {
4023 case e1000_82576:
4024 case e1000_i350:
4025 if (!(wvbr = rd32(E1000_WVBR)))
4026 return;
4027 break;
4028 default:
4029 break;
4030 }
4031
4032 adapter->wvbr |= wvbr;
4033}
4034
4035#define IGB_STAGGERED_QUEUE_OFFSET 8
4036
4037static void igb_spoof_check(struct igb_adapter *adapter)
4038{
4039 int j;
4040
4041 if (!adapter->wvbr)
4042 return;
4043
4044 for(j = 0; j < adapter->vfs_allocated_count; j++) {
4045 if (adapter->wvbr & (1 << j) ||
4046 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4047 dev_warn(&adapter->pdev->dev,
4048 "Spoof event(s) detected on VF %d\n", j);
4049 adapter->wvbr &=
4050 ~((1 << j) |
4051 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4052 }
4053 }
4054}
4055
9d5c8243 4056/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4057 * the phy
4058 */
9d5c8243
AK		 4059static void igb_update_phy_info(unsigned long data)
4060{
4061 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4062 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4063}
4064
4d6b725e 4065/**
b980ac18
JK		 4066 * igb_has_link - check shared code for link and determine up/down
4067 * @adapter: pointer to driver private info
4d6b725e 4068 **/
3145535a 4069bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4070{
4071 struct e1000_hw *hw = &adapter->hw;
4072 bool link_active = false;
4d6b725e
AD		 4073
4074 /* get_link_status is set on LSC (link status) interrupt or
4075 * rx sequence error interrupt. get_link_status will stay
4076 * false until the e1000_check_for_link establishes link
4077 * for copper adapters ONLY
4078 */
4079 switch (hw->phy.media_type) {
4080 case e1000_media_type_copper:
e5c3370f
AA		 4081 if (!hw->mac.get_link_status)
4082 return true;
4d6b725e 4083 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4084 hw->mac.ops.check_for_link(hw);
4085 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4086 break;
4087 default:
4088 case e1000_media_type_unknown:
4089 break;
4090 }
4091
aa9b8cc4
AA		 4092 if (((hw->mac.type == e1000_i210) ||
4093 (hw->mac.type == e1000_i211)) &&
4094 (hw->phy.id == I210_I_PHY_ID)) {
4095 if (!netif_carrier_ok(adapter->netdev)) {
4096 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4097 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4098 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4099 adapter->link_check_timeout = jiffies;
4100 }
4101 }
4102
4d6b725e
AD		 4103 return link_active;
4104}
4105
563988dc
SA		 4106static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4107{
4108 bool ret = false;
4109 u32 ctrl_ext, thstat;
4110
f96a8a0b 4111 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4112 if (hw->mac.type == e1000_i350) {
4113 thstat = rd32(E1000_THSTAT);
4114 ctrl_ext = rd32(E1000_CTRL_EXT);
4115
4116 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4117 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4118 ret = !!(thstat & event);
563988dc
SA		 4119 }
4120
4121 return ret;
4122}
4123
9d5c8243 4124/**
b980ac18
JK		 4125 * igb_watchdog - Timer Call-back
4126 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4127 **/
4128static void igb_watchdog(unsigned long data)
4129{
4130 struct igb_adapter *adapter = (struct igb_adapter *)data;
4131 /* Do the rest outside of interrupt context */
4132 schedule_work(&adapter->watchdog_task);
4133}
4134
4135static void igb_watchdog_task(struct work_struct *work)
4136{
4137 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4138 struct igb_adapter,
4139 watchdog_task);
9d5c8243 4140 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4141 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4142 struct net_device *netdev = adapter->netdev;
563988dc 4143 u32 link;
7a6ea550 4144 int i;
56cec249 4145 u32 connsw;
9d5c8243 4146
4d6b725e 4147 link = igb_has_link(adapter);
aa9b8cc4
AA		 4148
4149 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4150 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4151 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4152 else
4153 link = false;
4154 }
4155
56cec249
CW		 4156 /* Force link down if we have fiber to swap to */
4157 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4158 if (hw->phy.media_type == e1000_media_type_copper) {
4159 connsw = rd32(E1000_CONNSW);
4160 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4161 link = 0;
4162 }
4163 }
9d5c8243 4164 if (link) {
2bdfc4e2
CW		 4165 /* Perform a reset if the media type changed. */
4166 if (hw->dev_spec._82575.media_changed) {
4167 hw->dev_spec._82575.media_changed = false;
4168 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4169 igb_reset(adapter);
4170 }
749ab2cd
YZ		 4171 /* Cancel scheduled suspend requests. */
4172 pm_runtime_resume(netdev->dev.parent);
4173
9d5c8243
AK		 4174 if (!netif_carrier_ok(netdev)) {
4175 u32 ctrl;
330a6d6a 4176 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4177 &adapter->link_speed,
4178 &adapter->link_duplex);
9d5c8243
AK		 4179
4180 ctrl = rd32(E1000_CTRL);
527d47c1 4181 /* Links status message must follow this format */
876d2d6f
JK		 4182 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
4183 "Duplex, Flow Control: %s\n",
559e9c49
AD		 4184 netdev->name,
4185 adapter->link_speed,
4186 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4187 "Full" : "Half",
4188 (ctrl & E1000_CTRL_TFCE) &&
4189 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4190 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4191 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4192
f4c01e96
CW		 4193 /* disable EEE if enabled */
4194 if ((adapter->flags & IGB_FLAG_EEE) &&
4195 (adapter->link_duplex == HALF_DUPLEX)) {
4196 dev_info(&adapter->pdev->dev,
4197 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4198 adapter->hw.dev_spec._82575.eee_disable = true;
4199 adapter->flags &= ~IGB_FLAG_EEE;
4200 }
4201
c0ba4778
KS		 4202 /* check if SmartSpeed worked */
4203 igb_check_downshift(hw);
4204 if (phy->speed_downgraded)
4205 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4206
563988dc 4207 /* check for thermal sensor event */
876d2d6f
JK		 4208 if (igb_thermal_sensor_event(hw,
4209 E1000_THSTAT_LINK_THROTTLE)) {
4210 netdev_info(netdev, "The network adapter link "
4211 "speed was downshifted because it "
4212 "overheated\n");
7ef5ed1c 4213 }
563988dc 4214
d07f3e37 4215 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4216 adapter->tx_timeout_factor = 1;
4217 switch (adapter->link_speed) {
4218 case SPEED_10:
9d5c8243
AK		 4219 adapter->tx_timeout_factor = 14;
4220 break;
4221 case SPEED_100:
9d5c8243
AK		 4222 /* maybe add some timeout factor ? */
4223 break;
4224 }
4225
4226 netif_carrier_on(netdev);
9d5c8243 4227
4ae196df 4228 igb_ping_all_vfs(adapter);
17dc566c 4229 igb_check_vf_rate_limit(adapter);
4ae196df 4230
4b1a9877 4231 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4232 if (!test_bit(__IGB_DOWN, &adapter->state))
4233 mod_timer(&adapter->phy_info_timer,
4234 round_jiffies(jiffies + 2 * HZ));
4235 }
4236 } else {
4237 if (netif_carrier_ok(netdev)) {
4238 adapter->link_speed = 0;
4239 adapter->link_duplex = 0;
563988dc
SA		 4240
4241 /* check for thermal sensor event */
876d2d6f
JK		 4242 if (igb_thermal_sensor_event(hw,
4243 E1000_THSTAT_PWR_DOWN)) {
4244 netdev_err(netdev, "The network adapter was "
4245 "stopped because it overheated\n");
7ef5ed1c 4246 }
563988dc 4247
527d47c1
AD		 4248 /* Links status message must follow this format */
4249 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4250 netdev->name);
9d5c8243 4251 netif_carrier_off(netdev);
4b1a9877 4252
4ae196df
AD		 4253 igb_ping_all_vfs(adapter);
4254
4b1a9877 4255 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4256 if (!test_bit(__IGB_DOWN, &adapter->state))
4257 mod_timer(&adapter->phy_info_timer,
4258 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4259
56cec249
CW		 4260 /* link is down, time to check for alternate media */
4261 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4262 igb_check_swap_media(adapter);
4263 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4264 schedule_work(&adapter->reset_task);
4265 /* return immediately */
4266 return;
4267 }
4268 }
749ab2cd
YZ		 4269 pm_schedule_suspend(netdev->dev.parent,
4270 MSEC_PER_SEC * 5);
56cec249
CW		 4271
4272 /* also check for alternate media here */
4273 } else if (!netif_carrier_ok(netdev) &&
4274 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4275 igb_check_swap_media(adapter);
4276 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4277 schedule_work(&adapter->reset_task);
4278 /* return immediately */
4279 return;
4280 }
9d5c8243
AK		 4281 }
4282 }
4283
12dcd86b
ED		 4284 spin_lock(&adapter->stats64_lock);
4285 igb_update_stats(adapter, &adapter->stats64);
4286 spin_unlock(&adapter->stats64_lock);
9d5c8243 4287
dbabb065 4288 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4289 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4290 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4291 /* We've lost link, so the controller stops DMA,
4292 * but we've got queued Tx work that's never going
4293 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4294 * (Do the reset outside of interrupt context).
4295 */
dbabb065
AD		 4296 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4297 adapter->tx_timeout_count++;
4298 schedule_work(&adapter->reset_task);
4299 /* return immediately since reset is imminent */
4300 return;
4301 }
9d5c8243 4302 }
9d5c8243 4303
dbabb065 4304 /* Force detection of hung controller every watchdog period */
6d095fa8 4305 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4306 }
f7ba205e 4307
b980ac18 4308 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4309 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4310 u32 eics = 0;
0d1ae7f4
AD		 4311 for (i = 0; i < adapter->num_q_vectors; i++)
4312 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4313 wr32(E1000_EICS, eics);
4314 } else {
4315 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4316 }
9d5c8243 4317
13800469 4318 igb_spoof_check(adapter);
fc580751 4319 igb_ptp_rx_hang(adapter);
13800469 4320
9d5c8243 4321 /* Reset the timer */
aa9b8cc4
AA		 4322 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4323 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4324 mod_timer(&adapter->watchdog_timer,
4325 round_jiffies(jiffies + HZ));
4326 else
4327 mod_timer(&adapter->watchdog_timer,
4328 round_jiffies(jiffies + 2 * HZ));
4329 }
9d5c8243
AK		 4330}
4331
4332enum latency_range {
4333 lowest_latency = 0,
4334 low_latency = 1,
4335 bulk_latency = 2,
4336 latency_invalid = 255
4337};
4338
6eb5a7f1 4339/**
b980ac18
JK		 4340 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4341 * @q_vector: pointer to q_vector
6eb5a7f1 4342 *
b980ac18
JK		 4343 * Stores a new ITR value based on strictly on packet size. This
4344 * algorithm is less sophisticated than that used in igb_update_itr,
4345 * due to the difficulty of synchronizing statistics across multiple
4346 * receive rings. The divisors and thresholds used by this function
4347 * were determined based on theoretical maximum wire speed and testing
4348 * data, in order to minimize response time while increasing bulk
4349 * throughput.
406d4965 4350 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4351 * NOTE: This function is called only when operating in a multiqueue
4352 * receive environment.
6eb5a7f1 4353 **/
047e0030 4354static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4355{
047e0030 4356 int new_val = q_vector->itr_val;
6eb5a7f1 4357 int avg_wire_size = 0;
047e0030 4358 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4359 unsigned int packets;
9d5c8243 4360
6eb5a7f1
AD		 4361 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4362 * ints/sec - ITR timer value of 120 ticks.
4363 */
4364 if (adapter->link_speed != SPEED_1000) {
0ba82994 4365 new_val = IGB_4K_ITR;
6eb5a7f1 4366 goto set_itr_val;
9d5c8243 4367 }
047e0030 4368
0ba82994
AD		 4369 packets = q_vector->rx.total_packets;
4370 if (packets)
4371 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4372
0ba82994
AD		 4373 packets = q_vector->tx.total_packets;
4374 if (packets)
4375 avg_wire_size = max_t(u32, avg_wire_size,
4376 q_vector->tx.total_bytes / packets);
047e0030
AD		 4377
4378 /* if avg_wire_size isn't set no work was done */
4379 if (!avg_wire_size)
4380 goto clear_counts;
9d5c8243 4381
6eb5a7f1
AD		 4382 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4383 avg_wire_size += 24;
4384
4385 /* Don't starve jumbo frames */
4386 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4387
6eb5a7f1
AD		 4388 /* Give a little boost to mid-size frames */
4389 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4390 new_val = avg_wire_size / 3;
4391 else
4392 new_val = avg_wire_size / 2;
9d5c8243 4393
0ba82994
AD		 4394 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4395 if (new_val < IGB_20K_ITR &&
4396 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4397 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4398 new_val = IGB_20K_ITR;
abe1c363 4399
6eb5a7f1 4400set_itr_val:
047e0030
AD		 4401 if (new_val != q_vector->itr_val) {
4402 q_vector->itr_val = new_val;
4403 q_vector->set_itr = 1;
9d5c8243 4404 }
6eb5a7f1 4405clear_counts:
0ba82994
AD		 4406 q_vector->rx.total_bytes = 0;
4407 q_vector->rx.total_packets = 0;
4408 q_vector->tx.total_bytes = 0;
4409 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4410}
4411
4412/**
b980ac18
JK		 4413 * igb_update_itr - update the dynamic ITR value based on statistics
4414 * @q_vector: pointer to q_vector
4415 * @ring_container: ring info to update the itr for
4416 *
4417 * Stores a new ITR value based on packets and byte
4418 * counts during the last interrupt. The advantage of per interrupt
4419 * computation is faster updates and more accurate ITR for the current
4420 * traffic pattern. Constants in this function were computed
4421 * based on theoretical maximum wire speed and thresholds were set based
4422 * on testing data as well as attempting to minimize response time
4423 * while increasing bulk throughput.
406d4965 4424 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4425 * NOTE: These calculations are only valid when operating in a single-
4426 * queue environment.
9d5c8243 4427 **/
0ba82994
AD		 4428static void igb_update_itr(struct igb_q_vector *q_vector,
4429 struct igb_ring_container *ring_container)
9d5c8243 4430{
0ba82994
AD		 4431 unsigned int packets = ring_container->total_packets;
4432 unsigned int bytes = ring_container->total_bytes;
4433 u8 itrval = ring_container->itr;
9d5c8243 4434
0ba82994 4435 /* no packets, exit with status unchanged */
9d5c8243 4436 if (packets == 0)
0ba82994 4437 return;
9d5c8243 4438
0ba82994 4439 switch (itrval) {
9d5c8243
AK		 4440 case lowest_latency:
4441 /* handle TSO and jumbo frames */
4442 if (bytes/packets > 8000)
0ba82994 4443 itrval = bulk_latency;
9d5c8243 4444 else if ((packets < 5) && (bytes > 512))
0ba82994 4445 itrval = low_latency;
9d5c8243
AK		 4446 break;
4447 case low_latency: /* 50 usec aka 20000 ints/s */
4448 if (bytes > 10000) {
4449 /* this if handles the TSO accounting */
4450 if (bytes/packets > 8000) {
0ba82994 4451 itrval = bulk_latency;
9d5c8243 4452 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4453 itrval = bulk_latency;
9d5c8243 4454 } else if ((packets > 35)) {
0ba82994 4455 itrval = lowest_latency;
9d5c8243
AK		 4456 }
4457 } else if (bytes/packets > 2000) {
0ba82994 4458 itrval = bulk_latency;
9d5c8243 4459 } else if (packets <= 2 && bytes < 512) {
0ba82994 4460 itrval = lowest_latency;
9d5c8243
AK		 4461 }
4462 break;
4463 case bulk_latency: /* 250 usec aka 4000 ints/s */
4464 if (bytes > 25000) {
4465 if (packets > 35)
0ba82994 4466 itrval = low_latency;
1e5c3d21 4467 } else if (bytes < 1500) {
0ba82994 4468 itrval = low_latency;
9d5c8243
AK		 4469 }
4470 break;
4471 }
4472
0ba82994
AD		 4473 /* clear work counters since we have the values we need */
4474 ring_container->total_bytes = 0;
4475 ring_container->total_packets = 0;
4476
4477 /* write updated itr to ring container */
4478 ring_container->itr = itrval;
9d5c8243
AK		 4479}
4480
0ba82994 4481static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4482{
0ba82994 4483 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4484 u32 new_itr = q_vector->itr_val;
0ba82994 4485 u8 current_itr = 0;
9d5c8243
AK		 4486
4487 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4488 if (adapter->link_speed != SPEED_1000) {
4489 current_itr = 0;
0ba82994 4490 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4491 goto set_itr_now;
4492 }
4493
0ba82994
AD		 4494 igb_update_itr(q_vector, &q_vector->tx);
4495 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4496
0ba82994 4497 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4498
6eb5a7f1 4499 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4500 if (current_itr == lowest_latency &&
4501 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4502 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4503 current_itr = low_latency;
4504
9d5c8243
AK		 4505 switch (current_itr) {
4506 /* counts and packets in update_itr are dependent on these numbers */
4507 case lowest_latency:
0ba82994 4508 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4509 break;
4510 case low_latency:
0ba82994 4511 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4512 break;
4513 case bulk_latency:
0ba82994 4514 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4515 break;
4516 default:
4517 break;
4518 }
4519
4520set_itr_now:
047e0030 4521 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4522 /* this attempts to bias the interrupt rate towards Bulk
4523 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4524 * increasing
4525 */
047e0030 4526 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4527 max((new_itr * q_vector->itr_val) /
4528 (new_itr + (q_vector->itr_val >> 2)),
4529 new_itr) : new_itr;
9d5c8243
AK		 4530 /* Don't write the value here; it resets the adapter's
4531 * internal timer, and causes us to delay far longer than
4532 * we should between interrupts. Instead, we write the ITR
4533 * value at the beginning of the next interrupt so the timing
4534 * ends up being correct.
4535 */
047e0030
AD		 4536 q_vector->itr_val = new_itr;
4537 q_vector->set_itr = 1;
9d5c8243 4538 }
9d5c8243
AK		 4539}
4540
c50b52a0
SH		 4541static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4542 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4543{
4544 struct e1000_adv_tx_context_desc *context_desc;
4545 u16 i = tx_ring->next_to_use;
4546
4547 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4548
4549 i++;
4550 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4551
4552 /* set bits to identify this as an advanced context descriptor */
4553 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4554
4555 /* For 82575, context index must be unique per ring. */
866cff06 4556 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4557 mss_l4len_idx |= tx_ring->reg_idx << 4;
4558
4559 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4560 context_desc->seqnum_seed = 0;
4561 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4562 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4563}
4564
7af40ad9
AD		 4565static int igb_tso(struct igb_ring *tx_ring,
4566 struct igb_tx_buffer *first,
4567 u8 *hdr_len)
9d5c8243 4568{
7af40ad9 4569 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4570 u32 vlan_macip_lens, type_tucmd;
4571 u32 mss_l4len_idx, l4len;
4572
ed6aa105
AD		 4573 if (skb->ip_summed != CHECKSUM_PARTIAL)
4574 return 0;
4575
7d13a7d0
AD		 4576 if (!skb_is_gso(skb))
4577 return 0;
9d5c8243
AK		 4578
4579 if (skb_header_cloned(skb)) {
7af40ad9 4580 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4581 if (err)
4582 return err;
4583 }
4584
7d13a7d0
AD		 4585 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4586 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4587
7af40ad9 4588 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4589 struct iphdr *iph = ip_hdr(skb);
4590 iph->tot_len = 0;
4591 iph->check = 0;
4592 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4593 iph->daddr, 0,
4594 IPPROTO_TCP,
4595 0);
7d13a7d0 4596 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4597 first->tx_flags |= IGB_TX_FLAGS_TSO |
4598 IGB_TX_FLAGS_CSUM |
4599 IGB_TX_FLAGS_IPV4;
8e1e8a47 4600 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4601 ipv6_hdr(skb)->payload_len = 0;
4602 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4603 &ipv6_hdr(skb)->daddr,
4604 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4605 first->tx_flags |= IGB_TX_FLAGS_TSO |
4606 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4607 }
4608
7af40ad9 4609 /* compute header lengths */
7d13a7d0
AD		 4610 l4len = tcp_hdrlen(skb);
4611 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4612
7af40ad9
AD		 4613 /* update gso size and bytecount with header size */
4614 first->gso_segs = skb_shinfo(skb)->gso_segs;
4615 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4616
9d5c8243 4617 /* MSS L4LEN IDX */
7d13a7d0
AD		 4618 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4619 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4620
7d13a7d0
AD		 4621 /* VLAN MACLEN IPLEN */
4622 vlan_macip_lens = skb_network_header_len(skb);
4623 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4624 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4625
7d13a7d0 4626 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4627
7d13a7d0 4628 return 1;
9d5c8243
AK		 4629}
4630
7af40ad9 4631static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4632{
7af40ad9 4633 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4634 u32 vlan_macip_lens = 0;
4635 u32 mss_l4len_idx = 0;
4636 u32 type_tucmd = 0;
9d5c8243 4637
7d13a7d0 4638 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4639 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4640 return;
7d13a7d0
AD		 4641 } else {
4642 u8 l4_hdr = 0;
7af40ad9 4643 switch (first->protocol) {
7d13a7d0
AD		 4644 case __constant_htons(ETH_P_IP):
4645 vlan_macip_lens |= skb_network_header_len(skb);
4646 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4647 l4_hdr = ip_hdr(skb)->protocol;
4648 break;
4649 case __constant_htons(ETH_P_IPV6):
4650 vlan_macip_lens |= skb_network_header_len(skb);
4651 l4_hdr = ipv6_hdr(skb)->nexthdr;
4652 break;
4653 default:
4654 if (unlikely(net_ratelimit())) {
4655 dev_warn(tx_ring->dev,
b980ac18
JK		 4656 "partial checksum but proto=%x!\n",
4657 first->protocol);
fa4a7ef3 4658 }
7d13a7d0
AD		 4659 break;
4660 }
fa4a7ef3 4661
7d13a7d0
AD		 4662 switch (l4_hdr) {
4663 case IPPROTO_TCP:
4664 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4665 mss_l4len_idx = tcp_hdrlen(skb) <<
4666 E1000_ADVTXD_L4LEN_SHIFT;
4667 break;
4668 case IPPROTO_SCTP:
4669 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4670 mss_l4len_idx = sizeof(struct sctphdr) <<
4671 E1000_ADVTXD_L4LEN_SHIFT;
4672 break;
4673 case IPPROTO_UDP:
4674 mss_l4len_idx = sizeof(struct udphdr) <<
4675 E1000_ADVTXD_L4LEN_SHIFT;
4676 break;
4677 default:
4678 if (unlikely(net_ratelimit())) {
4679 dev_warn(tx_ring->dev,
b980ac18
JK		 4680 "partial checksum but l4 proto=%x!\n",
4681 l4_hdr);
44b0cda3 4682 }
7d13a7d0 4683 break;
9d5c8243 4684 }
7af40ad9
AD		 4685
4686 /* update TX checksum flag */
4687 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4688 }
9d5c8243 4689
7d13a7d0 4690 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4691 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4692
7d13a7d0 4693 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4694}
4695
1d9daf45
AD		 4696#define IGB_SET_FLAG(_input, _flag, _result) \
4697 ((_flag <= _result) ? \
4698 ((u32)(_input & _flag) * (_result / _flag)) : \
4699 ((u32)(_input & _flag) / (_flag / _result)))
4700
4701static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4702{
4703 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4704 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4705 E1000_ADVTXD_DCMD_DEXT |
4706 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4707
4708 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4709 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4710 (E1000_ADVTXD_DCMD_VLE));
4711
4712 /* set segmentation bits for TSO */
4713 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4714 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4715
4716 /* set timestamp bit if present */
1d9daf45
AD		 4717 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4718 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4719
1d9daf45
AD		 4720 /* insert frame checksum */
4721 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4722
4723 return cmd_type;
4724}
4725
7af40ad9
AD		 4726static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4727 union e1000_adv_tx_desc *tx_desc,
4728 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4729{
4730 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4731
1d9daf45
AD		 4732 /* 82575 requires a unique index per ring */
4733 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4734 olinfo_status |= tx_ring->reg_idx << 4;
4735
4736 /* insert L4 checksum */
1d9daf45
AD		 4737 olinfo_status |= IGB_SET_FLAG(tx_flags,
4738 IGB_TX_FLAGS_CSUM,
4739 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4740
1d9daf45
AD		 4741 /* insert IPv4 checksum */
4742 olinfo_status |= IGB_SET_FLAG(tx_flags,
4743 IGB_TX_FLAGS_IPV4,
4744 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4745
7af40ad9 4746 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4747}
4748
7af40ad9
AD		 4749static void igb_tx_map(struct igb_ring *tx_ring,
4750 struct igb_tx_buffer *first,
ebe42d16 4751 const u8 hdr_len)
9d5c8243 4752{
7af40ad9 4753 struct sk_buff *skb = first->skb;
c9f14bf3 4754 struct igb_tx_buffer *tx_buffer;
ebe42d16 4755 union e1000_adv_tx_desc *tx_desc;
80d0759e 4756 struct skb_frag_struct *frag;
ebe42d16 4757 dma_addr_t dma;
80d0759e 4758 unsigned int data_len, size;
7af40ad9 4759 u32 tx_flags = first->tx_flags;
1d9daf45 4760 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4761 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4762
4763 tx_desc = IGB_TX_DESC(tx_ring, i);
4764
80d0759e
AD		 4765 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4766
4767 size = skb_headlen(skb);
4768 data_len = skb->data_len;
ebe42d16
AD		 4769
4770 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4771
80d0759e
AD		 4772 tx_buffer = first;
4773
4774 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4775 if (dma_mapping_error(tx_ring->dev, dma))
4776 goto dma_error;
4777
4778 /* record length, and DMA address */
4779 dma_unmap_len_set(tx_buffer, len, size);
4780 dma_unmap_addr_set(tx_buffer, dma, dma);
4781
4782 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4783
ebe42d16
AD		 4784 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4785 tx_desc->read.cmd_type_len =
1d9daf45 4786 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4787
4788 i++;
4789 tx_desc++;
4790 if (i == tx_ring->count) {
4791 tx_desc = IGB_TX_DESC(tx_ring, 0);
4792 i = 0;
4793 }
80d0759e 4794 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4795
4796 dma += IGB_MAX_DATA_PER_TXD;
4797 size -= IGB_MAX_DATA_PER_TXD;
4798
ebe42d16
AD		 4799 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4800 }
4801
4802 if (likely(!data_len))
4803 break;
2bbfebe2 4804
1d9daf45 4805 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4806
65689fef 4807 i++;
ebe42d16
AD		 4808 tx_desc++;
4809 if (i == tx_ring->count) {
4810 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4811 i = 0;
ebe42d16 4812 }
80d0759e 4813 tx_desc->read.olinfo_status = 0;
65689fef 4814
9e903e08 4815 size = skb_frag_size(frag);
ebe42d16
AD		 4816 data_len -= size;
4817
4818 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4819 size, DMA_TO_DEVICE);
6366ad33 4820
c9f14bf3 4821 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4822 }
4823
ebe42d16 4824 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4825 cmd_type |= size | IGB_TXD_DCMD;
4826 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4827
80d0759e
AD		 4828 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4829
8542db05
AD		 4830 /* set the timestamp */
4831 first->time_stamp = jiffies;
4832
b980ac18 4833 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4834 * are new descriptors to fetch. (Only applicable for weak-ordered
4835 * memory model archs, such as IA-64).
4836 *
4837 * We also need this memory barrier to make certain all of the
4838 * status bits have been updated before next_to_watch is written.
4839 */
4840 wmb();
4841
8542db05 4842 /* set next_to_watch value indicating a packet is present */
ebe42d16 4843 first->next_to_watch = tx_desc;
9d5c8243 4844
ebe42d16
AD		 4845 i++;
4846 if (i == tx_ring->count)
4847 i = 0;
6366ad33 4848
ebe42d16 4849 tx_ring->next_to_use = i;
6366ad33 4850
ebe42d16 4851 writel(i, tx_ring->tail);
6366ad33 4852
ebe42d16 4853 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4854 * at a time, it synchronizes IO on IA64/Altix systems
4855 */
ebe42d16
AD		 4856 mmiowb();
4857
4858 return;
4859
4860dma_error:
4861 dev_err(tx_ring->dev, "TX DMA map failed\n");
4862
4863 /* clear dma mappings for failed tx_buffer_info map */
4864 for (;;) {
c9f14bf3
AD		 4865 tx_buffer = &tx_ring->tx_buffer_info[i];
4866 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4867 if (tx_buffer == first)
ebe42d16 4868 break;
a77ff709
NN		 4869 if (i == 0)
4870 i = tx_ring->count;
6366ad33 4871 i--;
6366ad33
AD		 4872 }
4873
9d5c8243 4874 tx_ring->next_to_use = i;
9d5c8243
AK		 4875}
4876
6ad4edfc 4877static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4878{
e694e964
AD		 4879 struct net_device *netdev = tx_ring->netdev;
4880
661086df 4881 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4882
9d5c8243
AK		 4883 /* Herbert's original patch had:
4884 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4885 * but since that doesn't exist yet, just open code it.
4886 */
9d5c8243
AK		 4887 smp_mb();
4888
4889 /* We need to check again in a case another CPU has just
b980ac18
JK		 4890 * made room available.
4891 */
c493ea45 4892 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4893 return -EBUSY;
4894
4895 /* A reprieve! */
661086df 4896 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4897
4898 u64_stats_update_begin(&tx_ring->tx_syncp2);
4899 tx_ring->tx_stats.restart_queue2++;
4900 u64_stats_update_end(&tx_ring->tx_syncp2);
4901
9d5c8243
AK		 4902 return 0;
4903}
4904
6ad4edfc 4905static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4906{
c493ea45 4907 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4908 return 0;
e694e964 4909 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4910}
4911
cd392f5c
AD		 4912netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4913 struct igb_ring *tx_ring)
9d5c8243 4914{
8542db05 4915 struct igb_tx_buffer *first;
ebe42d16 4916 int tso;
91d4ee33 4917 u32 tx_flags = 0;
21ba6fe1 4918 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4919 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4920 u8 hdr_len = 0;
9d5c8243 4921
21ba6fe1
AD		 4922 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4923 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4924 * + 2 desc gap to keep tail from touching head,
9d5c8243 4925 * + 1 desc for context descriptor,
21ba6fe1
AD		 4926 * otherwise try next time
4927 */
4928 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4929 unsigned short f;
4930 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4931 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4932 } else {
4933 count += skb_shinfo(skb)->nr_frags;
4934 }
4935
4936 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4937 /* this is a hard error */
9d5c8243
AK		 4938 return NETDEV_TX_BUSY;
4939 }
33af6bcc 4940
7af40ad9
AD		 4941 /* record the location of the first descriptor for this packet */
4942 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4943 first->skb = skb;
4944 first->bytecount = skb->len;
4945 first->gso_segs = 1;
4946
b66e2397
MV		 4947 skb_tx_timestamp(skb);
4948
b646c22e
AD		 4949 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4950 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4951
b646c22e
AD		 4952 if (!(adapter->ptp_tx_skb)) {
4953 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4954 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4955
4956 adapter->ptp_tx_skb = skb_get(skb);
4957 adapter->ptp_tx_start = jiffies;
4958 if (adapter->hw.mac.type == e1000_82576)
4959 schedule_work(&adapter->ptp_tx_work);
4960 }
33af6bcc 4961 }
9d5c8243 4962
eab6d18d 4963 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4964 tx_flags |= IGB_TX_FLAGS_VLAN;
4965 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4966 }
4967
7af40ad9
AD		 4968 /* record initial flags and protocol */
4969 first->tx_flags = tx_flags;
4970 first->protocol = protocol;
cdfd01fc 4971
7af40ad9
AD		 4972 tso = igb_tso(tx_ring, first, &hdr_len);
4973 if (tso < 0)
7d13a7d0 4974 goto out_drop;
7af40ad9
AD		 4975 else if (!tso)
4976 igb_tx_csum(tx_ring, first);
9d5c8243 4977
7af40ad9 4978 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4979
4980 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4981 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4982
9d5c8243 4983 return NETDEV_TX_OK;
7d13a7d0
AD		 4984
4985out_drop:
7af40ad9
AD		 4986 igb_unmap_and_free_tx_resource(tx_ring, first);
4987
7d13a7d0 4988 return NETDEV_TX_OK;
9d5c8243
AK		 4989}
4990
1cc3bd87
AD		 4991static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4992 struct sk_buff *skb)
4993{
4994 unsigned int r_idx = skb->queue_mapping;
4995
4996 if (r_idx >= adapter->num_tx_queues)
4997 r_idx = r_idx % adapter->num_tx_queues;
4998
4999 return adapter->tx_ring[r_idx];
5000}
5001
cd392f5c
AD		 5002static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5003 struct net_device *netdev)
9d5c8243
AK		 5004{
5005 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5006
5007 if (test_bit(__IGB_DOWN, &adapter->state)) {
5008 dev_kfree_skb_any(skb);
5009 return NETDEV_TX_OK;
5010 }
5011
5012 if (skb->len <= 0) {
5013 dev_kfree_skb_any(skb);
5014 return NETDEV_TX_OK;
5015 }
5016
b980ac18 5017 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5018 * in order to meet this minimum size requirement.
5019 */
ea5ceeab
TD		 5020 if (unlikely(skb->len < 17)) {
5021 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 5022 return NETDEV_TX_OK;
5023 skb->len = 17;
ea5ceeab 5024 skb_set_tail_pointer(skb, 17);
1cc3bd87 5025 }
9d5c8243 5026
1cc3bd87 5027 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5028}
5029
5030/**
b980ac18
JK		 5031 * igb_tx_timeout - Respond to a Tx Hang
5032 * @netdev: network interface device structure
9d5c8243
AK		 5033 **/
5034static void igb_tx_timeout(struct net_device *netdev)
5035{
5036 struct igb_adapter *adapter = netdev_priv(netdev);
5037 struct e1000_hw *hw = &adapter->hw;
5038
5039 /* Do the reset outside of interrupt context */
5040 adapter->tx_timeout_count++;
f7ba205e 5041
06218a8d 5042 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5043 hw->dev_spec._82575.global_device_reset = true;
5044
9d5c8243 5045 schedule_work(&adapter->reset_task);
265de409
AD		 5046 wr32(E1000_EICS,
5047 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5048}
5049
5050static void igb_reset_task(struct work_struct *work)
5051{
5052 struct igb_adapter *adapter;
5053 adapter = container_of(work, struct igb_adapter, reset_task);
5054
c97ec42a
TI		 5055 igb_dump(adapter);
5056 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5057 igb_reinit_locked(adapter);
5058}
5059
5060/**
b980ac18
JK		 5061 * igb_get_stats64 - Get System Network Statistics
5062 * @netdev: network interface device structure
5063 * @stats: rtnl_link_stats64 pointer
9d5c8243 5064 **/
12dcd86b 5065static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5066 struct rtnl_link_stats64 *stats)
9d5c8243 5067{
12dcd86b
ED		 5068 struct igb_adapter *adapter = netdev_priv(netdev);
5069
5070 spin_lock(&adapter->stats64_lock);
5071 igb_update_stats(adapter, &adapter->stats64);
5072 memcpy(stats, &adapter->stats64, sizeof(*stats));
5073 spin_unlock(&adapter->stats64_lock);
5074
5075 return stats;
9d5c8243
AK		 5076}
5077
5078/**
b980ac18
JK		 5079 * igb_change_mtu - Change the Maximum Transfer Unit
5080 * @netdev: network interface device structure
5081 * @new_mtu: new value for maximum frame size
9d5c8243 5082 *
b980ac18 5083 * Returns 0 on success, negative on failure
9d5c8243
AK		 5084 **/
5085static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5086{
5087 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5088 struct pci_dev *pdev = adapter->pdev;
153285f9 5089 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5090
c809d227 5091 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5092 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5093 return -EINVAL;
5094 }
5095
153285f9 5096#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5097 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5098 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5099 return -EINVAL;
5100 }
5101
2ccd994c
AD		 5102 /* adjust max frame to be at least the size of a standard frame */
5103 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5104 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5105
9d5c8243
AK		 5106 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5107 msleep(1);
73cd78f1 5108
9d5c8243
AK		 5109 /* igb_down has a dependency on max_frame_size */
5110 adapter->max_frame_size = max_frame;
559e9c49 5111
4c844851
AD		 5112 if (netif_running(netdev))
5113 igb_down(adapter);
9d5c8243 5114
090b1795 5115 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5116 netdev->mtu, new_mtu);
5117 netdev->mtu = new_mtu;
5118
5119 if (netif_running(netdev))
5120 igb_up(adapter);
5121 else
5122 igb_reset(adapter);
5123
5124 clear_bit(__IGB_RESETTING, &adapter->state);
5125
5126 return 0;
5127}
5128
5129/**
b980ac18
JK		 5130 * igb_update_stats - Update the board statistics counters
5131 * @adapter: board private structure
9d5c8243 5132 **/
12dcd86b
ED		 5133void igb_update_stats(struct igb_adapter *adapter,
5134 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5135{
5136 struct e1000_hw *hw = &adapter->hw;
5137 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5138 u32 reg, mpc;
9d5c8243 5139 u16 phy_tmp;
3f9c0164
AD		 5140 int i;
5141 u64 bytes, packets;
12dcd86b
ED		 5142 unsigned int start;
5143 u64 _bytes, _packets;
9d5c8243
AK		 5144
5145#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
5146
b980ac18 5147 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5148 * connection is down.
5149 */
5150 if (adapter->link_speed == 0)
5151 return;
5152 if (pci_channel_offline(pdev))
5153 return;
5154
3f9c0164
AD		 5155 bytes = 0;
5156 packets = 0;
7f90128e
AA		 5157
5158 rcu_read_lock();
3f9c0164 5159 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 5160 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 5161 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 5162
ae1c07a6
AD		 5163 if (rqdpc) {
5164 ring->rx_stats.drops += rqdpc;
5165 net_stats->rx_fifo_errors += rqdpc;
5166 }
12dcd86b
ED		 5167
5168 do {
57a7744e 5169 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5170 _bytes = ring->rx_stats.bytes;
5171 _packets = ring->rx_stats.packets;
57a7744e 5172 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5173 bytes += _bytes;
5174 packets += _packets;
3f9c0164
AD		 5175 }
5176
128e45eb
AD		 5177 net_stats->rx_bytes = bytes;
5178 net_stats->rx_packets = packets;
3f9c0164
AD		 5179
5180 bytes = 0;
5181 packets = 0;
5182 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5183 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5184 do {
57a7744e 5185 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5186 _bytes = ring->tx_stats.bytes;
5187 _packets = ring->tx_stats.packets;
57a7744e 5188 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5189 bytes += _bytes;
5190 packets += _packets;
3f9c0164 5191 }
128e45eb
AD		 5192 net_stats->tx_bytes = bytes;
5193 net_stats->tx_packets = packets;
7f90128e 5194 rcu_read_unlock();
3f9c0164
AD		 5195
5196 /* read stats registers */
9d5c8243
AK		 5197 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5198 adapter->stats.gprc += rd32(E1000_GPRC);
5199 adapter->stats.gorc += rd32(E1000_GORCL);
5200 rd32(E1000_GORCH); /* clear GORCL */
5201 adapter->stats.bprc += rd32(E1000_BPRC);
5202 adapter->stats.mprc += rd32(E1000_MPRC);
5203 adapter->stats.roc += rd32(E1000_ROC);
5204
5205 adapter->stats.prc64 += rd32(E1000_PRC64);
5206 adapter->stats.prc127 += rd32(E1000_PRC127);
5207 adapter->stats.prc255 += rd32(E1000_PRC255);
5208 adapter->stats.prc511 += rd32(E1000_PRC511);
5209 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5210 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5211 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5212 adapter->stats.sec += rd32(E1000_SEC);
5213
fa3d9a6d
MW		 5214 mpc = rd32(E1000_MPC);
5215 adapter->stats.mpc += mpc;
5216 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5217 adapter->stats.scc += rd32(E1000_SCC);
5218 adapter->stats.ecol += rd32(E1000_ECOL);
5219 adapter->stats.mcc += rd32(E1000_MCC);
5220 adapter->stats.latecol += rd32(E1000_LATECOL);
5221 adapter->stats.dc += rd32(E1000_DC);
5222 adapter->stats.rlec += rd32(E1000_RLEC);
5223 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5224 adapter->stats.xontxc += rd32(E1000_XONTXC);
5225 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5226 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5227 adapter->stats.fcruc += rd32(E1000_FCRUC);
5228 adapter->stats.gptc += rd32(E1000_GPTC);
5229 adapter->stats.gotc += rd32(E1000_GOTCL);
5230 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5231 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5232 adapter->stats.ruc += rd32(E1000_RUC);
5233 adapter->stats.rfc += rd32(E1000_RFC);
5234 adapter->stats.rjc += rd32(E1000_RJC);
5235 adapter->stats.tor += rd32(E1000_TORH);
5236 adapter->stats.tot += rd32(E1000_TOTH);
5237 adapter->stats.tpr += rd32(E1000_TPR);
5238
5239 adapter->stats.ptc64 += rd32(E1000_PTC64);
5240 adapter->stats.ptc127 += rd32(E1000_PTC127);
5241 adapter->stats.ptc255 += rd32(E1000_PTC255);
5242 adapter->stats.ptc511 += rd32(E1000_PTC511);
5243 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5244 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5245
5246 adapter->stats.mptc += rd32(E1000_MPTC);
5247 adapter->stats.bptc += rd32(E1000_BPTC);
5248
2d0b0f69
NN		 5249 adapter->stats.tpt += rd32(E1000_TPT);
5250 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5251
5252 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5253 /* read internal phy specific stats */
5254 reg = rd32(E1000_CTRL_EXT);
5255 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5256 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5257
5258 /* this stat has invalid values on i210/i211 */
5259 if ((hw->mac.type != e1000_i210) &&
5260 (hw->mac.type != e1000_i211))
5261 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5262 }
5263
9d5c8243
AK		 5264 adapter->stats.tsctc += rd32(E1000_TSCTC);
5265 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5266
5267 adapter->stats.iac += rd32(E1000_IAC);
5268 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5269 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5270 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5271 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5272 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5273 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5274 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5275 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5276
5277 /* Fill out the OS statistics structure */
128e45eb
AD		 5278 net_stats->multicast = adapter->stats.mprc;
5279 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5280
5281 /* Rx Errors */
5282
5283 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5284 * our own version based on RUC and ROC
5285 */
128e45eb 5286 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5287 adapter->stats.crcerrs + adapter->stats.algnerrc +
5288 adapter->stats.ruc + adapter->stats.roc +
5289 adapter->stats.cexterr;
128e45eb
AD		 5290 net_stats->rx_length_errors = adapter->stats.ruc +
5291 adapter->stats.roc;
5292 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5293 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5294 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5295
5296 /* Tx Errors */
128e45eb
AD		 5297 net_stats->tx_errors = adapter->stats.ecol +
5298 adapter->stats.latecol;
5299 net_stats->tx_aborted_errors = adapter->stats.ecol;
5300 net_stats->tx_window_errors = adapter->stats.latecol;
5301 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5302
5303 /* Tx Dropped needs to be maintained elsewhere */
5304
5305 /* Phy Stats */
5306 if (hw->phy.media_type == e1000_media_type_copper) {
5307 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5308 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5309 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5310 adapter->phy_stats.idle_errors += phy_tmp;
5311 }
5312 }
5313
5314 /* Management Stats */
5315 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5316 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5317 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5318
5319 /* OS2BMC Stats */
5320 reg = rd32(E1000_MANC);
5321 if (reg & E1000_MANC_EN_BMC2OS) {
5322 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5323 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5324 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5325 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5326 }
9d5c8243
AK		 5327}
5328
9d5c8243
AK		 5329static irqreturn_t igb_msix_other(int irq, void *data)
5330{
047e0030 5331 struct igb_adapter *adapter = data;
9d5c8243 5332 struct e1000_hw *hw = &adapter->hw;
844290e5 5333 u32 icr = rd32(E1000_ICR);
844290e5 5334 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5335
7f081d40
AD		 5336 if (icr & E1000_ICR_DRSTA)
5337 schedule_work(&adapter->reset_task);
5338
047e0030 5339 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5340 /* HW is reporting DMA is out of sync */
5341 adapter->stats.doosync++;
13800469
GR		 5342 /* The DMA Out of Sync is also indication of a spoof event
5343 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5344 * see if it is really a spoof event.
5345 */
13800469 5346 igb_check_wvbr(adapter);
dda0e083 5347 }
eebbbdba 5348
4ae196df
AD		 5349 /* Check for a mailbox event */
5350 if (icr & E1000_ICR_VMMB)
5351 igb_msg_task(adapter);
5352
5353 if (icr & E1000_ICR_LSC) {
5354 hw->mac.get_link_status = 1;
5355 /* guard against interrupt when we're going down */
5356 if (!test_bit(__IGB_DOWN, &adapter->state))
5357 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5358 }
5359
1f6e8178
MV		 5360 if (icr & E1000_ICR_TS) {
5361 u32 tsicr = rd32(E1000_TSICR);
5362
5363 if (tsicr & E1000_TSICR_TXTS) {
5364 /* acknowledge the interrupt */
5365 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5366 /* retrieve hardware timestamp */
5367 schedule_work(&adapter->ptp_tx_work);
5368 }
5369 }
1f6e8178 5370
844290e5 5371 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5372
5373 return IRQ_HANDLED;
5374}
5375
047e0030 5376static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5377{
26b39276 5378 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5379 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5380
047e0030
AD		 5381 if (!q_vector->set_itr)
5382 return;
73cd78f1 5383
047e0030
AD		 5384 if (!itr_val)
5385 itr_val = 0x4;
661086df 5386
26b39276
AD		 5387 if (adapter->hw.mac.type == e1000_82575)
5388 itr_val |= itr_val << 16;
661086df 5389 else
0ba82994 5390 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5391
047e0030
AD		 5392 writel(itr_val, q_vector->itr_register);
5393 q_vector->set_itr = 0;
6eb5a7f1
AD		 5394}
5395
047e0030 5396static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5397{
047e0030 5398 struct igb_q_vector *q_vector = data;
9d5c8243 5399
047e0030
AD		 5400 /* Write the ITR value calculated from the previous interrupt. */
5401 igb_write_itr(q_vector);
9d5c8243 5402
047e0030 5403 napi_schedule(&q_vector->napi);
844290e5 5404
047e0030 5405 return IRQ_HANDLED;
fe4506b6
JC		 5406}
5407
421e02f0 5408#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5409static void igb_update_tx_dca(struct igb_adapter *adapter,
5410 struct igb_ring *tx_ring,
5411 int cpu)
5412{
5413 struct e1000_hw *hw = &adapter->hw;
5414 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5415
5416 if (hw->mac.type != e1000_82575)
5417 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5418
b980ac18 5419 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5420 * DCA is enabled. This is due to a known issue in some chipsets
5421 * which will cause the DCA tag to be cleared.
5422 */
5423 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5424 E1000_DCA_TXCTRL_DATA_RRO_EN |
5425 E1000_DCA_TXCTRL_DESC_DCA_EN;
5426
5427 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5428}
5429
5430static void igb_update_rx_dca(struct igb_adapter *adapter,
5431 struct igb_ring *rx_ring,
5432 int cpu)
5433{
5434 struct e1000_hw *hw = &adapter->hw;
5435 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5436
5437 if (hw->mac.type != e1000_82575)
5438 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5439
b980ac18 5440 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5441 * DCA is enabled. This is due to a known issue in some chipsets
5442 * which will cause the DCA tag to be cleared.
5443 */
5444 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5445 E1000_DCA_RXCTRL_DESC_DCA_EN;
5446
5447 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5448}
5449
047e0030 5450static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5451{
047e0030 5452 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5453 int cpu = get_cpu();
fe4506b6 5454
047e0030
AD		 5455 if (q_vector->cpu == cpu)
5456 goto out_no_update;
5457
6a05004a
AD		 5458 if (q_vector->tx.ring)
5459 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5460
5461 if (q_vector->rx.ring)
5462 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5463
047e0030
AD		 5464 q_vector->cpu = cpu;
5465out_no_update:
fe4506b6
JC		 5466 put_cpu();
5467}
5468
5469static void igb_setup_dca(struct igb_adapter *adapter)
5470{
7e0e99ef 5471 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5472 int i;
5473
7dfc16fa 5474 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5475 return;
5476
7e0e99ef
AD		 5477 /* Always use CB2 mode, difference is masked in the CB driver. */
5478 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5479
047e0030 5480 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5481 adapter->q_vector[i]->cpu = -1;
5482 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5483 }
5484}
5485
5486static int __igb_notify_dca(struct device *dev, void *data)
5487{
5488 struct net_device *netdev = dev_get_drvdata(dev);
5489 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5490 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5491 struct e1000_hw *hw = &adapter->hw;
5492 unsigned long event = *(unsigned long *)data;
5493
5494 switch (event) {
5495 case DCA_PROVIDER_ADD:
5496 /* if already enabled, don't do it again */
7dfc16fa 5497 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5498 break;
fe4506b6 5499 if (dca_add_requester(dev) == 0) {
bbd98fe4 5500 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5501 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5502 igb_setup_dca(adapter);
5503 break;
5504 }
5505 /* Fall Through since DCA is disabled. */
5506 case DCA_PROVIDER_REMOVE:
7dfc16fa 5507 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5508 /* without this a class_device is left
b980ac18
JK		 5509 * hanging around in the sysfs model
5510 */
fe4506b6 5511 dca_remove_requester(dev);
090b1795 5512 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5513 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5514 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5515 }
5516 break;
5517 }
bbd98fe4 5518
fe4506b6 5519 return 0;
9d5c8243
AK		 5520}
5521
fe4506b6 5522static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5523 void *p)
fe4506b6
JC		 5524{
5525 int ret_val;
5526
5527 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5528 __igb_notify_dca);
fe4506b6
JC		 5529
5530 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5531}
421e02f0 5532#endif /* CONFIG_IGB_DCA */
9d5c8243 5533
0224d663
GR		 5534#ifdef CONFIG_PCI_IOV
5535static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5536{
5537 unsigned char mac_addr[ETH_ALEN];
0224d663 5538
5ac6f91d 5539 eth_zero_addr(mac_addr);
0224d663
GR		 5540 igb_set_vf_mac(adapter, vf, mac_addr);
5541
70ea4783
LL		 5542 /* By default spoof check is enabled for all VFs */
5543 adapter->vf_data[vf].spoofchk_enabled = true;
5544
f557147c 5545 return 0;
0224d663
GR		 5546}
5547
0224d663 5548#endif
4ae196df
AD		 5549static void igb_ping_all_vfs(struct igb_adapter *adapter)
5550{
5551 struct e1000_hw *hw = &adapter->hw;
5552 u32 ping;
5553 int i;
5554
5555 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5556 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5557 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5558 ping |= E1000_VT_MSGTYPE_CTS;
5559 igb_write_mbx(hw, &ping, 1, i);
5560 }
5561}
5562
7d5753f0
AD		 5563static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5564{
5565 struct e1000_hw *hw = &adapter->hw;
5566 u32 vmolr = rd32(E1000_VMOLR(vf));
5567 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5568
d85b9004 5569 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5570 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5571 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5572
5573 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5574 vmolr |= E1000_VMOLR_MPME;
d85b9004 5575 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5576 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5577 } else {
b980ac18 5578 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5579 * flag we need to write the hashes to the MTA as this step
5580 * was previously skipped
5581 */
5582 if (vf_data->num_vf_mc_hashes > 30) {
5583 vmolr |= E1000_VMOLR_MPME;
5584 } else if (vf_data->num_vf_mc_hashes) {
5585 int j;
5586 vmolr |= E1000_VMOLR_ROMPE;
5587 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5588 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5589 }
5590 }
5591
5592 wr32(E1000_VMOLR(vf), vmolr);
5593
5594 /* there are flags left unprocessed, likely not supported */
5595 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5596 return -EINVAL;
5597
5598 return 0;
7d5753f0
AD		 5599}
5600
4ae196df
AD		 5601static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5602 u32 *msgbuf, u32 vf)
5603{
5604 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5605 u16 *hash_list = (u16 *)&msgbuf[1];
5606 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5607 int i;
5608
7d5753f0 5609 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5610 * to this VF for later use to restore when the PF multi cast
5611 * list changes
5612 */
5613 vf_data->num_vf_mc_hashes = n;
5614
7d5753f0
AD		 5615 /* only up to 30 hash values supported */
5616 if (n > 30)
5617 n = 30;
5618
5619 /* store the hashes for later use */
4ae196df 5620 for (i = 0; i < n; i++)
a419aef8 5621 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5622
5623 /* Flush and reset the mta with the new values */
ff41f8dc 5624 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5625
5626 return 0;
5627}
5628
5629static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5630{
5631 struct e1000_hw *hw = &adapter->hw;
5632 struct vf_data_storage *vf_data;
5633 int i, j;
5634
5635 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5636 u32 vmolr = rd32(E1000_VMOLR(i));
5637 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5638
4ae196df 5639 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5640
5641 if ((vf_data->num_vf_mc_hashes > 30) ||
5642 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5643 vmolr |= E1000_VMOLR_MPME;
5644 } else if (vf_data->num_vf_mc_hashes) {
5645 vmolr |= E1000_VMOLR_ROMPE;
5646 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5647 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5648 }
5649 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5650 }
5651}
5652
5653static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5654{
5655 struct e1000_hw *hw = &adapter->hw;
5656 u32 pool_mask, reg, vid;
5657 int i;
5658
5659 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5660
5661 /* Find the vlan filter for this id */
5662 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5663 reg = rd32(E1000_VLVF(i));
5664
5665 /* remove the vf from the pool */
5666 reg &= ~pool_mask;
5667
5668 /* if pool is empty then remove entry from vfta */
5669 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5670 (reg & E1000_VLVF_VLANID_ENABLE)) {
5671 reg = 0;
5672 vid = reg & E1000_VLVF_VLANID_MASK;
5673 igb_vfta_set(hw, vid, false);
5674 }
5675
5676 wr32(E1000_VLVF(i), reg);
5677 }
ae641bdc
AD		 5678
5679 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5680}
5681
5682static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5683{
5684 struct e1000_hw *hw = &adapter->hw;
5685 u32 reg, i;
5686
51466239
AD		 5687 /* The vlvf table only exists on 82576 hardware and newer */
5688 if (hw->mac.type < e1000_82576)
5689 return -1;
5690
5691 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5692 if (!adapter->vfs_allocated_count)
5693 return -1;
5694
5695 /* Find the vlan filter for this id */
5696 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5697 reg = rd32(E1000_VLVF(i));
5698 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5699 vid == (reg & E1000_VLVF_VLANID_MASK))
5700 break;
5701 }
5702
5703 if (add) {
5704 if (i == E1000_VLVF_ARRAY_SIZE) {
5705 /* Did not find a matching VLAN ID entry that was
5706 * enabled. Search for a free filter entry, i.e.
5707 * one without the enable bit set
5708 */
5709 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5710 reg = rd32(E1000_VLVF(i));
5711 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5712 break;
5713 }
5714 }
5715 if (i < E1000_VLVF_ARRAY_SIZE) {
5716 /* Found an enabled/available entry */
5717 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5718
5719 /* if !enabled we need to set this up in vfta */
5720 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5721 /* add VID to filter table */
5722 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5723 reg |= E1000_VLVF_VLANID_ENABLE;
5724 }
cad6d05f
AD		 5725 reg &= ~E1000_VLVF_VLANID_MASK;
5726 reg |= vid;
4ae196df 5727 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5728
5729 /* do not modify RLPML for PF devices */
5730 if (vf >= adapter->vfs_allocated_count)
5731 return 0;
5732
5733 if (!adapter->vf_data[vf].vlans_enabled) {
5734 u32 size;
5735 reg = rd32(E1000_VMOLR(vf));
5736 size = reg & E1000_VMOLR_RLPML_MASK;
5737 size += 4;
5738 reg &= ~E1000_VMOLR_RLPML_MASK;
5739 reg |= size;
5740 wr32(E1000_VMOLR(vf), reg);
5741 }
ae641bdc 5742
51466239 5743 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5744 }
5745 } else {
5746 if (i < E1000_VLVF_ARRAY_SIZE) {
5747 /* remove vf from the pool */
5748 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5749 /* if pool is empty then remove entry from vfta */
5750 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5751 reg = 0;
5752 igb_vfta_set(hw, vid, false);
5753 }
5754 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5755
5756 /* do not modify RLPML for PF devices */
5757 if (vf >= adapter->vfs_allocated_count)
5758 return 0;
5759
5760 adapter->vf_data[vf].vlans_enabled--;
5761 if (!adapter->vf_data[vf].vlans_enabled) {
5762 u32 size;
5763 reg = rd32(E1000_VMOLR(vf));
5764 size = reg & E1000_VMOLR_RLPML_MASK;
5765 size -= 4;
5766 reg &= ~E1000_VMOLR_RLPML_MASK;
5767 reg |= size;
5768 wr32(E1000_VMOLR(vf), reg);
5769 }
4ae196df
AD		 5770 }
5771 }
8151d294
WM		 5772 return 0;
5773}
5774
5775static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5776{
5777 struct e1000_hw *hw = &adapter->hw;
5778
5779 if (vid)
5780 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5781 else
5782 wr32(E1000_VMVIR(vf), 0);
5783}
5784
5785static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5786 int vf, u16 vlan, u8 qos)
5787{
5788 int err = 0;
5789 struct igb_adapter *adapter = netdev_priv(netdev);
5790
5791 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5792 return -EINVAL;
5793 if (vlan || qos) {
5794 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5795 if (err)
5796 goto out;
5797 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5798 igb_set_vmolr(adapter, vf, !vlan);
5799 adapter->vf_data[vf].pf_vlan = vlan;
5800 adapter->vf_data[vf].pf_qos = qos;
5801 dev_info(&adapter->pdev->dev,
5802 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5803 if (test_bit(__IGB_DOWN, &adapter->state)) {
5804 dev_warn(&adapter->pdev->dev,
b980ac18 5805 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5806 dev_warn(&adapter->pdev->dev,
b980ac18 5807 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5808 }
5809 } else {
5810 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5811 false, vf);
8151d294
WM		 5812 igb_set_vmvir(adapter, vlan, vf);
5813 igb_set_vmolr(adapter, vf, true);
5814 adapter->vf_data[vf].pf_vlan = 0;
5815 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5816 }
8151d294 5817out:
b980ac18 5818 return err;
4ae196df
AD		 5819}
5820
6f3dc319
GR		 5821static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5822{
5823 struct e1000_hw *hw = &adapter->hw;
5824 int i;
5825 u32 reg;
5826
5827 /* Find the vlan filter for this id */
5828 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5829 reg = rd32(E1000_VLVF(i));
5830 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5831 vid == (reg & E1000_VLVF_VLANID_MASK))
5832 break;
5833 }
5834
5835 if (i >= E1000_VLVF_ARRAY_SIZE)
5836 i = -1;
5837
5838 return i;
5839}
5840
4ae196df
AD		 5841static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5842{
6f3dc319 5843 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5844 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5845 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5846 int err = 0;
4ae196df 5847
6f3dc319
GR		 5848 /* If in promiscuous mode we need to make sure the PF also has
5849 * the VLAN filter set.
5850 */
5851 if (add && (adapter->netdev->flags & IFF_PROMISC))
5852 err = igb_vlvf_set(adapter, vid, add,
5853 adapter->vfs_allocated_count);
5854 if (err)
5855 goto out;
5856
5857 err = igb_vlvf_set(adapter, vid, add, vf);
5858
5859 if (err)
5860 goto out;
5861
5862 /* Go through all the checks to see if the VLAN filter should
5863 * be wiped completely.
5864 */
5865 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5866 u32 vlvf, bits;
5867
5868 int regndx = igb_find_vlvf_entry(adapter, vid);
5869 if (regndx < 0)
5870 goto out;
5871 /* See if any other pools are set for this VLAN filter
5872 * entry other than the PF.
5873 */
5874 vlvf = bits = rd32(E1000_VLVF(regndx));
5875 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5876 adapter->vfs_allocated_count);
5877 /* If the filter was removed then ensure PF pool bit
5878 * is cleared if the PF only added itself to the pool
5879 * because the PF is in promiscuous mode.
5880 */
5881 if ((vlvf & VLAN_VID_MASK) == vid &&
5882 !test_bit(vid, adapter->active_vlans) &&
5883 !bits)
5884 igb_vlvf_set(adapter, vid, add,
5885 adapter->vfs_allocated_count);
5886 }
5887
5888out:
5889 return err;
4ae196df
AD		 5890}
5891
f2ca0dbe 5892static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5893{
8fa7e0f7
GR		 5894 /* clear flags - except flag that indicates PF has set the MAC */
5895 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5896 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5897
5898 /* reset offloads to defaults */
8151d294 5899 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5900
5901 /* reset vlans for device */
5902 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5903 if (adapter->vf_data[vf].pf_vlan)
5904 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5905 adapter->vf_data[vf].pf_vlan,
5906 adapter->vf_data[vf].pf_qos);
5907 else
5908 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5909
5910 /* reset multicast table array for vf */
5911 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5912
5913 /* Flush and reset the mta with the new values */
ff41f8dc 5914 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5915}
5916
f2ca0dbe
AD		 5917static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5918{
5919 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5920
5ac6f91d 5921 /* clear mac address as we were hotplug removed/added */
8151d294 5922 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5923 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5924
5925 /* process remaining reset events */
5926 igb_vf_reset(adapter, vf);
5927}
5928
5929static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5930{
5931 struct e1000_hw *hw = &adapter->hw;
5932 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5933 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5934 u32 reg, msgbuf[3];
5935 u8 *addr = (u8 *)(&msgbuf[1]);
5936
5937 /* process all the same items cleared in a function level reset */
f2ca0dbe 5938 igb_vf_reset(adapter, vf);
4ae196df
AD		 5939
5940 /* set vf mac address */
26ad9178 5941 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5942
5943 /* enable transmit and receive for vf */
5944 reg = rd32(E1000_VFTE);
5945 wr32(E1000_VFTE, reg | (1 << vf));
5946 reg = rd32(E1000_VFRE);
5947 wr32(E1000_VFRE, reg | (1 << vf));
5948
8fa7e0f7 5949 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5950
5951 /* reply to reset with ack and vf mac address */
5952 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 5953 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 5954 igb_write_mbx(hw, msgbuf, 3, vf);
5955}
5956
5957static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5958{
b980ac18 5959 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5960 * starting at the second 32 bit word of the msg array
5961 */
f2ca0dbe
AD		 5962 unsigned char *addr = (char *)&msg[1];
5963 int err = -1;
4ae196df 5964
f2ca0dbe
AD		 5965 if (is_valid_ether_addr(addr))
5966 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5967
f2ca0dbe 5968 return err;
4ae196df
AD		 5969}
5970
5971static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5972{
5973 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5974 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5975 u32 msg = E1000_VT_MSGTYPE_NACK;
5976
5977 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5978 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5979 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5980 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5981 vf_data->last_nack = jiffies;
4ae196df
AD		 5982 }
5983}
5984
f2ca0dbe 5985static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5986{
f2ca0dbe
AD		 5987 struct pci_dev *pdev = adapter->pdev;
5988 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5989 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5990 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5991 s32 retval;
5992
f2ca0dbe 5993 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5994
fef45f4c
AD		 5995 if (retval) {
5996 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5997 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5998 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5999 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6000 return;
6001 goto out;
6002 }
4ae196df
AD		 6003
6004 /* this is a message we already processed, do nothing */
6005 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6006 return;
4ae196df 6007
b980ac18 6008 /* until the vf completes a reset it should not be
4ae196df
AD		 6009 * allowed to start any configuration.
6010 */
4ae196df
AD		 6011 if (msgbuf[0] == E1000_VF_RESET) {
6012 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6013 return;
4ae196df
AD		 6014 }
6015
f2ca0dbe 6016 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6017 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6018 return;
6019 retval = -1;
6020 goto out;
4ae196df
AD		 6021 }
6022
6023 switch ((msgbuf[0] & 0xFFFF)) {
6024 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6025 retval = -EINVAL;
6026 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6027 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6028 else
6029 dev_warn(&pdev->dev,
b980ac18
JK		 6030 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6031 vf);
4ae196df 6032 break;
7d5753f0
AD		 6033 case E1000_VF_SET_PROMISC:
6034 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6035 break;
4ae196df
AD		 6036 case E1000_VF_SET_MULTICAST:
6037 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6038 break;
6039 case E1000_VF_SET_LPE:
6040 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6041 break;
6042 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6043 retval = -1;
6044 if (vf_data->pf_vlan)
6045 dev_warn(&pdev->dev,
b980ac18
JK		 6046 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6047 vf);
8151d294
WM		 6048 else
6049 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6050 break;
6051 default:
090b1795 6052 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6053 retval = -1;
6054 break;
6055 }
6056
fef45f4c
AD		 6057 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6058out:
4ae196df
AD		 6059 /* notify the VF of the results of what it sent us */
6060 if (retval)
6061 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6062 else
6063 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6064
4ae196df 6065 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6066}
4ae196df 6067
f2ca0dbe
AD		 6068static void igb_msg_task(struct igb_adapter *adapter)
6069{
6070 struct e1000_hw *hw = &adapter->hw;
6071 u32 vf;
6072
6073 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6074 /* process any reset requests */
6075 if (!igb_check_for_rst(hw, vf))
6076 igb_vf_reset_event(adapter, vf);
6077
6078 /* process any messages pending */
6079 if (!igb_check_for_msg(hw, vf))
6080 igb_rcv_msg_from_vf(adapter, vf);
6081
6082 /* process any acks */
6083 if (!igb_check_for_ack(hw, vf))
6084 igb_rcv_ack_from_vf(adapter, vf);
6085 }
4ae196df
AD		 6086}
6087
68d480c4
AD		 6088/**
6089 * igb_set_uta - Set unicast filter table address
6090 * @adapter: board private structure
6091 *
6092 * The unicast table address is a register array of 32-bit registers.
6093 * The table is meant to be used in a way similar to how the MTA is used
6094 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6095 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6096 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6097 **/
6098static void igb_set_uta(struct igb_adapter *adapter)
6099{
6100 struct e1000_hw *hw = &adapter->hw;
6101 int i;
6102
6103 /* The UTA table only exists on 82576 hardware and newer */
6104 if (hw->mac.type < e1000_82576)
6105 return;
6106
6107 /* we only need to do this if VMDq is enabled */
6108 if (!adapter->vfs_allocated_count)
6109 return;
6110
6111 for (i = 0; i < hw->mac.uta_reg_count; i++)
6112 array_wr32(E1000_UTA, i, ~0);
6113}
6114
9d5c8243 6115/**
b980ac18
JK		 6116 * igb_intr_msi - Interrupt Handler
6117 * @irq: interrupt number
6118 * @data: pointer to a network interface device structure
9d5c8243
AK		 6119 **/
6120static irqreturn_t igb_intr_msi(int irq, void *data)
6121{
047e0030
AD		 6122 struct igb_adapter *adapter = data;
6123 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6124 struct e1000_hw *hw = &adapter->hw;
6125 /* read ICR disables interrupts using IAM */
6126 u32 icr = rd32(E1000_ICR);
6127
047e0030 6128 igb_write_itr(q_vector);
9d5c8243 6129
7f081d40
AD		 6130 if (icr & E1000_ICR_DRSTA)
6131 schedule_work(&adapter->reset_task);
6132
047e0030 6133 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6134 /* HW is reporting DMA is out of sync */
6135 adapter->stats.doosync++;
6136 }
6137
9d5c8243
AK		 6138 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6139 hw->mac.get_link_status = 1;
6140 if (!test_bit(__IGB_DOWN, &adapter->state))
6141 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6142 }
6143
1f6e8178
MV		 6144 if (icr & E1000_ICR_TS) {
6145 u32 tsicr = rd32(E1000_TSICR);
6146
6147 if (tsicr & E1000_TSICR_TXTS) {
6148 /* acknowledge the interrupt */
6149 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6150 /* retrieve hardware timestamp */
6151 schedule_work(&adapter->ptp_tx_work);
6152 }
6153 }
1f6e8178 6154
047e0030 6155 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6156
6157 return IRQ_HANDLED;
6158}
6159
6160/**
b980ac18
JK		 6161 * igb_intr - Legacy Interrupt Handler
6162 * @irq: interrupt number
6163 * @data: pointer to a network interface device structure
9d5c8243
AK		 6164 **/
6165static irqreturn_t igb_intr(int irq, void *data)
6166{
047e0030
AD		 6167 struct igb_adapter *adapter = data;
6168 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6169 struct e1000_hw *hw = &adapter->hw;
6170 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6171 * need for the IMC write
6172 */
9d5c8243 6173 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6174
6175 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6176 * not set, then the adapter didn't send an interrupt
6177 */
9d5c8243
AK		 6178 if (!(icr & E1000_ICR_INT_ASSERTED))
6179 return IRQ_NONE;
6180
0ba82994
AD		 6181 igb_write_itr(q_vector);
6182
7f081d40
AD		 6183 if (icr & E1000_ICR_DRSTA)
6184 schedule_work(&adapter->reset_task);
6185
047e0030 6186 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6187 /* HW is reporting DMA is out of sync */
6188 adapter->stats.doosync++;
6189 }
6190
9d5c8243
AK		 6191 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6192 hw->mac.get_link_status = 1;
6193 /* guard against interrupt when we're going down */
6194 if (!test_bit(__IGB_DOWN, &adapter->state))
6195 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6196 }
6197
1f6e8178
MV		 6198 if (icr & E1000_ICR_TS) {
6199 u32 tsicr = rd32(E1000_TSICR);
6200
6201 if (tsicr & E1000_TSICR_TXTS) {
6202 /* acknowledge the interrupt */
6203 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6204 /* retrieve hardware timestamp */
6205 schedule_work(&adapter->ptp_tx_work);
6206 }
6207 }
1f6e8178 6208
047e0030 6209 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6210
6211 return IRQ_HANDLED;
6212}
6213
c50b52a0 6214static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6215{
047e0030 6216 struct igb_adapter *adapter = q_vector->adapter;
46544258 6217 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6218
0ba82994
AD		 6219 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6220 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6221 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6222 igb_set_itr(q_vector);
46544258 6223 else
047e0030 6224 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6225 }
6226
46544258 6227 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6228 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6229 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6230 else
6231 igb_irq_enable(adapter);
6232 }
9d5c8243
AK		 6233}
6234
46544258 6235/**
b980ac18
JK		 6236 * igb_poll - NAPI Rx polling callback
6237 * @napi: napi polling structure
6238 * @budget: count of how many packets we should handle
46544258
AD		 6239 **/
6240static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6241{
047e0030 6242 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6243 struct igb_q_vector,
6244 napi);
16eb8815 6245 bool clean_complete = true;
9d5c8243 6246
421e02f0 6247#ifdef CONFIG_IGB_DCA
047e0030
AD		 6248 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6249 igb_update_dca(q_vector);
fe4506b6 6250#endif
0ba82994 6251 if (q_vector->tx.ring)
13fde97a 6252 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6253
0ba82994 6254 if (q_vector->rx.ring)
cd392f5c 6255 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6256
16eb8815
AD		 6257 /* If all work not completed, return budget and keep polling */
6258 if (!clean_complete)
6259 return budget;
46544258 6260
9d5c8243 6261 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6262 napi_complete(napi);
6263 igb_ring_irq_enable(q_vector);
9d5c8243 6264
16eb8815 6265 return 0;
9d5c8243 6266}
6d8126f9 6267
9d5c8243 6268/**
b980ac18
JK		 6269 * igb_clean_tx_irq - Reclaim resources after transmit completes
6270 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6271 *
b980ac18 6272 * returns true if ring is completely cleaned
9d5c8243 6273 **/
047e0030 6274static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6275{
047e0030 6276 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6277 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6278 struct igb_tx_buffer *tx_buffer;
f4128785 6279 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6280 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6281 unsigned int budget = q_vector->tx.work_limit;
8542db05 6282 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6283
13fde97a
AD		 6284 if (test_bit(__IGB_DOWN, &adapter->state))
6285 return true;
0e014cb1 6286
06034649 6287 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6288 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6289 i -= tx_ring->count;
9d5c8243 6290
f4128785
AD		 6291 do {
6292 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6293
6294 /* if next_to_watch is not set then there is no work pending */
6295 if (!eop_desc)
6296 break;
13fde97a 6297
f4128785 6298 /* prevent any other reads prior to eop_desc */
70d289bc 6299 read_barrier_depends();
f4128785 6300
13fde97a
AD		 6301 /* if DD is not set pending work has not been completed */
6302 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6303 break;
6304
8542db05
AD		 6305 /* clear next_to_watch to prevent false hangs */
6306 tx_buffer->next_to_watch = NULL;
9d5c8243 6307
ebe42d16
AD		 6308 /* update the statistics for this packet */
6309 total_bytes += tx_buffer->bytecount;
6310 total_packets += tx_buffer->gso_segs;
13fde97a 6311
ebe42d16
AD		 6312 /* free the skb */
6313 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6314
ebe42d16
AD		 6315 /* unmap skb header data */
6316 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6317 dma_unmap_addr(tx_buffer, dma),
6318 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6319 DMA_TO_DEVICE);
6320
c9f14bf3
AD		 6321 /* clear tx_buffer data */
6322 tx_buffer->skb = NULL;
6323 dma_unmap_len_set(tx_buffer, len, 0);
6324
ebe42d16
AD		 6325 /* clear last DMA location and unmap remaining buffers */
6326 while (tx_desc != eop_desc) {
13fde97a
AD		 6327 tx_buffer++;
6328 tx_desc++;
9d5c8243 6329 i++;
8542db05
AD		 6330 if (unlikely(!i)) {
6331 i -= tx_ring->count;
06034649 6332 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6333 tx_desc = IGB_TX_DESC(tx_ring, 0);
6334 }
ebe42d16
AD		 6335
6336 /* unmap any remaining paged data */
c9f14bf3 6337 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6338 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6339 dma_unmap_addr(tx_buffer, dma),
6340 dma_unmap_len(tx_buffer, len),
ebe42d16 6341 DMA_TO_DEVICE);
c9f14bf3 6342 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6343 }
6344 }
6345
ebe42d16
AD		 6346 /* move us one more past the eop_desc for start of next pkt */
6347 tx_buffer++;
6348 tx_desc++;
6349 i++;
6350 if (unlikely(!i)) {
6351 i -= tx_ring->count;
6352 tx_buffer = tx_ring->tx_buffer_info;
6353 tx_desc = IGB_TX_DESC(tx_ring, 0);
6354 }
f4128785
AD		 6355
6356 /* issue prefetch for next Tx descriptor */
6357 prefetch(tx_desc);
6358
6359 /* update budget accounting */
6360 budget--;
6361 } while (likely(budget));
0e014cb1 6362
bdbc0631
ED		 6363 netdev_tx_completed_queue(txring_txq(tx_ring),
6364 total_packets, total_bytes);
8542db05 6365 i += tx_ring->count;
9d5c8243 6366 tx_ring->next_to_clean = i;
13fde97a
AD		 6367 u64_stats_update_begin(&tx_ring->tx_syncp);
6368 tx_ring->tx_stats.bytes += total_bytes;
6369 tx_ring->tx_stats.packets += total_packets;
6370 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6371 q_vector->tx.total_bytes += total_bytes;
6372 q_vector->tx.total_packets += total_packets;
9d5c8243 6373
6d095fa8 6374 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6375 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6376
9d5c8243 6377 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6378 * check with the clearing of time_stamp and movement of i
6379 */
6d095fa8 6380 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6381 if (tx_buffer->next_to_watch &&
8542db05 6382 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6383 (adapter->tx_timeout_factor * HZ)) &&
6384 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6385
9d5c8243 6386 /* detected Tx unit hang */
59d71989 6387 dev_err(tx_ring->dev,
9d5c8243 6388 "Detected Tx Unit Hang\n"
2d064c06 6389 " Tx Queue <%d>\n"
9d5c8243
AK		 6390 " TDH <%x>\n"
6391 " TDT <%x>\n"
6392 " next_to_use <%x>\n"
6393 " next_to_clean <%x>\n"
9d5c8243
AK		 6394 "buffer_info[next_to_clean]\n"
6395 " time_stamp <%lx>\n"
8542db05 6396 " next_to_watch <%p>\n"
9d5c8243
AK		 6397 " jiffies <%lx>\n"
6398 " desc.status <%x>\n",
2d064c06 6399 tx_ring->queue_index,
238ac817 6400 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6401 readl(tx_ring->tail),
9d5c8243
AK		 6402 tx_ring->next_to_use,
6403 tx_ring->next_to_clean,
8542db05 6404 tx_buffer->time_stamp,
f4128785 6405 tx_buffer->next_to_watch,
9d5c8243 6406 jiffies,
f4128785 6407 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6408 netif_stop_subqueue(tx_ring->netdev,
6409 tx_ring->queue_index);
6410
6411 /* we are about to reset, no point in enabling stuff */
6412 return true;
9d5c8243
AK		 6413 }
6414 }
13fde97a 6415
21ba6fe1 6416#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6417 if (unlikely(total_packets &&
b980ac18
JK		 6418 netif_carrier_ok(tx_ring->netdev) &&
6419 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6420 /* Make sure that anybody stopping the queue after this
6421 * sees the new next_to_clean.
6422 */
6423 smp_mb();
6424 if (__netif_subqueue_stopped(tx_ring->netdev,
6425 tx_ring->queue_index) &&
6426 !(test_bit(__IGB_DOWN, &adapter->state))) {
6427 netif_wake_subqueue(tx_ring->netdev,
6428 tx_ring->queue_index);
6429
6430 u64_stats_update_begin(&tx_ring->tx_syncp);
6431 tx_ring->tx_stats.restart_queue++;
6432 u64_stats_update_end(&tx_ring->tx_syncp);
6433 }
6434 }
6435
6436 return !!budget;
9d5c8243
AK		 6437}
6438
cbc8e55f 6439/**
b980ac18
JK		 6440 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6441 * @rx_ring: rx descriptor ring to store buffers on
6442 * @old_buff: donor buffer to have page reused
cbc8e55f 6443 *
b980ac18 6444 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6445 **/
6446static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6447 struct igb_rx_buffer *old_buff)
6448{
6449 struct igb_rx_buffer *new_buff;
6450 u16 nta = rx_ring->next_to_alloc;
6451
6452 new_buff = &rx_ring->rx_buffer_info[nta];
6453
6454 /* update, and store next to alloc */
6455 nta++;
6456 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6457
6458 /* transfer page from old buffer to new buffer */
6459 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6460
6461 /* sync the buffer for use by the device */
6462 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6463 old_buff->page_offset,
de78d1f9 6464 IGB_RX_BUFSZ,
cbc8e55f
AD		 6465 DMA_FROM_DEVICE);
6466}
6467
74e238ea
AD		 6468static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6469 struct page *page,
6470 unsigned int truesize)
6471{
6472 /* avoid re-using remote pages */
6473 if (unlikely(page_to_nid(page) != numa_node_id()))
6474 return false;
6475
6476#if (PAGE_SIZE < 8192)
6477 /* if we are only owner of page we can reuse it */
6478 if (unlikely(page_count(page) != 1))
6479 return false;
6480
6481 /* flip page offset to other buffer */
6482 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6483
6484 /* since we are the only owner of the page and we need to
6485 * increment it, just set the value to 2 in order to avoid
6486 * an unnecessary locked operation
6487 */
6488 atomic_set(&page->_count, 2);
6489#else
6490 /* move offset up to the next cache line */
6491 rx_buffer->page_offset += truesize;
6492
6493 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6494 return false;
6495
6496 /* bump ref count on page before it is given to the stack */
6497 get_page(page);
6498#endif
6499
6500 return true;
6501}
6502
cbc8e55f 6503/**
b980ac18
JK		 6504 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6505 * @rx_ring: rx descriptor ring to transact packets on
6506 * @rx_buffer: buffer containing page to add
6507 * @rx_desc: descriptor containing length of buffer written by hardware
6508 * @skb: sk_buff to place the data into
cbc8e55f 6509 *
b980ac18
JK		 6510 * This function will add the data contained in rx_buffer->page to the skb.
6511 * This is done either through a direct copy if the data in the buffer is
6512 * less than the skb header size, otherwise it will just attach the page as
6513 * a frag to the skb.
cbc8e55f 6514 *
b980ac18
JK		 6515 * The function will then update the page offset if necessary and return
6516 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6517 **/
6518static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6519 struct igb_rx_buffer *rx_buffer,
6520 union e1000_adv_rx_desc *rx_desc,
6521 struct sk_buff *skb)
6522{
6523 struct page *page = rx_buffer->page;
6524 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6525#if (PAGE_SIZE < 8192)
6526 unsigned int truesize = IGB_RX_BUFSZ;
6527#else
6528 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6529#endif
cbc8e55f
AD		 6530
6531 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6532 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6533
cbc8e55f
AD		 6534 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6535 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6536 va += IGB_TS_HDR_LEN;
6537 size -= IGB_TS_HDR_LEN;
6538 }
6539
cbc8e55f
AD		 6540 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6541
6542 /* we can reuse buffer as-is, just make sure it is local */
6543 if (likely(page_to_nid(page) == numa_node_id()))
6544 return true;
6545
6546 /* this page cannot be reused so discard it */
6547 put_page(page);
6548 return false;
6549 }
6550
6551 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6552 rx_buffer->page_offset, size, truesize);
cbc8e55f 6553
74e238ea
AD		 6554 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6555}
cbc8e55f 6556
2e334eee
AD		 6557static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6558 union e1000_adv_rx_desc *rx_desc,
6559 struct sk_buff *skb)
6560{
6561 struct igb_rx_buffer *rx_buffer;
6562 struct page *page;
6563
6564 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6565
2e334eee
AD		 6566 page = rx_buffer->page;
6567 prefetchw(page);
6568
6569 if (likely(!skb)) {
6570 void *page_addr = page_address(page) +
6571 rx_buffer->page_offset;
6572
6573 /* prefetch first cache line of first page */
6574 prefetch(page_addr);
6575#if L1_CACHE_BYTES < 128
6576 prefetch(page_addr + L1_CACHE_BYTES);
6577#endif
6578
6579 /* allocate a skb to store the frags */
6580 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6581 IGB_RX_HDR_LEN);
6582 if (unlikely(!skb)) {
6583 rx_ring->rx_stats.alloc_failed++;
6584 return NULL;
6585 }
6586
b980ac18 6587 /* we will be copying header into skb->data in
2e334eee
AD		 6588 * pskb_may_pull so it is in our interest to prefetch
6589 * it now to avoid a possible cache miss
6590 */
6591 prefetchw(skb->data);
6592 }
6593
6594 /* we are reusing so sync this buffer for CPU use */
6595 dma_sync_single_range_for_cpu(rx_ring->dev,
6596 rx_buffer->dma,
6597 rx_buffer->page_offset,
de78d1f9 6598 IGB_RX_BUFSZ,
2e334eee
AD		 6599 DMA_FROM_DEVICE);
6600
6601 /* pull page into skb */
6602 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6603 /* hand second half of page back to the ring */
6604 igb_reuse_rx_page(rx_ring, rx_buffer);
6605 } else {
6606 /* we are not reusing the buffer so unmap it */
6607 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6608 PAGE_SIZE, DMA_FROM_DEVICE);
6609 }
6610
6611 /* clear contents of rx_buffer */
6612 rx_buffer->page = NULL;
6613
6614 return skb;
6615}
6616
cd392f5c 6617static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6618 union e1000_adv_rx_desc *rx_desc,
6619 struct sk_buff *skb)
9d5c8243 6620{
bc8acf2c 6621 skb_checksum_none_assert(skb);
9d5c8243 6622
294e7d78 6623 /* Ignore Checksum bit is set */
3ceb90fd 6624 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6625 return;
6626
6627 /* Rx checksum disabled via ethtool */
6628 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6629 return;
85ad76b2 6630
9d5c8243 6631 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6632 if (igb_test_staterr(rx_desc,
6633 E1000_RXDEXT_STATERR_TCPE |
6634 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6635 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6636 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6637 * packets, (aka let the stack check the crc32c)
6638 */
866cff06
AD		 6639 if (!((skb->len == 60) &&
6640 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6641 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6642 ring->rx_stats.csum_err++;
12dcd86b
ED		 6643 u64_stats_update_end(&ring->rx_syncp);
6644 }
9d5c8243 6645 /* let the stack verify checksum errors */
9d5c8243
AK		 6646 return;
6647 }
6648 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6649 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6650 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6651 skb->ip_summed = CHECKSUM_UNNECESSARY;
6652
3ceb90fd
AD		 6653 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6654 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6655}
6656
077887c3
AD		 6657static inline void igb_rx_hash(struct igb_ring *ring,
6658 union e1000_adv_rx_desc *rx_desc,
6659 struct sk_buff *skb)
6660{
6661 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6662 skb_set_hash(skb,
6663 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6664 PKT_HASH_TYPE_L3);
077887c3
AD		 6665}
6666
2e334eee 6667/**
b980ac18
JK		 6668 * igb_is_non_eop - process handling of non-EOP buffers
6669 * @rx_ring: Rx ring being processed
6670 * @rx_desc: Rx descriptor for current buffer
6671 * @skb: current socket buffer containing buffer in progress
2e334eee 6672 *
b980ac18
JK		 6673 * This function updates next to clean. If the buffer is an EOP buffer
6674 * this function exits returning false, otherwise it will place the
6675 * sk_buff in the next buffer to be chained and return true indicating
6676 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6677 **/
6678static bool igb_is_non_eop(struct igb_ring *rx_ring,
6679 union e1000_adv_rx_desc *rx_desc)
6680{
6681 u32 ntc = rx_ring->next_to_clean + 1;
6682
6683 /* fetch, update, and store next to clean */
6684 ntc = (ntc < rx_ring->count) ? ntc : 0;
6685 rx_ring->next_to_clean = ntc;
6686
6687 prefetch(IGB_RX_DESC(rx_ring, ntc));
6688
6689 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6690 return false;
6691
6692 return true;
6693}
6694
1a1c225b 6695/**
b980ac18
JK		 6696 * igb_get_headlen - determine size of header for LRO/GRO
6697 * @data: pointer to the start of the headers
6698 * @max_len: total length of section to find headers in
1a1c225b 6699 *
b980ac18
JK		 6700 * This function is meant to determine the length of headers that will
6701 * be recognized by hardware for LRO, and GRO offloads. The main
6702 * motivation of doing this is to only perform one pull for IPv4 TCP
6703 * packets so that we can do basic things like calculating the gso_size
6704 * based on the average data per packet.
1a1c225b
AD		 6705 **/
6706static unsigned int igb_get_headlen(unsigned char *data,
6707 unsigned int max_len)
6708{
6709 union {
6710 unsigned char *network;
6711 /* l2 headers */
6712 struct ethhdr *eth;
6713 struct vlan_hdr *vlan;
6714 /* l3 headers */
6715 struct iphdr *ipv4;
6716 struct ipv6hdr *ipv6;
6717 } hdr;
6718 __be16 protocol;
6719 u8 nexthdr = 0; /* default to not TCP */
6720 u8 hlen;
6721
6722 /* this should never happen, but better safe than sorry */
6723 if (max_len < ETH_HLEN)
6724 return max_len;
6725
6726 /* initialize network frame pointer */
6727 hdr.network = data;
6728
6729 /* set first protocol and move network header forward */
6730 protocol = hdr.eth->h_proto;
6731 hdr.network += ETH_HLEN;
6732
6733 /* handle any vlan tag if present */
6734 if (protocol == __constant_htons(ETH_P_8021Q)) {
6735 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6736 return max_len;
6737
6738 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6739 hdr.network += VLAN_HLEN;
6740 }
6741
6742 /* handle L3 protocols */
6743 if (protocol == __constant_htons(ETH_P_IP)) {
6744 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6745 return max_len;
6746
6747 /* access ihl as a u8 to avoid unaligned access on ia64 */
6748 hlen = (hdr.network[0] & 0x0F) << 2;
6749
6750 /* verify hlen meets minimum size requirements */
6751 if (hlen < sizeof(struct iphdr))
6752 return hdr.network - data;
6753
f2fb4ab2 6754 /* record next protocol if header is present */
b9555f66 6755 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6756 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6757 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6758 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6759 return max_len;
6760
6761 /* record next protocol */
6762 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6763 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6764 } else {
6765 return hdr.network - data;
6766 }
6767
f2fb4ab2
AD		 6768 /* relocate pointer to start of L4 header */
6769 hdr.network += hlen;
6770
1a1c225b
AD		 6771 /* finally sort out TCP */
6772 if (nexthdr == IPPROTO_TCP) {
6773 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6774 return max_len;
6775
6776 /* access doff as a u8 to avoid unaligned access on ia64 */
6777 hlen = (hdr.network[12] & 0xF0) >> 2;
6778
6779 /* verify hlen meets minimum size requirements */
6780 if (hlen < sizeof(struct tcphdr))
6781 return hdr.network - data;
6782
6783 hdr.network += hlen;
6784 } else if (nexthdr == IPPROTO_UDP) {
6785 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6786 return max_len;
6787
6788 hdr.network += sizeof(struct udphdr);
6789 }
6790
b980ac18 6791 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6792 * data section of the packet and will be the end of the header.
6793 * If not then it probably represents the end of the last recognized
6794 * header.
6795 */
6796 if ((hdr.network - data) < max_len)
6797 return hdr.network - data;
6798 else
6799 return max_len;
6800}
6801
6802/**
b980ac18
JK		 6803 * igb_pull_tail - igb specific version of skb_pull_tail
6804 * @rx_ring: rx descriptor ring packet is being transacted on
6805 * @rx_desc: pointer to the EOP Rx descriptor
6806 * @skb: pointer to current skb being adjusted
1a1c225b 6807 *
b980ac18
JK		 6808 * This function is an igb specific version of __pskb_pull_tail. The
6809 * main difference between this version and the original function is that
6810 * this function can make several assumptions about the state of things
6811 * that allow for significant optimizations versus the standard function.
6812 * As a result we can do things like drop a frag and maintain an accurate
6813 * truesize for the skb.
1a1c225b
AD		 6814 */
6815static void igb_pull_tail(struct igb_ring *rx_ring,
6816 union e1000_adv_rx_desc *rx_desc,
6817 struct sk_buff *skb)
2d94d8ab 6818{
1a1c225b
AD		 6819 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6820 unsigned char *va;
6821 unsigned int pull_len;
6822
b980ac18 6823 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6824 * working with pages allocated out of the lomem pool per
6825 * alloc_page(GFP_ATOMIC)
2d94d8ab 6826 */
1a1c225b
AD		 6827 va = skb_frag_address(frag);
6828
1a1c225b
AD		 6829 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6830 /* retrieve timestamp from buffer */
6831 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6832
6833 /* update pointers to remove timestamp header */
6834 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6835 frag->page_offset += IGB_TS_HDR_LEN;
6836 skb->data_len -= IGB_TS_HDR_LEN;
6837 skb->len -= IGB_TS_HDR_LEN;
6838
6839 /* move va to start of packet data */
6840 va += IGB_TS_HDR_LEN;
6841 }
6842
b980ac18 6843 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6844 * 60 bytes if the skb->len is less than 60 for skb_pad.
6845 */
6846 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6847
6848 /* align pull length to size of long to optimize memcpy performance */
6849 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6850
6851 /* update all of the pointers */
6852 skb_frag_size_sub(frag, pull_len);
6853 frag->page_offset += pull_len;
6854 skb->data_len -= pull_len;
6855 skb->tail += pull_len;
6856}
6857
6858/**
b980ac18
JK		 6859 * igb_cleanup_headers - Correct corrupted or empty headers
6860 * @rx_ring: rx descriptor ring packet is being transacted on
6861 * @rx_desc: pointer to the EOP Rx descriptor
6862 * @skb: pointer to current skb being fixed
1a1c225b 6863 *
b980ac18
JK		 6864 * Address the case where we are pulling data in on pages only
6865 * and as such no data is present in the skb header.
1a1c225b 6866 *
b980ac18
JK		 6867 * In addition if skb is not at least 60 bytes we need to pad it so that
6868 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6869 *
b980ac18 6870 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6871 **/
6872static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6873 union e1000_adv_rx_desc *rx_desc,
6874 struct sk_buff *skb)
6875{
1a1c225b
AD		 6876 if (unlikely((igb_test_staterr(rx_desc,
6877 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6878 struct net_device *netdev = rx_ring->netdev;
6879 if (!(netdev->features & NETIF_F_RXALL)) {
6880 dev_kfree_skb_any(skb);
6881 return true;
6882 }
6883 }
6884
6885 /* place header in linear portion of buffer */
6886 if (skb_is_nonlinear(skb))
6887 igb_pull_tail(rx_ring, rx_desc, skb);
6888
6889 /* if skb_pad returns an error the skb was freed */
6890 if (unlikely(skb->len < 60)) {
6891 int pad_len = 60 - skb->len;
6892
6893 if (skb_pad(skb, pad_len))
6894 return true;
6895 __skb_put(skb, pad_len);
6896 }
6897
6898 return false;
2d94d8ab
AD		 6899}
6900
db2ee5bd 6901/**
b980ac18
JK		 6902 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6903 * @rx_ring: rx descriptor ring packet is being transacted on
6904 * @rx_desc: pointer to the EOP Rx descriptor
6905 * @skb: pointer to current skb being populated
db2ee5bd 6906 *
b980ac18
JK		 6907 * This function checks the ring, descriptor, and packet information in
6908 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6909 * other fields within the skb.
db2ee5bd
AD		 6910 **/
6911static void igb_process_skb_fields(struct igb_ring *rx_ring,
6912 union e1000_adv_rx_desc *rx_desc,
6913 struct sk_buff *skb)
6914{
6915 struct net_device *dev = rx_ring->netdev;
6916
6917 igb_rx_hash(rx_ring, rx_desc, skb);
6918
6919 igb_rx_checksum(rx_ring, rx_desc, skb);
6920
20a48412 6921 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6922
f646968f 6923 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6924 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6925 u16 vid;
6926 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6927 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6928 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6929 else
6930 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6931
86a9bad3 6932 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6933 }
6934
6935 skb_record_rx_queue(skb, rx_ring->queue_index);
6936
6937 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6938}
6939
2e334eee 6940static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6941{
0ba82994 6942 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6943 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6944 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6945 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6946
57ba34c9 6947 while (likely(total_packets < budget)) {
2e334eee 6948 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6949
2e334eee
AD		 6950 /* return some buffers to hardware, one at a time is too slow */
6951 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6952 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6953 cleaned_count = 0;
6954 }
bf36c1a0 6955
2e334eee 6956 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6957
2e334eee
AD		 6958 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6959 break;
9d5c8243 6960
74e238ea
AD		 6961 /* This memory barrier is needed to keep us from reading
6962 * any other fields out of the rx_desc until we know the
6963 * RXD_STAT_DD bit is set
6964 */
6965 rmb();
6966
2e334eee 6967 /* retrieve a buffer from the ring */
f9d40f6a 6968 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6969
2e334eee
AD		 6970 /* exit if we failed to retrieve a buffer */
6971 if (!skb)
6972 break;
1a1c225b 6973
2e334eee 6974 cleaned_count++;
1a1c225b 6975
2e334eee
AD		 6976 /* fetch next buffer in frame if non-eop */
6977 if (igb_is_non_eop(rx_ring, rx_desc))
6978 continue;
1a1c225b
AD		 6979
6980 /* verify the packet layout is correct */
6981 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6982 skb = NULL;
6983 continue;
9d5c8243 6984 }
9d5c8243 6985
db2ee5bd 6986 /* probably a little skewed due to removing CRC */
3ceb90fd 6987 total_bytes += skb->len;
3ceb90fd 6988
db2ee5bd
AD		 6989 /* populate checksum, timestamp, VLAN, and protocol */
6990 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6991
b2cb09b1 6992 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6993
1a1c225b
AD		 6994 /* reset skb pointer */
6995 skb = NULL;
6996
2e334eee
AD		 6997 /* update budget accounting */
6998 total_packets++;
57ba34c9 6999 }
bf36c1a0 7000
1a1c225b
AD		 7001 /* place incomplete frames back on ring for completion */
7002 rx_ring->skb = skb;
7003
12dcd86b 7004 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7005 rx_ring->rx_stats.packets += total_packets;
7006 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7007 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7008 q_vector->rx.total_packets += total_packets;
7009 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7010
7011 if (cleaned_count)
cd392f5c 7012 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7013
2e334eee 7014 return (total_packets < budget);
9d5c8243
AK		 7015}
7016
c023cd88 7017static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7018 struct igb_rx_buffer *bi)
c023cd88
AD		 7019{
7020 struct page *page = bi->page;
cbc8e55f 7021 dma_addr_t dma;
c023cd88 7022
cbc8e55f
AD		 7023 /* since we are recycling buffers we should seldom need to alloc */
7024 if (likely(page))
c023cd88
AD		 7025 return true;
7026
cbc8e55f
AD		 7027 /* alloc new page for storage */
7028 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
7029 if (unlikely(!page)) {
7030 rx_ring->rx_stats.alloc_failed++;
7031 return false;
c023cd88
AD		 7032 }
7033
cbc8e55f
AD		 7034 /* map page for use */
7035 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7036
b980ac18 7037 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7038 * there isn't much point in holding memory we can't use
7039 */
1a1c225b 7040 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7041 __free_page(page);
7042
c023cd88
AD		 7043 rx_ring->rx_stats.alloc_failed++;
7044 return false;
7045 }
7046
1a1c225b 7047 bi->dma = dma;
cbc8e55f
AD		 7048 bi->page = page;
7049 bi->page_offset = 0;
1a1c225b 7050
c023cd88
AD		 7051 return true;
7052}
7053
9d5c8243 7054/**
b980ac18
JK		 7055 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7056 * @adapter: address of board private structure
9d5c8243 7057 **/
cd392f5c 7058void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7059{
9d5c8243 7060 union e1000_adv_rx_desc *rx_desc;
06034649 7061 struct igb_rx_buffer *bi;
c023cd88 7062 u16 i = rx_ring->next_to_use;
9d5c8243 7063
cbc8e55f
AD		 7064 /* nothing to do */
7065 if (!cleaned_count)
7066 return;
7067
60136906 7068 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7069 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7070 i -= rx_ring->count;
9d5c8243 7071
cbc8e55f 7072 do {
1a1c225b 7073 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7074 break;
9d5c8243 7075
b980ac18 7076 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7077 * because each write-back erases this info.
7078 */
f9d40f6a 7079 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7080
c023cd88
AD		 7081 rx_desc++;
7082 bi++;
9d5c8243 7083 i++;
c023cd88 7084 if (unlikely(!i)) {
60136906 7085 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7086 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7087 i -= rx_ring->count;
7088 }
7089
7090 /* clear the hdr_addr for the next_to_use descriptor */
7091 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7092
7093 cleaned_count--;
7094 } while (cleaned_count);
9d5c8243 7095
c023cd88
AD		 7096 i += rx_ring->count;
7097
9d5c8243 7098 if (rx_ring->next_to_use != i) {
cbc8e55f 7099 /* record the next descriptor to use */
9d5c8243 7100 rx_ring->next_to_use = i;
9d5c8243 7101
cbc8e55f
AD		 7102 /* update next to alloc since we have filled the ring */
7103 rx_ring->next_to_alloc = i;
7104
b980ac18 7105 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7106 * know there are new descriptors to fetch. (Only
7107 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7108 * such as IA-64).
7109 */
9d5c8243 7110 wmb();
fce99e34 7111 writel(i, rx_ring->tail);
9d5c8243
AK		 7112 }
7113}
7114
7115/**
7116 * igb_mii_ioctl -
7117 * @netdev:
7118 * @ifreq:
7119 * @cmd:
7120 **/
7121static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7122{
7123 struct igb_adapter *adapter = netdev_priv(netdev);
7124 struct mii_ioctl_data *data = if_mii(ifr);
7125
7126 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7127 return -EOPNOTSUPP;
7128
7129 switch (cmd) {
7130 case SIOCGMIIPHY:
7131 data->phy_id = adapter->hw.phy.addr;
7132 break;
7133 case SIOCGMIIREG:
f5f4cf08
AD		 7134 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7135 &data->val_out))
9d5c8243
AK		 7136 return -EIO;
7137 break;
7138 case SIOCSMIIREG:
7139 default:
7140 return -EOPNOTSUPP;
7141 }
7142 return 0;
7143}
7144
7145/**
7146 * igb_ioctl -
7147 * @netdev:
7148 * @ifreq:
7149 * @cmd:
7150 **/
7151static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7152{
7153 switch (cmd) {
7154 case SIOCGMIIPHY:
7155 case SIOCGMIIREG:
7156 case SIOCSMIIREG:
7157 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 7158 case SIOCSHWTSTAMP:
a79f4f88 7159 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 7160 default:
7161 return -EOPNOTSUPP;
7162 }
7163}
7164
009bc06e
AD		 7165s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7166{
7167 struct igb_adapter *adapter = hw->back;
009bc06e 7168
23d028cc 7169 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7170 return -E1000_ERR_CONFIG;
7171
009bc06e
AD		 7172 return 0;
7173}
7174
7175s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7176{
7177 struct igb_adapter *adapter = hw->back;
009bc06e 7178
23d028cc 7179 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7180 return -E1000_ERR_CONFIG;
7181
009bc06e
AD		 7182 return 0;
7183}
7184
c8f44aff 7185static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7186{
7187 struct igb_adapter *adapter = netdev_priv(netdev);
7188 struct e1000_hw *hw = &adapter->hw;
7189 u32 ctrl, rctl;
f646968f 7190 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7191
5faf030c 7192 if (enable) {
9d5c8243
AK		 7193 /* enable VLAN tag insert/strip */
7194 ctrl = rd32(E1000_CTRL);
7195 ctrl |= E1000_CTRL_VME;
7196 wr32(E1000_CTRL, ctrl);
7197
51466239 7198 /* Disable CFI check */
9d5c8243 7199 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7200 rctl &= ~E1000_RCTL_CFIEN;
7201 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7202 } else {
7203 /* disable VLAN tag insert/strip */
7204 ctrl = rd32(E1000_CTRL);
7205 ctrl &= ~E1000_CTRL_VME;
7206 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7207 }
7208
e1739522 7209 igb_rlpml_set(adapter);
9d5c8243
AK		 7210}
7211
80d5c368
PM		 7212static int igb_vlan_rx_add_vid(struct net_device *netdev,
7213 __be16 proto, u16 vid)
9d5c8243
AK		 7214{
7215 struct igb_adapter *adapter = netdev_priv(netdev);
7216 struct e1000_hw *hw = &adapter->hw;
4ae196df 7217 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7218
51466239
AD		 7219 /* attempt to add filter to vlvf array */
7220 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7221
51466239
AD		 7222 /* add the filter since PF can receive vlans w/o entry in vlvf */
7223 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7224
7225 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7226
7227 return 0;
9d5c8243
AK		 7228}
7229
80d5c368
PM		 7230static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7231 __be16 proto, u16 vid)
9d5c8243
AK		 7232{
7233 struct igb_adapter *adapter = netdev_priv(netdev);
7234 struct e1000_hw *hw = &adapter->hw;
4ae196df 7235 int pf_id = adapter->vfs_allocated_count;
51466239 7236 s32 err;
9d5c8243 7237
51466239
AD		 7238 /* remove vlan from VLVF table array */
7239 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7240
51466239
AD		 7241 /* if vid was not present in VLVF just remove it from table */
7242 if (err)
4ae196df 7243 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7244
7245 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7246
7247 return 0;
9d5c8243
AK		 7248}
7249
7250static void igb_restore_vlan(struct igb_adapter *adapter)
7251{
b2cb09b1 7252 u16 vid;
9d5c8243 7253
5faf030c
AD		 7254 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7255
b2cb09b1 7256 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7257 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7258}
7259
14ad2513 7260int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7261{
090b1795 7262 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7263 struct e1000_mac_info *mac = &adapter->hw.mac;
7264
7265 mac->autoneg = 0;
7266
14ad2513 7267 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7268 * for the switch() below to work
7269 */
14ad2513
DD		 7270 if ((spd & 1) || (dplx & ~1))
7271 goto err_inval;
7272
f502ef7d
AA		 7273 /* Fiber NIC's only allow 1000 gbps Full duplex
7274 * and 100Mbps Full duplex for 100baseFx sfp
7275 */
7276 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7277 switch (spd + dplx) {
7278 case SPEED_10 + DUPLEX_HALF:
7279 case SPEED_10 + DUPLEX_FULL:
7280 case SPEED_100 + DUPLEX_HALF:
7281 goto err_inval;
7282 default:
7283 break;
7284 }
7285 }
cd2638a8 7286
14ad2513 7287 switch (spd + dplx) {
9d5c8243
AK		 7288 case SPEED_10 + DUPLEX_HALF:
7289 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7290 break;
7291 case SPEED_10 + DUPLEX_FULL:
7292 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7293 break;
7294 case SPEED_100 + DUPLEX_HALF:
7295 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7296 break;
7297 case SPEED_100 + DUPLEX_FULL:
7298 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7299 break;
7300 case SPEED_1000 + DUPLEX_FULL:
7301 mac->autoneg = 1;
7302 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7303 break;
7304 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7305 default:
14ad2513 7306 goto err_inval;
9d5c8243 7307 }
8376dad0
JB		 7308
7309 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7310 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7311
9d5c8243 7312 return 0;
14ad2513
DD		 7313
7314err_inval:
7315 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7316 return -EINVAL;
9d5c8243
AK		 7317}
7318
749ab2cd
YZ		 7319static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7320 bool runtime)
9d5c8243
AK		 7321{
7322 struct net_device *netdev = pci_get_drvdata(pdev);
7323 struct igb_adapter *adapter = netdev_priv(netdev);
7324 struct e1000_hw *hw = &adapter->hw;
2d064c06 7325 u32 ctrl, rctl, status;
749ab2cd 7326 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7327#ifdef CONFIG_PM
7328 int retval = 0;
7329#endif
7330
7331 netif_device_detach(netdev);
7332
a88f10ec 7333 if (netif_running(netdev))
749ab2cd 7334 __igb_close(netdev, true);
a88f10ec 7335
047e0030 7336 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7337
7338#ifdef CONFIG_PM
7339 retval = pci_save_state(pdev);
7340 if (retval)
7341 return retval;
7342#endif
7343
7344 status = rd32(E1000_STATUS);
7345 if (status & E1000_STATUS_LU)
7346 wufc &= ~E1000_WUFC_LNKC;
7347
7348 if (wufc) {
7349 igb_setup_rctl(adapter);
ff41f8dc 7350 igb_set_rx_mode(netdev);
9d5c8243
AK		 7351
7352 /* turn on all-multi mode if wake on multicast is enabled */
7353 if (wufc & E1000_WUFC_MC) {
7354 rctl = rd32(E1000_RCTL);
7355 rctl |= E1000_RCTL_MPE;
7356 wr32(E1000_RCTL, rctl);
7357 }
7358
7359 ctrl = rd32(E1000_CTRL);
7360 /* advertise wake from D3Cold */
7361 #define E1000_CTRL_ADVD3WUC 0x00100000
7362 /* phy power management enable */
7363 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7364 ctrl |= E1000_CTRL_ADVD3WUC;
7365 wr32(E1000_CTRL, ctrl);
7366
9d5c8243 7367 /* Allow time for pending master requests to run */
330a6d6a 7368 igb_disable_pcie_master(hw);
9d5c8243
AK		 7369
7370 wr32(E1000_WUC, E1000_WUC_PME_EN);
7371 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7372 } else {
7373 wr32(E1000_WUC, 0);
7374 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7375 }
7376
3fe7c4c9
RW		 7377 *enable_wake = wufc || adapter->en_mng_pt;
7378 if (!*enable_wake)
88a268c1
NN		 7379 igb_power_down_link(adapter);
7380 else
7381 igb_power_up_link(adapter);
9d5c8243
AK		 7382
7383 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7384 * would have already happened in close and is redundant.
7385 */
9d5c8243
AK		 7386 igb_release_hw_control(adapter);
7387
7388 pci_disable_device(pdev);
7389
9d5c8243
AK		 7390 return 0;
7391}
7392
7393#ifdef CONFIG_PM
d9dd966d 7394#ifdef CONFIG_PM_SLEEP
749ab2cd 7395static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7396{
7397 int retval;
7398 bool wake;
749ab2cd 7399 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7400
749ab2cd 7401 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7402 if (retval)
7403 return retval;
7404
7405 if (wake) {
7406 pci_prepare_to_sleep(pdev);
7407 } else {
7408 pci_wake_from_d3(pdev, false);
7409 pci_set_power_state(pdev, PCI_D3hot);
7410 }
7411
7412 return 0;
7413}
d9dd966d 7414#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7415
749ab2cd 7416static int igb_resume(struct device *dev)
9d5c8243 7417{
749ab2cd 7418 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7419 struct net_device *netdev = pci_get_drvdata(pdev);
7420 struct igb_adapter *adapter = netdev_priv(netdev);
7421 struct e1000_hw *hw = &adapter->hw;
7422 u32 err;
7423
7424 pci_set_power_state(pdev, PCI_D0);
7425 pci_restore_state(pdev);
b94f2d77 7426 pci_save_state(pdev);
42bfd33a 7427
aed5dec3 7428 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7429 if (err) {
7430 dev_err(&pdev->dev,
7431 "igb: Cannot enable PCI device from suspend\n");
7432 return err;
7433 }
7434 pci_set_master(pdev);
7435
7436 pci_enable_wake(pdev, PCI_D3hot, 0);
7437 pci_enable_wake(pdev, PCI_D3cold, 0);
7438
53c7d064 7439 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7440 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7441 return -ENOMEM;
9d5c8243
AK		 7442 }
7443
9d5c8243 7444 igb_reset(adapter);
a8564f03
AD		 7445
7446 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7447 * driver.
7448 */
a8564f03
AD		 7449 igb_get_hw_control(adapter);
7450
9d5c8243
AK		 7451 wr32(E1000_WUS, ~0);
7452
749ab2cd 7453 if (netdev->flags & IFF_UP) {
0c2cc02e 7454 rtnl_lock();
749ab2cd 7455 err = __igb_open(netdev, true);
0c2cc02e 7456 rtnl_unlock();
a88f10ec
AD		 7457 if (err)
7458 return err;
7459 }
9d5c8243
AK		 7460
7461 netif_device_attach(netdev);
749ab2cd
YZ		 7462 return 0;
7463}
7464
7465#ifdef CONFIG_PM_RUNTIME
7466static int igb_runtime_idle(struct device *dev)
7467{
7468 struct pci_dev *pdev = to_pci_dev(dev);
7469 struct net_device *netdev = pci_get_drvdata(pdev);
7470 struct igb_adapter *adapter = netdev_priv(netdev);
7471
7472 if (!igb_has_link(adapter))
7473 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7474
7475 return -EBUSY;
7476}
7477
7478static int igb_runtime_suspend(struct device *dev)
7479{
7480 struct pci_dev *pdev = to_pci_dev(dev);
7481 int retval;
7482 bool wake;
7483
7484 retval = __igb_shutdown(pdev, &wake, 1);
7485 if (retval)
7486 return retval;
7487
7488 if (wake) {
7489 pci_prepare_to_sleep(pdev);
7490 } else {
7491 pci_wake_from_d3(pdev, false);
7492 pci_set_power_state(pdev, PCI_D3hot);
7493 }
9d5c8243 7494
9d5c8243
AK		 7495 return 0;
7496}
749ab2cd
YZ		 7497
7498static int igb_runtime_resume(struct device *dev)
7499{
7500 return igb_resume(dev);
7501}
7502#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7503#endif
7504
7505static void igb_shutdown(struct pci_dev *pdev)
7506{
3fe7c4c9
RW		 7507 bool wake;
7508
749ab2cd 7509 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7510
7511 if (system_state == SYSTEM_POWER_OFF) {
7512 pci_wake_from_d3(pdev, wake);
7513 pci_set_power_state(pdev, PCI_D3hot);
7514 }
9d5c8243
AK		 7515}
7516
fa44f2f1
GR		 7517#ifdef CONFIG_PCI_IOV
7518static int igb_sriov_reinit(struct pci_dev *dev)
7519{
7520 struct net_device *netdev = pci_get_drvdata(dev);
7521 struct igb_adapter *adapter = netdev_priv(netdev);
7522 struct pci_dev *pdev = adapter->pdev;
7523
7524 rtnl_lock();
7525
7526 if (netif_running(netdev))
7527 igb_close(netdev);
7528
7529 igb_clear_interrupt_scheme(adapter);
7530
7531 igb_init_queue_configuration(adapter);
7532
7533 if (igb_init_interrupt_scheme(adapter, true)) {
7534 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7535 return -ENOMEM;
7536 }
7537
7538 if (netif_running(netdev))
7539 igb_open(netdev);
7540
7541 rtnl_unlock();
7542
7543 return 0;
7544}
7545
7546static int igb_pci_disable_sriov(struct pci_dev *dev)
7547{
7548 int err = igb_disable_sriov(dev);
7549
7550 if (!err)
7551 err = igb_sriov_reinit(dev);
7552
7553 return err;
7554}
7555
7556static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7557{
7558 int err = igb_enable_sriov(dev, num_vfs);
7559
7560 if (err)
7561 goto out;
7562
7563 err = igb_sriov_reinit(dev);
7564 if (!err)
7565 return num_vfs;
7566
7567out:
7568 return err;
7569}
7570
7571#endif
7572static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7573{
7574#ifdef CONFIG_PCI_IOV
7575 if (num_vfs == 0)
7576 return igb_pci_disable_sriov(dev);
7577 else
7578 return igb_pci_enable_sriov(dev, num_vfs);
7579#endif
7580 return 0;
7581}
7582
9d5c8243 7583#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7584/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7585 * without having to re-enable interrupts. It's not called while
7586 * the interrupt routine is executing.
7587 */
7588static void igb_netpoll(struct net_device *netdev)
7589{
7590 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7591 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7592 struct igb_q_vector *q_vector;
9d5c8243 7593 int i;
9d5c8243 7594
047e0030 7595 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7596 q_vector = adapter->q_vector[i];
cd14ef54 7597 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7598 wr32(E1000_EIMC, q_vector->eims_value);
7599 else
7600 igb_irq_disable(adapter);
047e0030 7601 napi_schedule(&q_vector->napi);
eebbbdba 7602 }
9d5c8243
AK		 7603}
7604#endif /* CONFIG_NET_POLL_CONTROLLER */
7605
7606/**
b980ac18
JK		 7607 * igb_io_error_detected - called when PCI error is detected
7608 * @pdev: Pointer to PCI device
7609 * @state: The current pci connection state
9d5c8243 7610 *
b980ac18
JK		 7611 * This function is called after a PCI bus error affecting
7612 * this device has been detected.
7613 **/
9d5c8243
AK		 7614static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7615 pci_channel_state_t state)
7616{
7617 struct net_device *netdev = pci_get_drvdata(pdev);
7618 struct igb_adapter *adapter = netdev_priv(netdev);
7619
7620 netif_device_detach(netdev);
7621
59ed6eec
AD		 7622 if (state == pci_channel_io_perm_failure)
7623 return PCI_ERS_RESULT_DISCONNECT;
7624
9d5c8243
AK		 7625 if (netif_running(netdev))
7626 igb_down(adapter);
7627 pci_disable_device(pdev);
7628
7629 /* Request a slot slot reset. */
7630 return PCI_ERS_RESULT_NEED_RESET;
7631}
7632
7633/**
b980ac18
JK		 7634 * igb_io_slot_reset - called after the pci bus has been reset.
7635 * @pdev: Pointer to PCI device
9d5c8243 7636 *
b980ac18
JK		 7637 * Restart the card from scratch, as if from a cold-boot. Implementation
7638 * resembles the first-half of the igb_resume routine.
7639 **/
9d5c8243
AK		 7640static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7641{
7642 struct net_device *netdev = pci_get_drvdata(pdev);
7643 struct igb_adapter *adapter = netdev_priv(netdev);
7644 struct e1000_hw *hw = &adapter->hw;
40a914fa 7645 pci_ers_result_t result;
42bfd33a 7646 int err;
9d5c8243 7647
aed5dec3 7648 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7649 dev_err(&pdev->dev,
7650 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7651 result = PCI_ERS_RESULT_DISCONNECT;
7652 } else {
7653 pci_set_master(pdev);
7654 pci_restore_state(pdev);
b94f2d77 7655 pci_save_state(pdev);
9d5c8243 7656
40a914fa
AD		 7657 pci_enable_wake(pdev, PCI_D3hot, 0);
7658 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7659
40a914fa
AD		 7660 igb_reset(adapter);
7661 wr32(E1000_WUS, ~0);
7662 result = PCI_ERS_RESULT_RECOVERED;
7663 }
9d5c8243 7664
ea943d41
JK		 7665 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7666 if (err) {
b980ac18
JK		 7667 dev_err(&pdev->dev,
7668 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7669 err);
ea943d41
JK		 7670 /* non-fatal, continue */
7671 }
40a914fa
AD		 7672
7673 return result;
9d5c8243
AK		 7674}
7675
7676/**
b980ac18
JK		 7677 * igb_io_resume - called when traffic can start flowing again.
7678 * @pdev: Pointer to PCI device
9d5c8243 7679 *
b980ac18
JK		 7680 * This callback is called when the error recovery driver tells us that
7681 * its OK to resume normal operation. Implementation resembles the
7682 * second-half of the igb_resume routine.
9d5c8243
AK		 7683 */
7684static void igb_io_resume(struct pci_dev *pdev)
7685{
7686 struct net_device *netdev = pci_get_drvdata(pdev);
7687 struct igb_adapter *adapter = netdev_priv(netdev);
7688
9d5c8243
AK		 7689 if (netif_running(netdev)) {
7690 if (igb_up(adapter)) {
7691 dev_err(&pdev->dev, "igb_up failed after reset\n");
7692 return;
7693 }
7694 }
7695
7696 netif_device_attach(netdev);
7697
7698 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7699 * driver.
7700 */
9d5c8243 7701 igb_get_hw_control(adapter);
9d5c8243
AK		 7702}
7703
26ad9178 7704static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7705 u8 qsel)
26ad9178
AD		 7706{
7707 u32 rar_low, rar_high;
7708 struct e1000_hw *hw = &adapter->hw;
7709
7710 /* HW expects these in little endian so we reverse the byte order
7711 * from network order (big endian) to little endian
7712 */
7713 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7714 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7715 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7716
7717 /* Indicate to hardware the Address is Valid. */
7718 rar_high |= E1000_RAH_AV;
7719
7720 if (hw->mac.type == e1000_82575)
7721 rar_high |= E1000_RAH_POOL_1 * qsel;
7722 else
7723 rar_high |= E1000_RAH_POOL_1 << qsel;
7724
7725 wr32(E1000_RAL(index), rar_low);
7726 wrfl();
7727 wr32(E1000_RAH(index), rar_high);
7728 wrfl();
7729}
7730
4ae196df 7731static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7732 int vf, unsigned char *mac_addr)
4ae196df
AD		 7733{
7734 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7735 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7736 * towards the first, as a result a collision should not be possible
7737 */
ff41f8dc 7738 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7739
37680117 7740 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7741
26ad9178 7742 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7743
7744 return 0;
7745}
7746
8151d294
WM		 7747static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7748{
7749 struct igb_adapter *adapter = netdev_priv(netdev);
7750 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7751 return -EINVAL;
7752 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7753 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7754 dev_info(&adapter->pdev->dev,
7755 "Reload the VF driver to make this change effective.");
8151d294 7756 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7757 dev_warn(&adapter->pdev->dev,
7758 "The VF MAC address has been set, but the PF device is not up.\n");
7759 dev_warn(&adapter->pdev->dev,
7760 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7761 }
7762 return igb_set_vf_mac(adapter, vf, mac);
7763}
7764
17dc566c
LL		 7765static int igb_link_mbps(int internal_link_speed)
7766{
7767 switch (internal_link_speed) {
7768 case SPEED_100:
7769 return 100;
7770 case SPEED_1000:
7771 return 1000;
7772 default:
7773 return 0;
7774 }
7775}
7776
7777static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7778 int link_speed)
7779{
7780 int rf_dec, rf_int;
7781 u32 bcnrc_val;
7782
7783 if (tx_rate != 0) {
7784 /* Calculate the rate factor values to set */
7785 rf_int = link_speed / tx_rate;
7786 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7787 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7788 tx_rate;
17dc566c
LL		 7789
7790 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7791 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7792 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7793 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7794 } else {
7795 bcnrc_val = 0;
7796 }
7797
7798 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7799 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7800 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7801 */
7802 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7803 wr32(E1000_RTTBCNRC, bcnrc_val);
7804}
7805
7806static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7807{
7808 int actual_link_speed, i;
7809 bool reset_rate = false;
7810
7811 /* VF TX rate limit was not set or not supported */
7812 if ((adapter->vf_rate_link_speed == 0) ||
7813 (adapter->hw.mac.type != e1000_82576))
7814 return;
7815
7816 actual_link_speed = igb_link_mbps(adapter->link_speed);
7817 if (actual_link_speed != adapter->vf_rate_link_speed) {
7818 reset_rate = true;
7819 adapter->vf_rate_link_speed = 0;
7820 dev_info(&adapter->pdev->dev,
b980ac18 7821 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7822 }
7823
7824 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7825 if (reset_rate)
7826 adapter->vf_data[i].tx_rate = 0;
7827
7828 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7829 adapter->vf_data[i].tx_rate,
7830 actual_link_speed);
17dc566c
LL		 7831 }
7832}
7833
8151d294
WM		 7834static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7835{
17dc566c
LL		 7836 struct igb_adapter *adapter = netdev_priv(netdev);
7837 struct e1000_hw *hw = &adapter->hw;
7838 int actual_link_speed;
7839
7840 if (hw->mac.type != e1000_82576)
7841 return -EOPNOTSUPP;
7842
7843 actual_link_speed = igb_link_mbps(adapter->link_speed);
7844 if ((vf >= adapter->vfs_allocated_count) ||
7845 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7846 (tx_rate < 0) || (tx_rate > actual_link_speed))
7847 return -EINVAL;
7848
7849 adapter->vf_rate_link_speed = actual_link_speed;
7850 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7851 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7852
7853 return 0;
8151d294
WM		 7854}
7855
70ea4783
LL		 7856static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7857 bool setting)
7858{
7859 struct igb_adapter *adapter = netdev_priv(netdev);
7860 struct e1000_hw *hw = &adapter->hw;
7861 u32 reg_val, reg_offset;
7862
7863 if (!adapter->vfs_allocated_count)
7864 return -EOPNOTSUPP;
7865
7866 if (vf >= adapter->vfs_allocated_count)
7867 return -EINVAL;
7868
7869 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7870 reg_val = rd32(reg_offset);
7871 if (setting)
7872 reg_val |= ((1 << vf) |
7873 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7874 else
7875 reg_val &= ~((1 << vf) |
7876 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7877 wr32(reg_offset, reg_val);
7878
7879 adapter->vf_data[vf].spoofchk_enabled = setting;
7880 return E1000_SUCCESS;
7881}
7882
8151d294
WM		 7883static int igb_ndo_get_vf_config(struct net_device *netdev,
7884 int vf, struct ifla_vf_info *ivi)
7885{
7886 struct igb_adapter *adapter = netdev_priv(netdev);
7887 if (vf >= adapter->vfs_allocated_count)
7888 return -EINVAL;
7889 ivi->vf = vf;
7890 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7891 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7892 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7893 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7894 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7895 return 0;
7896}
7897
4ae196df
AD		 7898static void igb_vmm_control(struct igb_adapter *adapter)
7899{
7900 struct e1000_hw *hw = &adapter->hw;
10d8e907 7901 u32 reg;
4ae196df 7902
52a1dd4d
AD		 7903 switch (hw->mac.type) {
7904 case e1000_82575:
f96a8a0b
CW		 7905 case e1000_i210:
7906 case e1000_i211:
ceb5f13b 7907 case e1000_i354:
52a1dd4d
AD		 7908 default:
7909 /* replication is not supported for 82575 */
4ae196df 7910 return;
52a1dd4d
AD		 7911 case e1000_82576:
7912 /* notify HW that the MAC is adding vlan tags */
7913 reg = rd32(E1000_DTXCTL);
7914 reg |= E1000_DTXCTL_VLAN_ADDED;
7915 wr32(E1000_DTXCTL, reg);
7916 case e1000_82580:
7917 /* enable replication vlan tag stripping */
7918 reg = rd32(E1000_RPLOLR);
7919 reg |= E1000_RPLOLR_STRVLAN;
7920 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7921 case e1000_i350:
7922 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7923 break;
7924 }
10d8e907 7925
d4960307
AD		 7926 if (adapter->vfs_allocated_count) {
7927 igb_vmdq_set_loopback_pf(hw, true);
7928 igb_vmdq_set_replication_pf(hw, true);
13800469 7929 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7930 adapter->vfs_allocated_count);
d4960307
AD		 7931 } else {
7932 igb_vmdq_set_loopback_pf(hw, false);
7933 igb_vmdq_set_replication_pf(hw, false);
7934 }
4ae196df
AD		 7935}
7936
b6e0c419
CW		 7937static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7938{
7939 struct e1000_hw *hw = &adapter->hw;
7940 u32 dmac_thr;
7941 u16 hwm;
7942
7943 if (hw->mac.type > e1000_82580) {
7944 if (adapter->flags & IGB_FLAG_DMAC) {
7945 u32 reg;
7946
7947 /* force threshold to 0. */
7948 wr32(E1000_DMCTXTH, 0);
7949
b980ac18 7950 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7951 * than the Rx threshold. Set hwm to PBA - max frame
7952 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7953 */
e8c626e9
MV		 7954 hwm = 64 * pba - adapter->max_frame_size / 16;
7955 if (hwm < 64 * (pba - 6))
7956 hwm = 64 * (pba - 6);
7957 reg = rd32(E1000_FCRTC);
7958 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7959 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7960 & E1000_FCRTC_RTH_COAL_MASK);
7961 wr32(E1000_FCRTC, reg);
7962
b980ac18 7963 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7964 * frame size, capping it at PBA - 10KB.
7965 */
7966 dmac_thr = pba - adapter->max_frame_size / 512;
7967 if (dmac_thr < pba - 10)
7968 dmac_thr = pba - 10;
b6e0c419
CW		 7969 reg = rd32(E1000_DMACR);
7970 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7971 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7972 & E1000_DMACR_DMACTHR_MASK);
7973
7974 /* transition to L0x or L1 if available..*/
7975 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7976
7977 /* watchdog timer= +-1000 usec in 32usec intervals */
7978 reg |= (1000 >> 5);
0c02dd98
MV		 7979
7980 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7981 if (hw->mac.type != e1000_i354)
7982 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7983
b6e0c419
CW		 7984 wr32(E1000_DMACR, reg);
7985
b980ac18 7986 /* no lower threshold to disable
b6e0c419
CW		 7987 * coalescing(smart fifb)-UTRESH=0
7988 */
7989 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7990
7991 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7992
7993 wr32(E1000_DMCTLX, reg);
7994
b980ac18 7995 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7996 * DMA coal
7997 */
7998 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7999 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8000
b980ac18 8001 /* make low power state decision controlled
b6e0c419
CW		 8002 * by DMA coal
8003 */
8004 reg = rd32(E1000_PCIEMISC);
8005 reg &= ~E1000_PCIEMISC_LX_DECISION;
8006 wr32(E1000_PCIEMISC, reg);
8007 } /* endif adapter->dmac is not disabled */
8008 } else if (hw->mac.type == e1000_82580) {
8009 u32 reg = rd32(E1000_PCIEMISC);
8010 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8011 wr32(E1000_DMACR, 0);
8012 }
8013}
8014
b980ac18
JK		 8015/**
8016 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8017 * @hw: pointer to hardware structure
8018 * @byte_offset: byte offset to read
8019 * @dev_addr: device address
8020 * @data: value read
8021 *
8022 * Performs byte read operation over I2C interface at
8023 * a specified device address.
b980ac18 8024 **/
441fc6fd 8025s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8026 u8 dev_addr, u8 *data)
441fc6fd
CW		 8027{
8028 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8029 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8030 s32 status;
8031 u16 swfw_mask = 0;
8032
8033 if (!this_client)
8034 return E1000_ERR_I2C;
8035
8036 swfw_mask = E1000_SWFW_PHY0_SM;
8037
8038 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
8039 != E1000_SUCCESS)
8040 return E1000_ERR_SWFW_SYNC;
8041
8042 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8043 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8044
8045 if (status < 0)
8046 return E1000_ERR_I2C;
8047 else {
8048 *data = status;
8049 return E1000_SUCCESS;
8050 }
8051}
8052
b980ac18
JK		 8053/**
8054 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8055 * @hw: pointer to hardware structure
8056 * @byte_offset: byte offset to write
8057 * @dev_addr: device address
8058 * @data: value to write
8059 *
8060 * Performs byte write operation over I2C interface at
8061 * a specified device address.
b980ac18 8062 **/
441fc6fd 8063s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8064 u8 dev_addr, u8 data)
441fc6fd
CW		 8065{
8066 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8067 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8068 s32 status;
8069 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8070
8071 if (!this_client)
8072 return E1000_ERR_I2C;
8073
8074 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
8075 return E1000_ERR_SWFW_SYNC;
8076 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8077 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8078
8079 if (status)
8080 return E1000_ERR_I2C;
8081 else
8082 return E1000_SUCCESS;
8083
8084}
907b7835
LMV		 8085
8086int igb_reinit_queues(struct igb_adapter *adapter)
8087{
8088 struct net_device *netdev = adapter->netdev;
8089 struct pci_dev *pdev = adapter->pdev;
8090 int err = 0;
8091
8092 if (netif_running(netdev))
8093 igb_close(netdev);
8094
02ef6e1d 8095 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8096
8097 if (igb_init_interrupt_scheme(adapter, true)) {
8098 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8099 return -ENOMEM;
8100 }
8101
8102 if (netif_running(netdev))
8103 err = igb_open(netdev);
8104
8105 return err;
8106}
9d5c8243 8107/* igb_main.c */
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