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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
65#define BUILD 3
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117};
118
119MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121void igb_reset(struct igb_adapter *);
122static int igb_setup_all_tx_resources(struct igb_adapter *);
123static int igb_setup_all_rx_resources(struct igb_adapter *);
124static void igb_free_all_tx_resources(struct igb_adapter *);
125static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 126static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 127static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 128static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 129static int igb_sw_init(struct igb_adapter *);
130static int igb_open(struct net_device *);
131static int igb_close(struct net_device *);
53c7d064 132static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 133static void igb_configure_tx(struct igb_adapter *);
134static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 135static void igb_clean_all_tx_rings(struct igb_adapter *);
136static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 137static void igb_clean_tx_ring(struct igb_ring *);
138static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 139static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 140static void igb_update_phy_info(unsigned long);
141static void igb_watchdog(unsigned long);
142static void igb_watchdog_task(struct work_struct *);
cd392f5c 143static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 144static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 146static int igb_change_mtu(struct net_device *, int);
147static int igb_set_mac(struct net_device *, void *);
68d480c4 148static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 149static irqreturn_t igb_intr(int irq, void *);
150static irqreturn_t igb_intr_msi(int irq, void *);
151static irqreturn_t igb_msix_other(int irq, void *);
047e0030 152static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 153#ifdef CONFIG_IGB_DCA
047e0030 154static void igb_update_dca(struct igb_q_vector *);
fe4506b6 155static void igb_setup_dca(struct igb_adapter *);
421e02f0 156#endif /* CONFIG_IGB_DCA */
661086df 157static int igb_poll(struct napi_struct *, int);
13fde97a 158static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 159static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 160static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161static void igb_tx_timeout(struct net_device *);
162static void igb_reset_task(struct work_struct *);
c8f44aff 163static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 164static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 166static void igb_restore_vlan(struct igb_adapter *);
26ad9178 167static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 168static void igb_ping_all_vfs(struct igb_adapter *);
169static void igb_msg_task(struct igb_adapter *);
4ae196df 170static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 171static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 172static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 173static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 177static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
8151d294
WM		 179static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
17dc566c 181static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 182
183#ifdef CONFIG_PCI_IOV
0224d663 184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
46a01698 185#endif
9d5c8243 186
9d5c8243 187#ifdef CONFIG_PM
d9dd966d 188#ifdef CONFIG_PM_SLEEP
749ab2cd 189static int igb_suspend(struct device *);
d9dd966d 190#endif
749ab2cd
YZ		 191static int igb_resume(struct device *);
192#ifdef CONFIG_PM_RUNTIME
193static int igb_runtime_suspend(struct device *dev);
194static int igb_runtime_resume(struct device *dev);
195static int igb_runtime_idle(struct device *dev);
196#endif
197static const struct dev_pm_ops igb_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 igb_runtime_idle)
201};
9d5c8243
AK		 202#endif
203static void igb_shutdown(struct pci_dev *);
fa44f2f1 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 205#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
207static struct notifier_block dca_notifier = {
208 .notifier_call = igb_notify_dca,
209 .next = NULL,
210 .priority = 0
211};
212#endif
9d5c8243
AK		 213#ifdef CONFIG_NET_POLL_CONTROLLER
214/* for netdump / net console */
215static void igb_netpoll(struct net_device *);
216#endif
37680117 217#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 218static unsigned int max_vfs = 0;
219module_param(max_vfs, uint, 0);
220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
221 "per physical function");
222#endif /* CONFIG_PCI_IOV */
223
9d5c8243
AK		 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
225 pci_channel_state_t);
226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
227static void igb_io_resume(struct pci_dev *);
228
3646f0e5 229static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 230 .error_detected = igb_io_error_detected,
231 .slot_reset = igb_io_slot_reset,
232 .resume = igb_io_resume,
233};
234
b6e0c419 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 236
237static struct pci_driver igb_driver = {
238 .name = igb_driver_name,
239 .id_table = igb_pci_tbl,
240 .probe = igb_probe,
9f9a12f8 241 .remove = igb_remove,
9d5c8243 242#ifdef CONFIG_PM
749ab2cd 243 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 244#endif
245 .shutdown = igb_shutdown,
fa44f2f1 246 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 247 .err_handler = &igb_err_handler
248};
249
250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
252MODULE_LICENSE("GPL");
253MODULE_VERSION(DRV_VERSION);
254
b3f4d599 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
256static int debug = -1;
257module_param(debug, int, 0);
258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
259
c97ec42a
TI		 260struct igb_reg_info {
261 u32 ofs;
262 char *name;
263};
264
265static const struct igb_reg_info igb_reg_info_tbl[] = {
266
267 /* General Registers */
268 {E1000_CTRL, "CTRL"},
269 {E1000_STATUS, "STATUS"},
270 {E1000_CTRL_EXT, "CTRL_EXT"},
271
272 /* Interrupt Registers */
273 {E1000_ICR, "ICR"},
274
275 /* RX Registers */
276 {E1000_RCTL, "RCTL"},
277 {E1000_RDLEN(0), "RDLEN"},
278 {E1000_RDH(0), "RDH"},
279 {E1000_RDT(0), "RDT"},
280 {E1000_RXDCTL(0), "RXDCTL"},
281 {E1000_RDBAL(0), "RDBAL"},
282 {E1000_RDBAH(0), "RDBAH"},
283
284 /* TX Registers */
285 {E1000_TCTL, "TCTL"},
286 {E1000_TDBAL(0), "TDBAL"},
287 {E1000_TDBAH(0), "TDBAH"},
288 {E1000_TDLEN(0), "TDLEN"},
289 {E1000_TDH(0), "TDH"},
290 {E1000_TDT(0), "TDT"},
291 {E1000_TXDCTL(0), "TXDCTL"},
292 {E1000_TDFH, "TDFH"},
293 {E1000_TDFT, "TDFT"},
294 {E1000_TDFHS, "TDFHS"},
295 {E1000_TDFPC, "TDFPC"},
296
297 /* List Terminator */
298 {}
299};
300
b980ac18 301/* igb_regdump - register printout routine */
c97ec42a
TI		 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
303{
304 int n = 0;
305 char rname[16];
306 u32 regs[8];
307
308 switch (reginfo->ofs) {
309 case E1000_RDLEN(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDLEN(n));
312 break;
313 case E1000_RDH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDH(n));
316 break;
317 case E1000_RDT(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDT(n));
320 break;
321 case E1000_RXDCTL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RXDCTL(n));
324 break;
325 case E1000_RDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_RDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAH(n));
332 break;
333 case E1000_TDBAL(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_RDBAL(n));
336 break;
337 case E1000_TDBAH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDBAH(n));
340 break;
341 case E1000_TDLEN(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDLEN(n));
344 break;
345 case E1000_TDH(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDH(n));
348 break;
349 case E1000_TDT(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TDT(n));
352 break;
353 case E1000_TXDCTL(0):
354 for (n = 0; n < 4; n++)
355 regs[n] = rd32(E1000_TXDCTL(n));
356 break;
357 default:
876d2d6f 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 359 return;
360 }
361
362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 regs[2], regs[3]);
c97ec42a
TI		 365}
366
b980ac18 367/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 368static void igb_dump(struct igb_adapter *adapter)
369{
370 struct net_device *netdev = adapter->netdev;
371 struct e1000_hw *hw = &adapter->hw;
372 struct igb_reg_info *reginfo;
c97ec42a
TI		 373 struct igb_ring *tx_ring;
374 union e1000_adv_tx_desc *tx_desc;
375 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 376 struct igb_ring *rx_ring;
377 union e1000_adv_rx_desc *rx_desc;
378 u32 staterr;
6ad4edfc 379 u16 i, n;
c97ec42a
TI		 380
381 if (!netif_msg_hw(adapter))
382 return;
383
384 /* Print netdevice Info */
385 if (netdev) {
386 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 387 pr_info("Device Name state trans_start "
388 "last_rx\n");
389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
390 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 391 }
392
393 /* Print Registers */
394 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 395 pr_info(" Register Name Value\n");
c97ec42a
TI		 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
397 reginfo->name; reginfo++) {
398 igb_regdump(hw, reginfo);
399 }
400
401 /* Print TX Ring Summary */
402 if (!netdev || !netif_running(netdev))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 407 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 408 struct igb_tx_buffer *buffer_info;
c97ec42a 409 tx_ring = adapter->tx_ring[n];
06034649 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
412 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 413 (u64)dma_unmap_addr(buffer_info, dma),
414 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 415 buffer_info->next_to_watch,
416 (u64)buffer_info->time_stamp);
c97ec42a
TI		 417 }
418
419 /* Print TX Rings */
420 if (!netif_msg_tx_done(adapter))
421 goto rx_ring_summary;
422
423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
424
425 /* Transmit Descriptor Formats
426 *
427 * Advanced Transmit Descriptor
428 * +--------------------------------------------------------------+
429 * 0 | Buffer Address [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
432 * +--------------------------------------------------------------+
433 * 63 46 45 40 39 38 36 35 32 31 24 15 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
442 "[bi->dma ] leng ntw timestamp "
443 "bi->skb\n");
c97ec42a
TI		 444
445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 446 const char *next_desc;
06034649 447 struct igb_tx_buffer *buffer_info;
60136906 448 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 449 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 450 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 451 if (i == tx_ring->next_to_use &&
452 i == tx_ring->next_to_clean)
453 next_desc = " NTC/U";
454 else if (i == tx_ring->next_to_use)
455 next_desc = " NTU";
456 else if (i == tx_ring->next_to_clean)
457 next_desc = " NTC";
458 else
459 next_desc = "";
460
461 pr_info("T [0x%03X] %016llX %016llX %016llX"
462 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
c9f14bf3
AD		 465 (u64)dma_unmap_addr(buffer_info, dma),
466 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 467 buffer_info->next_to_watch,
468 (u64)buffer_info->time_stamp,
876d2d6f 469 buffer_info->skb, next_desc);
c97ec42a 470
b669588a 471 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS,
b669588a 474 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 475 dma_unmap_len(buffer_info, len),
476 true);
c97ec42a
TI		 477 }
478 }
479
480 /* Print RX Rings Summary */
481rx_ring_summary:
482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 483 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 486 pr_info(" %5d %5X %5X\n",
487 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 488 }
489
490 /* Print RX Rings */
491 if (!netif_msg_rx_status(adapter))
492 goto exit;
493
494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
495
496 /* Advanced Receive Descriptor (Read) Format
497 * 63 1 0
498 * +-----------------------------------------------------+
499 * 0 | Packet Buffer Address [63:1] |A0/NSE|
500 * +----------------------------------------------+------+
501 * 8 | Header Buffer Address [63:1] | DD |
502 * +-----------------------------------------------------+
503 *
504 *
505 * Advanced Receive Descriptor (Write-Back) Format
506 *
507 * 63 48 47 32 31 30 21 20 17 16 4 3 0
508 * +------------------------------------------------------+
509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
510 * | Checksum Ident | | | | Type | Type |
511 * +------------------------------------------------------+
512 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
513 * +------------------------------------------------------+
514 * 63 48 47 32 31 20 19 0
515 */
516
517 for (n = 0; n < adapter->num_rx_queues; n++) {
518 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 519 pr_info("------------------------------------\n");
520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 526
527 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 528 const char *next_desc;
06034649
AD		 529 struct igb_rx_buffer *buffer_info;
530 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 531 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 532 u0 = (struct my_u0 *)rx_desc;
533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 534
535 if (i == rx_ring->next_to_use)
536 next_desc = " NTU";
537 else if (i == rx_ring->next_to_clean)
538 next_desc = " NTC";
539 else
540 next_desc = "";
541
c97ec42a
TI		 542 if (staterr & E1000_RXD_STAT_DD) {
543 /* Descriptor Done */
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
545 "RWB", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
1a1c225b 548 next_desc);
c97ec42a 549 } else {
1a1c225b
AD		 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
551 "R ", i,
c97ec42a
TI		 552 le64_to_cpu(u0->a),
553 le64_to_cpu(u0->b),
554 (u64)buffer_info->dma,
1a1c225b 555 next_desc);
c97ec42a 556
b669588a 557 if (netif_msg_pktdata(adapter) &&
1a1c225b 558 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 559 print_hex_dump(KERN_INFO, "",
560 DUMP_PREFIX_ADDRESS,
561 16, 1,
b669588a
ET		 562 page_address(buffer_info->page) +
563 buffer_info->page_offset,
de78d1f9 564 IGB_RX_BUFSZ, true);
c97ec42a
TI		 565 }
566 }
c97ec42a
TI		 567 }
568 }
569
570exit:
571 return;
572}
573
b980ac18
JK		 574/**
575 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 576 * @hw: pointer to hardware structure
577 * @i2cctl: Current value of I2CCTL register
578 *
579 * Returns the I2C data bit value
b980ac18 580 **/
441fc6fd
CW		 581static int igb_get_i2c_data(void *data)
582{
583 struct igb_adapter *adapter = (struct igb_adapter *)data;
584 struct e1000_hw *hw = &adapter->hw;
585 s32 i2cctl = rd32(E1000_I2CPARAMS);
586
587 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
588}
589
b980ac18
JK		 590/**
591 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 592 * @data: pointer to hardware structure
593 * @state: I2C data value (0 or 1) to set
594 *
595 * Sets the I2C data bit
b980ac18 596 **/
441fc6fd
CW		 597static void igb_set_i2c_data(void *data, int state)
598{
599 struct igb_adapter *adapter = (struct igb_adapter *)data;
600 struct e1000_hw *hw = &adapter->hw;
601 s32 i2cctl = rd32(E1000_I2CPARAMS);
602
603 if (state)
604 i2cctl |= E1000_I2C_DATA_OUT;
605 else
606 i2cctl &= ~E1000_I2C_DATA_OUT;
607
608 i2cctl &= ~E1000_I2C_DATA_OE_N;
609 i2cctl |= E1000_I2C_CLK_OE_N;
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612
613}
614
b980ac18
JK		 615/**
616 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 617 * @data: pointer to hardware structure
618 * @state: state to set clock
619 *
620 * Sets the I2C clock line to state
b980ac18 621 **/
441fc6fd
CW		 622static void igb_set_i2c_clk(void *data, int state)
623{
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 if (state) {
629 i2cctl |= E1000_I2C_CLK_OUT;
630 i2cctl &= ~E1000_I2C_CLK_OE_N;
631 } else {
632 i2cctl &= ~E1000_I2C_CLK_OUT;
633 i2cctl &= ~E1000_I2C_CLK_OE_N;
634 }
635 wr32(E1000_I2CPARAMS, i2cctl);
636 wrfl();
637}
638
b980ac18
JK		 639/**
640 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 641 * @data: pointer to hardware structure
642 *
643 * Gets the I2C clock state
b980ac18 644 **/
441fc6fd
CW		 645static int igb_get_i2c_clk(void *data)
646{
647 struct igb_adapter *adapter = (struct igb_adapter *)data;
648 struct e1000_hw *hw = &adapter->hw;
649 s32 i2cctl = rd32(E1000_I2CPARAMS);
650
651 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
652}
653
654static const struct i2c_algo_bit_data igb_i2c_algo = {
655 .setsda = igb_set_i2c_data,
656 .setscl = igb_set_i2c_clk,
657 .getsda = igb_get_i2c_data,
658 .getscl = igb_get_i2c_clk,
659 .udelay = 5,
660 .timeout = 20,
661};
662
9d5c8243 663/**
b980ac18
JK		 664 * igb_get_hw_dev - return device
665 * @hw: pointer to hardware structure
666 *
667 * used by hardware layer to print debugging information
9d5c8243 668 **/
c041076a 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 670{
671 struct igb_adapter *adapter = hw->back;
c041076a 672 return adapter->netdev;
9d5c8243 673}
38c845c7 674
9d5c8243 675/**
b980ac18 676 * igb_init_module - Driver Registration Routine
9d5c8243 677 *
b980ac18
JK		 678 * igb_init_module is the first routine called when the driver is
679 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 680 **/
681static int __init igb_init_module(void)
682{
683 int ret;
876d2d6f 684 pr_info("%s - version %s\n",
9d5c8243
AK		 685 igb_driver_string, igb_driver_version);
686
876d2d6f 687 pr_info("%s\n", igb_copyright);
9d5c8243 688
421e02f0 689#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 690 dca_register_notify(&dca_notifier);
691#endif
bbd98fe4 692 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 693 return ret;
694}
695
696module_init(igb_init_module);
697
698/**
b980ac18 699 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 700 *
b980ac18
JK		 701 * igb_exit_module is called just before the driver is removed
702 * from memory.
9d5c8243
AK		 703 **/
704static void __exit igb_exit_module(void)
705{
421e02f0 706#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 707 dca_unregister_notify(&dca_notifier);
708#endif
9d5c8243
AK		 709 pci_unregister_driver(&igb_driver);
710}
711
712module_exit(igb_exit_module);
713
26bc19ec
AD		 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
715/**
b980ac18
JK		 716 * igb_cache_ring_register - Descriptor ring to register mapping
717 * @adapter: board private structure to initialize
26bc19ec 718 *
b980ac18
JK		 719 * Once we know the feature-set enabled for the device, we'll cache
720 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 721 **/
722static void igb_cache_ring_register(struct igb_adapter *adapter)
723{
ee1b9f06 724 int i = 0, j = 0;
047e0030 725 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 726
727 switch (adapter->hw.mac.type) {
728 case e1000_82576:
729 /* The queues are allocated for virtualization such that VF 0
730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
731 * In order to avoid collision we start at the first free queue
732 * and continue consuming queues in the same sequence
733 */
ee1b9f06 734 if (adapter->vfs_allocated_count) {
a99955fc 735 for (; i < adapter->rss_queues; i++)
3025a446 736 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 737 Q_IDX_82576(i);
ee1b9f06 738 }
26bc19ec 739 case e1000_82575:
55cac248 740 case e1000_82580:
d2ba2ed8 741 case e1000_i350:
ceb5f13b 742 case e1000_i354:
f96a8a0b
CW		 743 case e1000_i210:
744 case e1000_i211:
26bc19ec 745 default:
ee1b9f06 746 for (; i < adapter->num_rx_queues; i++)
3025a446 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 748 for (; j < adapter->num_tx_queues; j++)
3025a446 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 750 break;
751 }
752}
753
4be000c8
AD		 754/**
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
760 *
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
765 **/
766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
768{
769 u32 ivar = array_rd32(E1000_IVAR0, index);
770
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
773
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
776
777 array_wr32(E1000_IVAR0, index, ivar);
778}
779
9d5c8243 780#define IGB_N0_QUEUE -1
047e0030 781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 782{
047e0030 783 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 784 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
4be000c8 787 u32 msixbm = 0;
047e0030 788
0ba82994
AD		 789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 793
794 switch (hw->mac.type) {
795 case e1000_82575:
9d5c8243 796 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
800 */
047e0030 801 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 803 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 805 if (!adapter->msix_entries && msix_vector == 0)
806 msixbm |= E1000_EIMS_OTHER;
9d5c8243 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 808 q_vector->eims_value = msixbm;
2d064c06
AD		 809 break;
810 case e1000_82576:
b980ac18 811 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
814 * column offset.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 rx_queue & 0x7,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
822 tx_queue & 0x7,
823 ((tx_queue & 0x8) << 1) + 8);
047e0030 824 q_vector->eims_value = 1 << msix_vector;
2d064c06 825 break;
55cac248 826 case e1000_82580:
d2ba2ed8 827 case e1000_i350:
ceb5f13b 828 case e1000_i354:
f96a8a0b
CW		 829 case e1000_i210:
830 case e1000_i211:
b980ac18 831 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
835 * row index.
836 */
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
839 rx_queue >> 1,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
843 tx_queue >> 1,
844 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 845 q_vector->eims_value = 1 << msix_vector;
846 break;
2d064c06
AD		 847 default:
848 BUG();
849 break;
850 }
26b39276
AD		 851
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
854
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
9d5c8243
AK		 857}
858
859/**
b980ac18
JK		 860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
9d5c8243 862 *
b980ac18
JK		 863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
9d5c8243
AK		 865 **/
866static void igb_configure_msix(struct igb_adapter *adapter)
867{
868 u32 tmp;
869 int i, vector = 0;
870 struct e1000_hw *hw = &adapter->hw;
871
872 adapter->eims_enable_mask = 0;
9d5c8243
AK		 873
874 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 875 switch (hw->mac.type) {
876 case e1000_82575:
9d5c8243
AK		 877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
880
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
884
885 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 886
887 /* enable msix_other interrupt */
b980ac18 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 889 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 890
2d064c06
AD		 891 break;
892
893 case e1000_82576:
55cac248 894 case e1000_82580:
d2ba2ed8 895 case e1000_i350:
ceb5f13b 896 case e1000_i354:
f96a8a0b
CW		 897 case e1000_i210:
898 case e1000_i211:
047e0030 899 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 900 * won't stick. And it will take days to debug.
901 */
047e0030 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
904 E1000_GPIE_NSICR);
047e0030
AD		 905
906 /* enable msix_other interrupt */
907 adapter->eims_other = 1 << vector;
2d064c06 908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 909
047e0030 910 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 911 break;
912 default:
913 /* do nothing, since nothing else supports MSI-X */
914 break;
915 } /* switch (hw->mac.type) */
047e0030
AD		 916
917 adapter->eims_enable_mask |= adapter->eims_other;
918
26b39276
AD		 919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 921
9d5c8243
AK		 922 wrfl();
923}
924
925/**
b980ac18
JK		 926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
9d5c8243 928 *
b980ac18
JK		 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
930 * kernel.
9d5c8243
AK		 931 **/
932static int igb_request_msix(struct igb_adapter *adapter)
933{
934 struct net_device *netdev = adapter->netdev;
047e0030 935 struct e1000_hw *hw = &adapter->hw;
52285b76 936 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 937
047e0030 938 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 939 igb_msix_other, 0, netdev->name, adapter);
047e0030 940 if (err)
52285b76 941 goto err_out;
047e0030
AD		 942
943 for (i = 0; i < adapter->num_q_vectors; i++) {
944 struct igb_q_vector *q_vector = adapter->q_vector[i];
945
52285b76
SA		 946 vector++;
947
047e0030
AD		 948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
949
0ba82994 950 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 952 q_vector->rx.ring->queue_index);
953 else if (q_vector->tx.ring)
047e0030 954 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 955 q_vector->tx.ring->queue_index);
956 else if (q_vector->rx.ring)
047e0030 957 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 958 q_vector->rx.ring->queue_index);
9d5c8243 959 else
047e0030
AD		 960 sprintf(q_vector->name, "%s-unused", netdev->name);
961
9d5c8243 962 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 963 igb_msix_ring, 0, q_vector->name,
964 q_vector);
9d5c8243 965 if (err)
52285b76 966 goto err_free;
9d5c8243
AK		 967 }
968
9d5c8243
AK		 969 igb_configure_msix(adapter);
970 return 0;
52285b76
SA		 971
972err_free:
973 /* free already assigned IRQs */
974 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
975
976 vector--;
977 for (i = 0; i < vector; i++) {
978 free_irq(adapter->msix_entries[free_vector++].vector,
979 adapter->q_vector[i]);
980 }
981err_out:
9d5c8243
AK		 982 return err;
983}
984
985static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
986{
987 if (adapter->msix_entries) {
988 pci_disable_msix(adapter->pdev);
989 kfree(adapter->msix_entries);
990 adapter->msix_entries = NULL;
047e0030 991 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 992 pci_disable_msi(adapter->pdev);
047e0030 993 }
9d5c8243
AK		 994}
995
5536d210 996/**
b980ac18
JK		 997 * igb_free_q_vector - Free memory allocated for specific interrupt vector
998 * @adapter: board private structure to initialize
999 * @v_idx: Index of vector to be freed
5536d210 1000 *
b980ac18
JK		 1001 * This function frees the memory allocated to the q_vector. In addition if
1002 * NAPI is enabled it will delete any references to the NAPI struct prior
1003 * to freeing the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009 if (q_vector->tx.ring)
1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1011
1012 if (q_vector->rx.ring)
1013 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1014
1015 adapter->q_vector[v_idx] = NULL;
1016 netif_napi_del(&q_vector->napi);
1017
7f90128e 1018 /* igb_get_stats64() might access the rings on this vector,
5536d210
AD		 1019 * we must wait a grace period before freeing it.
1020 */
1021 kfree_rcu(q_vector, rcu);
1022}
1023
047e0030 1024/**
b980ac18
JK		 1025 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1026 * @adapter: board private structure to initialize
047e0030 1027 *
b980ac18
JK		 1028 * This function frees the memory allocated to the q_vectors. In addition if
1029 * NAPI is enabled it will delete any references to the NAPI struct prior
1030 * to freeing the q_vector.
047e0030
AD		 1031 **/
1032static void igb_free_q_vectors(struct igb_adapter *adapter)
1033{
5536d210
AD		 1034 int v_idx = adapter->num_q_vectors;
1035
1036 adapter->num_tx_queues = 0;
1037 adapter->num_rx_queues = 0;
047e0030 1038 adapter->num_q_vectors = 0;
5536d210
AD		 1039
1040 while (v_idx--)
1041 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1042}
1043
1044/**
b980ac18
JK		 1045 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1046 * @adapter: board private structure to initialize
047e0030 1047 *
b980ac18
JK		 1048 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1049 * MSI-X interrupts allocated.
047e0030
AD		 1050 */
1051static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1052{
047e0030
AD		 1053 igb_free_q_vectors(adapter);
1054 igb_reset_interrupt_capability(adapter);
1055}
9d5c8243
AK		 1056
1057/**
b980ac18
JK		 1058 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1059 * @adapter: board private structure to initialize
1060 * @msix: boolean value of MSIX capability
9d5c8243 1061 *
b980ac18
JK		 1062 * Attempt to configure interrupts using the best available
1063 * capabilities of the hardware and kernel.
9d5c8243 1064 **/
53c7d064 1065static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1066{
1067 int err;
1068 int numvecs, i;
1069
53c7d064
SA		 1070 if (!msix)
1071 goto msi_only;
1072
83b7180d 1073 /* Number of supported queues. */
a99955fc 1074 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1075 if (adapter->vfs_allocated_count)
1076 adapter->num_tx_queues = 1;
1077 else
1078 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1079
b980ac18 1080 /* start with one vector for every Rx queue */
047e0030
AD		 1081 numvecs = adapter->num_rx_queues;
1082
b980ac18 1083 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1084 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1085 numvecs += adapter->num_tx_queues;
047e0030
AD		 1086
1087 /* store the number of vectors reserved for queues */
1088 adapter->num_q_vectors = numvecs;
1089
1090 /* add 1 vector for link status interrupts */
1091 numvecs++;
9d5c8243
AK		 1092 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1093 GFP_KERNEL);
f96a8a0b 1094
9d5c8243
AK		 1095 if (!adapter->msix_entries)
1096 goto msi_only;
1097
1098 for (i = 0; i < numvecs; i++)
1099 adapter->msix_entries[i].entry = i;
1100
1101 err = pci_enable_msix(adapter->pdev,
1102 adapter->msix_entries,
1103 numvecs);
1104 if (err == 0)
0c2cc02e 1105 return;
9d5c8243
AK		 1106
1107 igb_reset_interrupt_capability(adapter);
1108
1109 /* If we can't do MSI-X, try MSI */
1110msi_only:
2a3abf6d
AD		 1111#ifdef CONFIG_PCI_IOV
1112 /* disable SR-IOV for non MSI-X configurations */
1113 if (adapter->vf_data) {
1114 struct e1000_hw *hw = &adapter->hw;
1115 /* disable iov and allow time for transactions to clear */
1116 pci_disable_sriov(adapter->pdev);
1117 msleep(500);
1118
1119 kfree(adapter->vf_data);
1120 adapter->vf_data = NULL;
1121 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1122 wrfl();
2a3abf6d
AD		 1123 msleep(100);
1124 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1125 }
1126#endif
4fc82adf 1127 adapter->vfs_allocated_count = 0;
a99955fc 1128 adapter->rss_queues = 1;
4fc82adf 1129 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1130 adapter->num_rx_queues = 1;
661086df 1131 adapter->num_tx_queues = 1;
047e0030 1132 adapter->num_q_vectors = 1;
9d5c8243 1133 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1134 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1135}
1136
5536d210
AD		 1137static void igb_add_ring(struct igb_ring *ring,
1138 struct igb_ring_container *head)
1139{
1140 head->ring = ring;
1141 head->count++;
1142}
1143
047e0030 1144/**
b980ac18
JK		 1145 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1146 * @adapter: board private structure to initialize
1147 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1148 * @v_idx: index of vector in adapter struct
1149 * @txr_count: total number of Tx rings to allocate
1150 * @txr_idx: index of first Tx ring to allocate
1151 * @rxr_count: total number of Rx rings to allocate
1152 * @rxr_idx: index of first Rx ring to allocate
047e0030 1153 *
b980ac18 1154 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1155 **/
5536d210
AD		 1156static int igb_alloc_q_vector(struct igb_adapter *adapter,
1157 int v_count, int v_idx,
1158 int txr_count, int txr_idx,
1159 int rxr_count, int rxr_idx)
047e0030
AD		 1160{
1161 struct igb_q_vector *q_vector;
5536d210
AD		 1162 struct igb_ring *ring;
1163 int ring_count, size;
047e0030 1164
5536d210
AD		 1165 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1166 if (txr_count > 1 || rxr_count > 1)
1167 return -ENOMEM;
1168
1169 ring_count = txr_count + rxr_count;
1170 size = sizeof(struct igb_q_vector) +
1171 (sizeof(struct igb_ring) * ring_count);
1172
1173 /* allocate q_vector and rings */
1174 q_vector = kzalloc(size, GFP_KERNEL);
1175 if (!q_vector)
1176 return -ENOMEM;
1177
1178 /* initialize NAPI */
1179 netif_napi_add(adapter->netdev, &q_vector->napi,
1180 igb_poll, 64);
1181
1182 /* tie q_vector and adapter together */
1183 adapter->q_vector[v_idx] = q_vector;
1184 q_vector->adapter = adapter;
1185
1186 /* initialize work limits */
1187 q_vector->tx.work_limit = adapter->tx_work_limit;
1188
1189 /* initialize ITR configuration */
1190 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1191 q_vector->itr_val = IGB_START_ITR;
1192
1193 /* initialize pointer to rings */
1194 ring = q_vector->ring;
1195
4e227667
AD		 1196 /* intialize ITR */
1197 if (rxr_count) {
1198 /* rx or rx/tx vector */
1199 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1200 q_vector->itr_val = adapter->rx_itr_setting;
1201 } else {
1202 /* tx only vector */
1203 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1204 q_vector->itr_val = adapter->tx_itr_setting;
1205 }
1206
5536d210
AD		 1207 if (txr_count) {
1208 /* assign generic ring traits */
1209 ring->dev = &adapter->pdev->dev;
1210 ring->netdev = adapter->netdev;
1211
1212 /* configure backlink on ring */
1213 ring->q_vector = q_vector;
1214
1215 /* update q_vector Tx values */
1216 igb_add_ring(ring, &q_vector->tx);
1217
1218 /* For 82575, context index must be unique per ring. */
1219 if (adapter->hw.mac.type == e1000_82575)
1220 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1221
1222 /* apply Tx specific ring traits */
1223 ring->count = adapter->tx_ring_count;
1224 ring->queue_index = txr_idx;
1225
1226 /* assign ring to adapter */
1227 adapter->tx_ring[txr_idx] = ring;
1228
1229 /* push pointer to next ring */
1230 ring++;
047e0030 1231 }
81c2fc22 1232
5536d210
AD		 1233 if (rxr_count) {
1234 /* assign generic ring traits */
1235 ring->dev = &adapter->pdev->dev;
1236 ring->netdev = adapter->netdev;
047e0030 1237
5536d210
AD		 1238 /* configure backlink on ring */
1239 ring->q_vector = q_vector;
047e0030 1240
5536d210
AD		 1241 /* update q_vector Rx values */
1242 igb_add_ring(ring, &q_vector->rx);
047e0030 1243
5536d210
AD		 1244 /* set flag indicating ring supports SCTP checksum offload */
1245 if (adapter->hw.mac.type >= e1000_82576)
1246 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1247
ceb5f13b
CW		 1248 /*
1249 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1250 * have the tag byte-swapped.
b980ac18 1251 */
5536d210
AD		 1252 if (adapter->hw.mac.type >= e1000_i350)
1253 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1254
5536d210
AD		 1255 /* apply Rx specific ring traits */
1256 ring->count = adapter->rx_ring_count;
1257 ring->queue_index = rxr_idx;
1258
1259 /* assign ring to adapter */
1260 adapter->rx_ring[rxr_idx] = ring;
1261 }
1262
1263 return 0;
047e0030
AD		 1264}
1265
5536d210 1266
047e0030 1267/**
b980ac18
JK		 1268 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1269 * @adapter: board private structure to initialize
047e0030 1270 *
b980ac18
JK		 1271 * We allocate one q_vector per queue interrupt. If allocation fails we
1272 * return -ENOMEM.
047e0030 1273 **/
5536d210 1274static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1275{
5536d210
AD		 1276 int q_vectors = adapter->num_q_vectors;
1277 int rxr_remaining = adapter->num_rx_queues;
1278 int txr_remaining = adapter->num_tx_queues;
1279 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1280 int err;
047e0030 1281
5536d210
AD		 1282 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1283 for (; rxr_remaining; v_idx++) {
1284 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1285 0, 0, 1, rxr_idx);
047e0030 1286
5536d210
AD		 1287 if (err)
1288 goto err_out;
1289
1290 /* update counts and index */
1291 rxr_remaining--;
1292 rxr_idx++;
047e0030 1293 }
047e0030 1294 }
5536d210
AD		 1295
1296 for (; v_idx < q_vectors; v_idx++) {
1297 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1298 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1299 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1300 tqpv, txr_idx, rqpv, rxr_idx);
1301
1302 if (err)
1303 goto err_out;
1304
1305 /* update counts and index */
1306 rxr_remaining -= rqpv;
1307 txr_remaining -= tqpv;
1308 rxr_idx++;
1309 txr_idx++;
1310 }
1311
047e0030 1312 return 0;
5536d210
AD		 1313
1314err_out:
1315 adapter->num_tx_queues = 0;
1316 adapter->num_rx_queues = 0;
1317 adapter->num_q_vectors = 0;
1318
1319 while (v_idx--)
1320 igb_free_q_vector(adapter, v_idx);
1321
1322 return -ENOMEM;
047e0030
AD		 1323}
1324
1325/**
b980ac18
JK		 1326 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1327 * @adapter: board private structure to initialize
1328 * @msix: boolean value of MSIX capability
047e0030 1329 *
b980ac18 1330 * This function initializes the interrupts and allocates all of the queues.
047e0030 1331 **/
53c7d064 1332static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1333{
1334 struct pci_dev *pdev = adapter->pdev;
1335 int err;
1336
53c7d064 1337 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1338
1339 err = igb_alloc_q_vectors(adapter);
1340 if (err) {
1341 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1342 goto err_alloc_q_vectors;
1343 }
1344
5536d210 1345 igb_cache_ring_register(adapter);
047e0030
AD		 1346
1347 return 0;
5536d210 1348
047e0030
AD		 1349err_alloc_q_vectors:
1350 igb_reset_interrupt_capability(adapter);
1351 return err;
1352}
1353
9d5c8243 1354/**
b980ac18
JK		 1355 * igb_request_irq - initialize interrupts
1356 * @adapter: board private structure to initialize
9d5c8243 1357 *
b980ac18
JK		 1358 * Attempts to configure interrupts using the best available
1359 * capabilities of the hardware and kernel.
9d5c8243
AK		 1360 **/
1361static int igb_request_irq(struct igb_adapter *adapter)
1362{
1363 struct net_device *netdev = adapter->netdev;
047e0030 1364 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1365 int err = 0;
1366
1367 if (adapter->msix_entries) {
1368 err = igb_request_msix(adapter);
844290e5 1369 if (!err)
9d5c8243 1370 goto request_done;
9d5c8243 1371 /* fall back to MSI */
5536d210
AD		 1372 igb_free_all_tx_resources(adapter);
1373 igb_free_all_rx_resources(adapter);
53c7d064 1374
047e0030 1375 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1376 err = igb_init_interrupt_scheme(adapter, false);
1377 if (err)
047e0030 1378 goto request_done;
53c7d064 1379
047e0030
AD		 1380 igb_setup_all_tx_resources(adapter);
1381 igb_setup_all_rx_resources(adapter);
53c7d064 1382 igb_configure(adapter);
9d5c8243 1383 }
844290e5 1384
c74d588e
AD		 1385 igb_assign_vector(adapter->q_vector[0], 0);
1386
7dfc16fa 1387 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1388 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1389 netdev->name, adapter);
9d5c8243
AK		 1390 if (!err)
1391 goto request_done;
047e0030 1392
9d5c8243
AK		 1393 /* fall back to legacy interrupts */
1394 igb_reset_interrupt_capability(adapter);
7dfc16fa 1395 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1396 }
1397
c74d588e 1398 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1399 netdev->name, adapter);
9d5c8243 1400
6cb5e577 1401 if (err)
c74d588e 1402 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1403 err);
9d5c8243
AK		 1404
1405request_done:
1406 return err;
1407}
1408
1409static void igb_free_irq(struct igb_adapter *adapter)
1410{
9d5c8243
AK		 1411 if (adapter->msix_entries) {
1412 int vector = 0, i;
1413
047e0030 1414 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1415
0d1ae7f4 1416 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1417 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1418 adapter->q_vector[i]);
047e0030
AD		 1419 } else {
1420 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1421 }
9d5c8243
AK		 1422}
1423
1424/**
b980ac18
JK		 1425 * igb_irq_disable - Mask off interrupt generation on the NIC
1426 * @adapter: board private structure
9d5c8243
AK		 1427 **/
1428static void igb_irq_disable(struct igb_adapter *adapter)
1429{
1430 struct e1000_hw *hw = &adapter->hw;
1431
b980ac18 1432 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1433 * mapped into these registers and so clearing the bits can cause
1434 * issues on the VF drivers so we only need to clear what we set
1435 */
9d5c8243 1436 if (adapter->msix_entries) {
2dfd1212
AD		 1437 u32 regval = rd32(E1000_EIAM);
1438 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1439 wr32(E1000_EIMC, adapter->eims_enable_mask);
1440 regval = rd32(E1000_EIAC);
1441 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1442 }
844290e5
PW		 1443
1444 wr32(E1000_IAM, 0);
9d5c8243
AK		 1445 wr32(E1000_IMC, ~0);
1446 wrfl();
81a61859
ET		 1447 if (adapter->msix_entries) {
1448 int i;
1449 for (i = 0; i < adapter->num_q_vectors; i++)
1450 synchronize_irq(adapter->msix_entries[i].vector);
1451 } else {
1452 synchronize_irq(adapter->pdev->irq);
1453 }
9d5c8243
AK		 1454}
1455
1456/**
b980ac18
JK		 1457 * igb_irq_enable - Enable default interrupt generation settings
1458 * @adapter: board private structure
9d5c8243
AK		 1459 **/
1460static void igb_irq_enable(struct igb_adapter *adapter)
1461{
1462 struct e1000_hw *hw = &adapter->hw;
1463
1464 if (adapter->msix_entries) {
06218a8d 1465 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1466 u32 regval = rd32(E1000_EIAC);
1467 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1468 regval = rd32(E1000_EIAM);
1469 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1470 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1471 if (adapter->vfs_allocated_count) {
4ae196df 1472 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1473 ims |= E1000_IMS_VMMB;
1474 }
1475 wr32(E1000_IMS, ims);
844290e5 1476 } else {
55cac248
AD		 1477 wr32(E1000_IMS, IMS_ENABLE_MASK |
1478 E1000_IMS_DRSTA);
1479 wr32(E1000_IAM, IMS_ENABLE_MASK |
1480 E1000_IMS_DRSTA);
844290e5 1481 }
9d5c8243
AK		 1482}
1483
1484static void igb_update_mng_vlan(struct igb_adapter *adapter)
1485{
51466239 1486 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1487 u16 vid = adapter->hw.mng_cookie.vlan_id;
1488 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1489
1490 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1491 /* add VID to filter table */
1492 igb_vfta_set(hw, vid, true);
1493 adapter->mng_vlan_id = vid;
1494 } else {
1495 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1496 }
1497
1498 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1499 (vid != old_vid) &&
b2cb09b1 1500 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1501 /* remove VID from filter table */
1502 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1503 }
1504}
1505
1506/**
b980ac18
JK		 1507 * igb_release_hw_control - release control of the h/w to f/w
1508 * @adapter: address of board private structure
9d5c8243 1509 *
b980ac18
JK		 1510 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1511 * For ASF and Pass Through versions of f/w this means that the
1512 * driver is no longer loaded.
9d5c8243
AK		 1513 **/
1514static void igb_release_hw_control(struct igb_adapter *adapter)
1515{
1516 struct e1000_hw *hw = &adapter->hw;
1517 u32 ctrl_ext;
1518
1519 /* Let firmware take over control of h/w */
1520 ctrl_ext = rd32(E1000_CTRL_EXT);
1521 wr32(E1000_CTRL_EXT,
1522 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1523}
1524
9d5c8243 1525/**
b980ac18
JK		 1526 * igb_get_hw_control - get control of the h/w from f/w
1527 * @adapter: address of board private structure
9d5c8243 1528 *
b980ac18
JK		 1529 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1530 * For ASF and Pass Through versions of f/w this means that
1531 * the driver is loaded.
9d5c8243
AK		 1532 **/
1533static void igb_get_hw_control(struct igb_adapter *adapter)
1534{
1535 struct e1000_hw *hw = &adapter->hw;
1536 u32 ctrl_ext;
1537
1538 /* Let firmware know the driver has taken over */
1539 ctrl_ext = rd32(E1000_CTRL_EXT);
1540 wr32(E1000_CTRL_EXT,
1541 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1542}
1543
9d5c8243 1544/**
b980ac18
JK		 1545 * igb_configure - configure the hardware for RX and TX
1546 * @adapter: private board structure
9d5c8243
AK		 1547 **/
1548static void igb_configure(struct igb_adapter *adapter)
1549{
1550 struct net_device *netdev = adapter->netdev;
1551 int i;
1552
1553 igb_get_hw_control(adapter);
ff41f8dc 1554 igb_set_rx_mode(netdev);
9d5c8243
AK		 1555
1556 igb_restore_vlan(adapter);
9d5c8243 1557
85b430b4 1558 igb_setup_tctl(adapter);
06cf2666 1559 igb_setup_mrqc(adapter);
9d5c8243 1560 igb_setup_rctl(adapter);
85b430b4
AD		 1561
1562 igb_configure_tx(adapter);
9d5c8243 1563 igb_configure_rx(adapter);
662d7205
AD		 1564
1565 igb_rx_fifo_flush_82575(&adapter->hw);
1566
c493ea45 1567 /* call igb_desc_unused which always leaves
9d5c8243 1568 * at least 1 descriptor unused to make sure
b980ac18
JK		 1569 * next_to_use != next_to_clean
1570 */
9d5c8243 1571 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1572 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1573 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1574 }
9d5c8243
AK		 1575}
1576
88a268c1 1577/**
b980ac18
JK		 1578 * igb_power_up_link - Power up the phy/serdes link
1579 * @adapter: address of board private structure
88a268c1
NN		 1580 **/
1581void igb_power_up_link(struct igb_adapter *adapter)
1582{
76886596
AA		 1583 igb_reset_phy(&adapter->hw);
1584
88a268c1
NN		 1585 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1586 igb_power_up_phy_copper(&adapter->hw);
1587 else
1588 igb_power_up_serdes_link_82575(&adapter->hw);
1589}
1590
1591/**
b980ac18
JK		 1592 * igb_power_down_link - Power down the phy/serdes link
1593 * @adapter: address of board private structure
88a268c1
NN		 1594 */
1595static void igb_power_down_link(struct igb_adapter *adapter)
1596{
1597 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1598 igb_power_down_phy_copper_82575(&adapter->hw);
1599 else
1600 igb_shutdown_serdes_link_82575(&adapter->hw);
1601}
9d5c8243
AK		 1602
1603/**
b980ac18
JK		 1604 * igb_up - Open the interface and prepare it to handle traffic
1605 * @adapter: board private structure
9d5c8243 1606 **/
9d5c8243
AK		 1607int igb_up(struct igb_adapter *adapter)
1608{
1609 struct e1000_hw *hw = &adapter->hw;
1610 int i;
1611
1612 /* hardware has been reset, we need to reload some things */
1613 igb_configure(adapter);
1614
1615 clear_bit(__IGB_DOWN, &adapter->state);
1616
0d1ae7f4
AD		 1617 for (i = 0; i < adapter->num_q_vectors; i++)
1618 napi_enable(&(adapter->q_vector[i]->napi));
1619
844290e5 1620 if (adapter->msix_entries)
9d5c8243 1621 igb_configure_msix(adapter);
feeb2721
AD		 1622 else
1623 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1624
1625 /* Clear any pending interrupts. */
1626 rd32(E1000_ICR);
1627 igb_irq_enable(adapter);
1628
d4960307
AD		 1629 /* notify VFs that reset has been completed */
1630 if (adapter->vfs_allocated_count) {
1631 u32 reg_data = rd32(E1000_CTRL_EXT);
1632 reg_data |= E1000_CTRL_EXT_PFRSTD;
1633 wr32(E1000_CTRL_EXT, reg_data);
1634 }
1635
4cb9be7a
JB		 1636 netif_tx_start_all_queues(adapter->netdev);
1637
25568a53
AD		 1638 /* start the watchdog. */
1639 hw->mac.get_link_status = 1;
1640 schedule_work(&adapter->watchdog_task);
1641
9d5c8243
AK		 1642 return 0;
1643}
1644
1645void igb_down(struct igb_adapter *adapter)
1646{
9d5c8243 1647 struct net_device *netdev = adapter->netdev;
330a6d6a 1648 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1649 u32 tctl, rctl;
1650 int i;
1651
1652 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1653 * reschedule our watchdog timer
1654 */
9d5c8243
AK		 1655 set_bit(__IGB_DOWN, &adapter->state);
1656
1657 /* disable receives in the hardware */
1658 rctl = rd32(E1000_RCTL);
1659 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1660 /* flush and sleep below */
1661
fd2ea0a7 1662 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1663
1664 /* disable transmits in the hardware */
1665 tctl = rd32(E1000_TCTL);
1666 tctl &= ~E1000_TCTL_EN;
1667 wr32(E1000_TCTL, tctl);
1668 /* flush both disables and wait for them to finish */
1669 wrfl();
1670 msleep(10);
1671
41f149a2
CW		 1672 igb_irq_disable(adapter);
1673
1674 for (i = 0; i < adapter->num_q_vectors; i++) {
1675 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1676 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1677 }
9d5c8243 1678
9d5c8243
AK		 1679
1680 del_timer_sync(&adapter->watchdog_timer);
1681 del_timer_sync(&adapter->phy_info_timer);
1682
9d5c8243 1683 netif_carrier_off(netdev);
04fe6358
AD		 1684
1685 /* record the stats before reset*/
12dcd86b
ED		 1686 spin_lock(&adapter->stats64_lock);
1687 igb_update_stats(adapter, &adapter->stats64);
1688 spin_unlock(&adapter->stats64_lock);
04fe6358 1689
9d5c8243
AK		 1690 adapter->link_speed = 0;
1691 adapter->link_duplex = 0;
1692
3023682e
JK		 1693 if (!pci_channel_offline(adapter->pdev))
1694 igb_reset(adapter);
9d5c8243
AK		 1695 igb_clean_all_tx_rings(adapter);
1696 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1697#ifdef CONFIG_IGB_DCA
1698
1699 /* since we reset the hardware DCA settings were cleared */
1700 igb_setup_dca(adapter);
1701#endif
9d5c8243
AK		 1702}
1703
1704void igb_reinit_locked(struct igb_adapter *adapter)
1705{
1706 WARN_ON(in_interrupt());
1707 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1708 msleep(1);
1709 igb_down(adapter);
1710 igb_up(adapter);
1711 clear_bit(__IGB_RESETTING, &adapter->state);
1712}
1713
1714void igb_reset(struct igb_adapter *adapter)
1715{
090b1795 1716 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1717 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1718 struct e1000_mac_info *mac = &hw->mac;
1719 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1720 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1721
1722 /* Repartition Pba for greater than 9k mtu
1723 * To take effect CTRL.RST is required.
1724 */
fa4dfae0 1725 switch (mac->type) {
d2ba2ed8 1726 case e1000_i350:
ceb5f13b 1727 case e1000_i354:
55cac248
AD		 1728 case e1000_82580:
1729 pba = rd32(E1000_RXPBS);
1730 pba = igb_rxpbs_adjust_82580(pba);
1731 break;
fa4dfae0 1732 case e1000_82576:
d249be54
AD		 1733 pba = rd32(E1000_RXPBS);
1734 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1735 break;
1736 case e1000_82575:
f96a8a0b
CW		 1737 case e1000_i210:
1738 case e1000_i211:
fa4dfae0
AD		 1739 default:
1740 pba = E1000_PBA_34K;
1741 break;
2d064c06 1742 }
9d5c8243 1743
2d064c06
AD		 1744 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1745 (mac->type < e1000_82576)) {
9d5c8243
AK		 1746 /* adjust PBA for jumbo frames */
1747 wr32(E1000_PBA, pba);
1748
1749 /* To maintain wire speed transmits, the Tx FIFO should be
1750 * large enough to accommodate two full transmit packets,
1751 * rounded up to the next 1KB and expressed in KB. Likewise,
1752 * the Rx FIFO should be large enough to accommodate at least
1753 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1754 * expressed in KB.
1755 */
9d5c8243
AK		 1756 pba = rd32(E1000_PBA);
1757 /* upper 16 bits has Tx packet buffer allocation size in KB */
1758 tx_space = pba >> 16;
1759 /* lower 16 bits has Rx packet buffer allocation size in KB */
1760 pba &= 0xffff;
b980ac18
JK		 1761 /* the Tx fifo also stores 16 bytes of information about the Tx
1762 * but don't include ethernet FCS because hardware appends it
1763 */
9d5c8243 1764 min_tx_space = (adapter->max_frame_size +
85e8d004 1765 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1766 ETH_FCS_LEN) * 2;
1767 min_tx_space = ALIGN(min_tx_space, 1024);
1768 min_tx_space >>= 10;
1769 /* software strips receive CRC, so leave room for it */
1770 min_rx_space = adapter->max_frame_size;
1771 min_rx_space = ALIGN(min_rx_space, 1024);
1772 min_rx_space >>= 10;
1773
1774 /* If current Tx allocation is less than the min Tx FIFO size,
1775 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1776 * allocation, take space away from current Rx allocation
1777 */
9d5c8243
AK		 1778 if (tx_space < min_tx_space &&
1779 ((min_tx_space - tx_space) < pba)) {
1780 pba = pba - (min_tx_space - tx_space);
1781
b980ac18
JK		 1782 /* if short on Rx space, Rx wins and must trump Tx
1783 * adjustment
1784 */
9d5c8243
AK		 1785 if (pba < min_rx_space)
1786 pba = min_rx_space;
1787 }
2d064c06 1788 wr32(E1000_PBA, pba);
9d5c8243 1789 }
9d5c8243
AK		 1790
1791 /* flow control settings */
1792 /* The high water mark must be low enough to fit one full frame
1793 * (or the size used for early receive) above it in the Rx FIFO.
1794 * Set it to the lower of:
1795 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1796 * - the full Rx FIFO size minus one full frame
1797 */
9d5c8243 1798 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1799 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1800
d48507fe 1801 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1802 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1803 fc->pause_time = 0xFFFF;
1804 fc->send_xon = 1;
0cce119a 1805 fc->current_mode = fc->requested_mode;
9d5c8243 1806
4ae196df
AD		 1807 /* disable receive for all VFs and wait one second */
1808 if (adapter->vfs_allocated_count) {
1809 int i;
1810 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1811 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1812
1813 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1814 igb_ping_all_vfs(adapter);
4ae196df
AD		 1815
1816 /* disable transmits and receives */
1817 wr32(E1000_VFRE, 0);
1818 wr32(E1000_VFTE, 0);
1819 }
1820
9d5c8243 1821 /* Allow time for pending master requests to run */
330a6d6a 1822 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1823 wr32(E1000_WUC, 0);
1824
330a6d6a 1825 if (hw->mac.ops.init_hw(hw))
090b1795 1826 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1827
b980ac18 1828 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1829 * control is off when forcing speed.
1830 */
1831 if (!hw->mac.autoneg)
1832 igb_force_mac_fc(hw);
1833
b6e0c419 1834 igb_init_dmac(adapter, pba);
e428893b
CW		 1835#ifdef CONFIG_IGB_HWMON
1836 /* Re-initialize the thermal sensor on i350 devices. */
1837 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1838 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1839 /* If present, re-initialize the external thermal sensor
1840 * interface.
1841 */
1842 if (adapter->ets)
1843 mac->ops.init_thermal_sensor_thresh(hw);
1844 }
1845 }
1846#endif
88a268c1
NN		 1847 if (!netif_running(adapter->netdev))
1848 igb_power_down_link(adapter);
1849
9d5c8243
AK		 1850 igb_update_mng_vlan(adapter);
1851
1852 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1853 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1854
1f6e8178
MV		 1855 /* Re-enable PTP, where applicable. */
1856 igb_ptp_reset(adapter);
1f6e8178 1857
330a6d6a 1858 igb_get_phy_info(hw);
9d5c8243
AK		 1859}
1860
c8f44aff
MM		 1861static netdev_features_t igb_fix_features(struct net_device *netdev,
1862 netdev_features_t features)
b2cb09b1 1863{
b980ac18
JK		 1864 /* Since there is no support for separate Rx/Tx vlan accel
1865 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 1866 */
f646968f
PM		 1867 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1868 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 1869 else
f646968f 1870 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 1871
1872 return features;
1873}
1874
c8f44aff
MM		 1875static int igb_set_features(struct net_device *netdev,
1876 netdev_features_t features)
ac52caa3 1877{
c8f44aff 1878 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1879 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1880
f646968f 1881 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 1882 igb_vlan_mode(netdev, features);
1883
89eaefb6
BG		 1884 if (!(changed & NETIF_F_RXALL))
1885 return 0;
1886
1887 netdev->features = features;
1888
1889 if (netif_running(netdev))
1890 igb_reinit_locked(adapter);
1891 else
1892 igb_reset(adapter);
1893
ac52caa3
MM		 1894 return 0;
1895}
1896
2e5c6922 1897static const struct net_device_ops igb_netdev_ops = {
559e9c49 1898 .ndo_open = igb_open,
2e5c6922 1899 .ndo_stop = igb_close,
cd392f5c 1900 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1901 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1902 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1903 .ndo_set_mac_address = igb_set_mac,
1904 .ndo_change_mtu = igb_change_mtu,
1905 .ndo_do_ioctl = igb_ioctl,
1906 .ndo_tx_timeout = igb_tx_timeout,
1907 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1908 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1909 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1910 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1911 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1912 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 1913 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 1914 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1915#ifdef CONFIG_NET_POLL_CONTROLLER
1916 .ndo_poll_controller = igb_netpoll,
1917#endif
b2cb09b1
JP		 1918 .ndo_fix_features = igb_fix_features,
1919 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1920};
1921
d67974f0
CW		 1922/**
1923 * igb_set_fw_version - Configure version string for ethtool
1924 * @adapter: adapter struct
d67974f0
CW		 1925 **/
1926void igb_set_fw_version(struct igb_adapter *adapter)
1927{
1928 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1929 struct e1000_fw_version fw;
1930
1931 igb_get_fw_version(hw, &fw);
1932
1933 switch (hw->mac.type) {
7dc98a62 1934 case e1000_i210:
0b1a6f2e 1935 case e1000_i211:
7dc98a62
CW		 1936 if (!(igb_get_flash_presence_i210(hw))) {
1937 snprintf(adapter->fw_version,
1938 sizeof(adapter->fw_version),
1939 "%2d.%2d-%d",
1940 fw.invm_major, fw.invm_minor,
1941 fw.invm_img_type);
1942 break;
1943 }
1944 /* fall through */
0b1a6f2e
CW		 1945 default:
1946 /* if option is rom valid, display its version too */
1947 if (fw.or_valid) {
1948 snprintf(adapter->fw_version,
1949 sizeof(adapter->fw_version),
1950 "%d.%d, 0x%08x, %d.%d.%d",
1951 fw.eep_major, fw.eep_minor, fw.etrack_id,
1952 fw.or_major, fw.or_build, fw.or_patch);
1953 /* no option rom */
7dc98a62 1954 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 1955 snprintf(adapter->fw_version,
7dc98a62
CW		 1956 sizeof(adapter->fw_version),
1957 "%d.%d, 0x%08x",
1958 fw.eep_major, fw.eep_minor, fw.etrack_id);
1959 } else {
1960 snprintf(adapter->fw_version,
1961 sizeof(adapter->fw_version),
1962 "%d.%d.%d",
1963 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 1964 }
1965 break;
d67974f0 1966 }
d67974f0
CW		 1967 return;
1968}
1969
b980ac18
JK		 1970/**
1971 * igb_init_i2c - Init I2C interface
441fc6fd 1972 * @adapter: pointer to adapter structure
b980ac18 1973 **/
441fc6fd
CW		 1974static s32 igb_init_i2c(struct igb_adapter *adapter)
1975{
1976 s32 status = E1000_SUCCESS;
1977
1978 /* I2C interface supported on i350 devices */
1979 if (adapter->hw.mac.type != e1000_i350)
1980 return E1000_SUCCESS;
1981
1982 /* Initialize the i2c bus which is controlled by the registers.
1983 * This bus will use the i2c_algo_bit structue that implements
1984 * the protocol through toggling of the 4 bits in the register.
1985 */
1986 adapter->i2c_adap.owner = THIS_MODULE;
1987 adapter->i2c_algo = igb_i2c_algo;
1988 adapter->i2c_algo.data = adapter;
1989 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1990 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1991 strlcpy(adapter->i2c_adap.name, "igb BB",
1992 sizeof(adapter->i2c_adap.name));
1993 status = i2c_bit_add_bus(&adapter->i2c_adap);
1994 return status;
1995}
1996
9d5c8243 1997/**
b980ac18
JK		 1998 * igb_probe - Device Initialization Routine
1999 * @pdev: PCI device information struct
2000 * @ent: entry in igb_pci_tbl
9d5c8243 2001 *
b980ac18 2002 * Returns 0 on success, negative on failure
9d5c8243 2003 *
b980ac18
JK		 2004 * igb_probe initializes an adapter identified by a pci_dev structure.
2005 * The OS initialization, configuring of the adapter private structure,
2006 * and a hardware reset occur.
9d5c8243 2007 **/
1dd06ae8 2008static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2009{
2010 struct net_device *netdev;
2011 struct igb_adapter *adapter;
2012 struct e1000_hw *hw;
4337e993 2013 u16 eeprom_data = 0;
9835fd73 2014 s32 ret_val;
4337e993 2015 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 2016 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2017 unsigned long mmio_start, mmio_len;
2d6a5e95 2018 int err, pci_using_dac;
9835fd73 2019 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2020
bded64a7
AG		 2021 /* Catch broken hardware that put the wrong VF device ID in
2022 * the PCIe SR-IOV capability.
2023 */
2024 if (pdev->is_virtfn) {
2025 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2026 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2027 return -EINVAL;
2028 }
2029
aed5dec3 2030 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2031 if (err)
2032 return err;
2033
2034 pci_using_dac = 0;
59d71989 2035 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2036 if (!err) {
59d71989 2037 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 2038 if (!err)
2039 pci_using_dac = 1;
2040 } else {
59d71989 2041 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2042 if (err) {
b980ac18
JK		 2043 err = dma_set_coherent_mask(&pdev->dev,
2044 DMA_BIT_MASK(32));
9d5c8243 2045 if (err) {
b980ac18
JK		 2046 dev_err(&pdev->dev,
2047 "No usable DMA configuration, aborting\n");
9d5c8243
AK		 2048 goto err_dma;
2049 }
2050 }
2051 }
2052
aed5dec3 2053 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2054 IORESOURCE_MEM),
2055 igb_driver_name);
9d5c8243
AK		 2056 if (err)
2057 goto err_pci_reg;
2058
19d5afd4 2059 pci_enable_pcie_error_reporting(pdev);
40a914fa 2060
9d5c8243 2061 pci_set_master(pdev);
c682fc23 2062 pci_save_state(pdev);
9d5c8243
AK		 2063
2064 err = -ENOMEM;
1bfaf07b 2065 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2066 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2067 if (!netdev)
2068 goto err_alloc_etherdev;
2069
2070 SET_NETDEV_DEV(netdev, &pdev->dev);
2071
2072 pci_set_drvdata(pdev, netdev);
2073 adapter = netdev_priv(netdev);
2074 adapter->netdev = netdev;
2075 adapter->pdev = pdev;
2076 hw = &adapter->hw;
2077 hw->back = adapter;
b3f4d599 2078 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2079
2080 mmio_start = pci_resource_start(pdev, 0);
2081 mmio_len = pci_resource_len(pdev, 0);
2082
2083 err = -EIO;
28b0759c
AD		 2084 hw->hw_addr = ioremap(mmio_start, mmio_len);
2085 if (!hw->hw_addr)
9d5c8243
AK		 2086 goto err_ioremap;
2087
2e5c6922 2088 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2089 igb_set_ethtool_ops(netdev);
9d5c8243 2090 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2091
2092 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2093
2094 netdev->mem_start = mmio_start;
2095 netdev->mem_end = mmio_start + mmio_len;
2096
9d5c8243
AK		 2097 /* PCI config space info */
2098 hw->vendor_id = pdev->vendor;
2099 hw->device_id = pdev->device;
2100 hw->revision_id = pdev->revision;
2101 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2102 hw->subsystem_device_id = pdev->subsystem_device;
2103
9d5c8243
AK		 2104 /* Copy the default MAC, PHY and NVM function pointers */
2105 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2106 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2107 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2108 /* Initialize skew-specific constants */
2109 err = ei->get_invariants(hw);
2110 if (err)
450c87c8 2111 goto err_sw_init;
9d5c8243 2112
450c87c8 2113 /* setup the private structure */
9d5c8243
AK		 2114 err = igb_sw_init(adapter);
2115 if (err)
2116 goto err_sw_init;
2117
2118 igb_get_bus_info_pcie(hw);
2119
2120 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2121
2122 /* Copper options */
2123 if (hw->phy.media_type == e1000_media_type_copper) {
2124 hw->phy.mdix = AUTO_ALL_MODES;
2125 hw->phy.disable_polarity_correction = false;
2126 hw->phy.ms_type = e1000_ms_hw_default;
2127 }
2128
2129 if (igb_check_reset_block(hw))
2130 dev_info(&pdev->dev,
2131 "PHY reset is blocked due to SOL/IDER session.\n");
2132
b980ac18 2133 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2134 * set by igb_sw_init so we should use an or instead of an
2135 * assignment.
2136 */
2137 netdev->features |= NETIF_F_SG |
2138 NETIF_F_IP_CSUM |
2139 NETIF_F_IPV6_CSUM |
2140 NETIF_F_TSO |
2141 NETIF_F_TSO6 |
2142 NETIF_F_RXHASH |
2143 NETIF_F_RXCSUM |
f646968f
PM		 2144 NETIF_F_HW_VLAN_CTAG_RX |
2145 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2146
2147 /* copy netdev features into list of user selectable features */
2148 netdev->hw_features |= netdev->features;
89eaefb6 2149 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2150
2151 /* set this bit last since it cannot be part of hw_features */
f646968f 2152 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2153
2154 netdev->vlan_features |= NETIF_F_TSO |
2155 NETIF_F_TSO6 |
2156 NETIF_F_IP_CSUM |
2157 NETIF_F_IPV6_CSUM |
2158 NETIF_F_SG;
48f29ffc 2159
6b8f0922
BG		 2160 netdev->priv_flags |= IFF_SUPP_NOFCS;
2161
7b872a55 2162 if (pci_using_dac) {
9d5c8243 2163 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2164 netdev->vlan_features |= NETIF_F_HIGHDMA;
2165 }
9d5c8243 2166
ac52caa3
MM		 2167 if (hw->mac.type >= e1000_82576) {
2168 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2169 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2170 }
b9473560 2171
01789349
JP		 2172 netdev->priv_flags |= IFF_UNICAST_FLT;
2173
330a6d6a 2174 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2175
2176 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2177 * known good starting state
2178 */
9d5c8243
AK		 2179 hw->mac.ops.reset_hw(hw);
2180
ef3a0092
CW		 2181 /* make sure the NVM is good , i211/i210 parts can have special NVM
2182 * that doesn't contain a checksum
f96a8a0b 2183 */
ef3a0092
CW		 2184 switch (hw->mac.type) {
2185 case e1000_i210:
2186 case e1000_i211:
2187 if (igb_get_flash_presence_i210(hw)) {
2188 if (hw->nvm.ops.validate(hw) < 0) {
2189 dev_err(&pdev->dev,
2190 "The NVM Checksum Is Not Valid\n");
2191 err = -EIO;
2192 goto err_eeprom;
2193 }
2194 }
2195 break;
2196 default:
f96a8a0b
CW		 2197 if (hw->nvm.ops.validate(hw) < 0) {
2198 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2199 err = -EIO;
2200 goto err_eeprom;
2201 }
ef3a0092 2202 break;
9d5c8243
AK		 2203 }
2204
2205 /* copy the MAC address out of the NVM */
2206 if (hw->mac.ops.read_mac_addr(hw))
2207 dev_err(&pdev->dev, "NVM Read Error\n");
2208
2209 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2210
aaeb6cdf 2211 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2212 dev_err(&pdev->dev, "Invalid MAC Address\n");
2213 err = -EIO;
2214 goto err_eeprom;
2215 }
2216
d67974f0
CW		 2217 /* get firmware version for ethtool -i */
2218 igb_set_fw_version(adapter);
2219
c061b18d 2220 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2221 (unsigned long) adapter);
c061b18d 2222 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2223 (unsigned long) adapter);
9d5c8243
AK		 2224
2225 INIT_WORK(&adapter->reset_task, igb_reset_task);
2226 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2227
450c87c8 2228 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2229 adapter->fc_autoneg = true;
2230 hw->mac.autoneg = true;
2231 hw->phy.autoneg_advertised = 0x2f;
2232
0cce119a
AD		 2233 hw->fc.requested_mode = e1000_fc_default;
2234 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2235
9d5c8243
AK		 2236 igb_validate_mdi_setting(hw);
2237
63d4a8f9 2238 /* By default, support wake on port A */
a2cf8b6c 2239 if (hw->bus.func == 0)
63d4a8f9
MV		 2240 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2241
2242 /* Check the NVM for wake support on non-port A ports */
2243 if (hw->mac.type >= e1000_82580)
55cac248 2244 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2245 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2246 &eeprom_data);
a2cf8b6c
AD		 2247 else if (hw->bus.func == 1)
2248 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2249
63d4a8f9
MV		 2250 if (eeprom_data & IGB_EEPROM_APME)
2251 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2252
2253 /* now that we have the eeprom settings, apply the special cases where
2254 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2255 * lan on a particular port
2256 */
9d5c8243
AK		 2257 switch (pdev->device) {
2258 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2259 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2260 break;
2261 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2262 case E1000_DEV_ID_82576_FIBER:
2263 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2264 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2265 * regardless of eeprom setting
2266 */
9d5c8243 2267 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2268 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2269 break;
c8ea5ea9 2270 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2271 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2272 /* if quad port adapter, disable WoL on all but port A */
2273 if (global_quad_port_a != 0)
63d4a8f9 2274 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2275 else
2276 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2277 /* Reset for multiple quad port adapters */
2278 if (++global_quad_port_a == 4)
2279 global_quad_port_a = 0;
2280 break;
63d4a8f9
MV		 2281 default:
2282 /* If the device can't wake, don't set software support */
2283 if (!device_can_wakeup(&adapter->pdev->dev))
2284 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2285 }
2286
2287 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2288 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2289 adapter->wol |= E1000_WUFC_MAG;
2290
2291 /* Some vendors want WoL disabled by default, but still supported */
2292 if ((hw->mac.type == e1000_i350) &&
2293 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2294 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2295 adapter->wol = 0;
2296 }
2297
2298 device_set_wakeup_enable(&adapter->pdev->dev,
2299 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2300
2301 /* reset the hardware with the new settings */
2302 igb_reset(adapter);
2303
441fc6fd
CW		 2304 /* Init the I2C interface */
2305 err = igb_init_i2c(adapter);
2306 if (err) {
2307 dev_err(&pdev->dev, "failed to init i2c interface\n");
2308 goto err_eeprom;
2309 }
2310
9d5c8243
AK		 2311 /* let the f/w know that the h/w is now under the control of the
2312 * driver. */
2313 igb_get_hw_control(adapter);
2314
9d5c8243
AK		 2315 strcpy(netdev->name, "eth%d");
2316 err = register_netdev(netdev);
2317 if (err)
2318 goto err_register;
2319
b168dfc5
JB		 2320 /* carrier off reporting is important to ethtool even BEFORE open */
2321 netif_carrier_off(netdev);
2322
421e02f0 2323#ifdef CONFIG_IGB_DCA
bbd98fe4 2324 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2325 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2326 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2327 igb_setup_dca(adapter);
2328 }
fe4506b6 2329
38c845c7 2330#endif
e428893b
CW		 2331#ifdef CONFIG_IGB_HWMON
2332 /* Initialize the thermal sensor on i350 devices. */
2333 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2334 u16 ets_word;
3c89f6d0 2335
b980ac18 2336 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2337 * external thermal sensor.
2338 */
2339 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2340 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2341 adapter->ets = true;
2342 else
2343 adapter->ets = false;
2344 if (igb_sysfs_init(adapter))
2345 dev_err(&pdev->dev,
2346 "failed to allocate sysfs resources\n");
2347 } else {
2348 adapter->ets = false;
2349 }
2350#endif
673b8b70 2351 /* do hw tstamp init after resetting */
7ebae817 2352 igb_ptp_init(adapter);
673b8b70 2353
9d5c8243 2354 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2355 /* print bus type/speed/width info, not applicable to i354 */
2356 if (hw->mac.type != e1000_i354) {
2357 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2358 netdev->name,
2359 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2360 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2361 "unknown"),
2362 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2363 "Width x4" :
2364 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2365 "Width x2" :
2366 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2367 "Width x1" : "unknown"), netdev->dev_addr);
2368 }
9d5c8243 2369
9835fd73
CW		 2370 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2371 if (ret_val)
2372 strcpy(part_str, "Unknown");
2373 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2374 dev_info(&pdev->dev,
2375 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2376 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2377 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2378 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2379 switch (hw->mac.type) {
2380 case e1000_i350:
f96a8a0b
CW		 2381 case e1000_i210:
2382 case e1000_i211:
09b068d4
CW		 2383 igb_set_eee_i350(hw);
2384 break;
ceb5f13b
CW		 2385 case e1000_i354:
2386 if (hw->phy.media_type == e1000_media_type_copper) {
2387 if ((rd32(E1000_CTRL_EXT) &
2388 E1000_CTRL_EXT_LINK_MODE_SGMII))
2389 igb_set_eee_i354(hw);
2390 }
2391 break;
09b068d4
CW		 2392 default:
2393 break;
2394 }
749ab2cd
YZ		 2395
2396 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2397 return 0;
2398
2399err_register:
2400 igb_release_hw_control(adapter);
441fc6fd 2401 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2402err_eeprom:
2403 if (!igb_check_reset_block(hw))
f5f4cf08 2404 igb_reset_phy(hw);
9d5c8243
AK		 2405
2406 if (hw->flash_address)
2407 iounmap(hw->flash_address);
9d5c8243 2408err_sw_init:
047e0030 2409 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2410 iounmap(hw->hw_addr);
2411err_ioremap:
2412 free_netdev(netdev);
2413err_alloc_etherdev:
559e9c49 2414 pci_release_selected_regions(pdev,
b980ac18 2415 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2416err_pci_reg:
2417err_dma:
2418 pci_disable_device(pdev);
2419 return err;
2420}
2421
fa44f2f1
GR		 2422#ifdef CONFIG_PCI_IOV
2423static int igb_disable_sriov(struct pci_dev *pdev)
2424{
2425 struct net_device *netdev = pci_get_drvdata(pdev);
2426 struct igb_adapter *adapter = netdev_priv(netdev);
2427 struct e1000_hw *hw = &adapter->hw;
2428
2429 /* reclaim resources allocated to VFs */
2430 if (adapter->vf_data) {
2431 /* disable iov and allow time for transactions to clear */
b09186d2 2432 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2433 dev_warn(&pdev->dev,
2434 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2435 return -EPERM;
2436 } else {
2437 pci_disable_sriov(pdev);
2438 msleep(500);
2439 }
2440
2441 kfree(adapter->vf_data);
2442 adapter->vf_data = NULL;
2443 adapter->vfs_allocated_count = 0;
2444 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2445 wrfl();
2446 msleep(100);
2447 dev_info(&pdev->dev, "IOV Disabled\n");
2448
2449 /* Re-enable DMA Coalescing flag since IOV is turned off */
2450 adapter->flags |= IGB_FLAG_DMAC;
2451 }
2452
2453 return 0;
2454}
2455
2456static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2457{
2458 struct net_device *netdev = pci_get_drvdata(pdev);
2459 struct igb_adapter *adapter = netdev_priv(netdev);
2460 int old_vfs = pci_num_vf(pdev);
2461 int err = 0;
2462 int i;
2463
50267196
MW		 2464 if (!adapter->msix_entries) {
2465 err = -EPERM;
2466 goto out;
2467 }
2468
fa44f2f1
GR		 2469 if (!num_vfs)
2470 goto out;
2471 else if (old_vfs && old_vfs == num_vfs)
2472 goto out;
2473 else if (old_vfs && old_vfs != num_vfs)
2474 err = igb_disable_sriov(pdev);
2475
2476 if (err)
2477 goto out;
2478
2479 if (num_vfs > 7) {
2480 err = -EPERM;
2481 goto out;
2482 }
2483
2484 adapter->vfs_allocated_count = num_vfs;
2485
2486 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2487 sizeof(struct vf_data_storage), GFP_KERNEL);
2488
2489 /* if allocation failed then we do not support SR-IOV */
2490 if (!adapter->vf_data) {
2491 adapter->vfs_allocated_count = 0;
2492 dev_err(&pdev->dev,
2493 "Unable to allocate memory for VF Data Storage\n");
2494 err = -ENOMEM;
2495 goto out;
2496 }
2497
2498 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2499 if (err)
2500 goto err_out;
2501
2502 dev_info(&pdev->dev, "%d VFs allocated\n",
2503 adapter->vfs_allocated_count);
2504 for (i = 0; i < adapter->vfs_allocated_count; i++)
2505 igb_vf_configure(adapter, i);
2506
2507 /* DMA Coalescing is not supported in IOV mode. */
2508 adapter->flags &= ~IGB_FLAG_DMAC;
2509 goto out;
2510
2511err_out:
2512 kfree(adapter->vf_data);
2513 adapter->vf_data = NULL;
2514 adapter->vfs_allocated_count = 0;
2515out:
2516 return err;
2517}
2518
2519#endif
b980ac18 2520/**
441fc6fd
CW		 2521 * igb_remove_i2c - Cleanup I2C interface
2522 * @adapter: pointer to adapter structure
b980ac18 2523 **/
441fc6fd
CW		 2524static void igb_remove_i2c(struct igb_adapter *adapter)
2525{
441fc6fd
CW		 2526 /* free the adapter bus structure */
2527 i2c_del_adapter(&adapter->i2c_adap);
2528}
2529
9d5c8243 2530/**
b980ac18
JK		 2531 * igb_remove - Device Removal Routine
2532 * @pdev: PCI device information struct
9d5c8243 2533 *
b980ac18
JK		 2534 * igb_remove is called by the PCI subsystem to alert the driver
2535 * that it should release a PCI device. The could be caused by a
2536 * Hot-Plug event, or because the driver is going to be removed from
2537 * memory.
9d5c8243 2538 **/
9f9a12f8 2539static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2540{
2541 struct net_device *netdev = pci_get_drvdata(pdev);
2542 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2543 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2544
749ab2cd 2545 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2546#ifdef CONFIG_IGB_HWMON
2547 igb_sysfs_exit(adapter);
2548#endif
441fc6fd 2549 igb_remove_i2c(adapter);
a79f4f88 2550 igb_ptp_stop(adapter);
b980ac18 2551 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2552 * disable watchdog from being rescheduled.
2553 */
9d5c8243
AK		 2554 set_bit(__IGB_DOWN, &adapter->state);
2555 del_timer_sync(&adapter->watchdog_timer);
2556 del_timer_sync(&adapter->phy_info_timer);
2557
760141a5
TH		 2558 cancel_work_sync(&adapter->reset_task);
2559 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2560
421e02f0 2561#ifdef CONFIG_IGB_DCA
7dfc16fa 2562 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2563 dev_info(&pdev->dev, "DCA disabled\n");
2564 dca_remove_requester(&pdev->dev);
7dfc16fa 2565 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2566 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2567 }
2568#endif
2569
9d5c8243 2570 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2571 * would have already happened in close and is redundant.
2572 */
9d5c8243
AK		 2573 igb_release_hw_control(adapter);
2574
2575 unregister_netdev(netdev);
2576
047e0030 2577 igb_clear_interrupt_scheme(adapter);
9d5c8243 2578
37680117 2579#ifdef CONFIG_PCI_IOV
fa44f2f1 2580 igb_disable_sriov(pdev);
37680117 2581#endif
559e9c49 2582
28b0759c
AD		 2583 iounmap(hw->hw_addr);
2584 if (hw->flash_address)
2585 iounmap(hw->flash_address);
559e9c49 2586 pci_release_selected_regions(pdev,
b980ac18 2587 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2588
1128c756 2589 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2590 free_netdev(netdev);
2591
19d5afd4 2592 pci_disable_pcie_error_reporting(pdev);
40a914fa 2593
9d5c8243
AK		 2594 pci_disable_device(pdev);
2595}
2596
a6b623e0 2597/**
b980ac18
JK		 2598 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2599 * @adapter: board private structure to initialize
a6b623e0 2600 *
b980ac18
JK		 2601 * This function initializes the vf specific data storage and then attempts to
2602 * allocate the VFs. The reason for ordering it this way is because it is much
2603 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2604 * the memory for the VFs.
a6b623e0 2605 **/
9f9a12f8 2606static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2607{
2608#ifdef CONFIG_PCI_IOV
2609 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2610 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2611
f96a8a0b
CW		 2612 /* Virtualization features not supported on i210 family. */
2613 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2614 return;
2615
fa44f2f1 2616 pci_sriov_set_totalvfs(pdev, 7);
d5e51a10 2617 igb_enable_sriov(pdev, max_vfs);
0224d663 2618
a6b623e0
AD		 2619#endif /* CONFIG_PCI_IOV */
2620}
2621
fa44f2f1 2622static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2623{
2624 struct e1000_hw *hw = &adapter->hw;
374a542d 2625 u32 max_rss_queues;
9d5c8243 2626
374a542d 2627 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2628 switch (hw->mac.type) {
374a542d
MV		 2629 case e1000_i211:
2630 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2631 break;
2632 case e1000_82575:
f96a8a0b 2633 case e1000_i210:
374a542d
MV		 2634 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2635 break;
2636 case e1000_i350:
2637 /* I350 cannot do RSS and SR-IOV at the same time */
2638 if (!!adapter->vfs_allocated_count) {
2639 max_rss_queues = 1;
2640 break;
2641 }
2642 /* fall through */
2643 case e1000_82576:
2644 if (!!adapter->vfs_allocated_count) {
2645 max_rss_queues = 2;
2646 break;
2647 }
2648 /* fall through */
2649 case e1000_82580:
ceb5f13b 2650 case e1000_i354:
374a542d
MV		 2651 default:
2652 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2653 break;
374a542d
MV		 2654 }
2655
2656 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2657
2658 /* Determine if we need to pair queues. */
2659 switch (hw->mac.type) {
2660 case e1000_82575:
f96a8a0b 2661 case e1000_i211:
374a542d 2662 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2663 break;
374a542d 2664 case e1000_82576:
b980ac18 2665 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2666 * should pair the queues in order to conserve interrupts due
2667 * to limited supply.
2668 */
2669 if ((adapter->rss_queues > 1) &&
2670 (adapter->vfs_allocated_count > 6))
2671 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2672 /* fall through */
2673 case e1000_82580:
2674 case e1000_i350:
ceb5f13b 2675 case e1000_i354:
374a542d 2676 case e1000_i210:
f96a8a0b 2677 default:
b980ac18 2678 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2679 * order to conserve interrupts due to limited supply.
2680 */
2681 if (adapter->rss_queues > (max_rss_queues / 2))
2682 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2683 break;
2684 }
fa44f2f1
GR		 2685}
2686
2687/**
b980ac18
JK		 2688 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2689 * @adapter: board private structure to initialize
fa44f2f1 2690 *
b980ac18
JK		 2691 * igb_sw_init initializes the Adapter private data structure.
2692 * Fields are initialized based on PCI device information and
2693 * OS network device settings (MTU size).
fa44f2f1
GR		 2694 **/
2695static int igb_sw_init(struct igb_adapter *adapter)
2696{
2697 struct e1000_hw *hw = &adapter->hw;
2698 struct net_device *netdev = adapter->netdev;
2699 struct pci_dev *pdev = adapter->pdev;
2700
2701 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2702
2703 /* set default ring sizes */
2704 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2705 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2706
2707 /* set default ITR values */
2708 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2709 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2710
2711 /* set default work limits */
2712 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2713
2714 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2715 VLAN_HLEN;
2716 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2717
2718 spin_lock_init(&adapter->stats64_lock);
2719#ifdef CONFIG_PCI_IOV
2720 switch (hw->mac.type) {
2721 case e1000_82576:
2722 case e1000_i350:
2723 if (max_vfs > 7) {
2724 dev_warn(&pdev->dev,
2725 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2726 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2727 } else
2728 adapter->vfs_allocated_count = max_vfs;
2729 if (adapter->vfs_allocated_count)
2730 dev_warn(&pdev->dev,
2731 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2732 break;
2733 default:
2734 break;
2735 }
2736#endif /* CONFIG_PCI_IOV */
2737
2738 igb_init_queue_configuration(adapter);
a99955fc 2739
1128c756 2740 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2741 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2742 GFP_ATOMIC);
1128c756 2743
a6b623e0 2744 /* This call may decrease the number of queues */
53c7d064 2745 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2746 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2747 return -ENOMEM;
2748 }
2749
a6b623e0
AD		 2750 igb_probe_vfs(adapter);
2751
9d5c8243
AK		 2752 /* Explicitly disable IRQ since the NIC can be in any state. */
2753 igb_irq_disable(adapter);
2754
f96a8a0b 2755 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2756 adapter->flags &= ~IGB_FLAG_DMAC;
2757
9d5c8243
AK		 2758 set_bit(__IGB_DOWN, &adapter->state);
2759 return 0;
2760}
2761
2762/**
b980ac18
JK		 2763 * igb_open - Called when a network interface is made active
2764 * @netdev: network interface device structure
9d5c8243 2765 *
b980ac18 2766 * Returns 0 on success, negative value on failure
9d5c8243 2767 *
b980ac18
JK		 2768 * The open entry point is called when a network interface is made
2769 * active by the system (IFF_UP). At this point all resources needed
2770 * for transmit and receive operations are allocated, the interrupt
2771 * handler is registered with the OS, the watchdog timer is started,
2772 * and the stack is notified that the interface is ready.
9d5c8243 2773 **/
749ab2cd 2774static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2775{
2776 struct igb_adapter *adapter = netdev_priv(netdev);
2777 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2778 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2779 int err;
2780 int i;
2781
2782 /* disallow open during test */
749ab2cd
YZ		 2783 if (test_bit(__IGB_TESTING, &adapter->state)) {
2784 WARN_ON(resuming);
9d5c8243 2785 return -EBUSY;
749ab2cd
YZ		 2786 }
2787
2788 if (!resuming)
2789 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2790
b168dfc5
JB		 2791 netif_carrier_off(netdev);
2792
9d5c8243
AK		 2793 /* allocate transmit descriptors */
2794 err = igb_setup_all_tx_resources(adapter);
2795 if (err)
2796 goto err_setup_tx;
2797
2798 /* allocate receive descriptors */
2799 err = igb_setup_all_rx_resources(adapter);
2800 if (err)
2801 goto err_setup_rx;
2802
88a268c1 2803 igb_power_up_link(adapter);
9d5c8243 2804
9d5c8243
AK		 2805 /* before we allocate an interrupt, we must be ready to handle it.
2806 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2807 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2808 * clean_rx handler before we do so.
2809 */
9d5c8243
AK		 2810 igb_configure(adapter);
2811
2812 err = igb_request_irq(adapter);
2813 if (err)
2814 goto err_req_irq;
2815
0c2cc02e
AD		 2816 /* Notify the stack of the actual queue counts. */
2817 err = netif_set_real_num_tx_queues(adapter->netdev,
2818 adapter->num_tx_queues);
2819 if (err)
2820 goto err_set_queues;
2821
2822 err = netif_set_real_num_rx_queues(adapter->netdev,
2823 adapter->num_rx_queues);
2824 if (err)
2825 goto err_set_queues;
2826
9d5c8243
AK		 2827 /* From here on the code is the same as igb_up() */
2828 clear_bit(__IGB_DOWN, &adapter->state);
2829
0d1ae7f4
AD		 2830 for (i = 0; i < adapter->num_q_vectors; i++)
2831 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2832
2833 /* Clear any pending interrupts. */
2834 rd32(E1000_ICR);
844290e5
PW		 2835
2836 igb_irq_enable(adapter);
2837
d4960307
AD		 2838 /* notify VFs that reset has been completed */
2839 if (adapter->vfs_allocated_count) {
2840 u32 reg_data = rd32(E1000_CTRL_EXT);
2841 reg_data |= E1000_CTRL_EXT_PFRSTD;
2842 wr32(E1000_CTRL_EXT, reg_data);
2843 }
2844
d55b53ff
JK		 2845 netif_tx_start_all_queues(netdev);
2846
749ab2cd
YZ		 2847 if (!resuming)
2848 pm_runtime_put(&pdev->dev);
2849
25568a53
AD		 2850 /* start the watchdog. */
2851 hw->mac.get_link_status = 1;
2852 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2853
2854 return 0;
2855
0c2cc02e
AD		 2856err_set_queues:
2857 igb_free_irq(adapter);
9d5c8243
AK		 2858err_req_irq:
2859 igb_release_hw_control(adapter);
88a268c1 2860 igb_power_down_link(adapter);
9d5c8243
AK		 2861 igb_free_all_rx_resources(adapter);
2862err_setup_rx:
2863 igb_free_all_tx_resources(adapter);
2864err_setup_tx:
2865 igb_reset(adapter);
749ab2cd
YZ		 2866 if (!resuming)
2867 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2868
2869 return err;
2870}
2871
749ab2cd
YZ		 2872static int igb_open(struct net_device *netdev)
2873{
2874 return __igb_open(netdev, false);
2875}
2876
9d5c8243 2877/**
b980ac18
JK		 2878 * igb_close - Disables a network interface
2879 * @netdev: network interface device structure
9d5c8243 2880 *
b980ac18 2881 * Returns 0, this is not allowed to fail
9d5c8243 2882 *
b980ac18
JK		 2883 * The close entry point is called when an interface is de-activated
2884 * by the OS. The hardware is still under the driver's control, but
2885 * needs to be disabled. A global MAC reset is issued to stop the
2886 * hardware, and all transmit and receive resources are freed.
9d5c8243 2887 **/
749ab2cd 2888static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2889{
2890 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2891 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2892
2893 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2894
749ab2cd
YZ		 2895 if (!suspending)
2896 pm_runtime_get_sync(&pdev->dev);
2897
2898 igb_down(adapter);
9d5c8243
AK		 2899 igb_free_irq(adapter);
2900
2901 igb_free_all_tx_resources(adapter);
2902 igb_free_all_rx_resources(adapter);
2903
749ab2cd
YZ		 2904 if (!suspending)
2905 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2906 return 0;
2907}
2908
749ab2cd
YZ		 2909static int igb_close(struct net_device *netdev)
2910{
2911 return __igb_close(netdev, false);
2912}
2913
9d5c8243 2914/**
b980ac18
JK		 2915 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2916 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 2917 *
b980ac18 2918 * Return 0 on success, negative on failure
9d5c8243 2919 **/
80785298 2920int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2921{
59d71989 2922 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2923 int size;
2924
06034649 2925 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2926
2927 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2928 if (!tx_ring->tx_buffer_info)
9d5c8243 2929 goto err;
9d5c8243
AK		 2930
2931 /* round up to nearest 4K */
85e8d004 2932 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2933 tx_ring->size = ALIGN(tx_ring->size, 4096);
2934
5536d210
AD		 2935 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2936 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2937 if (!tx_ring->desc)
2938 goto err;
2939
9d5c8243
AK		 2940 tx_ring->next_to_use = 0;
2941 tx_ring->next_to_clean = 0;
81c2fc22 2942
9d5c8243
AK		 2943 return 0;
2944
2945err:
06034649 2946 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2947 tx_ring->tx_buffer_info = NULL;
2948 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2949 return -ENOMEM;
2950}
2951
2952/**
b980ac18
JK		 2953 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2954 * (Descriptors) for all queues
2955 * @adapter: board private structure
9d5c8243 2956 *
b980ac18 2957 * Return 0 on success, negative on failure
9d5c8243
AK		 2958 **/
2959static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2960{
439705e1 2961 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2962 int i, err = 0;
2963
2964 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2965 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2966 if (err) {
439705e1 2967 dev_err(&pdev->dev,
9d5c8243
AK		 2968 "Allocation for Tx Queue %u failed\n", i);
2969 for (i--; i >= 0; i--)
3025a446 2970 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2971 break;
2972 }
2973 }
2974
2975 return err;
2976}
2977
2978/**
b980ac18
JK		 2979 * igb_setup_tctl - configure the transmit control registers
2980 * @adapter: Board private structure
9d5c8243 2981 **/
d7ee5b3a 2982void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2983{
9d5c8243
AK		 2984 struct e1000_hw *hw = &adapter->hw;
2985 u32 tctl;
9d5c8243 2986
85b430b4
AD		 2987 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2988 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2989
2990 /* Program the Transmit Control Register */
9d5c8243
AK		 2991 tctl = rd32(E1000_TCTL);
2992 tctl &= ~E1000_TCTL_CT;
2993 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2994 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2995
2996 igb_config_collision_dist(hw);
2997
9d5c8243
AK		 2998 /* Enable transmits */
2999 tctl |= E1000_TCTL_EN;
3000
3001 wr32(E1000_TCTL, tctl);
3002}
3003
85b430b4 3004/**
b980ac18
JK		 3005 * igb_configure_tx_ring - Configure transmit ring after Reset
3006 * @adapter: board private structure
3007 * @ring: tx ring to configure
85b430b4 3008 *
b980ac18 3009 * Configure a transmit ring after a reset.
85b430b4 3010 **/
d7ee5b3a
AD		 3011void igb_configure_tx_ring(struct igb_adapter *adapter,
3012 struct igb_ring *ring)
85b430b4
AD		 3013{
3014 struct e1000_hw *hw = &adapter->hw;
a74420e0 3015 u32 txdctl = 0;
85b430b4
AD		 3016 u64 tdba = ring->dma;
3017 int reg_idx = ring->reg_idx;
3018
3019 /* disable the queue */
a74420e0 3020 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3021 wrfl();
3022 mdelay(10);
3023
3024 wr32(E1000_TDLEN(reg_idx),
b980ac18 3025 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3026 wr32(E1000_TDBAL(reg_idx),
b980ac18 3027 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3028 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3029
fce99e34 3030 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3031 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3032 writel(0, ring->tail);
85b430b4
AD		 3033
3034 txdctl |= IGB_TX_PTHRESH;
3035 txdctl |= IGB_TX_HTHRESH << 8;
3036 txdctl |= IGB_TX_WTHRESH << 16;
3037
3038 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3039 wr32(E1000_TXDCTL(reg_idx), txdctl);
3040}
3041
3042/**
b980ac18
JK		 3043 * igb_configure_tx - Configure transmit Unit after Reset
3044 * @adapter: board private structure
85b430b4 3045 *
b980ac18 3046 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3047 **/
3048static void igb_configure_tx(struct igb_adapter *adapter)
3049{
3050 int i;
3051
3052 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3053 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3054}
3055
9d5c8243 3056/**
b980ac18
JK		 3057 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3058 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3059 *
b980ac18 3060 * Returns 0 on success, negative on failure
9d5c8243 3061 **/
80785298 3062int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3063{
59d71989 3064 struct device *dev = rx_ring->dev;
f33005a6 3065 int size;
9d5c8243 3066
06034649 3067 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3068
3069 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3070 if (!rx_ring->rx_buffer_info)
9d5c8243 3071 goto err;
9d5c8243 3072
9d5c8243 3073 /* Round up to nearest 4K */
f33005a6 3074 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3075 rx_ring->size = ALIGN(rx_ring->size, 4096);
3076
5536d210
AD		 3077 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3078 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3079 if (!rx_ring->desc)
3080 goto err;
3081
cbc8e55f 3082 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3083 rx_ring->next_to_clean = 0;
3084 rx_ring->next_to_use = 0;
9d5c8243 3085
9d5c8243
AK		 3086 return 0;
3087
3088err:
06034649
AD		 3089 vfree(rx_ring->rx_buffer_info);
3090 rx_ring->rx_buffer_info = NULL;
f33005a6 3091 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3092 return -ENOMEM;
3093}
3094
3095/**
b980ac18
JK		 3096 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3097 * (Descriptors) for all queues
3098 * @adapter: board private structure
9d5c8243 3099 *
b980ac18 3100 * Return 0 on success, negative on failure
9d5c8243
AK		 3101 **/
3102static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3103{
439705e1 3104 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3105 int i, err = 0;
3106
3107 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3108 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3109 if (err) {
439705e1 3110 dev_err(&pdev->dev,
9d5c8243
AK		 3111 "Allocation for Rx Queue %u failed\n", i);
3112 for (i--; i >= 0; i--)
3025a446 3113 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3114 break;
3115 }
3116 }
3117
3118 return err;
3119}
3120
06cf2666 3121/**
b980ac18
JK		 3122 * igb_setup_mrqc - configure the multiple receive queue control registers
3123 * @adapter: Board private structure
06cf2666
AD		 3124 **/
3125static void igb_setup_mrqc(struct igb_adapter *adapter)
3126{
3127 struct e1000_hw *hw = &adapter->hw;
3128 u32 mrqc, rxcsum;
ed12cc9a 3129 u32 j, num_rx_queues;
a57fe23e
AD		 3130 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3131 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3132 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3133 0xFA01ACBE };
06cf2666
AD		 3134
3135 /* Fill out hash function seeds */
a57fe23e
AD		 3136 for (j = 0; j < 10; j++)
3137 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3138
a99955fc 3139 num_rx_queues = adapter->rss_queues;
06cf2666 3140
797fd4be 3141 switch (hw->mac.type) {
797fd4be
AD		 3142 case e1000_82576:
3143 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3144 if (adapter->vfs_allocated_count)
06cf2666 3145 num_rx_queues = 2;
797fd4be
AD		 3146 break;
3147 default:
3148 break;
06cf2666
AD		 3149 }
3150
ed12cc9a
LMV		 3151 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3152 for (j = 0; j < IGB_RETA_SIZE; j++)
3153 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3154 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3155 }
ed12cc9a 3156 igb_write_rss_indir_tbl(adapter);
06cf2666 3157
b980ac18 3158 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3159 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3160 * offloads as they are enabled by default
3161 */
3162 rxcsum = rd32(E1000_RXCSUM);
3163 rxcsum |= E1000_RXCSUM_PCSD;
3164
3165 if (adapter->hw.mac.type >= e1000_82576)
3166 /* Enable Receive Checksum Offload for SCTP */
3167 rxcsum |= E1000_RXCSUM_CRCOFL;
3168
3169 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3170 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3171
039454a8
AA		 3172 /* Generate RSS hash based on packet types, TCP/UDP
3173 * port numbers and/or IPv4/v6 src and dst addresses
3174 */
f96a8a0b
CW		 3175 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3176 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3177 E1000_MRQC_RSS_FIELD_IPV6 |
3178 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3179 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3180
039454a8
AA		 3181 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3182 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3183 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3184 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3185
06cf2666
AD		 3186 /* If VMDq is enabled then we set the appropriate mode for that, else
3187 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3188 * if we are only using one queue
3189 */
06cf2666
AD		 3190 if (adapter->vfs_allocated_count) {
3191 if (hw->mac.type > e1000_82575) {
3192 /* Set the default pool for the PF's first queue */
3193 u32 vtctl = rd32(E1000_VT_CTL);
3194 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3195 E1000_VT_CTL_DISABLE_DEF_POOL);
3196 vtctl |= adapter->vfs_allocated_count <<
3197 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3198 wr32(E1000_VT_CTL, vtctl);
3199 }
a99955fc 3200 if (adapter->rss_queues > 1)
f96a8a0b 3201 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3202 else
f96a8a0b 3203 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3204 } else {
f96a8a0b
CW		 3205 if (hw->mac.type != e1000_i211)
3206 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3207 }
3208 igb_vmm_control(adapter);
3209
06cf2666
AD		 3210 wr32(E1000_MRQC, mrqc);
3211}
3212
9d5c8243 3213/**
b980ac18
JK		 3214 * igb_setup_rctl - configure the receive control registers
3215 * @adapter: Board private structure
9d5c8243 3216 **/
d7ee5b3a 3217void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3218{
3219 struct e1000_hw *hw = &adapter->hw;
3220 u32 rctl;
9d5c8243
AK		 3221
3222 rctl = rd32(E1000_RCTL);
3223
3224 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3225 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3226
69d728ba 3227 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3228 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3229
b980ac18 3230 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3231 * redirection as it did with e1000. Newer features require
3232 * that the HW strips the CRC.
73cd78f1 3233 */
87cb7e8c 3234 rctl |= E1000_RCTL_SECRC;
9d5c8243 3235
559e9c49 3236 /* disable store bad packets and clear size bits. */
ec54d7d6 3237 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3238
6ec43fe6
AD		 3239 /* enable LPE to prevent packets larger than max_frame_size */
3240 rctl |= E1000_RCTL_LPE;
9d5c8243 3241
952f72a8
AD		 3242 /* disable queue 0 to prevent tail write w/o re-config */
3243 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3244
e1739522
AD		 3245 /* Attention!!! For SR-IOV PF driver operations you must enable
3246 * queue drop for all VF and PF queues to prevent head of line blocking
3247 * if an un-trusted VF does not provide descriptors to hardware.
3248 */
3249 if (adapter->vfs_allocated_count) {
e1739522
AD		 3250 /* set all queue drop enable bits */
3251 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3252 }
3253
89eaefb6
BG		 3254 /* This is useful for sniffing bad packets. */
3255 if (adapter->netdev->features & NETIF_F_RXALL) {
3256 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3257 * in e1000e_set_rx_mode
3258 */
89eaefb6
BG		 3259 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3260 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3261 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3262
3263 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3264 E1000_RCTL_DPF | /* Allow filtered pause */
3265 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3266 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3267 * and that breaks VLANs.
3268 */
3269 }
3270
9d5c8243
AK		 3271 wr32(E1000_RCTL, rctl);
3272}
3273
7d5753f0
AD		 3274static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3275 int vfn)
3276{
3277 struct e1000_hw *hw = &adapter->hw;
3278 u32 vmolr;
3279
3280 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3281 * increase the size to support vlan tags
3282 */
7d5753f0
AD		 3283 if (vfn < adapter->vfs_allocated_count &&
3284 adapter->vf_data[vfn].vlans_enabled)
3285 size += VLAN_TAG_SIZE;
3286
3287 vmolr = rd32(E1000_VMOLR(vfn));
3288 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3289 vmolr |= size | E1000_VMOLR_LPE;
3290 wr32(E1000_VMOLR(vfn), vmolr);
3291
3292 return 0;
3293}
3294
e1739522 3295/**
b980ac18
JK		 3296 * igb_rlpml_set - set maximum receive packet size
3297 * @adapter: board private structure
e1739522 3298 *
b980ac18 3299 * Configure maximum receivable packet size.
e1739522
AD		 3300 **/
3301static void igb_rlpml_set(struct igb_adapter *adapter)
3302{
153285f9 3303 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3304 struct e1000_hw *hw = &adapter->hw;
3305 u16 pf_id = adapter->vfs_allocated_count;
3306
e1739522
AD		 3307 if (pf_id) {
3308 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3309 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3310 * to our max jumbo frame size, in case we need to enable
3311 * jumbo frames on one of the rings later.
3312 * This will not pass over-length frames into the default
3313 * queue because it's gated by the VMOLR.RLPML.
3314 */
7d5753f0 3315 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3316 }
3317
3318 wr32(E1000_RLPML, max_frame_size);
3319}
3320
8151d294
WM		 3321static inline void igb_set_vmolr(struct igb_adapter *adapter,
3322 int vfn, bool aupe)
7d5753f0
AD		 3323{
3324 struct e1000_hw *hw = &adapter->hw;
3325 u32 vmolr;
3326
b980ac18 3327 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3328 * we should exit and do nothing
3329 */
3330 if (hw->mac.type < e1000_82576)
3331 return;
3332
3333 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3334 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3335 if (aupe)
b980ac18 3336 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3337 else
3338 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3339
3340 /* clear all bits that might not be set */
3341 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3342
a99955fc 3343 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3344 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3345 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3346 * multicast packets
3347 */
3348 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3349 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3350
3351 wr32(E1000_VMOLR(vfn), vmolr);
3352}
3353
85b430b4 3354/**
b980ac18
JK		 3355 * igb_configure_rx_ring - Configure a receive ring after Reset
3356 * @adapter: board private structure
3357 * @ring: receive ring to be configured
85b430b4 3358 *
b980ac18 3359 * Configure the Rx unit of the MAC after a reset.
85b430b4 3360 **/
d7ee5b3a 3361void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3362 struct igb_ring *ring)
85b430b4
AD		 3363{
3364 struct e1000_hw *hw = &adapter->hw;
3365 u64 rdba = ring->dma;
3366 int reg_idx = ring->reg_idx;
a74420e0 3367 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3368
3369 /* disable the queue */
a74420e0 3370 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3371
3372 /* Set DMA base address registers */
3373 wr32(E1000_RDBAL(reg_idx),
3374 rdba & 0x00000000ffffffffULL);
3375 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3376 wr32(E1000_RDLEN(reg_idx),
b980ac18 3377 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3378
3379 /* initialize head and tail */
fce99e34 3380 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3381 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3382 writel(0, ring->tail);
85b430b4 3383
952f72a8 3384 /* set descriptor configuration */
44390ca6 3385 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3386 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3387 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3388 if (hw->mac.type >= e1000_82580)
757b77e2 3389 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3390 /* Only set Drop Enable if we are supporting multiple queues */
3391 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3392 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3393
3394 wr32(E1000_SRRCTL(reg_idx), srrctl);
3395
7d5753f0 3396 /* set filtering for VMDQ pools */
8151d294 3397 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3398
85b430b4
AD		 3399 rxdctl |= IGB_RX_PTHRESH;
3400 rxdctl |= IGB_RX_HTHRESH << 8;
3401 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3402
3403 /* enable receive descriptor fetching */
3404 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3405 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3406}
3407
9d5c8243 3408/**
b980ac18
JK		 3409 * igb_configure_rx - Configure receive Unit after Reset
3410 * @adapter: board private structure
9d5c8243 3411 *
b980ac18 3412 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3413 **/
3414static void igb_configure_rx(struct igb_adapter *adapter)
3415{
9107584e 3416 int i;
9d5c8243 3417
68d480c4
AD		 3418 /* set UTA to appropriate mode */
3419 igb_set_uta(adapter);
3420
26ad9178
AD		 3421 /* set the correct pool for the PF default MAC address in entry 0 */
3422 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3423 adapter->vfs_allocated_count);
26ad9178 3424
06cf2666 3425 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3426 * the Base and Length of the Rx Descriptor Ring
3427 */
f9d40f6a
AD		 3428 for (i = 0; i < adapter->num_rx_queues; i++)
3429 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3430}
3431
3432/**
b980ac18
JK		 3433 * igb_free_tx_resources - Free Tx Resources per Queue
3434 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3435 *
b980ac18 3436 * Free all transmit software resources
9d5c8243 3437 **/
68fd9910 3438void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3439{
3b644cf6 3440 igb_clean_tx_ring(tx_ring);
9d5c8243 3441
06034649
AD		 3442 vfree(tx_ring->tx_buffer_info);
3443 tx_ring->tx_buffer_info = NULL;
9d5c8243 3444
439705e1
AD		 3445 /* if not set, then don't free */
3446 if (!tx_ring->desc)
3447 return;
3448
59d71989
AD		 3449 dma_free_coherent(tx_ring->dev, tx_ring->size,
3450 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3451
3452 tx_ring->desc = NULL;
3453}
3454
3455/**
b980ac18
JK		 3456 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3457 * @adapter: board private structure
9d5c8243 3458 *
b980ac18 3459 * Free all transmit software resources
9d5c8243
AK		 3460 **/
3461static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3462{
3463 int i;
3464
3465 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3466 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3467}
3468
ebe42d16
AD		 3469void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3470 struct igb_tx_buffer *tx_buffer)
3471{
3472 if (tx_buffer->skb) {
3473 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3474 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3475 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3476 dma_unmap_addr(tx_buffer, dma),
3477 dma_unmap_len(tx_buffer, len),
ebe42d16 3478 DMA_TO_DEVICE);
c9f14bf3 3479 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3480 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3481 dma_unmap_addr(tx_buffer, dma),
3482 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3483 DMA_TO_DEVICE);
3484 }
3485 tx_buffer->next_to_watch = NULL;
3486 tx_buffer->skb = NULL;
c9f14bf3 3487 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3488 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3489}
3490
3491/**
b980ac18
JK		 3492 * igb_clean_tx_ring - Free Tx Buffers
3493 * @tx_ring: ring to be cleaned
9d5c8243 3494 **/
3b644cf6 3495static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3496{
06034649 3497 struct igb_tx_buffer *buffer_info;
9d5c8243 3498 unsigned long size;
6ad4edfc 3499 u16 i;
9d5c8243 3500
06034649 3501 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3502 return;
3503 /* Free all the Tx ring sk_buffs */
3504
3505 for (i = 0; i < tx_ring->count; i++) {
06034649 3506 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3507 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3508 }
3509
dad8a3b3
JF		 3510 netdev_tx_reset_queue(txring_txq(tx_ring));
3511
06034649
AD		 3512 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3513 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3514
3515 /* Zero out the descriptor ring */
9d5c8243
AK		 3516 memset(tx_ring->desc, 0, tx_ring->size);
3517
3518 tx_ring->next_to_use = 0;
3519 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3520}
3521
3522/**
b980ac18
JK		 3523 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3524 * @adapter: board private structure
9d5c8243
AK		 3525 **/
3526static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3527{
3528 int i;
3529
3530 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3531 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3532}
3533
3534/**
b980ac18
JK		 3535 * igb_free_rx_resources - Free Rx Resources
3536 * @rx_ring: ring to clean the resources from
9d5c8243 3537 *
b980ac18 3538 * Free all receive software resources
9d5c8243 3539 **/
68fd9910 3540void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3541{
3b644cf6 3542 igb_clean_rx_ring(rx_ring);
9d5c8243 3543
06034649
AD		 3544 vfree(rx_ring->rx_buffer_info);
3545 rx_ring->rx_buffer_info = NULL;
9d5c8243 3546
439705e1
AD		 3547 /* if not set, then don't free */
3548 if (!rx_ring->desc)
3549 return;
3550
59d71989
AD		 3551 dma_free_coherent(rx_ring->dev, rx_ring->size,
3552 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3553
3554 rx_ring->desc = NULL;
3555}
3556
3557/**
b980ac18
JK		 3558 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3559 * @adapter: board private structure
9d5c8243 3560 *
b980ac18 3561 * Free all receive software resources
9d5c8243
AK		 3562 **/
3563static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3564{
3565 int i;
3566
3567 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3568 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3569}
3570
3571/**
b980ac18
JK		 3572 * igb_clean_rx_ring - Free Rx Buffers per Queue
3573 * @rx_ring: ring to free buffers from
9d5c8243 3574 **/
3b644cf6 3575static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3576{
9d5c8243 3577 unsigned long size;
c023cd88 3578 u16 i;
9d5c8243 3579
1a1c225b
AD		 3580 if (rx_ring->skb)
3581 dev_kfree_skb(rx_ring->skb);
3582 rx_ring->skb = NULL;
3583
06034649 3584 if (!rx_ring->rx_buffer_info)
9d5c8243 3585 return;
439705e1 3586
9d5c8243
AK		 3587 /* Free all the Rx ring sk_buffs */
3588 for (i = 0; i < rx_ring->count; i++) {
06034649 3589 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3590
cbc8e55f
AD		 3591 if (!buffer_info->page)
3592 continue;
3593
3594 dma_unmap_page(rx_ring->dev,
3595 buffer_info->dma,
3596 PAGE_SIZE,
3597 DMA_FROM_DEVICE);
3598 __free_page(buffer_info->page);
3599
1a1c225b 3600 buffer_info->page = NULL;
9d5c8243
AK		 3601 }
3602
06034649
AD		 3603 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3604 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3605
3606 /* Zero out the descriptor ring */
3607 memset(rx_ring->desc, 0, rx_ring->size);
3608
cbc8e55f 3609 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3610 rx_ring->next_to_clean = 0;
3611 rx_ring->next_to_use = 0;
9d5c8243
AK		 3612}
3613
3614/**
b980ac18
JK		 3615 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3616 * @adapter: board private structure
9d5c8243
AK		 3617 **/
3618static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3619{
3620 int i;
3621
3622 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3623 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3624}
3625
3626/**
b980ac18
JK		 3627 * igb_set_mac - Change the Ethernet Address of the NIC
3628 * @netdev: network interface device structure
3629 * @p: pointer to an address structure
9d5c8243 3630 *
b980ac18 3631 * Returns 0 on success, negative on failure
9d5c8243
AK		 3632 **/
3633static int igb_set_mac(struct net_device *netdev, void *p)
3634{
3635 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3636 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3637 struct sockaddr *addr = p;
3638
3639 if (!is_valid_ether_addr(addr->sa_data))
3640 return -EADDRNOTAVAIL;
3641
3642 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3643 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3644
26ad9178
AD		 3645 /* set the correct pool for the new PF MAC address in entry 0 */
3646 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3647 adapter->vfs_allocated_count);
e1739522 3648
9d5c8243
AK		 3649 return 0;
3650}
3651
3652/**
b980ac18
JK		 3653 * igb_write_mc_addr_list - write multicast addresses to MTA
3654 * @netdev: network interface device structure
9d5c8243 3655 *
b980ac18
JK		 3656 * Writes multicast address list to the MTA hash table.
3657 * Returns: -ENOMEM on failure
3658 * 0 on no addresses written
3659 * X on writing X addresses to MTA
9d5c8243 3660 **/
68d480c4 3661static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3662{
3663 struct igb_adapter *adapter = netdev_priv(netdev);
3664 struct e1000_hw *hw = &adapter->hw;
22bedad3 3665 struct netdev_hw_addr *ha;
68d480c4 3666 u8 *mta_list;
9d5c8243
AK		 3667 int i;
3668
4cd24eaf 3669 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3670 /* nothing to program, so clear mc list */
3671 igb_update_mc_addr_list(hw, NULL, 0);
3672 igb_restore_vf_multicasts(adapter);
3673 return 0;
3674 }
9d5c8243 3675
4cd24eaf 3676 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3677 if (!mta_list)
3678 return -ENOMEM;
ff41f8dc 3679
68d480c4 3680 /* The shared function expects a packed array of only addresses. */
48e2f183 3681 i = 0;
22bedad3
JP		 3682 netdev_for_each_mc_addr(ha, netdev)
3683 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3684
68d480c4
AD		 3685 igb_update_mc_addr_list(hw, mta_list, i);
3686 kfree(mta_list);
3687
4cd24eaf 3688 return netdev_mc_count(netdev);
68d480c4
AD		 3689}
3690
3691/**
b980ac18
JK		 3692 * igb_write_uc_addr_list - write unicast addresses to RAR table
3693 * @netdev: network interface device structure
68d480c4 3694 *
b980ac18
JK		 3695 * Writes unicast address list to the RAR table.
3696 * Returns: -ENOMEM on failure/insufficient address space
3697 * 0 on no addresses written
3698 * X on writing X addresses to the RAR table
68d480c4
AD		 3699 **/
3700static int igb_write_uc_addr_list(struct net_device *netdev)
3701{
3702 struct igb_adapter *adapter = netdev_priv(netdev);
3703 struct e1000_hw *hw = &adapter->hw;
3704 unsigned int vfn = adapter->vfs_allocated_count;
3705 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3706 int count = 0;
3707
3708 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3709 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3710 return -ENOMEM;
9d5c8243 3711
32e7bfc4 3712 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3713 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3714
3715 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3716 if (!rar_entries)
3717 break;
26ad9178 3718 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3719 rar_entries--,
3720 vfn);
68d480c4 3721 count++;
ff41f8dc
AD		 3722 }
3723 }
3724 /* write the addresses in reverse order to avoid write combining */
3725 for (; rar_entries > 0 ; rar_entries--) {
3726 wr32(E1000_RAH(rar_entries), 0);
3727 wr32(E1000_RAL(rar_entries), 0);
3728 }
3729 wrfl();
3730
68d480c4
AD		 3731 return count;
3732}
3733
3734/**
b980ac18
JK		 3735 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3736 * @netdev: network interface device structure
68d480c4 3737 *
b980ac18
JK		 3738 * The set_rx_mode entry point is called whenever the unicast or multicast
3739 * address lists or the network interface flags are updated. This routine is
3740 * responsible for configuring the hardware for proper unicast, multicast,
3741 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3742 **/
3743static void igb_set_rx_mode(struct net_device *netdev)
3744{
3745 struct igb_adapter *adapter = netdev_priv(netdev);
3746 struct e1000_hw *hw = &adapter->hw;
3747 unsigned int vfn = adapter->vfs_allocated_count;
3748 u32 rctl, vmolr = 0;
3749 int count;
3750
3751 /* Check for Promiscuous and All Multicast modes */
3752 rctl = rd32(E1000_RCTL);
3753
3754 /* clear the effected bits */
3755 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3756
3757 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3758 /* retain VLAN HW filtering if in VT mode */
7e44892c 3759 if (adapter->vfs_allocated_count)
6f3dc319 3760 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3761 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3762 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3763 } else {
3764 if (netdev->flags & IFF_ALLMULTI) {
3765 rctl |= E1000_RCTL_MPE;
3766 vmolr |= E1000_VMOLR_MPME;
3767 } else {
b980ac18 3768 /* Write addresses to the MTA, if the attempt fails
25985edc 3769 * then we should just turn on promiscuous mode so
68d480c4
AD		 3770 * that we can at least receive multicast traffic
3771 */
3772 count = igb_write_mc_addr_list(netdev);
3773 if (count < 0) {
3774 rctl |= E1000_RCTL_MPE;
3775 vmolr |= E1000_VMOLR_MPME;
3776 } else if (count) {
3777 vmolr |= E1000_VMOLR_ROMPE;
3778 }
3779 }
b980ac18 3780 /* Write addresses to available RAR registers, if there is not
68d480c4 3781 * sufficient space to store all the addresses then enable
25985edc 3782 * unicast promiscuous mode
68d480c4
AD		 3783 */
3784 count = igb_write_uc_addr_list(netdev);
3785 if (count < 0) {
3786 rctl |= E1000_RCTL_UPE;
3787 vmolr |= E1000_VMOLR_ROPE;
3788 }
3789 rctl |= E1000_RCTL_VFE;
28fc06f5 3790 }
68d480c4 3791 wr32(E1000_RCTL, rctl);
28fc06f5 3792
b980ac18 3793 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3794 * the VMOLR to enable the appropriate modes. Without this workaround
3795 * we will have issues with VLAN tag stripping not being done for frames
3796 * that are only arriving because we are the default pool
3797 */
f96a8a0b 3798 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3799 return;
9d5c8243 3800
68d480c4 3801 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3802 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3803 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3804 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3805}
3806
13800469
GR		 3807static void igb_check_wvbr(struct igb_adapter *adapter)
3808{
3809 struct e1000_hw *hw = &adapter->hw;
3810 u32 wvbr = 0;
3811
3812 switch (hw->mac.type) {
3813 case e1000_82576:
3814 case e1000_i350:
3815 if (!(wvbr = rd32(E1000_WVBR)))
3816 return;
3817 break;
3818 default:
3819 break;
3820 }
3821
3822 adapter->wvbr |= wvbr;
3823}
3824
3825#define IGB_STAGGERED_QUEUE_OFFSET 8
3826
3827static void igb_spoof_check(struct igb_adapter *adapter)
3828{
3829 int j;
3830
3831 if (!adapter->wvbr)
3832 return;
3833
3834 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3835 if (adapter->wvbr & (1 << j) ||
3836 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3837 dev_warn(&adapter->pdev->dev,
3838 "Spoof event(s) detected on VF %d\n", j);
3839 adapter->wvbr &=
3840 ~((1 << j) |
3841 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3842 }
3843 }
3844}
3845
9d5c8243 3846/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 3847 * the phy
3848 */
9d5c8243
AK		 3849static void igb_update_phy_info(unsigned long data)
3850{
3851 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3852 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3853}
3854
4d6b725e 3855/**
b980ac18
JK		 3856 * igb_has_link - check shared code for link and determine up/down
3857 * @adapter: pointer to driver private info
4d6b725e 3858 **/
3145535a 3859bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3860{
3861 struct e1000_hw *hw = &adapter->hw;
3862 bool link_active = false;
4d6b725e
AD		 3863
3864 /* get_link_status is set on LSC (link status) interrupt or
3865 * rx sequence error interrupt. get_link_status will stay
3866 * false until the e1000_check_for_link establishes link
3867 * for copper adapters ONLY
3868 */
3869 switch (hw->phy.media_type) {
3870 case e1000_media_type_copper:
e5c3370f
AA		 3871 if (!hw->mac.get_link_status)
3872 return true;
4d6b725e 3873 case e1000_media_type_internal_serdes:
e5c3370f
AA		 3874 hw->mac.ops.check_for_link(hw);
3875 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 3876 break;
3877 default:
3878 case e1000_media_type_unknown:
3879 break;
3880 }
3881
3882 return link_active;
3883}
3884
563988dc
SA		 3885static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3886{
3887 bool ret = false;
3888 u32 ctrl_ext, thstat;
3889
f96a8a0b 3890 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3891 if (hw->mac.type == e1000_i350) {
3892 thstat = rd32(E1000_THSTAT);
3893 ctrl_ext = rd32(E1000_CTRL_EXT);
3894
3895 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 3896 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 3897 ret = !!(thstat & event);
563988dc
SA		 3898 }
3899
3900 return ret;
3901}
3902
9d5c8243 3903/**
b980ac18
JK		 3904 * igb_watchdog - Timer Call-back
3905 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 3906 **/
3907static void igb_watchdog(unsigned long data)
3908{
3909 struct igb_adapter *adapter = (struct igb_adapter *)data;
3910 /* Do the rest outside of interrupt context */
3911 schedule_work(&adapter->watchdog_task);
3912}
3913
3914static void igb_watchdog_task(struct work_struct *work)
3915{
3916 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 3917 struct igb_adapter,
3918 watchdog_task);
9d5c8243 3919 struct e1000_hw *hw = &adapter->hw;
c0ba4778 3920 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 3921 struct net_device *netdev = adapter->netdev;
563988dc 3922 u32 link;
7a6ea550 3923 int i;
9d5c8243 3924
4d6b725e 3925 link = igb_has_link(adapter);
9d5c8243 3926 if (link) {
749ab2cd
YZ		 3927 /* Cancel scheduled suspend requests. */
3928 pm_runtime_resume(netdev->dev.parent);
3929
9d5c8243
AK		 3930 if (!netif_carrier_ok(netdev)) {
3931 u32 ctrl;
330a6d6a 3932 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 3933 &adapter->link_speed,
3934 &adapter->link_duplex);
9d5c8243
AK		 3935
3936 ctrl = rd32(E1000_CTRL);
527d47c1 3937 /* Links status message must follow this format */
876d2d6f
JK		 3938 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3939 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3940 netdev->name,
3941 adapter->link_speed,
3942 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3943 "Full" : "Half",
3944 (ctrl & E1000_CTRL_TFCE) &&
3945 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3946 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3947 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3948
c0ba4778
KS		 3949 /* check if SmartSpeed worked */
3950 igb_check_downshift(hw);
3951 if (phy->speed_downgraded)
3952 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3953
563988dc 3954 /* check for thermal sensor event */
876d2d6f
JK		 3955 if (igb_thermal_sensor_event(hw,
3956 E1000_THSTAT_LINK_THROTTLE)) {
3957 netdev_info(netdev, "The network adapter link "
3958 "speed was downshifted because it "
3959 "overheated\n");
7ef5ed1c 3960 }
563988dc 3961
d07f3e37 3962 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3963 adapter->tx_timeout_factor = 1;
3964 switch (adapter->link_speed) {
3965 case SPEED_10:
9d5c8243
AK		 3966 adapter->tx_timeout_factor = 14;
3967 break;
3968 case SPEED_100:
9d5c8243
AK		 3969 /* maybe add some timeout factor ? */
3970 break;
3971 }
3972
3973 netif_carrier_on(netdev);
9d5c8243 3974
4ae196df 3975 igb_ping_all_vfs(adapter);
17dc566c 3976 igb_check_vf_rate_limit(adapter);
4ae196df 3977
4b1a9877 3978 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3979 if (!test_bit(__IGB_DOWN, &adapter->state))
3980 mod_timer(&adapter->phy_info_timer,
3981 round_jiffies(jiffies + 2 * HZ));
3982 }
3983 } else {
3984 if (netif_carrier_ok(netdev)) {
3985 adapter->link_speed = 0;
3986 adapter->link_duplex = 0;
563988dc
SA		 3987
3988 /* check for thermal sensor event */
876d2d6f
JK		 3989 if (igb_thermal_sensor_event(hw,
3990 E1000_THSTAT_PWR_DOWN)) {
3991 netdev_err(netdev, "The network adapter was "
3992 "stopped because it overheated\n");
7ef5ed1c 3993 }
563988dc 3994
527d47c1
AD		 3995 /* Links status message must follow this format */
3996 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3997 netdev->name);
9d5c8243 3998 netif_carrier_off(netdev);
4b1a9877 3999
4ae196df
AD		 4000 igb_ping_all_vfs(adapter);
4001
4b1a9877 4002 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4003 if (!test_bit(__IGB_DOWN, &adapter->state))
4004 mod_timer(&adapter->phy_info_timer,
4005 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 4006
4007 pm_schedule_suspend(netdev->dev.parent,
4008 MSEC_PER_SEC * 5);
9d5c8243
AK		 4009 }
4010 }
4011
12dcd86b
ED		 4012 spin_lock(&adapter->stats64_lock);
4013 igb_update_stats(adapter, &adapter->stats64);
4014 spin_unlock(&adapter->stats64_lock);
9d5c8243 4015
dbabb065 4016 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4017 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4018 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4019 /* We've lost link, so the controller stops DMA,
4020 * but we've got queued Tx work that's never going
4021 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4022 * (Do the reset outside of interrupt context).
4023 */
dbabb065
AD		 4024 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4025 adapter->tx_timeout_count++;
4026 schedule_work(&adapter->reset_task);
4027 /* return immediately since reset is imminent */
4028 return;
4029 }
9d5c8243 4030 }
9d5c8243 4031
dbabb065 4032 /* Force detection of hung controller every watchdog period */
6d095fa8 4033 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4034 }
f7ba205e 4035
b980ac18 4036 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4037 if (adapter->msix_entries) {
047e0030 4038 u32 eics = 0;
0d1ae7f4
AD		 4039 for (i = 0; i < adapter->num_q_vectors; i++)
4040 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4041 wr32(E1000_EICS, eics);
4042 } else {
4043 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4044 }
9d5c8243 4045
13800469 4046 igb_spoof_check(adapter);
fc580751 4047 igb_ptp_rx_hang(adapter);
13800469 4048
9d5c8243
AK		 4049 /* Reset the timer */
4050 if (!test_bit(__IGB_DOWN, &adapter->state))
4051 mod_timer(&adapter->watchdog_timer,
4052 round_jiffies(jiffies + 2 * HZ));
4053}
4054
4055enum latency_range {
4056 lowest_latency = 0,
4057 low_latency = 1,
4058 bulk_latency = 2,
4059 latency_invalid = 255
4060};
4061
6eb5a7f1 4062/**
b980ac18
JK		 4063 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4064 * @q_vector: pointer to q_vector
6eb5a7f1 4065 *
b980ac18
JK		 4066 * Stores a new ITR value based on strictly on packet size. This
4067 * algorithm is less sophisticated than that used in igb_update_itr,
4068 * due to the difficulty of synchronizing statistics across multiple
4069 * receive rings. The divisors and thresholds used by this function
4070 * were determined based on theoretical maximum wire speed and testing
4071 * data, in order to minimize response time while increasing bulk
4072 * throughput.
4073 * This functionality is controlled by the InterruptThrottleRate module
4074 * parameter (see igb_param.c)
4075 * NOTE: This function is called only when operating in a multiqueue
4076 * receive environment.
6eb5a7f1 4077 **/
047e0030 4078static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4079{
047e0030 4080 int new_val = q_vector->itr_val;
6eb5a7f1 4081 int avg_wire_size = 0;
047e0030 4082 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4083 unsigned int packets;
9d5c8243 4084
6eb5a7f1
AD		 4085 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4086 * ints/sec - ITR timer value of 120 ticks.
4087 */
4088 if (adapter->link_speed != SPEED_1000) {
0ba82994 4089 new_val = IGB_4K_ITR;
6eb5a7f1 4090 goto set_itr_val;
9d5c8243 4091 }
047e0030 4092
0ba82994
AD		 4093 packets = q_vector->rx.total_packets;
4094 if (packets)
4095 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4096
0ba82994
AD		 4097 packets = q_vector->tx.total_packets;
4098 if (packets)
4099 avg_wire_size = max_t(u32, avg_wire_size,
4100 q_vector->tx.total_bytes / packets);
047e0030
AD		 4101
4102 /* if avg_wire_size isn't set no work was done */
4103 if (!avg_wire_size)
4104 goto clear_counts;
9d5c8243 4105
6eb5a7f1
AD		 4106 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4107 avg_wire_size += 24;
4108
4109 /* Don't starve jumbo frames */
4110 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4111
6eb5a7f1
AD		 4112 /* Give a little boost to mid-size frames */
4113 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4114 new_val = avg_wire_size / 3;
4115 else
4116 new_val = avg_wire_size / 2;
9d5c8243 4117
0ba82994
AD		 4118 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4119 if (new_val < IGB_20K_ITR &&
4120 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4121 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4122 new_val = IGB_20K_ITR;
abe1c363 4123
6eb5a7f1 4124set_itr_val:
047e0030
AD		 4125 if (new_val != q_vector->itr_val) {
4126 q_vector->itr_val = new_val;
4127 q_vector->set_itr = 1;
9d5c8243 4128 }
6eb5a7f1 4129clear_counts:
0ba82994
AD		 4130 q_vector->rx.total_bytes = 0;
4131 q_vector->rx.total_packets = 0;
4132 q_vector->tx.total_bytes = 0;
4133 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4134}
4135
4136/**
b980ac18
JK		 4137 * igb_update_itr - update the dynamic ITR value based on statistics
4138 * @q_vector: pointer to q_vector
4139 * @ring_container: ring info to update the itr for
4140 *
4141 * Stores a new ITR value based on packets and byte
4142 * counts during the last interrupt. The advantage of per interrupt
4143 * computation is faster updates and more accurate ITR for the current
4144 * traffic pattern. Constants in this function were computed
4145 * based on theoretical maximum wire speed and thresholds were set based
4146 * on testing data as well as attempting to minimize response time
4147 * while increasing bulk throughput.
4148 * this functionality is controlled by the InterruptThrottleRate module
4149 * parameter (see igb_param.c)
4150 * NOTE: These calculations are only valid when operating in a single-
4151 * queue environment.
9d5c8243 4152 **/
0ba82994
AD		 4153static void igb_update_itr(struct igb_q_vector *q_vector,
4154 struct igb_ring_container *ring_container)
9d5c8243 4155{
0ba82994
AD		 4156 unsigned int packets = ring_container->total_packets;
4157 unsigned int bytes = ring_container->total_bytes;
4158 u8 itrval = ring_container->itr;
9d5c8243 4159
0ba82994 4160 /* no packets, exit with status unchanged */
9d5c8243 4161 if (packets == 0)
0ba82994 4162 return;
9d5c8243 4163
0ba82994 4164 switch (itrval) {
9d5c8243
AK		 4165 case lowest_latency:
4166 /* handle TSO and jumbo frames */
4167 if (bytes/packets > 8000)
0ba82994 4168 itrval = bulk_latency;
9d5c8243 4169 else if ((packets < 5) && (bytes > 512))
0ba82994 4170 itrval = low_latency;
9d5c8243
AK		 4171 break;
4172 case low_latency: /* 50 usec aka 20000 ints/s */
4173 if (bytes > 10000) {
4174 /* this if handles the TSO accounting */
4175 if (bytes/packets > 8000) {
0ba82994 4176 itrval = bulk_latency;
9d5c8243 4177 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4178 itrval = bulk_latency;
9d5c8243 4179 } else if ((packets > 35)) {
0ba82994 4180 itrval = lowest_latency;
9d5c8243
AK		 4181 }
4182 } else if (bytes/packets > 2000) {
0ba82994 4183 itrval = bulk_latency;
9d5c8243 4184 } else if (packets <= 2 && bytes < 512) {
0ba82994 4185 itrval = lowest_latency;
9d5c8243
AK		 4186 }
4187 break;
4188 case bulk_latency: /* 250 usec aka 4000 ints/s */
4189 if (bytes > 25000) {
4190 if (packets > 35)
0ba82994 4191 itrval = low_latency;
1e5c3d21 4192 } else if (bytes < 1500) {
0ba82994 4193 itrval = low_latency;
9d5c8243
AK		 4194 }
4195 break;
4196 }
4197
0ba82994
AD		 4198 /* clear work counters since we have the values we need */
4199 ring_container->total_bytes = 0;
4200 ring_container->total_packets = 0;
4201
4202 /* write updated itr to ring container */
4203 ring_container->itr = itrval;
9d5c8243
AK		 4204}
4205
0ba82994 4206static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4207{
0ba82994 4208 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4209 u32 new_itr = q_vector->itr_val;
0ba82994 4210 u8 current_itr = 0;
9d5c8243
AK		 4211
4212 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4213 if (adapter->link_speed != SPEED_1000) {
4214 current_itr = 0;
0ba82994 4215 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4216 goto set_itr_now;
4217 }
4218
0ba82994
AD		 4219 igb_update_itr(q_vector, &q_vector->tx);
4220 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4221
0ba82994 4222 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4223
6eb5a7f1 4224 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4225 if (current_itr == lowest_latency &&
4226 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4227 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4228 current_itr = low_latency;
4229
9d5c8243
AK		 4230 switch (current_itr) {
4231 /* counts and packets in update_itr are dependent on these numbers */
4232 case lowest_latency:
0ba82994 4233 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4234 break;
4235 case low_latency:
0ba82994 4236 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4237 break;
4238 case bulk_latency:
0ba82994 4239 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4240 break;
4241 default:
4242 break;
4243 }
4244
4245set_itr_now:
047e0030 4246 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4247 /* this attempts to bias the interrupt rate towards Bulk
4248 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4249 * increasing
4250 */
047e0030 4251 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4252 max((new_itr * q_vector->itr_val) /
4253 (new_itr + (q_vector->itr_val >> 2)),
4254 new_itr) : new_itr;
9d5c8243
AK		 4255 /* Don't write the value here; it resets the adapter's
4256 * internal timer, and causes us to delay far longer than
4257 * we should between interrupts. Instead, we write the ITR
4258 * value at the beginning of the next interrupt so the timing
4259 * ends up being correct.
4260 */
047e0030
AD		 4261 q_vector->itr_val = new_itr;
4262 q_vector->set_itr = 1;
9d5c8243 4263 }
9d5c8243
AK		 4264}
4265
c50b52a0
SH		 4266static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4267 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4268{
4269 struct e1000_adv_tx_context_desc *context_desc;
4270 u16 i = tx_ring->next_to_use;
4271
4272 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4273
4274 i++;
4275 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4276
4277 /* set bits to identify this as an advanced context descriptor */
4278 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4279
4280 /* For 82575, context index must be unique per ring. */
866cff06 4281 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4282 mss_l4len_idx |= tx_ring->reg_idx << 4;
4283
4284 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4285 context_desc->seqnum_seed = 0;
4286 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4287 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4288}
4289
7af40ad9
AD		 4290static int igb_tso(struct igb_ring *tx_ring,
4291 struct igb_tx_buffer *first,
4292 u8 *hdr_len)
9d5c8243 4293{
7af40ad9 4294 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4295 u32 vlan_macip_lens, type_tucmd;
4296 u32 mss_l4len_idx, l4len;
4297
ed6aa105
AD		 4298 if (skb->ip_summed != CHECKSUM_PARTIAL)
4299 return 0;
4300
7d13a7d0
AD		 4301 if (!skb_is_gso(skb))
4302 return 0;
9d5c8243
AK		 4303
4304 if (skb_header_cloned(skb)) {
7af40ad9 4305 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4306 if (err)
4307 return err;
4308 }
4309
7d13a7d0
AD		 4310 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4311 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4312
7af40ad9 4313 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4314 struct iphdr *iph = ip_hdr(skb);
4315 iph->tot_len = 0;
4316 iph->check = 0;
4317 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4318 iph->daddr, 0,
4319 IPPROTO_TCP,
4320 0);
7d13a7d0 4321 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4322 first->tx_flags |= IGB_TX_FLAGS_TSO |
4323 IGB_TX_FLAGS_CSUM |
4324 IGB_TX_FLAGS_IPV4;
8e1e8a47 4325 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4326 ipv6_hdr(skb)->payload_len = 0;
4327 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4328 &ipv6_hdr(skb)->daddr,
4329 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4330 first->tx_flags |= IGB_TX_FLAGS_TSO |
4331 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4332 }
4333
7af40ad9 4334 /* compute header lengths */
7d13a7d0
AD		 4335 l4len = tcp_hdrlen(skb);
4336 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4337
7af40ad9
AD		 4338 /* update gso size and bytecount with header size */
4339 first->gso_segs = skb_shinfo(skb)->gso_segs;
4340 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4341
9d5c8243 4342 /* MSS L4LEN IDX */
7d13a7d0
AD		 4343 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4344 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4345
7d13a7d0
AD		 4346 /* VLAN MACLEN IPLEN */
4347 vlan_macip_lens = skb_network_header_len(skb);
4348 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4349 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4350
7d13a7d0 4351 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4352
7d13a7d0 4353 return 1;
9d5c8243
AK		 4354}
4355
7af40ad9 4356static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4357{
7af40ad9 4358 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4359 u32 vlan_macip_lens = 0;
4360 u32 mss_l4len_idx = 0;
4361 u32 type_tucmd = 0;
9d5c8243 4362
7d13a7d0 4363 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4364 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4365 return;
7d13a7d0
AD		 4366 } else {
4367 u8 l4_hdr = 0;
7af40ad9 4368 switch (first->protocol) {
7d13a7d0
AD		 4369 case __constant_htons(ETH_P_IP):
4370 vlan_macip_lens |= skb_network_header_len(skb);
4371 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4372 l4_hdr = ip_hdr(skb)->protocol;
4373 break;
4374 case __constant_htons(ETH_P_IPV6):
4375 vlan_macip_lens |= skb_network_header_len(skb);
4376 l4_hdr = ipv6_hdr(skb)->nexthdr;
4377 break;
4378 default:
4379 if (unlikely(net_ratelimit())) {
4380 dev_warn(tx_ring->dev,
b980ac18
JK		 4381 "partial checksum but proto=%x!\n",
4382 first->protocol);
fa4a7ef3 4383 }
7d13a7d0
AD		 4384 break;
4385 }
fa4a7ef3 4386
7d13a7d0
AD		 4387 switch (l4_hdr) {
4388 case IPPROTO_TCP:
4389 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4390 mss_l4len_idx = tcp_hdrlen(skb) <<
4391 E1000_ADVTXD_L4LEN_SHIFT;
4392 break;
4393 case IPPROTO_SCTP:
4394 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4395 mss_l4len_idx = sizeof(struct sctphdr) <<
4396 E1000_ADVTXD_L4LEN_SHIFT;
4397 break;
4398 case IPPROTO_UDP:
4399 mss_l4len_idx = sizeof(struct udphdr) <<
4400 E1000_ADVTXD_L4LEN_SHIFT;
4401 break;
4402 default:
4403 if (unlikely(net_ratelimit())) {
4404 dev_warn(tx_ring->dev,
b980ac18
JK		 4405 "partial checksum but l4 proto=%x!\n",
4406 l4_hdr);
44b0cda3 4407 }
7d13a7d0 4408 break;
9d5c8243 4409 }
7af40ad9
AD		 4410
4411 /* update TX checksum flag */
4412 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4413 }
9d5c8243 4414
7d13a7d0 4415 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4416 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4417
7d13a7d0 4418 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4419}
4420
1d9daf45
AD		 4421#define IGB_SET_FLAG(_input, _flag, _result) \
4422 ((_flag <= _result) ? \
4423 ((u32)(_input & _flag) * (_result / _flag)) : \
4424 ((u32)(_input & _flag) / (_flag / _result)))
4425
4426static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4427{
4428 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4429 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4430 E1000_ADVTXD_DCMD_DEXT |
4431 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4432
4433 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4434 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4435 (E1000_ADVTXD_DCMD_VLE));
4436
4437 /* set segmentation bits for TSO */
4438 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4439 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4440
4441 /* set timestamp bit if present */
1d9daf45
AD		 4442 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4443 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4444
1d9daf45
AD		 4445 /* insert frame checksum */
4446 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4447
4448 return cmd_type;
4449}
4450
7af40ad9
AD		 4451static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4452 union e1000_adv_tx_desc *tx_desc,
4453 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4454{
4455 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4456
1d9daf45
AD		 4457 /* 82575 requires a unique index per ring */
4458 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4459 olinfo_status |= tx_ring->reg_idx << 4;
4460
4461 /* insert L4 checksum */
1d9daf45
AD		 4462 olinfo_status |= IGB_SET_FLAG(tx_flags,
4463 IGB_TX_FLAGS_CSUM,
4464 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4465
1d9daf45
AD		 4466 /* insert IPv4 checksum */
4467 olinfo_status |= IGB_SET_FLAG(tx_flags,
4468 IGB_TX_FLAGS_IPV4,
4469 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4470
7af40ad9 4471 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4472}
4473
7af40ad9
AD		 4474static void igb_tx_map(struct igb_ring *tx_ring,
4475 struct igb_tx_buffer *first,
ebe42d16 4476 const u8 hdr_len)
9d5c8243 4477{
7af40ad9 4478 struct sk_buff *skb = first->skb;
c9f14bf3 4479 struct igb_tx_buffer *tx_buffer;
ebe42d16 4480 union e1000_adv_tx_desc *tx_desc;
80d0759e 4481 struct skb_frag_struct *frag;
ebe42d16 4482 dma_addr_t dma;
80d0759e 4483 unsigned int data_len, size;
7af40ad9 4484 u32 tx_flags = first->tx_flags;
1d9daf45 4485 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4486 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4487
4488 tx_desc = IGB_TX_DESC(tx_ring, i);
4489
80d0759e
AD		 4490 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4491
4492 size = skb_headlen(skb);
4493 data_len = skb->data_len;
ebe42d16
AD		 4494
4495 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4496
80d0759e
AD		 4497 tx_buffer = first;
4498
4499 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4500 if (dma_mapping_error(tx_ring->dev, dma))
4501 goto dma_error;
4502
4503 /* record length, and DMA address */
4504 dma_unmap_len_set(tx_buffer, len, size);
4505 dma_unmap_addr_set(tx_buffer, dma, dma);
4506
4507 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4508
ebe42d16
AD		 4509 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4510 tx_desc->read.cmd_type_len =
1d9daf45 4511 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4512
4513 i++;
4514 tx_desc++;
4515 if (i == tx_ring->count) {
4516 tx_desc = IGB_TX_DESC(tx_ring, 0);
4517 i = 0;
4518 }
80d0759e 4519 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4520
4521 dma += IGB_MAX_DATA_PER_TXD;
4522 size -= IGB_MAX_DATA_PER_TXD;
4523
ebe42d16
AD		 4524 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4525 }
4526
4527 if (likely(!data_len))
4528 break;
2bbfebe2 4529
1d9daf45 4530 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4531
65689fef 4532 i++;
ebe42d16
AD		 4533 tx_desc++;
4534 if (i == tx_ring->count) {
4535 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4536 i = 0;
ebe42d16 4537 }
80d0759e 4538 tx_desc->read.olinfo_status = 0;
65689fef 4539
9e903e08 4540 size = skb_frag_size(frag);
ebe42d16
AD		 4541 data_len -= size;
4542
4543 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4544 size, DMA_TO_DEVICE);
6366ad33 4545
c9f14bf3 4546 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4547 }
4548
ebe42d16 4549 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4550 cmd_type |= size | IGB_TXD_DCMD;
4551 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4552
80d0759e
AD		 4553 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4554
8542db05
AD		 4555 /* set the timestamp */
4556 first->time_stamp = jiffies;
4557
b980ac18 4558 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4559 * are new descriptors to fetch. (Only applicable for weak-ordered
4560 * memory model archs, such as IA-64).
4561 *
4562 * We also need this memory barrier to make certain all of the
4563 * status bits have been updated before next_to_watch is written.
4564 */
4565 wmb();
4566
8542db05 4567 /* set next_to_watch value indicating a packet is present */
ebe42d16 4568 first->next_to_watch = tx_desc;
9d5c8243 4569
ebe42d16
AD		 4570 i++;
4571 if (i == tx_ring->count)
4572 i = 0;
6366ad33 4573
ebe42d16 4574 tx_ring->next_to_use = i;
6366ad33 4575
ebe42d16 4576 writel(i, tx_ring->tail);
6366ad33 4577
ebe42d16 4578 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4579 * at a time, it synchronizes IO on IA64/Altix systems
4580 */
ebe42d16
AD		 4581 mmiowb();
4582
4583 return;
4584
4585dma_error:
4586 dev_err(tx_ring->dev, "TX DMA map failed\n");
4587
4588 /* clear dma mappings for failed tx_buffer_info map */
4589 for (;;) {
c9f14bf3
AD		 4590 tx_buffer = &tx_ring->tx_buffer_info[i];
4591 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4592 if (tx_buffer == first)
ebe42d16 4593 break;
a77ff709
NN		 4594 if (i == 0)
4595 i = tx_ring->count;
6366ad33 4596 i--;
6366ad33
AD		 4597 }
4598
9d5c8243 4599 tx_ring->next_to_use = i;
9d5c8243
AK		 4600}
4601
6ad4edfc 4602static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4603{
e694e964
AD		 4604 struct net_device *netdev = tx_ring->netdev;
4605
661086df 4606 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4607
9d5c8243
AK		 4608 /* Herbert's original patch had:
4609 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4610 * but since that doesn't exist yet, just open code it.
4611 */
9d5c8243
AK		 4612 smp_mb();
4613
4614 /* We need to check again in a case another CPU has just
b980ac18
JK		 4615 * made room available.
4616 */
c493ea45 4617 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4618 return -EBUSY;
4619
4620 /* A reprieve! */
661086df 4621 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4622
4623 u64_stats_update_begin(&tx_ring->tx_syncp2);
4624 tx_ring->tx_stats.restart_queue2++;
4625 u64_stats_update_end(&tx_ring->tx_syncp2);
4626
9d5c8243
AK		 4627 return 0;
4628}
4629
6ad4edfc 4630static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4631{
c493ea45 4632 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4633 return 0;
e694e964 4634 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4635}
4636
cd392f5c
AD		 4637netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4638 struct igb_ring *tx_ring)
9d5c8243 4639{
8542db05 4640 struct igb_tx_buffer *first;
ebe42d16 4641 int tso;
91d4ee33 4642 u32 tx_flags = 0;
21ba6fe1 4643 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4644 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4645 u8 hdr_len = 0;
9d5c8243 4646
21ba6fe1
AD		 4647 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4648 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4649 * + 2 desc gap to keep tail from touching head,
9d5c8243 4650 * + 1 desc for context descriptor,
21ba6fe1
AD		 4651 * otherwise try next time
4652 */
4653 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4654 unsigned short f;
4655 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4656 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4657 } else {
4658 count += skb_shinfo(skb)->nr_frags;
4659 }
4660
4661 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4662 /* this is a hard error */
9d5c8243
AK		 4663 return NETDEV_TX_BUSY;
4664 }
33af6bcc 4665
7af40ad9
AD		 4666 /* record the location of the first descriptor for this packet */
4667 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4668 first->skb = skb;
4669 first->bytecount = skb->len;
4670 first->gso_segs = 1;
4671
b66e2397
MV		 4672 skb_tx_timestamp(skb);
4673
b646c22e
AD		 4674 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4675 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4676
b646c22e
AD		 4677 if (!(adapter->ptp_tx_skb)) {
4678 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4679 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4680
4681 adapter->ptp_tx_skb = skb_get(skb);
4682 adapter->ptp_tx_start = jiffies;
4683 if (adapter->hw.mac.type == e1000_82576)
4684 schedule_work(&adapter->ptp_tx_work);
4685 }
33af6bcc 4686 }
9d5c8243 4687
eab6d18d 4688 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4689 tx_flags |= IGB_TX_FLAGS_VLAN;
4690 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4691 }
4692
7af40ad9
AD		 4693 /* record initial flags and protocol */
4694 first->tx_flags = tx_flags;
4695 first->protocol = protocol;
cdfd01fc 4696
7af40ad9
AD		 4697 tso = igb_tso(tx_ring, first, &hdr_len);
4698 if (tso < 0)
7d13a7d0 4699 goto out_drop;
7af40ad9
AD		 4700 else if (!tso)
4701 igb_tx_csum(tx_ring, first);
9d5c8243 4702
7af40ad9 4703 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4704
4705 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4706 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4707
9d5c8243 4708 return NETDEV_TX_OK;
7d13a7d0
AD		 4709
4710out_drop:
7af40ad9
AD		 4711 igb_unmap_and_free_tx_resource(tx_ring, first);
4712
7d13a7d0 4713 return NETDEV_TX_OK;
9d5c8243
AK		 4714}
4715
1cc3bd87
AD		 4716static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4717 struct sk_buff *skb)
4718{
4719 unsigned int r_idx = skb->queue_mapping;
4720
4721 if (r_idx >= adapter->num_tx_queues)
4722 r_idx = r_idx % adapter->num_tx_queues;
4723
4724 return adapter->tx_ring[r_idx];
4725}
4726
cd392f5c
AD		 4727static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4728 struct net_device *netdev)
9d5c8243
AK		 4729{
4730 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4731
4732 if (test_bit(__IGB_DOWN, &adapter->state)) {
4733 dev_kfree_skb_any(skb);
4734 return NETDEV_TX_OK;
4735 }
4736
4737 if (skb->len <= 0) {
4738 dev_kfree_skb_any(skb);
4739 return NETDEV_TX_OK;
4740 }
4741
b980ac18 4742 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4743 * in order to meet this minimum size requirement.
4744 */
ea5ceeab
TD		 4745 if (unlikely(skb->len < 17)) {
4746 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4747 return NETDEV_TX_OK;
4748 skb->len = 17;
ea5ceeab 4749 skb_set_tail_pointer(skb, 17);
1cc3bd87 4750 }
9d5c8243 4751
1cc3bd87 4752 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4753}
4754
4755/**
b980ac18
JK		 4756 * igb_tx_timeout - Respond to a Tx Hang
4757 * @netdev: network interface device structure
9d5c8243
AK		 4758 **/
4759static void igb_tx_timeout(struct net_device *netdev)
4760{
4761 struct igb_adapter *adapter = netdev_priv(netdev);
4762 struct e1000_hw *hw = &adapter->hw;
4763
4764 /* Do the reset outside of interrupt context */
4765 adapter->tx_timeout_count++;
f7ba205e 4766
06218a8d 4767 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4768 hw->dev_spec._82575.global_device_reset = true;
4769
9d5c8243 4770 schedule_work(&adapter->reset_task);
265de409
AD		 4771 wr32(E1000_EICS,
4772 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4773}
4774
4775static void igb_reset_task(struct work_struct *work)
4776{
4777 struct igb_adapter *adapter;
4778 adapter = container_of(work, struct igb_adapter, reset_task);
4779
c97ec42a
TI		 4780 igb_dump(adapter);
4781 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4782 igb_reinit_locked(adapter);
4783}
4784
4785/**
b980ac18
JK		 4786 * igb_get_stats64 - Get System Network Statistics
4787 * @netdev: network interface device structure
4788 * @stats: rtnl_link_stats64 pointer
9d5c8243 4789 **/
12dcd86b 4790static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 4791 struct rtnl_link_stats64 *stats)
9d5c8243 4792{
12dcd86b
ED		 4793 struct igb_adapter *adapter = netdev_priv(netdev);
4794
4795 spin_lock(&adapter->stats64_lock);
4796 igb_update_stats(adapter, &adapter->stats64);
4797 memcpy(stats, &adapter->stats64, sizeof(*stats));
4798 spin_unlock(&adapter->stats64_lock);
4799
4800 return stats;
9d5c8243
AK		 4801}
4802
4803/**
b980ac18
JK		 4804 * igb_change_mtu - Change the Maximum Transfer Unit
4805 * @netdev: network interface device structure
4806 * @new_mtu: new value for maximum frame size
9d5c8243 4807 *
b980ac18 4808 * Returns 0 on success, negative on failure
9d5c8243
AK		 4809 **/
4810static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4811{
4812 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4813 struct pci_dev *pdev = adapter->pdev;
153285f9 4814 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4815
c809d227 4816 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4817 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4818 return -EINVAL;
4819 }
4820
153285f9 4821#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4822 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4823 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4824 return -EINVAL;
4825 }
4826
2ccd994c
AD		 4827 /* adjust max frame to be at least the size of a standard frame */
4828 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4829 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4830
9d5c8243
AK		 4831 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4832 msleep(1);
73cd78f1 4833
9d5c8243
AK		 4834 /* igb_down has a dependency on max_frame_size */
4835 adapter->max_frame_size = max_frame;
559e9c49 4836
4c844851
AD		 4837 if (netif_running(netdev))
4838 igb_down(adapter);
9d5c8243 4839
090b1795 4840 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4841 netdev->mtu, new_mtu);
4842 netdev->mtu = new_mtu;
4843
4844 if (netif_running(netdev))
4845 igb_up(adapter);
4846 else
4847 igb_reset(adapter);
4848
4849 clear_bit(__IGB_RESETTING, &adapter->state);
4850
4851 return 0;
4852}
4853
4854/**
b980ac18
JK		 4855 * igb_update_stats - Update the board statistics counters
4856 * @adapter: board private structure
9d5c8243 4857 **/
12dcd86b
ED		 4858void igb_update_stats(struct igb_adapter *adapter,
4859 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4860{
4861 struct e1000_hw *hw = &adapter->hw;
4862 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4863 u32 reg, mpc;
9d5c8243 4864 u16 phy_tmp;
3f9c0164
AD		 4865 int i;
4866 u64 bytes, packets;
12dcd86b
ED		 4867 unsigned int start;
4868 u64 _bytes, _packets;
9d5c8243
AK		 4869
4870#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4871
b980ac18 4872 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 4873 * connection is down.
4874 */
4875 if (adapter->link_speed == 0)
4876 return;
4877 if (pci_channel_offline(pdev))
4878 return;
4879
3f9c0164
AD		 4880 bytes = 0;
4881 packets = 0;
7f90128e
AA		 4882
4883 rcu_read_lock();
3f9c0164 4884 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4885 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4886 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4887
ae1c07a6
AD		 4888 if (rqdpc) {
4889 ring->rx_stats.drops += rqdpc;
4890 net_stats->rx_fifo_errors += rqdpc;
4891 }
12dcd86b
ED		 4892
4893 do {
4894 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4895 _bytes = ring->rx_stats.bytes;
4896 _packets = ring->rx_stats.packets;
4897 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4898 bytes += _bytes;
4899 packets += _packets;
3f9c0164
AD		 4900 }
4901
128e45eb
AD		 4902 net_stats->rx_bytes = bytes;
4903 net_stats->rx_packets = packets;
3f9c0164
AD		 4904
4905 bytes = 0;
4906 packets = 0;
4907 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4908 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4909 do {
4910 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4911 _bytes = ring->tx_stats.bytes;
4912 _packets = ring->tx_stats.packets;
4913 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4914 bytes += _bytes;
4915 packets += _packets;
3f9c0164 4916 }
128e45eb
AD		 4917 net_stats->tx_bytes = bytes;
4918 net_stats->tx_packets = packets;
7f90128e 4919 rcu_read_unlock();
3f9c0164
AD		 4920
4921 /* read stats registers */
9d5c8243
AK		 4922 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4923 adapter->stats.gprc += rd32(E1000_GPRC);
4924 adapter->stats.gorc += rd32(E1000_GORCL);
4925 rd32(E1000_GORCH); /* clear GORCL */
4926 adapter->stats.bprc += rd32(E1000_BPRC);
4927 adapter->stats.mprc += rd32(E1000_MPRC);
4928 adapter->stats.roc += rd32(E1000_ROC);
4929
4930 adapter->stats.prc64 += rd32(E1000_PRC64);
4931 adapter->stats.prc127 += rd32(E1000_PRC127);
4932 adapter->stats.prc255 += rd32(E1000_PRC255);
4933 adapter->stats.prc511 += rd32(E1000_PRC511);
4934 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4935 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4936 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4937 adapter->stats.sec += rd32(E1000_SEC);
4938
fa3d9a6d
MW		 4939 mpc = rd32(E1000_MPC);
4940 adapter->stats.mpc += mpc;
4941 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4942 adapter->stats.scc += rd32(E1000_SCC);
4943 adapter->stats.ecol += rd32(E1000_ECOL);
4944 adapter->stats.mcc += rd32(E1000_MCC);
4945 adapter->stats.latecol += rd32(E1000_LATECOL);
4946 adapter->stats.dc += rd32(E1000_DC);
4947 adapter->stats.rlec += rd32(E1000_RLEC);
4948 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4949 adapter->stats.xontxc += rd32(E1000_XONTXC);
4950 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4951 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4952 adapter->stats.fcruc += rd32(E1000_FCRUC);
4953 adapter->stats.gptc += rd32(E1000_GPTC);
4954 adapter->stats.gotc += rd32(E1000_GOTCL);
4955 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4956 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4957 adapter->stats.ruc += rd32(E1000_RUC);
4958 adapter->stats.rfc += rd32(E1000_RFC);
4959 adapter->stats.rjc += rd32(E1000_RJC);
4960 adapter->stats.tor += rd32(E1000_TORH);
4961 adapter->stats.tot += rd32(E1000_TOTH);
4962 adapter->stats.tpr += rd32(E1000_TPR);
4963
4964 adapter->stats.ptc64 += rd32(E1000_PTC64);
4965 adapter->stats.ptc127 += rd32(E1000_PTC127);
4966 adapter->stats.ptc255 += rd32(E1000_PTC255);
4967 adapter->stats.ptc511 += rd32(E1000_PTC511);
4968 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4969 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4970
4971 adapter->stats.mptc += rd32(E1000_MPTC);
4972 adapter->stats.bptc += rd32(E1000_BPTC);
4973
2d0b0f69
NN		 4974 adapter->stats.tpt += rd32(E1000_TPT);
4975 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4976
4977 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4978 /* read internal phy specific stats */
4979 reg = rd32(E1000_CTRL_EXT);
4980 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4981 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4982
4983 /* this stat has invalid values on i210/i211 */
4984 if ((hw->mac.type != e1000_i210) &&
4985 (hw->mac.type != e1000_i211))
4986 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4987 }
4988
9d5c8243
AK		 4989 adapter->stats.tsctc += rd32(E1000_TSCTC);
4990 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4991
4992 adapter->stats.iac += rd32(E1000_IAC);
4993 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4994 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4995 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4996 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4997 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4998 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4999 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5000 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5001
5002 /* Fill out the OS statistics structure */
128e45eb
AD		 5003 net_stats->multicast = adapter->stats.mprc;
5004 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5005
5006 /* Rx Errors */
5007
5008 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5009 * our own version based on RUC and ROC
5010 */
128e45eb 5011 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5012 adapter->stats.crcerrs + adapter->stats.algnerrc +
5013 adapter->stats.ruc + adapter->stats.roc +
5014 adapter->stats.cexterr;
128e45eb
AD		 5015 net_stats->rx_length_errors = adapter->stats.ruc +
5016 adapter->stats.roc;
5017 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5018 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5019 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5020
5021 /* Tx Errors */
128e45eb
AD		 5022 net_stats->tx_errors = adapter->stats.ecol +
5023 adapter->stats.latecol;
5024 net_stats->tx_aborted_errors = adapter->stats.ecol;
5025 net_stats->tx_window_errors = adapter->stats.latecol;
5026 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5027
5028 /* Tx Dropped needs to be maintained elsewhere */
5029
5030 /* Phy Stats */
5031 if (hw->phy.media_type == e1000_media_type_copper) {
5032 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5033 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5034 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5035 adapter->phy_stats.idle_errors += phy_tmp;
5036 }
5037 }
5038
5039 /* Management Stats */
5040 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5041 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5042 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5043
5044 /* OS2BMC Stats */
5045 reg = rd32(E1000_MANC);
5046 if (reg & E1000_MANC_EN_BMC2OS) {
5047 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5048 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5049 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5050 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5051 }
9d5c8243
AK		 5052}
5053
9d5c8243
AK		 5054static irqreturn_t igb_msix_other(int irq, void *data)
5055{
047e0030 5056 struct igb_adapter *adapter = data;
9d5c8243 5057 struct e1000_hw *hw = &adapter->hw;
844290e5 5058 u32 icr = rd32(E1000_ICR);
844290e5 5059 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5060
7f081d40
AD		 5061 if (icr & E1000_ICR_DRSTA)
5062 schedule_work(&adapter->reset_task);
5063
047e0030 5064 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5065 /* HW is reporting DMA is out of sync */
5066 adapter->stats.doosync++;
13800469
GR		 5067 /* The DMA Out of Sync is also indication of a spoof event
5068 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5069 * see if it is really a spoof event.
5070 */
13800469 5071 igb_check_wvbr(adapter);
dda0e083 5072 }
eebbbdba 5073
4ae196df
AD		 5074 /* Check for a mailbox event */
5075 if (icr & E1000_ICR_VMMB)
5076 igb_msg_task(adapter);
5077
5078 if (icr & E1000_ICR_LSC) {
5079 hw->mac.get_link_status = 1;
5080 /* guard against interrupt when we're going down */
5081 if (!test_bit(__IGB_DOWN, &adapter->state))
5082 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5083 }
5084
1f6e8178
MV		 5085 if (icr & E1000_ICR_TS) {
5086 u32 tsicr = rd32(E1000_TSICR);
5087
5088 if (tsicr & E1000_TSICR_TXTS) {
5089 /* acknowledge the interrupt */
5090 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5091 /* retrieve hardware timestamp */
5092 schedule_work(&adapter->ptp_tx_work);
5093 }
5094 }
1f6e8178 5095
844290e5 5096 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5097
5098 return IRQ_HANDLED;
5099}
5100
047e0030 5101static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5102{
26b39276 5103 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5104 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5105
047e0030
AD		 5106 if (!q_vector->set_itr)
5107 return;
73cd78f1 5108
047e0030
AD		 5109 if (!itr_val)
5110 itr_val = 0x4;
661086df 5111
26b39276
AD		 5112 if (adapter->hw.mac.type == e1000_82575)
5113 itr_val |= itr_val << 16;
661086df 5114 else
0ba82994 5115 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5116
047e0030
AD		 5117 writel(itr_val, q_vector->itr_register);
5118 q_vector->set_itr = 0;
6eb5a7f1
AD		 5119}
5120
047e0030 5121static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5122{
047e0030 5123 struct igb_q_vector *q_vector = data;
9d5c8243 5124
047e0030
AD		 5125 /* Write the ITR value calculated from the previous interrupt. */
5126 igb_write_itr(q_vector);
9d5c8243 5127
047e0030 5128 napi_schedule(&q_vector->napi);
844290e5 5129
047e0030 5130 return IRQ_HANDLED;
fe4506b6
JC		 5131}
5132
421e02f0 5133#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5134static void igb_update_tx_dca(struct igb_adapter *adapter,
5135 struct igb_ring *tx_ring,
5136 int cpu)
5137{
5138 struct e1000_hw *hw = &adapter->hw;
5139 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5140
5141 if (hw->mac.type != e1000_82575)
5142 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5143
b980ac18 5144 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5145 * DCA is enabled. This is due to a known issue in some chipsets
5146 * which will cause the DCA tag to be cleared.
5147 */
5148 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5149 E1000_DCA_TXCTRL_DATA_RRO_EN |
5150 E1000_DCA_TXCTRL_DESC_DCA_EN;
5151
5152 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5153}
5154
5155static void igb_update_rx_dca(struct igb_adapter *adapter,
5156 struct igb_ring *rx_ring,
5157 int cpu)
5158{
5159 struct e1000_hw *hw = &adapter->hw;
5160 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5161
5162 if (hw->mac.type != e1000_82575)
5163 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5164
b980ac18 5165 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5166 * DCA is enabled. This is due to a known issue in some chipsets
5167 * which will cause the DCA tag to be cleared.
5168 */
5169 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5170 E1000_DCA_RXCTRL_DESC_DCA_EN;
5171
5172 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5173}
5174
047e0030 5175static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5176{
047e0030 5177 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5178 int cpu = get_cpu();
fe4506b6 5179
047e0030
AD		 5180 if (q_vector->cpu == cpu)
5181 goto out_no_update;
5182
6a05004a
AD		 5183 if (q_vector->tx.ring)
5184 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5185
5186 if (q_vector->rx.ring)
5187 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5188
047e0030
AD		 5189 q_vector->cpu = cpu;
5190out_no_update:
fe4506b6
JC		 5191 put_cpu();
5192}
5193
5194static void igb_setup_dca(struct igb_adapter *adapter)
5195{
7e0e99ef 5196 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5197 int i;
5198
7dfc16fa 5199 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5200 return;
5201
7e0e99ef
AD		 5202 /* Always use CB2 mode, difference is masked in the CB driver. */
5203 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5204
047e0030 5205 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5206 adapter->q_vector[i]->cpu = -1;
5207 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5208 }
5209}
5210
5211static int __igb_notify_dca(struct device *dev, void *data)
5212{
5213 struct net_device *netdev = dev_get_drvdata(dev);
5214 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5215 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5216 struct e1000_hw *hw = &adapter->hw;
5217 unsigned long event = *(unsigned long *)data;
5218
5219 switch (event) {
5220 case DCA_PROVIDER_ADD:
5221 /* if already enabled, don't do it again */
7dfc16fa 5222 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5223 break;
fe4506b6 5224 if (dca_add_requester(dev) == 0) {
bbd98fe4 5225 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5226 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5227 igb_setup_dca(adapter);
5228 break;
5229 }
5230 /* Fall Through since DCA is disabled. */
5231 case DCA_PROVIDER_REMOVE:
7dfc16fa 5232 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5233 /* without this a class_device is left
b980ac18
JK		 5234 * hanging around in the sysfs model
5235 */
fe4506b6 5236 dca_remove_requester(dev);
090b1795 5237 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5238 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5239 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5240 }
5241 break;
5242 }
bbd98fe4 5243
fe4506b6 5244 return 0;
9d5c8243
AK		 5245}
5246
fe4506b6 5247static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5248 void *p)
fe4506b6
JC		 5249{
5250 int ret_val;
5251
5252 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5253 __igb_notify_dca);
fe4506b6
JC		 5254
5255 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5256}
421e02f0 5257#endif /* CONFIG_IGB_DCA */
9d5c8243 5258
0224d663
GR		 5259#ifdef CONFIG_PCI_IOV
5260static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5261{
5262 unsigned char mac_addr[ETH_ALEN];
0224d663 5263
5ac6f91d 5264 eth_zero_addr(mac_addr);
0224d663
GR		 5265 igb_set_vf_mac(adapter, vf, mac_addr);
5266
70ea4783
LL		 5267 /* By default spoof check is enabled for all VFs */
5268 adapter->vf_data[vf].spoofchk_enabled = true;
5269
f557147c 5270 return 0;
0224d663
GR		 5271}
5272
0224d663 5273#endif
4ae196df
AD		 5274static void igb_ping_all_vfs(struct igb_adapter *adapter)
5275{
5276 struct e1000_hw *hw = &adapter->hw;
5277 u32 ping;
5278 int i;
5279
5280 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5281 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5282 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5283 ping |= E1000_VT_MSGTYPE_CTS;
5284 igb_write_mbx(hw, &ping, 1, i);
5285 }
5286}
5287
7d5753f0
AD		 5288static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5289{
5290 struct e1000_hw *hw = &adapter->hw;
5291 u32 vmolr = rd32(E1000_VMOLR(vf));
5292 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5293
d85b9004 5294 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5295 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5296 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5297
5298 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5299 vmolr |= E1000_VMOLR_MPME;
d85b9004 5300 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5301 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5302 } else {
b980ac18 5303 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5304 * flag we need to write the hashes to the MTA as this step
5305 * was previously skipped
5306 */
5307 if (vf_data->num_vf_mc_hashes > 30) {
5308 vmolr |= E1000_VMOLR_MPME;
5309 } else if (vf_data->num_vf_mc_hashes) {
5310 int j;
5311 vmolr |= E1000_VMOLR_ROMPE;
5312 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5313 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5314 }
5315 }
5316
5317 wr32(E1000_VMOLR(vf), vmolr);
5318
5319 /* there are flags left unprocessed, likely not supported */
5320 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5321 return -EINVAL;
5322
5323 return 0;
7d5753f0
AD		 5324}
5325
4ae196df
AD		 5326static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5327 u32 *msgbuf, u32 vf)
5328{
5329 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5330 u16 *hash_list = (u16 *)&msgbuf[1];
5331 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5332 int i;
5333
7d5753f0 5334 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5335 * to this VF for later use to restore when the PF multi cast
5336 * list changes
5337 */
5338 vf_data->num_vf_mc_hashes = n;
5339
7d5753f0
AD		 5340 /* only up to 30 hash values supported */
5341 if (n > 30)
5342 n = 30;
5343
5344 /* store the hashes for later use */
4ae196df 5345 for (i = 0; i < n; i++)
a419aef8 5346 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5347
5348 /* Flush and reset the mta with the new values */
ff41f8dc 5349 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5350
5351 return 0;
5352}
5353
5354static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5355{
5356 struct e1000_hw *hw = &adapter->hw;
5357 struct vf_data_storage *vf_data;
5358 int i, j;
5359
5360 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5361 u32 vmolr = rd32(E1000_VMOLR(i));
5362 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5363
4ae196df 5364 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5365
5366 if ((vf_data->num_vf_mc_hashes > 30) ||
5367 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5368 vmolr |= E1000_VMOLR_MPME;
5369 } else if (vf_data->num_vf_mc_hashes) {
5370 vmolr |= E1000_VMOLR_ROMPE;
5371 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5372 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5373 }
5374 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5375 }
5376}
5377
5378static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5379{
5380 struct e1000_hw *hw = &adapter->hw;
5381 u32 pool_mask, reg, vid;
5382 int i;
5383
5384 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5385
5386 /* Find the vlan filter for this id */
5387 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5388 reg = rd32(E1000_VLVF(i));
5389
5390 /* remove the vf from the pool */
5391 reg &= ~pool_mask;
5392
5393 /* if pool is empty then remove entry from vfta */
5394 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5395 (reg & E1000_VLVF_VLANID_ENABLE)) {
5396 reg = 0;
5397 vid = reg & E1000_VLVF_VLANID_MASK;
5398 igb_vfta_set(hw, vid, false);
5399 }
5400
5401 wr32(E1000_VLVF(i), reg);
5402 }
ae641bdc
AD		 5403
5404 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5405}
5406
5407static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5408{
5409 struct e1000_hw *hw = &adapter->hw;
5410 u32 reg, i;
5411
51466239
AD		 5412 /* The vlvf table only exists on 82576 hardware and newer */
5413 if (hw->mac.type < e1000_82576)
5414 return -1;
5415
5416 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5417 if (!adapter->vfs_allocated_count)
5418 return -1;
5419
5420 /* Find the vlan filter for this id */
5421 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5422 reg = rd32(E1000_VLVF(i));
5423 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5424 vid == (reg & E1000_VLVF_VLANID_MASK))
5425 break;
5426 }
5427
5428 if (add) {
5429 if (i == E1000_VLVF_ARRAY_SIZE) {
5430 /* Did not find a matching VLAN ID entry that was
5431 * enabled. Search for a free filter entry, i.e.
5432 * one without the enable bit set
5433 */
5434 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5435 reg = rd32(E1000_VLVF(i));
5436 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5437 break;
5438 }
5439 }
5440 if (i < E1000_VLVF_ARRAY_SIZE) {
5441 /* Found an enabled/available entry */
5442 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5443
5444 /* if !enabled we need to set this up in vfta */
5445 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5446 /* add VID to filter table */
5447 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5448 reg |= E1000_VLVF_VLANID_ENABLE;
5449 }
cad6d05f
AD		 5450 reg &= ~E1000_VLVF_VLANID_MASK;
5451 reg |= vid;
4ae196df 5452 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5453
5454 /* do not modify RLPML for PF devices */
5455 if (vf >= adapter->vfs_allocated_count)
5456 return 0;
5457
5458 if (!adapter->vf_data[vf].vlans_enabled) {
5459 u32 size;
5460 reg = rd32(E1000_VMOLR(vf));
5461 size = reg & E1000_VMOLR_RLPML_MASK;
5462 size += 4;
5463 reg &= ~E1000_VMOLR_RLPML_MASK;
5464 reg |= size;
5465 wr32(E1000_VMOLR(vf), reg);
5466 }
ae641bdc 5467
51466239 5468 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5469 }
5470 } else {
5471 if (i < E1000_VLVF_ARRAY_SIZE) {
5472 /* remove vf from the pool */
5473 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5474 /* if pool is empty then remove entry from vfta */
5475 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5476 reg = 0;
5477 igb_vfta_set(hw, vid, false);
5478 }
5479 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5480
5481 /* do not modify RLPML for PF devices */
5482 if (vf >= adapter->vfs_allocated_count)
5483 return 0;
5484
5485 adapter->vf_data[vf].vlans_enabled--;
5486 if (!adapter->vf_data[vf].vlans_enabled) {
5487 u32 size;
5488 reg = rd32(E1000_VMOLR(vf));
5489 size = reg & E1000_VMOLR_RLPML_MASK;
5490 size -= 4;
5491 reg &= ~E1000_VMOLR_RLPML_MASK;
5492 reg |= size;
5493 wr32(E1000_VMOLR(vf), reg);
5494 }
4ae196df
AD		 5495 }
5496 }
8151d294
WM		 5497 return 0;
5498}
5499
5500static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5501{
5502 struct e1000_hw *hw = &adapter->hw;
5503
5504 if (vid)
5505 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5506 else
5507 wr32(E1000_VMVIR(vf), 0);
5508}
5509
5510static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5511 int vf, u16 vlan, u8 qos)
5512{
5513 int err = 0;
5514 struct igb_adapter *adapter = netdev_priv(netdev);
5515
5516 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5517 return -EINVAL;
5518 if (vlan || qos) {
5519 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5520 if (err)
5521 goto out;
5522 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5523 igb_set_vmolr(adapter, vf, !vlan);
5524 adapter->vf_data[vf].pf_vlan = vlan;
5525 adapter->vf_data[vf].pf_qos = qos;
5526 dev_info(&adapter->pdev->dev,
5527 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5528 if (test_bit(__IGB_DOWN, &adapter->state)) {
5529 dev_warn(&adapter->pdev->dev,
b980ac18 5530 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5531 dev_warn(&adapter->pdev->dev,
b980ac18 5532 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5533 }
5534 } else {
5535 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5536 false, vf);
8151d294
WM		 5537 igb_set_vmvir(adapter, vlan, vf);
5538 igb_set_vmolr(adapter, vf, true);
5539 adapter->vf_data[vf].pf_vlan = 0;
5540 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5541 }
8151d294 5542out:
b980ac18 5543 return err;
4ae196df
AD		 5544}
5545
6f3dc319
GR		 5546static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5547{
5548 struct e1000_hw *hw = &adapter->hw;
5549 int i;
5550 u32 reg;
5551
5552 /* Find the vlan filter for this id */
5553 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5554 reg = rd32(E1000_VLVF(i));
5555 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5556 vid == (reg & E1000_VLVF_VLANID_MASK))
5557 break;
5558 }
5559
5560 if (i >= E1000_VLVF_ARRAY_SIZE)
5561 i = -1;
5562
5563 return i;
5564}
5565
4ae196df
AD		 5566static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5567{
6f3dc319 5568 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5569 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5570 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5571 int err = 0;
4ae196df 5572
6f3dc319
GR		 5573 /* If in promiscuous mode we need to make sure the PF also has
5574 * the VLAN filter set.
5575 */
5576 if (add && (adapter->netdev->flags & IFF_PROMISC))
5577 err = igb_vlvf_set(adapter, vid, add,
5578 adapter->vfs_allocated_count);
5579 if (err)
5580 goto out;
5581
5582 err = igb_vlvf_set(adapter, vid, add, vf);
5583
5584 if (err)
5585 goto out;
5586
5587 /* Go through all the checks to see if the VLAN filter should
5588 * be wiped completely.
5589 */
5590 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5591 u32 vlvf, bits;
5592
5593 int regndx = igb_find_vlvf_entry(adapter, vid);
5594 if (regndx < 0)
5595 goto out;
5596 /* See if any other pools are set for this VLAN filter
5597 * entry other than the PF.
5598 */
5599 vlvf = bits = rd32(E1000_VLVF(regndx));
5600 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5601 adapter->vfs_allocated_count);
5602 /* If the filter was removed then ensure PF pool bit
5603 * is cleared if the PF only added itself to the pool
5604 * because the PF is in promiscuous mode.
5605 */
5606 if ((vlvf & VLAN_VID_MASK) == vid &&
5607 !test_bit(vid, adapter->active_vlans) &&
5608 !bits)
5609 igb_vlvf_set(adapter, vid, add,
5610 adapter->vfs_allocated_count);
5611 }
5612
5613out:
5614 return err;
4ae196df
AD		 5615}
5616
f2ca0dbe 5617static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5618{
8fa7e0f7
GR		 5619 /* clear flags - except flag that indicates PF has set the MAC */
5620 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5621 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5622
5623 /* reset offloads to defaults */
8151d294 5624 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5625
5626 /* reset vlans for device */
5627 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5628 if (adapter->vf_data[vf].pf_vlan)
5629 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5630 adapter->vf_data[vf].pf_vlan,
5631 adapter->vf_data[vf].pf_qos);
5632 else
5633 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5634
5635 /* reset multicast table array for vf */
5636 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5637
5638 /* Flush and reset the mta with the new values */
ff41f8dc 5639 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5640}
5641
f2ca0dbe
AD		 5642static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5643{
5644 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5645
5ac6f91d 5646 /* clear mac address as we were hotplug removed/added */
8151d294 5647 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5648 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5649
5650 /* process remaining reset events */
5651 igb_vf_reset(adapter, vf);
5652}
5653
5654static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5655{
5656 struct e1000_hw *hw = &adapter->hw;
5657 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5658 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5659 u32 reg, msgbuf[3];
5660 u8 *addr = (u8 *)(&msgbuf[1]);
5661
5662 /* process all the same items cleared in a function level reset */
f2ca0dbe 5663 igb_vf_reset(adapter, vf);
4ae196df
AD		 5664
5665 /* set vf mac address */
26ad9178 5666 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5667
5668 /* enable transmit and receive for vf */
5669 reg = rd32(E1000_VFTE);
5670 wr32(E1000_VFTE, reg | (1 << vf));
5671 reg = rd32(E1000_VFRE);
5672 wr32(E1000_VFRE, reg | (1 << vf));
5673
8fa7e0f7 5674 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5675
5676 /* reply to reset with ack and vf mac address */
5677 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5678 memcpy(addr, vf_mac, 6);
5679 igb_write_mbx(hw, msgbuf, 3, vf);
5680}
5681
5682static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5683{
b980ac18 5684 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5685 * starting at the second 32 bit word of the msg array
5686 */
f2ca0dbe
AD		 5687 unsigned char *addr = (char *)&msg[1];
5688 int err = -1;
4ae196df 5689
f2ca0dbe
AD		 5690 if (is_valid_ether_addr(addr))
5691 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5692
f2ca0dbe 5693 return err;
4ae196df
AD		 5694}
5695
5696static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5697{
5698 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5699 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5700 u32 msg = E1000_VT_MSGTYPE_NACK;
5701
5702 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5703 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5704 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5705 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5706 vf_data->last_nack = jiffies;
4ae196df
AD		 5707 }
5708}
5709
f2ca0dbe 5710static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5711{
f2ca0dbe
AD		 5712 struct pci_dev *pdev = adapter->pdev;
5713 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5714 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5715 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5716 s32 retval;
5717
f2ca0dbe 5718 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5719
fef45f4c
AD		 5720 if (retval) {
5721 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5722 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5723 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5724 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5725 return;
5726 goto out;
5727 }
4ae196df
AD		 5728
5729 /* this is a message we already processed, do nothing */
5730 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5731 return;
4ae196df 5732
b980ac18 5733 /* until the vf completes a reset it should not be
4ae196df
AD		 5734 * allowed to start any configuration.
5735 */
4ae196df
AD		 5736 if (msgbuf[0] == E1000_VF_RESET) {
5737 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5738 return;
4ae196df
AD		 5739 }
5740
f2ca0dbe 5741 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5742 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5743 return;
5744 retval = -1;
5745 goto out;
4ae196df
AD		 5746 }
5747
5748 switch ((msgbuf[0] & 0xFFFF)) {
5749 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5750 retval = -EINVAL;
5751 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5752 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5753 else
5754 dev_warn(&pdev->dev,
b980ac18
JK		 5755 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5756 vf);
4ae196df 5757 break;
7d5753f0
AD		 5758 case E1000_VF_SET_PROMISC:
5759 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5760 break;
4ae196df
AD		 5761 case E1000_VF_SET_MULTICAST:
5762 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5763 break;
5764 case E1000_VF_SET_LPE:
5765 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5766 break;
5767 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5768 retval = -1;
5769 if (vf_data->pf_vlan)
5770 dev_warn(&pdev->dev,
b980ac18
JK		 5771 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5772 vf);
8151d294
WM		 5773 else
5774 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5775 break;
5776 default:
090b1795 5777 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5778 retval = -1;
5779 break;
5780 }
5781
fef45f4c
AD		 5782 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5783out:
4ae196df
AD		 5784 /* notify the VF of the results of what it sent us */
5785 if (retval)
5786 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5787 else
5788 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5789
4ae196df 5790 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5791}
4ae196df 5792
f2ca0dbe
AD		 5793static void igb_msg_task(struct igb_adapter *adapter)
5794{
5795 struct e1000_hw *hw = &adapter->hw;
5796 u32 vf;
5797
5798 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5799 /* process any reset requests */
5800 if (!igb_check_for_rst(hw, vf))
5801 igb_vf_reset_event(adapter, vf);
5802
5803 /* process any messages pending */
5804 if (!igb_check_for_msg(hw, vf))
5805 igb_rcv_msg_from_vf(adapter, vf);
5806
5807 /* process any acks */
5808 if (!igb_check_for_ack(hw, vf))
5809 igb_rcv_ack_from_vf(adapter, vf);
5810 }
4ae196df
AD		 5811}
5812
68d480c4
AD		 5813/**
5814 * igb_set_uta - Set unicast filter table address
5815 * @adapter: board private structure
5816 *
5817 * The unicast table address is a register array of 32-bit registers.
5818 * The table is meant to be used in a way similar to how the MTA is used
5819 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5820 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5821 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5822 **/
5823static void igb_set_uta(struct igb_adapter *adapter)
5824{
5825 struct e1000_hw *hw = &adapter->hw;
5826 int i;
5827
5828 /* The UTA table only exists on 82576 hardware and newer */
5829 if (hw->mac.type < e1000_82576)
5830 return;
5831
5832 /* we only need to do this if VMDq is enabled */
5833 if (!adapter->vfs_allocated_count)
5834 return;
5835
5836 for (i = 0; i < hw->mac.uta_reg_count; i++)
5837 array_wr32(E1000_UTA, i, ~0);
5838}
5839
9d5c8243 5840/**
b980ac18
JK		 5841 * igb_intr_msi - Interrupt Handler
5842 * @irq: interrupt number
5843 * @data: pointer to a network interface device structure
9d5c8243
AK		 5844 **/
5845static irqreturn_t igb_intr_msi(int irq, void *data)
5846{
047e0030
AD		 5847 struct igb_adapter *adapter = data;
5848 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5849 struct e1000_hw *hw = &adapter->hw;
5850 /* read ICR disables interrupts using IAM */
5851 u32 icr = rd32(E1000_ICR);
5852
047e0030 5853 igb_write_itr(q_vector);
9d5c8243 5854
7f081d40
AD		 5855 if (icr & E1000_ICR_DRSTA)
5856 schedule_work(&adapter->reset_task);
5857
047e0030 5858 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5859 /* HW is reporting DMA is out of sync */
5860 adapter->stats.doosync++;
5861 }
5862
9d5c8243
AK		 5863 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5864 hw->mac.get_link_status = 1;
5865 if (!test_bit(__IGB_DOWN, &adapter->state))
5866 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5867 }
5868
1f6e8178
MV		 5869 if (icr & E1000_ICR_TS) {
5870 u32 tsicr = rd32(E1000_TSICR);
5871
5872 if (tsicr & E1000_TSICR_TXTS) {
5873 /* acknowledge the interrupt */
5874 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5875 /* retrieve hardware timestamp */
5876 schedule_work(&adapter->ptp_tx_work);
5877 }
5878 }
1f6e8178 5879
047e0030 5880 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5881
5882 return IRQ_HANDLED;
5883}
5884
5885/**
b980ac18
JK		 5886 * igb_intr - Legacy Interrupt Handler
5887 * @irq: interrupt number
5888 * @data: pointer to a network interface device structure
9d5c8243
AK		 5889 **/
5890static irqreturn_t igb_intr(int irq, void *data)
5891{
047e0030
AD		 5892 struct igb_adapter *adapter = data;
5893 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5894 struct e1000_hw *hw = &adapter->hw;
5895 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 5896 * need for the IMC write
5897 */
9d5c8243 5898 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5899
5900 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 5901 * not set, then the adapter didn't send an interrupt
5902 */
9d5c8243
AK		 5903 if (!(icr & E1000_ICR_INT_ASSERTED))
5904 return IRQ_NONE;
5905
0ba82994
AD		 5906 igb_write_itr(q_vector);
5907
7f081d40
AD		 5908 if (icr & E1000_ICR_DRSTA)
5909 schedule_work(&adapter->reset_task);
5910
047e0030 5911 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5912 /* HW is reporting DMA is out of sync */
5913 adapter->stats.doosync++;
5914 }
5915
9d5c8243
AK		 5916 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5917 hw->mac.get_link_status = 1;
5918 /* guard against interrupt when we're going down */
5919 if (!test_bit(__IGB_DOWN, &adapter->state))
5920 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5921 }
5922
1f6e8178
MV		 5923 if (icr & E1000_ICR_TS) {
5924 u32 tsicr = rd32(E1000_TSICR);
5925
5926 if (tsicr & E1000_TSICR_TXTS) {
5927 /* acknowledge the interrupt */
5928 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5929 /* retrieve hardware timestamp */
5930 schedule_work(&adapter->ptp_tx_work);
5931 }
5932 }
1f6e8178 5933
047e0030 5934 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5935
5936 return IRQ_HANDLED;
5937}
5938
c50b52a0 5939static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5940{
047e0030 5941 struct igb_adapter *adapter = q_vector->adapter;
46544258 5942 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5943
0ba82994
AD		 5944 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5945 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5946 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5947 igb_set_itr(q_vector);
46544258 5948 else
047e0030 5949 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5950 }
5951
46544258
AD		 5952 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5953 if (adapter->msix_entries)
047e0030 5954 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5955 else
5956 igb_irq_enable(adapter);
5957 }
9d5c8243
AK		 5958}
5959
46544258 5960/**
b980ac18
JK		 5961 * igb_poll - NAPI Rx polling callback
5962 * @napi: napi polling structure
5963 * @budget: count of how many packets we should handle
46544258
AD		 5964 **/
5965static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5966{
047e0030 5967 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 5968 struct igb_q_vector,
5969 napi);
16eb8815 5970 bool clean_complete = true;
9d5c8243 5971
421e02f0 5972#ifdef CONFIG_IGB_DCA
047e0030
AD		 5973 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5974 igb_update_dca(q_vector);
fe4506b6 5975#endif
0ba82994 5976 if (q_vector->tx.ring)
13fde97a 5977 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5978
0ba82994 5979 if (q_vector->rx.ring)
cd392f5c 5980 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5981
16eb8815
AD		 5982 /* If all work not completed, return budget and keep polling */
5983 if (!clean_complete)
5984 return budget;
46544258 5985
9d5c8243 5986 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5987 napi_complete(napi);
5988 igb_ring_irq_enable(q_vector);
9d5c8243 5989
16eb8815 5990 return 0;
9d5c8243 5991}
6d8126f9 5992
9d5c8243 5993/**
b980ac18
JK		 5994 * igb_clean_tx_irq - Reclaim resources after transmit completes
5995 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5996 *
b980ac18 5997 * returns true if ring is completely cleaned
9d5c8243 5998 **/
047e0030 5999static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6000{
047e0030 6001 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6002 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6003 struct igb_tx_buffer *tx_buffer;
f4128785 6004 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6005 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6006 unsigned int budget = q_vector->tx.work_limit;
8542db05 6007 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6008
13fde97a
AD		 6009 if (test_bit(__IGB_DOWN, &adapter->state))
6010 return true;
0e014cb1 6011
06034649 6012 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6013 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6014 i -= tx_ring->count;
9d5c8243 6015
f4128785
AD		 6016 do {
6017 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6018
6019 /* if next_to_watch is not set then there is no work pending */
6020 if (!eop_desc)
6021 break;
13fde97a 6022
f4128785 6023 /* prevent any other reads prior to eop_desc */
70d289bc 6024 read_barrier_depends();
f4128785 6025
13fde97a
AD		 6026 /* if DD is not set pending work has not been completed */
6027 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6028 break;
6029
8542db05
AD		 6030 /* clear next_to_watch to prevent false hangs */
6031 tx_buffer->next_to_watch = NULL;
9d5c8243 6032
ebe42d16
AD		 6033 /* update the statistics for this packet */
6034 total_bytes += tx_buffer->bytecount;
6035 total_packets += tx_buffer->gso_segs;
13fde97a 6036
ebe42d16
AD		 6037 /* free the skb */
6038 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6039
ebe42d16
AD		 6040 /* unmap skb header data */
6041 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6042 dma_unmap_addr(tx_buffer, dma),
6043 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6044 DMA_TO_DEVICE);
6045
c9f14bf3
AD		 6046 /* clear tx_buffer data */
6047 tx_buffer->skb = NULL;
6048 dma_unmap_len_set(tx_buffer, len, 0);
6049
ebe42d16
AD		 6050 /* clear last DMA location and unmap remaining buffers */
6051 while (tx_desc != eop_desc) {
13fde97a
AD		 6052 tx_buffer++;
6053 tx_desc++;
9d5c8243 6054 i++;
8542db05
AD		 6055 if (unlikely(!i)) {
6056 i -= tx_ring->count;
06034649 6057 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6058 tx_desc = IGB_TX_DESC(tx_ring, 0);
6059 }
ebe42d16
AD		 6060
6061 /* unmap any remaining paged data */
c9f14bf3 6062 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6063 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6064 dma_unmap_addr(tx_buffer, dma),
6065 dma_unmap_len(tx_buffer, len),
ebe42d16 6066 DMA_TO_DEVICE);
c9f14bf3 6067 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6068 }
6069 }
6070
ebe42d16
AD		 6071 /* move us one more past the eop_desc for start of next pkt */
6072 tx_buffer++;
6073 tx_desc++;
6074 i++;
6075 if (unlikely(!i)) {
6076 i -= tx_ring->count;
6077 tx_buffer = tx_ring->tx_buffer_info;
6078 tx_desc = IGB_TX_DESC(tx_ring, 0);
6079 }
f4128785
AD		 6080
6081 /* issue prefetch for next Tx descriptor */
6082 prefetch(tx_desc);
6083
6084 /* update budget accounting */
6085 budget--;
6086 } while (likely(budget));
0e014cb1 6087
bdbc0631
ED		 6088 netdev_tx_completed_queue(txring_txq(tx_ring),
6089 total_packets, total_bytes);
8542db05 6090 i += tx_ring->count;
9d5c8243 6091 tx_ring->next_to_clean = i;
13fde97a
AD		 6092 u64_stats_update_begin(&tx_ring->tx_syncp);
6093 tx_ring->tx_stats.bytes += total_bytes;
6094 tx_ring->tx_stats.packets += total_packets;
6095 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6096 q_vector->tx.total_bytes += total_bytes;
6097 q_vector->tx.total_packets += total_packets;
9d5c8243 6098
6d095fa8 6099 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6100 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6101
9d5c8243 6102 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6103 * check with the clearing of time_stamp and movement of i
6104 */
6d095fa8 6105 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6106 if (tx_buffer->next_to_watch &&
8542db05 6107 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6108 (adapter->tx_timeout_factor * HZ)) &&
6109 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6110
9d5c8243 6111 /* detected Tx unit hang */
59d71989 6112 dev_err(tx_ring->dev,
9d5c8243 6113 "Detected Tx Unit Hang\n"
2d064c06 6114 " Tx Queue <%d>\n"
9d5c8243
AK		 6115 " TDH <%x>\n"
6116 " TDT <%x>\n"
6117 " next_to_use <%x>\n"
6118 " next_to_clean <%x>\n"
9d5c8243
AK		 6119 "buffer_info[next_to_clean]\n"
6120 " time_stamp <%lx>\n"
8542db05 6121 " next_to_watch <%p>\n"
9d5c8243
AK		 6122 " jiffies <%lx>\n"
6123 " desc.status <%x>\n",
2d064c06 6124 tx_ring->queue_index,
238ac817 6125 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6126 readl(tx_ring->tail),
9d5c8243
AK		 6127 tx_ring->next_to_use,
6128 tx_ring->next_to_clean,
8542db05 6129 tx_buffer->time_stamp,
f4128785 6130 tx_buffer->next_to_watch,
9d5c8243 6131 jiffies,
f4128785 6132 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6133 netif_stop_subqueue(tx_ring->netdev,
6134 tx_ring->queue_index);
6135
6136 /* we are about to reset, no point in enabling stuff */
6137 return true;
9d5c8243
AK		 6138 }
6139 }
13fde97a 6140
21ba6fe1 6141#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6142 if (unlikely(total_packets &&
b980ac18
JK		 6143 netif_carrier_ok(tx_ring->netdev) &&
6144 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6145 /* Make sure that anybody stopping the queue after this
6146 * sees the new next_to_clean.
6147 */
6148 smp_mb();
6149 if (__netif_subqueue_stopped(tx_ring->netdev,
6150 tx_ring->queue_index) &&
6151 !(test_bit(__IGB_DOWN, &adapter->state))) {
6152 netif_wake_subqueue(tx_ring->netdev,
6153 tx_ring->queue_index);
6154
6155 u64_stats_update_begin(&tx_ring->tx_syncp);
6156 tx_ring->tx_stats.restart_queue++;
6157 u64_stats_update_end(&tx_ring->tx_syncp);
6158 }
6159 }
6160
6161 return !!budget;
9d5c8243
AK		 6162}
6163
cbc8e55f 6164/**
b980ac18
JK		 6165 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6166 * @rx_ring: rx descriptor ring to store buffers on
6167 * @old_buff: donor buffer to have page reused
cbc8e55f 6168 *
b980ac18 6169 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6170 **/
6171static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6172 struct igb_rx_buffer *old_buff)
6173{
6174 struct igb_rx_buffer *new_buff;
6175 u16 nta = rx_ring->next_to_alloc;
6176
6177 new_buff = &rx_ring->rx_buffer_info[nta];
6178
6179 /* update, and store next to alloc */
6180 nta++;
6181 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6182
6183 /* transfer page from old buffer to new buffer */
6184 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6185
6186 /* sync the buffer for use by the device */
6187 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6188 old_buff->page_offset,
de78d1f9 6189 IGB_RX_BUFSZ,
cbc8e55f
AD		 6190 DMA_FROM_DEVICE);
6191}
6192
74e238ea
AD		 6193static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6194 struct page *page,
6195 unsigned int truesize)
6196{
6197 /* avoid re-using remote pages */
6198 if (unlikely(page_to_nid(page) != numa_node_id()))
6199 return false;
6200
6201#if (PAGE_SIZE < 8192)
6202 /* if we are only owner of page we can reuse it */
6203 if (unlikely(page_count(page) != 1))
6204 return false;
6205
6206 /* flip page offset to other buffer */
6207 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6208
6209 /* since we are the only owner of the page and we need to
6210 * increment it, just set the value to 2 in order to avoid
6211 * an unnecessary locked operation
6212 */
6213 atomic_set(&page->_count, 2);
6214#else
6215 /* move offset up to the next cache line */
6216 rx_buffer->page_offset += truesize;
6217
6218 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6219 return false;
6220
6221 /* bump ref count on page before it is given to the stack */
6222 get_page(page);
6223#endif
6224
6225 return true;
6226}
6227
cbc8e55f 6228/**
b980ac18
JK		 6229 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6230 * @rx_ring: rx descriptor ring to transact packets on
6231 * @rx_buffer: buffer containing page to add
6232 * @rx_desc: descriptor containing length of buffer written by hardware
6233 * @skb: sk_buff to place the data into
cbc8e55f 6234 *
b980ac18
JK		 6235 * This function will add the data contained in rx_buffer->page to the skb.
6236 * This is done either through a direct copy if the data in the buffer is
6237 * less than the skb header size, otherwise it will just attach the page as
6238 * a frag to the skb.
cbc8e55f 6239 *
b980ac18
JK		 6240 * The function will then update the page offset if necessary and return
6241 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6242 **/
6243static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6244 struct igb_rx_buffer *rx_buffer,
6245 union e1000_adv_rx_desc *rx_desc,
6246 struct sk_buff *skb)
6247{
6248 struct page *page = rx_buffer->page;
6249 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6250#if (PAGE_SIZE < 8192)
6251 unsigned int truesize = IGB_RX_BUFSZ;
6252#else
6253 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6254#endif
cbc8e55f
AD		 6255
6256 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6257 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6258
cbc8e55f
AD		 6259 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6260 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6261 va += IGB_TS_HDR_LEN;
6262 size -= IGB_TS_HDR_LEN;
6263 }
6264
cbc8e55f
AD		 6265 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6266
6267 /* we can reuse buffer as-is, just make sure it is local */
6268 if (likely(page_to_nid(page) == numa_node_id()))
6269 return true;
6270
6271 /* this page cannot be reused so discard it */
6272 put_page(page);
6273 return false;
6274 }
6275
6276 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6277 rx_buffer->page_offset, size, truesize);
cbc8e55f 6278
74e238ea
AD		 6279 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6280}
cbc8e55f 6281
2e334eee
AD		 6282static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6283 union e1000_adv_rx_desc *rx_desc,
6284 struct sk_buff *skb)
6285{
6286 struct igb_rx_buffer *rx_buffer;
6287 struct page *page;
6288
6289 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6290
2e334eee
AD		 6291 page = rx_buffer->page;
6292 prefetchw(page);
6293
6294 if (likely(!skb)) {
6295 void *page_addr = page_address(page) +
6296 rx_buffer->page_offset;
6297
6298 /* prefetch first cache line of first page */
6299 prefetch(page_addr);
6300#if L1_CACHE_BYTES < 128
6301 prefetch(page_addr + L1_CACHE_BYTES);
6302#endif
6303
6304 /* allocate a skb to store the frags */
6305 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6306 IGB_RX_HDR_LEN);
6307 if (unlikely(!skb)) {
6308 rx_ring->rx_stats.alloc_failed++;
6309 return NULL;
6310 }
6311
b980ac18 6312 /* we will be copying header into skb->data in
2e334eee
AD		 6313 * pskb_may_pull so it is in our interest to prefetch
6314 * it now to avoid a possible cache miss
6315 */
6316 prefetchw(skb->data);
6317 }
6318
6319 /* we are reusing so sync this buffer for CPU use */
6320 dma_sync_single_range_for_cpu(rx_ring->dev,
6321 rx_buffer->dma,
6322 rx_buffer->page_offset,
de78d1f9 6323 IGB_RX_BUFSZ,
2e334eee
AD		 6324 DMA_FROM_DEVICE);
6325
6326 /* pull page into skb */
6327 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6328 /* hand second half of page back to the ring */
6329 igb_reuse_rx_page(rx_ring, rx_buffer);
6330 } else {
6331 /* we are not reusing the buffer so unmap it */
6332 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6333 PAGE_SIZE, DMA_FROM_DEVICE);
6334 }
6335
6336 /* clear contents of rx_buffer */
6337 rx_buffer->page = NULL;
6338
6339 return skb;
6340}
6341
cd392f5c 6342static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6343 union e1000_adv_rx_desc *rx_desc,
6344 struct sk_buff *skb)
9d5c8243 6345{
bc8acf2c 6346 skb_checksum_none_assert(skb);
9d5c8243 6347
294e7d78 6348 /* Ignore Checksum bit is set */
3ceb90fd 6349 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6350 return;
6351
6352 /* Rx checksum disabled via ethtool */
6353 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6354 return;
85ad76b2 6355
9d5c8243 6356 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6357 if (igb_test_staterr(rx_desc,
6358 E1000_RXDEXT_STATERR_TCPE |
6359 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6360 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6361 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6362 * packets, (aka let the stack check the crc32c)
6363 */
866cff06
AD		 6364 if (!((skb->len == 60) &&
6365 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6366 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6367 ring->rx_stats.csum_err++;
12dcd86b
ED		 6368 u64_stats_update_end(&ring->rx_syncp);
6369 }
9d5c8243 6370 /* let the stack verify checksum errors */
9d5c8243
AK		 6371 return;
6372 }
6373 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6374 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6375 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6376 skb->ip_summed = CHECKSUM_UNNECESSARY;
6377
3ceb90fd
AD		 6378 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6379 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6380}
6381
077887c3
AD		 6382static inline void igb_rx_hash(struct igb_ring *ring,
6383 union e1000_adv_rx_desc *rx_desc,
6384 struct sk_buff *skb)
6385{
6386 if (ring->netdev->features & NETIF_F_RXHASH)
6387 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6388}
6389
2e334eee 6390/**
b980ac18
JK		 6391 * igb_is_non_eop - process handling of non-EOP buffers
6392 * @rx_ring: Rx ring being processed
6393 * @rx_desc: Rx descriptor for current buffer
6394 * @skb: current socket buffer containing buffer in progress
2e334eee 6395 *
b980ac18
JK		 6396 * This function updates next to clean. If the buffer is an EOP buffer
6397 * this function exits returning false, otherwise it will place the
6398 * sk_buff in the next buffer to be chained and return true indicating
6399 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6400 **/
6401static bool igb_is_non_eop(struct igb_ring *rx_ring,
6402 union e1000_adv_rx_desc *rx_desc)
6403{
6404 u32 ntc = rx_ring->next_to_clean + 1;
6405
6406 /* fetch, update, and store next to clean */
6407 ntc = (ntc < rx_ring->count) ? ntc : 0;
6408 rx_ring->next_to_clean = ntc;
6409
6410 prefetch(IGB_RX_DESC(rx_ring, ntc));
6411
6412 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6413 return false;
6414
6415 return true;
6416}
6417
1a1c225b 6418/**
b980ac18
JK		 6419 * igb_get_headlen - determine size of header for LRO/GRO
6420 * @data: pointer to the start of the headers
6421 * @max_len: total length of section to find headers in
1a1c225b 6422 *
b980ac18
JK		 6423 * This function is meant to determine the length of headers that will
6424 * be recognized by hardware for LRO, and GRO offloads. The main
6425 * motivation of doing this is to only perform one pull for IPv4 TCP
6426 * packets so that we can do basic things like calculating the gso_size
6427 * based on the average data per packet.
1a1c225b
AD		 6428 **/
6429static unsigned int igb_get_headlen(unsigned char *data,
6430 unsigned int max_len)
6431{
6432 union {
6433 unsigned char *network;
6434 /* l2 headers */
6435 struct ethhdr *eth;
6436 struct vlan_hdr *vlan;
6437 /* l3 headers */
6438 struct iphdr *ipv4;
6439 struct ipv6hdr *ipv6;
6440 } hdr;
6441 __be16 protocol;
6442 u8 nexthdr = 0; /* default to not TCP */
6443 u8 hlen;
6444
6445 /* this should never happen, but better safe than sorry */
6446 if (max_len < ETH_HLEN)
6447 return max_len;
6448
6449 /* initialize network frame pointer */
6450 hdr.network = data;
6451
6452 /* set first protocol and move network header forward */
6453 protocol = hdr.eth->h_proto;
6454 hdr.network += ETH_HLEN;
6455
6456 /* handle any vlan tag if present */
6457 if (protocol == __constant_htons(ETH_P_8021Q)) {
6458 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6459 return max_len;
6460
6461 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6462 hdr.network += VLAN_HLEN;
6463 }
6464
6465 /* handle L3 protocols */
6466 if (protocol == __constant_htons(ETH_P_IP)) {
6467 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6468 return max_len;
6469
6470 /* access ihl as a u8 to avoid unaligned access on ia64 */
6471 hlen = (hdr.network[0] & 0x0F) << 2;
6472
6473 /* verify hlen meets minimum size requirements */
6474 if (hlen < sizeof(struct iphdr))
6475 return hdr.network - data;
6476
f2fb4ab2 6477 /* record next protocol if header is present */
b9555f66 6478 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6479 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6480 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6481 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6482 return max_len;
6483
6484 /* record next protocol */
6485 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6486 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6487 } else {
6488 return hdr.network - data;
6489 }
6490
f2fb4ab2
AD		 6491 /* relocate pointer to start of L4 header */
6492 hdr.network += hlen;
6493
1a1c225b
AD		 6494 /* finally sort out TCP */
6495 if (nexthdr == IPPROTO_TCP) {
6496 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6497 return max_len;
6498
6499 /* access doff as a u8 to avoid unaligned access on ia64 */
6500 hlen = (hdr.network[12] & 0xF0) >> 2;
6501
6502 /* verify hlen meets minimum size requirements */
6503 if (hlen < sizeof(struct tcphdr))
6504 return hdr.network - data;
6505
6506 hdr.network += hlen;
6507 } else if (nexthdr == IPPROTO_UDP) {
6508 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6509 return max_len;
6510
6511 hdr.network += sizeof(struct udphdr);
6512 }
6513
b980ac18 6514 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6515 * data section of the packet and will be the end of the header.
6516 * If not then it probably represents the end of the last recognized
6517 * header.
6518 */
6519 if ((hdr.network - data) < max_len)
6520 return hdr.network - data;
6521 else
6522 return max_len;
6523}
6524
6525/**
b980ac18
JK		 6526 * igb_pull_tail - igb specific version of skb_pull_tail
6527 * @rx_ring: rx descriptor ring packet is being transacted on
6528 * @rx_desc: pointer to the EOP Rx descriptor
6529 * @skb: pointer to current skb being adjusted
1a1c225b 6530 *
b980ac18
JK		 6531 * This function is an igb specific version of __pskb_pull_tail. The
6532 * main difference between this version and the original function is that
6533 * this function can make several assumptions about the state of things
6534 * that allow for significant optimizations versus the standard function.
6535 * As a result we can do things like drop a frag and maintain an accurate
6536 * truesize for the skb.
1a1c225b
AD		 6537 */
6538static void igb_pull_tail(struct igb_ring *rx_ring,
6539 union e1000_adv_rx_desc *rx_desc,
6540 struct sk_buff *skb)
2d94d8ab 6541{
1a1c225b
AD		 6542 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6543 unsigned char *va;
6544 unsigned int pull_len;
6545
b980ac18 6546 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6547 * working with pages allocated out of the lomem pool per
6548 * alloc_page(GFP_ATOMIC)
2d94d8ab 6549 */
1a1c225b
AD		 6550 va = skb_frag_address(frag);
6551
1a1c225b
AD		 6552 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6553 /* retrieve timestamp from buffer */
6554 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6555
6556 /* update pointers to remove timestamp header */
6557 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6558 frag->page_offset += IGB_TS_HDR_LEN;
6559 skb->data_len -= IGB_TS_HDR_LEN;
6560 skb->len -= IGB_TS_HDR_LEN;
6561
6562 /* move va to start of packet data */
6563 va += IGB_TS_HDR_LEN;
6564 }
6565
b980ac18 6566 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6567 * 60 bytes if the skb->len is less than 60 for skb_pad.
6568 */
6569 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6570
6571 /* align pull length to size of long to optimize memcpy performance */
6572 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6573
6574 /* update all of the pointers */
6575 skb_frag_size_sub(frag, pull_len);
6576 frag->page_offset += pull_len;
6577 skb->data_len -= pull_len;
6578 skb->tail += pull_len;
6579}
6580
6581/**
b980ac18
JK		 6582 * igb_cleanup_headers - Correct corrupted or empty headers
6583 * @rx_ring: rx descriptor ring packet is being transacted on
6584 * @rx_desc: pointer to the EOP Rx descriptor
6585 * @skb: pointer to current skb being fixed
1a1c225b 6586 *
b980ac18
JK		 6587 * Address the case where we are pulling data in on pages only
6588 * and as such no data is present in the skb header.
1a1c225b 6589 *
b980ac18
JK		 6590 * In addition if skb is not at least 60 bytes we need to pad it so that
6591 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6592 *
b980ac18 6593 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6594 **/
6595static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6596 union e1000_adv_rx_desc *rx_desc,
6597 struct sk_buff *skb)
6598{
1a1c225b
AD		 6599 if (unlikely((igb_test_staterr(rx_desc,
6600 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6601 struct net_device *netdev = rx_ring->netdev;
6602 if (!(netdev->features & NETIF_F_RXALL)) {
6603 dev_kfree_skb_any(skb);
6604 return true;
6605 }
6606 }
6607
6608 /* place header in linear portion of buffer */
6609 if (skb_is_nonlinear(skb))
6610 igb_pull_tail(rx_ring, rx_desc, skb);
6611
6612 /* if skb_pad returns an error the skb was freed */
6613 if (unlikely(skb->len < 60)) {
6614 int pad_len = 60 - skb->len;
6615
6616 if (skb_pad(skb, pad_len))
6617 return true;
6618 __skb_put(skb, pad_len);
6619 }
6620
6621 return false;
2d94d8ab
AD		 6622}
6623
db2ee5bd 6624/**
b980ac18
JK		 6625 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6626 * @rx_ring: rx descriptor ring packet is being transacted on
6627 * @rx_desc: pointer to the EOP Rx descriptor
6628 * @skb: pointer to current skb being populated
db2ee5bd 6629 *
b980ac18
JK		 6630 * This function checks the ring, descriptor, and packet information in
6631 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6632 * other fields within the skb.
db2ee5bd
AD		 6633 **/
6634static void igb_process_skb_fields(struct igb_ring *rx_ring,
6635 union e1000_adv_rx_desc *rx_desc,
6636 struct sk_buff *skb)
6637{
6638 struct net_device *dev = rx_ring->netdev;
6639
6640 igb_rx_hash(rx_ring, rx_desc, skb);
6641
6642 igb_rx_checksum(rx_ring, rx_desc, skb);
6643
20a48412 6644 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6645
f646968f 6646 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6647 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6648 u16 vid;
6649 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6650 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6651 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6652 else
6653 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6654
86a9bad3 6655 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6656 }
6657
6658 skb_record_rx_queue(skb, rx_ring->queue_index);
6659
6660 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6661}
6662
2e334eee 6663static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6664{
0ba82994 6665 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6666 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6667 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6668 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6669
2e334eee
AD		 6670 do {
6671 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6672
2e334eee
AD		 6673 /* return some buffers to hardware, one at a time is too slow */
6674 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6675 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6676 cleaned_count = 0;
6677 }
bf36c1a0 6678
2e334eee 6679 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6680
2e334eee
AD		 6681 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6682 break;
9d5c8243 6683
74e238ea
AD		 6684 /* This memory barrier is needed to keep us from reading
6685 * any other fields out of the rx_desc until we know the
6686 * RXD_STAT_DD bit is set
6687 */
6688 rmb();
6689
2e334eee 6690 /* retrieve a buffer from the ring */
f9d40f6a 6691 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6692
2e334eee
AD		 6693 /* exit if we failed to retrieve a buffer */
6694 if (!skb)
6695 break;
1a1c225b 6696
2e334eee 6697 cleaned_count++;
1a1c225b 6698
2e334eee
AD		 6699 /* fetch next buffer in frame if non-eop */
6700 if (igb_is_non_eop(rx_ring, rx_desc))
6701 continue;
1a1c225b
AD		 6702
6703 /* verify the packet layout is correct */
6704 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6705 skb = NULL;
6706 continue;
9d5c8243 6707 }
9d5c8243 6708
db2ee5bd 6709 /* probably a little skewed due to removing CRC */
3ceb90fd 6710 total_bytes += skb->len;
3ceb90fd 6711
db2ee5bd
AD		 6712 /* populate checksum, timestamp, VLAN, and protocol */
6713 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6714
b2cb09b1 6715 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6716
1a1c225b
AD		 6717 /* reset skb pointer */
6718 skb = NULL;
6719
2e334eee
AD		 6720 /* update budget accounting */
6721 total_packets++;
6722 } while (likely(total_packets < budget));
bf36c1a0 6723
1a1c225b
AD		 6724 /* place incomplete frames back on ring for completion */
6725 rx_ring->skb = skb;
6726
12dcd86b 6727 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6728 rx_ring->rx_stats.packets += total_packets;
6729 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6730 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6731 q_vector->rx.total_packets += total_packets;
6732 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6733
6734 if (cleaned_count)
cd392f5c 6735 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6736
2e334eee 6737 return (total_packets < budget);
9d5c8243
AK		 6738}
6739
c023cd88 6740static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6741 struct igb_rx_buffer *bi)
c023cd88
AD		 6742{
6743 struct page *page = bi->page;
cbc8e55f 6744 dma_addr_t dma;
c023cd88 6745
cbc8e55f
AD		 6746 /* since we are recycling buffers we should seldom need to alloc */
6747 if (likely(page))
c023cd88
AD		 6748 return true;
6749
cbc8e55f
AD		 6750 /* alloc new page for storage */
6751 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6752 if (unlikely(!page)) {
6753 rx_ring->rx_stats.alloc_failed++;
6754 return false;
c023cd88
AD		 6755 }
6756
cbc8e55f
AD		 6757 /* map page for use */
6758 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6759
b980ac18 6760 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6761 * there isn't much point in holding memory we can't use
6762 */
1a1c225b 6763 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6764 __free_page(page);
6765
c023cd88
AD		 6766 rx_ring->rx_stats.alloc_failed++;
6767 return false;
6768 }
6769
1a1c225b 6770 bi->dma = dma;
cbc8e55f
AD		 6771 bi->page = page;
6772 bi->page_offset = 0;
1a1c225b 6773
c023cd88
AD		 6774 return true;
6775}
6776
9d5c8243 6777/**
b980ac18
JK		 6778 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6779 * @adapter: address of board private structure
9d5c8243 6780 **/
cd392f5c 6781void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6782{
9d5c8243 6783 union e1000_adv_rx_desc *rx_desc;
06034649 6784 struct igb_rx_buffer *bi;
c023cd88 6785 u16 i = rx_ring->next_to_use;
9d5c8243 6786
cbc8e55f
AD		 6787 /* nothing to do */
6788 if (!cleaned_count)
6789 return;
6790
60136906 6791 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6792 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6793 i -= rx_ring->count;
9d5c8243 6794
cbc8e55f 6795 do {
1a1c225b 6796 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6797 break;
9d5c8243 6798
b980ac18 6799 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6800 * because each write-back erases this info.
6801 */
f9d40f6a 6802 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6803
c023cd88
AD		 6804 rx_desc++;
6805 bi++;
9d5c8243 6806 i++;
c023cd88 6807 if (unlikely(!i)) {
60136906 6808 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6809 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6810 i -= rx_ring->count;
6811 }
6812
6813 /* clear the hdr_addr for the next_to_use descriptor */
6814 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6815
6816 cleaned_count--;
6817 } while (cleaned_count);
9d5c8243 6818
c023cd88
AD		 6819 i += rx_ring->count;
6820
9d5c8243 6821 if (rx_ring->next_to_use != i) {
cbc8e55f 6822 /* record the next descriptor to use */
9d5c8243 6823 rx_ring->next_to_use = i;
9d5c8243 6824
cbc8e55f
AD		 6825 /* update next to alloc since we have filled the ring */
6826 rx_ring->next_to_alloc = i;
6827
b980ac18 6828 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 6829 * know there are new descriptors to fetch. (Only
6830 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6831 * such as IA-64).
6832 */
9d5c8243 6833 wmb();
fce99e34 6834 writel(i, rx_ring->tail);
9d5c8243
AK		 6835 }
6836}
6837
6838/**
6839 * igb_mii_ioctl -
6840 * @netdev:
6841 * @ifreq:
6842 * @cmd:
6843 **/
6844static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6845{
6846 struct igb_adapter *adapter = netdev_priv(netdev);
6847 struct mii_ioctl_data *data = if_mii(ifr);
6848
6849 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6850 return -EOPNOTSUPP;
6851
6852 switch (cmd) {
6853 case SIOCGMIIPHY:
6854 data->phy_id = adapter->hw.phy.addr;
6855 break;
6856 case SIOCGMIIREG:
f5f4cf08
AD		 6857 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6858 &data->val_out))
9d5c8243
AK		 6859 return -EIO;
6860 break;
6861 case SIOCSMIIREG:
6862 default:
6863 return -EOPNOTSUPP;
6864 }
6865 return 0;
6866}
6867
6868/**
6869 * igb_ioctl -
6870 * @netdev:
6871 * @ifreq:
6872 * @cmd:
6873 **/
6874static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6875{
6876 switch (cmd) {
6877 case SIOCGMIIPHY:
6878 case SIOCGMIIREG:
6879 case SIOCSMIIREG:
6880 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6881 case SIOCSHWTSTAMP:
a79f4f88 6882 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6883 default:
6884 return -EOPNOTSUPP;
6885 }
6886}
6887
009bc06e
AD		 6888s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6889{
6890 struct igb_adapter *adapter = hw->back;
009bc06e 6891
23d028cc 6892 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6893 return -E1000_ERR_CONFIG;
6894
009bc06e
AD		 6895 return 0;
6896}
6897
6898s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6899{
6900 struct igb_adapter *adapter = hw->back;
009bc06e 6901
23d028cc 6902 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6903 return -E1000_ERR_CONFIG;
6904
009bc06e
AD		 6905 return 0;
6906}
6907
c8f44aff 6908static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6909{
6910 struct igb_adapter *adapter = netdev_priv(netdev);
6911 struct e1000_hw *hw = &adapter->hw;
6912 u32 ctrl, rctl;
f646968f 6913 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 6914
5faf030c 6915 if (enable) {
9d5c8243
AK		 6916 /* enable VLAN tag insert/strip */
6917 ctrl = rd32(E1000_CTRL);
6918 ctrl |= E1000_CTRL_VME;
6919 wr32(E1000_CTRL, ctrl);
6920
51466239 6921 /* Disable CFI check */
9d5c8243 6922 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6923 rctl &= ~E1000_RCTL_CFIEN;
6924 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6925 } else {
6926 /* disable VLAN tag insert/strip */
6927 ctrl = rd32(E1000_CTRL);
6928 ctrl &= ~E1000_CTRL_VME;
6929 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6930 }
6931
e1739522 6932 igb_rlpml_set(adapter);
9d5c8243
AK		 6933}
6934
80d5c368
PM		 6935static int igb_vlan_rx_add_vid(struct net_device *netdev,
6936 __be16 proto, u16 vid)
9d5c8243
AK		 6937{
6938 struct igb_adapter *adapter = netdev_priv(netdev);
6939 struct e1000_hw *hw = &adapter->hw;
4ae196df 6940 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6941
51466239
AD		 6942 /* attempt to add filter to vlvf array */
6943 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6944
51466239
AD		 6945 /* add the filter since PF can receive vlans w/o entry in vlvf */
6946 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6947
6948 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6949
6950 return 0;
9d5c8243
AK		 6951}
6952
80d5c368
PM		 6953static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6954 __be16 proto, u16 vid)
9d5c8243
AK		 6955{
6956 struct igb_adapter *adapter = netdev_priv(netdev);
6957 struct e1000_hw *hw = &adapter->hw;
4ae196df 6958 int pf_id = adapter->vfs_allocated_count;
51466239 6959 s32 err;
9d5c8243 6960
51466239
AD		 6961 /* remove vlan from VLVF table array */
6962 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6963
51466239
AD		 6964 /* if vid was not present in VLVF just remove it from table */
6965 if (err)
4ae196df 6966 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6967
6968 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6969
6970 return 0;
9d5c8243
AK		 6971}
6972
6973static void igb_restore_vlan(struct igb_adapter *adapter)
6974{
b2cb09b1 6975 u16 vid;
9d5c8243 6976
5faf030c
AD		 6977 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6978
b2cb09b1 6979 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 6980 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 6981}
6982
14ad2513 6983int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6984{
090b1795 6985 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6986 struct e1000_mac_info *mac = &adapter->hw.mac;
6987
6988 mac->autoneg = 0;
6989
14ad2513 6990 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 6991 * for the switch() below to work
6992 */
14ad2513
DD		 6993 if ((spd & 1) || (dplx & ~1))
6994 goto err_inval;
6995
f502ef7d
AA		 6996 /* Fiber NIC's only allow 1000 gbps Full duplex
6997 * and 100Mbps Full duplex for 100baseFx sfp
6998 */
6999 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7000 switch (spd + dplx) {
7001 case SPEED_10 + DUPLEX_HALF:
7002 case SPEED_10 + DUPLEX_FULL:
7003 case SPEED_100 + DUPLEX_HALF:
7004 goto err_inval;
7005 default:
7006 break;
7007 }
7008 }
cd2638a8 7009
14ad2513 7010 switch (spd + dplx) {
9d5c8243
AK		 7011 case SPEED_10 + DUPLEX_HALF:
7012 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7013 break;
7014 case SPEED_10 + DUPLEX_FULL:
7015 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7016 break;
7017 case SPEED_100 + DUPLEX_HALF:
7018 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7019 break;
7020 case SPEED_100 + DUPLEX_FULL:
7021 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7022 break;
7023 case SPEED_1000 + DUPLEX_FULL:
7024 mac->autoneg = 1;
7025 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7026 break;
7027 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7028 default:
14ad2513 7029 goto err_inval;
9d5c8243 7030 }
8376dad0
JB		 7031
7032 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7033 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7034
9d5c8243 7035 return 0;
14ad2513
DD		 7036
7037err_inval:
7038 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7039 return -EINVAL;
9d5c8243
AK		 7040}
7041
749ab2cd
YZ		 7042static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7043 bool runtime)
9d5c8243
AK		 7044{
7045 struct net_device *netdev = pci_get_drvdata(pdev);
7046 struct igb_adapter *adapter = netdev_priv(netdev);
7047 struct e1000_hw *hw = &adapter->hw;
2d064c06 7048 u32 ctrl, rctl, status;
749ab2cd 7049 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7050#ifdef CONFIG_PM
7051 int retval = 0;
7052#endif
7053
7054 netif_device_detach(netdev);
7055
a88f10ec 7056 if (netif_running(netdev))
749ab2cd 7057 __igb_close(netdev, true);
a88f10ec 7058
047e0030 7059 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7060
7061#ifdef CONFIG_PM
7062 retval = pci_save_state(pdev);
7063 if (retval)
7064 return retval;
7065#endif
7066
7067 status = rd32(E1000_STATUS);
7068 if (status & E1000_STATUS_LU)
7069 wufc &= ~E1000_WUFC_LNKC;
7070
7071 if (wufc) {
7072 igb_setup_rctl(adapter);
ff41f8dc 7073 igb_set_rx_mode(netdev);
9d5c8243
AK		 7074
7075 /* turn on all-multi mode if wake on multicast is enabled */
7076 if (wufc & E1000_WUFC_MC) {
7077 rctl = rd32(E1000_RCTL);
7078 rctl |= E1000_RCTL_MPE;
7079 wr32(E1000_RCTL, rctl);
7080 }
7081
7082 ctrl = rd32(E1000_CTRL);
7083 /* advertise wake from D3Cold */
7084 #define E1000_CTRL_ADVD3WUC 0x00100000
7085 /* phy power management enable */
7086 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7087 ctrl |= E1000_CTRL_ADVD3WUC;
7088 wr32(E1000_CTRL, ctrl);
7089
9d5c8243 7090 /* Allow time for pending master requests to run */
330a6d6a 7091 igb_disable_pcie_master(hw);
9d5c8243
AK		 7092
7093 wr32(E1000_WUC, E1000_WUC_PME_EN);
7094 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7095 } else {
7096 wr32(E1000_WUC, 0);
7097 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7098 }
7099
3fe7c4c9
RW		 7100 *enable_wake = wufc || adapter->en_mng_pt;
7101 if (!*enable_wake)
88a268c1
NN		 7102 igb_power_down_link(adapter);
7103 else
7104 igb_power_up_link(adapter);
9d5c8243
AK		 7105
7106 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7107 * would have already happened in close and is redundant.
7108 */
9d5c8243
AK		 7109 igb_release_hw_control(adapter);
7110
7111 pci_disable_device(pdev);
7112
9d5c8243
AK		 7113 return 0;
7114}
7115
7116#ifdef CONFIG_PM
d9dd966d 7117#ifdef CONFIG_PM_SLEEP
749ab2cd 7118static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7119{
7120 int retval;
7121 bool wake;
749ab2cd 7122 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7123
749ab2cd 7124 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7125 if (retval)
7126 return retval;
7127
7128 if (wake) {
7129 pci_prepare_to_sleep(pdev);
7130 } else {
7131 pci_wake_from_d3(pdev, false);
7132 pci_set_power_state(pdev, PCI_D3hot);
7133 }
7134
7135 return 0;
7136}
d9dd966d 7137#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7138
749ab2cd 7139static int igb_resume(struct device *dev)
9d5c8243 7140{
749ab2cd 7141 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7142 struct net_device *netdev = pci_get_drvdata(pdev);
7143 struct igb_adapter *adapter = netdev_priv(netdev);
7144 struct e1000_hw *hw = &adapter->hw;
7145 u32 err;
7146
7147 pci_set_power_state(pdev, PCI_D0);
7148 pci_restore_state(pdev);
b94f2d77 7149 pci_save_state(pdev);
42bfd33a 7150
aed5dec3 7151 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7152 if (err) {
7153 dev_err(&pdev->dev,
7154 "igb: Cannot enable PCI device from suspend\n");
7155 return err;
7156 }
7157 pci_set_master(pdev);
7158
7159 pci_enable_wake(pdev, PCI_D3hot, 0);
7160 pci_enable_wake(pdev, PCI_D3cold, 0);
7161
53c7d064 7162 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7163 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7164 return -ENOMEM;
9d5c8243
AK		 7165 }
7166
9d5c8243 7167 igb_reset(adapter);
a8564f03
AD		 7168
7169 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7170 * driver.
7171 */
a8564f03
AD		 7172 igb_get_hw_control(adapter);
7173
9d5c8243
AK		 7174 wr32(E1000_WUS, ~0);
7175
749ab2cd 7176 if (netdev->flags & IFF_UP) {
0c2cc02e 7177 rtnl_lock();
749ab2cd 7178 err = __igb_open(netdev, true);
0c2cc02e 7179 rtnl_unlock();
a88f10ec
AD		 7180 if (err)
7181 return err;
7182 }
9d5c8243
AK		 7183
7184 netif_device_attach(netdev);
749ab2cd
YZ		 7185 return 0;
7186}
7187
7188#ifdef CONFIG_PM_RUNTIME
7189static int igb_runtime_idle(struct device *dev)
7190{
7191 struct pci_dev *pdev = to_pci_dev(dev);
7192 struct net_device *netdev = pci_get_drvdata(pdev);
7193 struct igb_adapter *adapter = netdev_priv(netdev);
7194
7195 if (!igb_has_link(adapter))
7196 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7197
7198 return -EBUSY;
7199}
7200
7201static int igb_runtime_suspend(struct device *dev)
7202{
7203 struct pci_dev *pdev = to_pci_dev(dev);
7204 int retval;
7205 bool wake;
7206
7207 retval = __igb_shutdown(pdev, &wake, 1);
7208 if (retval)
7209 return retval;
7210
7211 if (wake) {
7212 pci_prepare_to_sleep(pdev);
7213 } else {
7214 pci_wake_from_d3(pdev, false);
7215 pci_set_power_state(pdev, PCI_D3hot);
7216 }
9d5c8243 7217
9d5c8243
AK		 7218 return 0;
7219}
749ab2cd
YZ		 7220
7221static int igb_runtime_resume(struct device *dev)
7222{
7223 return igb_resume(dev);
7224}
7225#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7226#endif
7227
7228static void igb_shutdown(struct pci_dev *pdev)
7229{
3fe7c4c9
RW		 7230 bool wake;
7231
749ab2cd 7232 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7233
7234 if (system_state == SYSTEM_POWER_OFF) {
7235 pci_wake_from_d3(pdev, wake);
7236 pci_set_power_state(pdev, PCI_D3hot);
7237 }
9d5c8243
AK		 7238}
7239
fa44f2f1
GR		 7240#ifdef CONFIG_PCI_IOV
7241static int igb_sriov_reinit(struct pci_dev *dev)
7242{
7243 struct net_device *netdev = pci_get_drvdata(dev);
7244 struct igb_adapter *adapter = netdev_priv(netdev);
7245 struct pci_dev *pdev = adapter->pdev;
7246
7247 rtnl_lock();
7248
7249 if (netif_running(netdev))
7250 igb_close(netdev);
7251
7252 igb_clear_interrupt_scheme(adapter);
7253
7254 igb_init_queue_configuration(adapter);
7255
7256 if (igb_init_interrupt_scheme(adapter, true)) {
7257 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7258 return -ENOMEM;
7259 }
7260
7261 if (netif_running(netdev))
7262 igb_open(netdev);
7263
7264 rtnl_unlock();
7265
7266 return 0;
7267}
7268
7269static int igb_pci_disable_sriov(struct pci_dev *dev)
7270{
7271 int err = igb_disable_sriov(dev);
7272
7273 if (!err)
7274 err = igb_sriov_reinit(dev);
7275
7276 return err;
7277}
7278
7279static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7280{
7281 int err = igb_enable_sriov(dev, num_vfs);
7282
7283 if (err)
7284 goto out;
7285
7286 err = igb_sriov_reinit(dev);
7287 if (!err)
7288 return num_vfs;
7289
7290out:
7291 return err;
7292}
7293
7294#endif
7295static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7296{
7297#ifdef CONFIG_PCI_IOV
7298 if (num_vfs == 0)
7299 return igb_pci_disable_sriov(dev);
7300 else
7301 return igb_pci_enable_sriov(dev, num_vfs);
7302#endif
7303 return 0;
7304}
7305
9d5c8243 7306#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7307/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7308 * without having to re-enable interrupts. It's not called while
7309 * the interrupt routine is executing.
7310 */
7311static void igb_netpoll(struct net_device *netdev)
7312{
7313 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7314 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7315 struct igb_q_vector *q_vector;
9d5c8243 7316 int i;
9d5c8243 7317
047e0030 7318 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7319 q_vector = adapter->q_vector[i];
7320 if (adapter->msix_entries)
7321 wr32(E1000_EIMC, q_vector->eims_value);
7322 else
7323 igb_irq_disable(adapter);
047e0030 7324 napi_schedule(&q_vector->napi);
eebbbdba 7325 }
9d5c8243
AK		 7326}
7327#endif /* CONFIG_NET_POLL_CONTROLLER */
7328
7329/**
b980ac18
JK		 7330 * igb_io_error_detected - called when PCI error is detected
7331 * @pdev: Pointer to PCI device
7332 * @state: The current pci connection state
9d5c8243 7333 *
b980ac18
JK		 7334 * This function is called after a PCI bus error affecting
7335 * this device has been detected.
7336 **/
9d5c8243
AK		 7337static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7338 pci_channel_state_t state)
7339{
7340 struct net_device *netdev = pci_get_drvdata(pdev);
7341 struct igb_adapter *adapter = netdev_priv(netdev);
7342
7343 netif_device_detach(netdev);
7344
59ed6eec
AD		 7345 if (state == pci_channel_io_perm_failure)
7346 return PCI_ERS_RESULT_DISCONNECT;
7347
9d5c8243
AK		 7348 if (netif_running(netdev))
7349 igb_down(adapter);
7350 pci_disable_device(pdev);
7351
7352 /* Request a slot slot reset. */
7353 return PCI_ERS_RESULT_NEED_RESET;
7354}
7355
7356/**
b980ac18
JK		 7357 * igb_io_slot_reset - called after the pci bus has been reset.
7358 * @pdev: Pointer to PCI device
9d5c8243 7359 *
b980ac18
JK		 7360 * Restart the card from scratch, as if from a cold-boot. Implementation
7361 * resembles the first-half of the igb_resume routine.
7362 **/
9d5c8243
AK		 7363static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7364{
7365 struct net_device *netdev = pci_get_drvdata(pdev);
7366 struct igb_adapter *adapter = netdev_priv(netdev);
7367 struct e1000_hw *hw = &adapter->hw;
40a914fa 7368 pci_ers_result_t result;
42bfd33a 7369 int err;
9d5c8243 7370
aed5dec3 7371 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7372 dev_err(&pdev->dev,
7373 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7374 result = PCI_ERS_RESULT_DISCONNECT;
7375 } else {
7376 pci_set_master(pdev);
7377 pci_restore_state(pdev);
b94f2d77 7378 pci_save_state(pdev);
9d5c8243 7379
40a914fa
AD		 7380 pci_enable_wake(pdev, PCI_D3hot, 0);
7381 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7382
40a914fa
AD		 7383 igb_reset(adapter);
7384 wr32(E1000_WUS, ~0);
7385 result = PCI_ERS_RESULT_RECOVERED;
7386 }
9d5c8243 7387
ea943d41
JK		 7388 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7389 if (err) {
b980ac18
JK		 7390 dev_err(&pdev->dev,
7391 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7392 err);
ea943d41
JK		 7393 /* non-fatal, continue */
7394 }
40a914fa
AD		 7395
7396 return result;
9d5c8243
AK		 7397}
7398
7399/**
b980ac18
JK		 7400 * igb_io_resume - called when traffic can start flowing again.
7401 * @pdev: Pointer to PCI device
9d5c8243 7402 *
b980ac18
JK		 7403 * This callback is called when the error recovery driver tells us that
7404 * its OK to resume normal operation. Implementation resembles the
7405 * second-half of the igb_resume routine.
9d5c8243
AK		 7406 */
7407static void igb_io_resume(struct pci_dev *pdev)
7408{
7409 struct net_device *netdev = pci_get_drvdata(pdev);
7410 struct igb_adapter *adapter = netdev_priv(netdev);
7411
9d5c8243
AK		 7412 if (netif_running(netdev)) {
7413 if (igb_up(adapter)) {
7414 dev_err(&pdev->dev, "igb_up failed after reset\n");
7415 return;
7416 }
7417 }
7418
7419 netif_device_attach(netdev);
7420
7421 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7422 * driver.
7423 */
9d5c8243 7424 igb_get_hw_control(adapter);
9d5c8243
AK		 7425}
7426
26ad9178 7427static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7428 u8 qsel)
26ad9178
AD		 7429{
7430 u32 rar_low, rar_high;
7431 struct e1000_hw *hw = &adapter->hw;
7432
7433 /* HW expects these in little endian so we reverse the byte order
7434 * from network order (big endian) to little endian
7435 */
7436 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7437 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7438 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7439
7440 /* Indicate to hardware the Address is Valid. */
7441 rar_high |= E1000_RAH_AV;
7442
7443 if (hw->mac.type == e1000_82575)
7444 rar_high |= E1000_RAH_POOL_1 * qsel;
7445 else
7446 rar_high |= E1000_RAH_POOL_1 << qsel;
7447
7448 wr32(E1000_RAL(index), rar_low);
7449 wrfl();
7450 wr32(E1000_RAH(index), rar_high);
7451 wrfl();
7452}
7453
4ae196df 7454static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7455 int vf, unsigned char *mac_addr)
4ae196df
AD		 7456{
7457 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7458 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7459 * towards the first, as a result a collision should not be possible
7460 */
ff41f8dc 7461 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7462
37680117 7463 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7464
26ad9178 7465 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7466
7467 return 0;
7468}
7469
8151d294
WM		 7470static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7471{
7472 struct igb_adapter *adapter = netdev_priv(netdev);
7473 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7474 return -EINVAL;
7475 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7476 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7477 dev_info(&adapter->pdev->dev,
7478 "Reload the VF driver to make this change effective.");
8151d294 7479 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7480 dev_warn(&adapter->pdev->dev,
7481 "The VF MAC address has been set, but the PF device is not up.\n");
7482 dev_warn(&adapter->pdev->dev,
7483 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7484 }
7485 return igb_set_vf_mac(adapter, vf, mac);
7486}
7487
17dc566c
LL		 7488static int igb_link_mbps(int internal_link_speed)
7489{
7490 switch (internal_link_speed) {
7491 case SPEED_100:
7492 return 100;
7493 case SPEED_1000:
7494 return 1000;
7495 default:
7496 return 0;
7497 }
7498}
7499
7500static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7501 int link_speed)
7502{
7503 int rf_dec, rf_int;
7504 u32 bcnrc_val;
7505
7506 if (tx_rate != 0) {
7507 /* Calculate the rate factor values to set */
7508 rf_int = link_speed / tx_rate;
7509 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7510 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7511 tx_rate;
17dc566c
LL		 7512
7513 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7514 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7515 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7516 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7517 } else {
7518 bcnrc_val = 0;
7519 }
7520
7521 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7522 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7523 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7524 */
7525 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7526 wr32(E1000_RTTBCNRC, bcnrc_val);
7527}
7528
7529static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7530{
7531 int actual_link_speed, i;
7532 bool reset_rate = false;
7533
7534 /* VF TX rate limit was not set or not supported */
7535 if ((adapter->vf_rate_link_speed == 0) ||
7536 (adapter->hw.mac.type != e1000_82576))
7537 return;
7538
7539 actual_link_speed = igb_link_mbps(adapter->link_speed);
7540 if (actual_link_speed != adapter->vf_rate_link_speed) {
7541 reset_rate = true;
7542 adapter->vf_rate_link_speed = 0;
7543 dev_info(&adapter->pdev->dev,
b980ac18 7544 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7545 }
7546
7547 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7548 if (reset_rate)
7549 adapter->vf_data[i].tx_rate = 0;
7550
7551 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7552 adapter->vf_data[i].tx_rate,
7553 actual_link_speed);
17dc566c
LL		 7554 }
7555}
7556
8151d294
WM		 7557static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7558{
17dc566c
LL		 7559 struct igb_adapter *adapter = netdev_priv(netdev);
7560 struct e1000_hw *hw = &adapter->hw;
7561 int actual_link_speed;
7562
7563 if (hw->mac.type != e1000_82576)
7564 return -EOPNOTSUPP;
7565
7566 actual_link_speed = igb_link_mbps(adapter->link_speed);
7567 if ((vf >= adapter->vfs_allocated_count) ||
7568 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7569 (tx_rate < 0) || (tx_rate > actual_link_speed))
7570 return -EINVAL;
7571
7572 adapter->vf_rate_link_speed = actual_link_speed;
7573 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7574 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7575
7576 return 0;
8151d294
WM		 7577}
7578
70ea4783
LL		 7579static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7580 bool setting)
7581{
7582 struct igb_adapter *adapter = netdev_priv(netdev);
7583 struct e1000_hw *hw = &adapter->hw;
7584 u32 reg_val, reg_offset;
7585
7586 if (!adapter->vfs_allocated_count)
7587 return -EOPNOTSUPP;
7588
7589 if (vf >= adapter->vfs_allocated_count)
7590 return -EINVAL;
7591
7592 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7593 reg_val = rd32(reg_offset);
7594 if (setting)
7595 reg_val |= ((1 << vf) |
7596 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7597 else
7598 reg_val &= ~((1 << vf) |
7599 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7600 wr32(reg_offset, reg_val);
7601
7602 adapter->vf_data[vf].spoofchk_enabled = setting;
7603 return E1000_SUCCESS;
7604}
7605
8151d294
WM		 7606static int igb_ndo_get_vf_config(struct net_device *netdev,
7607 int vf, struct ifla_vf_info *ivi)
7608{
7609 struct igb_adapter *adapter = netdev_priv(netdev);
7610 if (vf >= adapter->vfs_allocated_count)
7611 return -EINVAL;
7612 ivi->vf = vf;
7613 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7614 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7615 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7616 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7617 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7618 return 0;
7619}
7620
4ae196df
AD		 7621static void igb_vmm_control(struct igb_adapter *adapter)
7622{
7623 struct e1000_hw *hw = &adapter->hw;
10d8e907 7624 u32 reg;
4ae196df 7625
52a1dd4d
AD		 7626 switch (hw->mac.type) {
7627 case e1000_82575:
f96a8a0b
CW		 7628 case e1000_i210:
7629 case e1000_i211:
ceb5f13b 7630 case e1000_i354:
52a1dd4d
AD		 7631 default:
7632 /* replication is not supported for 82575 */
4ae196df 7633 return;
52a1dd4d
AD		 7634 case e1000_82576:
7635 /* notify HW that the MAC is adding vlan tags */
7636 reg = rd32(E1000_DTXCTL);
7637 reg |= E1000_DTXCTL_VLAN_ADDED;
7638 wr32(E1000_DTXCTL, reg);
7639 case e1000_82580:
7640 /* enable replication vlan tag stripping */
7641 reg = rd32(E1000_RPLOLR);
7642 reg |= E1000_RPLOLR_STRVLAN;
7643 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7644 case e1000_i350:
7645 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7646 break;
7647 }
10d8e907 7648
d4960307
AD		 7649 if (adapter->vfs_allocated_count) {
7650 igb_vmdq_set_loopback_pf(hw, true);
7651 igb_vmdq_set_replication_pf(hw, true);
13800469 7652 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7653 adapter->vfs_allocated_count);
d4960307
AD		 7654 } else {
7655 igb_vmdq_set_loopback_pf(hw, false);
7656 igb_vmdq_set_replication_pf(hw, false);
7657 }
4ae196df
AD		 7658}
7659
b6e0c419
CW		 7660static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7661{
7662 struct e1000_hw *hw = &adapter->hw;
7663 u32 dmac_thr;
7664 u16 hwm;
7665
7666 if (hw->mac.type > e1000_82580) {
7667 if (adapter->flags & IGB_FLAG_DMAC) {
7668 u32 reg;
7669
7670 /* force threshold to 0. */
7671 wr32(E1000_DMCTXTH, 0);
7672
b980ac18 7673 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7674 * than the Rx threshold. Set hwm to PBA - max frame
7675 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7676 */
e8c626e9
MV		 7677 hwm = 64 * pba - adapter->max_frame_size / 16;
7678 if (hwm < 64 * (pba - 6))
7679 hwm = 64 * (pba - 6);
7680 reg = rd32(E1000_FCRTC);
7681 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7682 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7683 & E1000_FCRTC_RTH_COAL_MASK);
7684 wr32(E1000_FCRTC, reg);
7685
b980ac18 7686 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7687 * frame size, capping it at PBA - 10KB.
7688 */
7689 dmac_thr = pba - adapter->max_frame_size / 512;
7690 if (dmac_thr < pba - 10)
7691 dmac_thr = pba - 10;
b6e0c419
CW		 7692 reg = rd32(E1000_DMACR);
7693 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7694 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7695 & E1000_DMACR_DMACTHR_MASK);
7696
7697 /* transition to L0x or L1 if available..*/
7698 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7699
7700 /* watchdog timer= +-1000 usec in 32usec intervals */
7701 reg |= (1000 >> 5);
0c02dd98
MV		 7702
7703 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7704 if (hw->mac.type != e1000_i354)
7705 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7706
b6e0c419
CW		 7707 wr32(E1000_DMACR, reg);
7708
b980ac18 7709 /* no lower threshold to disable
b6e0c419
CW		 7710 * coalescing(smart fifb)-UTRESH=0
7711 */
7712 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7713
7714 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7715
7716 wr32(E1000_DMCTLX, reg);
7717
b980ac18 7718 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7719 * DMA coal
7720 */
7721 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7722 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7723
b980ac18 7724 /* make low power state decision controlled
b6e0c419
CW		 7725 * by DMA coal
7726 */
7727 reg = rd32(E1000_PCIEMISC);
7728 reg &= ~E1000_PCIEMISC_LX_DECISION;
7729 wr32(E1000_PCIEMISC, reg);
7730 } /* endif adapter->dmac is not disabled */
7731 } else if (hw->mac.type == e1000_82580) {
7732 u32 reg = rd32(E1000_PCIEMISC);
7733 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7734 wr32(E1000_DMACR, 0);
7735 }
7736}
7737
b980ac18
JK		 7738/**
7739 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7740 * @hw: pointer to hardware structure
7741 * @byte_offset: byte offset to read
7742 * @dev_addr: device address
7743 * @data: value read
7744 *
7745 * Performs byte read operation over I2C interface at
7746 * a specified device address.
b980ac18 7747 **/
441fc6fd 7748s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7749 u8 dev_addr, u8 *data)
441fc6fd
CW		 7750{
7751 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7752 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7753 s32 status;
7754 u16 swfw_mask = 0;
7755
7756 if (!this_client)
7757 return E1000_ERR_I2C;
7758
7759 swfw_mask = E1000_SWFW_PHY0_SM;
7760
7761 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7762 != E1000_SUCCESS)
7763 return E1000_ERR_SWFW_SYNC;
7764
7765 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7766 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7767
7768 if (status < 0)
7769 return E1000_ERR_I2C;
7770 else {
7771 *data = status;
7772 return E1000_SUCCESS;
7773 }
7774}
7775
b980ac18
JK		 7776/**
7777 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7778 * @hw: pointer to hardware structure
7779 * @byte_offset: byte offset to write
7780 * @dev_addr: device address
7781 * @data: value to write
7782 *
7783 * Performs byte write operation over I2C interface at
7784 * a specified device address.
b980ac18 7785 **/
441fc6fd 7786s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7787 u8 dev_addr, u8 data)
441fc6fd
CW		 7788{
7789 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7790 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7791 s32 status;
7792 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7793
7794 if (!this_client)
7795 return E1000_ERR_I2C;
7796
7797 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7798 return E1000_ERR_SWFW_SYNC;
7799 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7800 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7801
7802 if (status)
7803 return E1000_ERR_I2C;
7804 else
7805 return E1000_SUCCESS;
7806
7807}
9d5c8243 7808/* igb_main.c */
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