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Merge tag 'for-linus-20190118' of git://git.kernel.dk/linux-block
[mirror_ubuntu-disco-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
c2f6f3ee 16#include <linux/clk.h>
1da177e4
LT		 17#include <linux/delay.h>
18#include <linux/ethtool.h>
f1e911d5 19#include <linux/phy.h>
1da177e4
LT		 20#include <linux/if_vlan.h>
21#include <linux/crc32.h>
22#include <linux/in.h>
098b01ad 23#include <linux/io.h>
1da177e4
LT		 24#include <linux/ip.h>
25#include <linux/tcp.h>
a6b7a407 26#include <linux/interrupt.h>
1da177e4 27#include <linux/dma-mapping.h>
e1759441 28#include <linux/pm_runtime.h>
bca03d5f 29#include <linux/firmware.h>
70c71606 30#include <linux/prefetch.h>
e974604b 31#include <linux/ipv6.h>
32#include <net/ip6_checksum.h>
1da177e4 33
1da177e4 34#define MODULENAME "r8169"
1da177e4 35
bca03d5f 36#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
37#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 38#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
39#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 40#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 41#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
42#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 43#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 44#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 45#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 46#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 47#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 48#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 49#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 50#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 51#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
52#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
53#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
54#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 55
b57b7e5a 56#define R8169_MSG_DEFAULT \
f0e837d9 57 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 58
1da177e4
LT		 59/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 61static const int multicast_filter_limit = 32;
1da177e4 62
aee77e4a 63#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 64#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
65
66#define R8169_REGS_SIZE 256
1d0254dd 67#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 68#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 69#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 70#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
71#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
72
1da177e4 73/* write/read MMIO register */
1ef7286e
AS		 74#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
75#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
76#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
77#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
78#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
79#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 80
81enum mac_version {
85bffe6c
FR		 82 RTL_GIGA_MAC_VER_01 = 0,
83 RTL_GIGA_MAC_VER_02,
84 RTL_GIGA_MAC_VER_03,
85 RTL_GIGA_MAC_VER_04,
86 RTL_GIGA_MAC_VER_05,
87 RTL_GIGA_MAC_VER_06,
88 RTL_GIGA_MAC_VER_07,
89 RTL_GIGA_MAC_VER_08,
90 RTL_GIGA_MAC_VER_09,
91 RTL_GIGA_MAC_VER_10,
92 RTL_GIGA_MAC_VER_11,
93 RTL_GIGA_MAC_VER_12,
94 RTL_GIGA_MAC_VER_13,
95 RTL_GIGA_MAC_VER_14,
96 RTL_GIGA_MAC_VER_15,
97 RTL_GIGA_MAC_VER_16,
98 RTL_GIGA_MAC_VER_17,
99 RTL_GIGA_MAC_VER_18,
100 RTL_GIGA_MAC_VER_19,
101 RTL_GIGA_MAC_VER_20,
102 RTL_GIGA_MAC_VER_21,
103 RTL_GIGA_MAC_VER_22,
104 RTL_GIGA_MAC_VER_23,
105 RTL_GIGA_MAC_VER_24,
106 RTL_GIGA_MAC_VER_25,
107 RTL_GIGA_MAC_VER_26,
108 RTL_GIGA_MAC_VER_27,
109 RTL_GIGA_MAC_VER_28,
110 RTL_GIGA_MAC_VER_29,
111 RTL_GIGA_MAC_VER_30,
112 RTL_GIGA_MAC_VER_31,
113 RTL_GIGA_MAC_VER_32,
114 RTL_GIGA_MAC_VER_33,
70090424 115 RTL_GIGA_MAC_VER_34,
c2218925
HW		 116 RTL_GIGA_MAC_VER_35,
117 RTL_GIGA_MAC_VER_36,
7e18dca1 118 RTL_GIGA_MAC_VER_37,
b3d7b2f2 119 RTL_GIGA_MAC_VER_38,
5598bfe5 120 RTL_GIGA_MAC_VER_39,
c558386b
HW		 121 RTL_GIGA_MAC_VER_40,
122 RTL_GIGA_MAC_VER_41,
57538c4a 123 RTL_GIGA_MAC_VER_42,
58152cd4 124 RTL_GIGA_MAC_VER_43,
45dd95c4 125 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 126 RTL_GIGA_MAC_VER_45,
127 RTL_GIGA_MAC_VER_46,
128 RTL_GIGA_MAC_VER_47,
129 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 130 RTL_GIGA_MAC_VER_49,
131 RTL_GIGA_MAC_VER_50,
132 RTL_GIGA_MAC_VER_51,
85bffe6c 133 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 134};
135
d58d46b5
FR		 136#define JUMBO_1K ETH_DATA_LEN
137#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
138#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
139#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
140#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
141
3c6bee1d 142static const struct {
1da177e4 143 const char *name;
953a12cc 144 const char *fw_name;
85bffe6c
FR		 145} rtl_chip_infos[] = {
146 /* PCI devices. */
abe8b2f7
HK		 147 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
148 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
149 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
150 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
151 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
152 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
85bffe6c 153 /* PCI-E devices. */
abe8b2f7
HK		 154 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
155 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
156 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
157 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
158 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
159 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
160 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
161 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
162 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
163 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
164 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
165 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
166 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
167 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
168 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
169 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
170 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
171 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
172 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
173 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
174 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
175 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
176 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
177 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
178 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
180 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
181 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
182 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
183 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
184 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
185 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
186 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
187 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
188 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
189 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
190 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
191 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
192 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
193 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
194 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
195 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
196 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
197 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
198 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
953a12cc
FR		 199};
200
bcf0bf90
FR		 201enum cfg_version {
202 RTL_CFG_0 = 0x00,
203 RTL_CFG_1,
204 RTL_CFG_2
205};
206
9baa3c34 207static const struct pci_device_id rtl8169_pci_tbl[] = {
36352991
KHF		 208 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
209 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
6f0d3088
HK		 210 { PCI_VDEVICE(REALTEK, 0x8129), RTL_CFG_0 },
211 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_2 },
212 { PCI_VDEVICE(REALTEK, 0x8161), RTL_CFG_1 },
213 { PCI_VDEVICE(REALTEK, 0x8167), RTL_CFG_0 },
214 { PCI_VDEVICE(REALTEK, 0x8168), RTL_CFG_1 },
215 { PCI_VDEVICE(NCUBE, 0x8168), RTL_CFG_1 },
216 { PCI_VDEVICE(REALTEK, 0x8169), RTL_CFG_0 },
217 { PCI_VENDOR_ID_DLINK, 0x4300,
218 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
219 { PCI_VDEVICE(DLINK, 0x4300), RTL_CFG_0 },
220 { PCI_VDEVICE(DLINK, 0x4302), RTL_CFG_0 },
221 { PCI_VDEVICE(AT, 0xc107), RTL_CFG_0 },
222 { PCI_VDEVICE(USR, 0x0116), RTL_CFG_0 },
bcf0bf90
FR		 223 { PCI_VENDOR_ID_LINKSYS, 0x1032,
224 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 225 { 0x0001, 0x8168,
226 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
6f0d3088 227 {}
1da177e4
LT		 228};
229
230MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
231
27896c83 232static int use_dac = -1;
b57b7e5a
SH		 233static struct {
234 u32 msg_enable;
235} debug = { -1 };
1da177e4 236
07d3f51f
FR		 237enum rtl_registers {
238 MAC0 = 0, /* Ethernet hardware address. */
773d2021 239 MAC4 = 4,
07d3f51f
FR		 240 MAR0 = 8, /* Multicast filter. */
241 CounterAddrLow = 0x10,
242 CounterAddrHigh = 0x14,
243 TxDescStartAddrLow = 0x20,
244 TxDescStartAddrHigh = 0x24,
245 TxHDescStartAddrLow = 0x28,
246 TxHDescStartAddrHigh = 0x2c,
247 FLASH = 0x30,
248 ERSR = 0x36,
249 ChipCmd = 0x37,
250 TxPoll = 0x38,
251 IntrMask = 0x3c,
252 IntrStatus = 0x3e,
4f6b00e5 253
07d3f51f 254 TxConfig = 0x40,
4f6b00e5
HW		 255#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
256#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 257
4f6b00e5
HW		 258 RxConfig = 0x44,
259#define RX128_INT_EN (1 << 15) /* 8111c and later */
260#define RX_MULTI_EN (1 << 14) /* 8111c only */
261#define RXCFG_FIFO_SHIFT 13
262 /* No threshold before first PCI xfer */
263#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 264#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 265#define RXCFG_DMA_SHIFT 8
266 /* Unlimited maximum PCI burst. */
267#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 268
07d3f51f
FR		 269 RxMissed = 0x4c,
270 Cfg9346 = 0x50,
271 Config0 = 0x51,
272 Config1 = 0x52,
273 Config2 = 0x53,
d387b427
FR		 274#define PME_SIGNAL (1 << 5) /* 8168c and later */
275
07d3f51f
FR		 276 Config3 = 0x54,
277 Config4 = 0x55,
278 Config5 = 0x56,
279 MultiIntr = 0x5c,
280 PHYAR = 0x60,
07d3f51f
FR		 281 PHYstatus = 0x6c,
282 RxMaxSize = 0xda,
283 CPlusCmd = 0xe0,
284 IntrMitigate = 0xe2,
50970831
FR		 285
286#define RTL_COALESCE_MASK 0x0f
287#define RTL_COALESCE_SHIFT 4
288#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
289#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
290
07d3f51f
FR		 291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
f0298f81 293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
294
295#define NoEarlyTx 0x3f /* Max value : no early transmit. */
296
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
298
299#define TxPacketMax (8064 >> 7)
3090bd9a 300#define EarlySize 0x27
f0298f81 301
07d3f51f
FR		 302 FuncEvent = 0xf0,
303 FuncEventMask = 0xf4,
304 FuncPresetState = 0xf8,
935e2218
CHL		 305 IBCR0 = 0xf8,
306 IBCR2 = 0xf9,
307 IBIMR0 = 0xfa,
308 IBISR0 = 0xfb,
07d3f51f 309 FuncForceEvent = 0xfc,
1da177e4
LT		 310};
311
f162a5d1
FR		 312enum rtl8168_8101_registers {
313 CSIDR = 0x64,
314 CSIAR = 0x68,
315#define CSIAR_FLAG 0x80000000
316#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 317#define CSIAR_BYTE_ENABLE 0x0000f000
318#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 319 PMCH = 0x6f,
f162a5d1
FR		 320 EPHYAR = 0x80,
321#define EPHYAR_FLAG 0x80000000
322#define EPHYAR_WRITE_CMD 0x80000000
323#define EPHYAR_REG_MASK 0x1f
324#define EPHYAR_REG_SHIFT 16
325#define EPHYAR_DATA_MASK 0xffff
5a5e4443 326 DLLPR = 0xd0,
4f6b00e5 327#define PFM_EN (1 << 6)
6e1d0b89 328#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 329 DBG_REG = 0xd1,
330#define FIX_NAK_1 (1 << 4)
331#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 332 TWSI = 0xd2,
333 MCU = 0xd3,
4f6b00e5 334#define NOW_IS_OOB (1 << 7)
c558386b
HW		 335#define TX_EMPTY (1 << 5)
336#define RX_EMPTY (1 << 4)
337#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 338#define EN_NDP (1 << 3)
339#define EN_OOB_RESET (1 << 2)
c558386b 340#define LINK_LIST_RDY (1 << 1)
daf9df6d 341 EFUSEAR = 0xdc,
342#define EFUSEAR_FLAG 0x80000000
343#define EFUSEAR_WRITE_CMD 0x80000000
344#define EFUSEAR_READ_CMD 0x00000000
345#define EFUSEAR_REG_MASK 0x03ff
346#define EFUSEAR_REG_SHIFT 8
347#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 348 MISC_1 = 0xf2,
349#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 350};
351
c0e45c1c 352enum rtl8168_registers {
4f6b00e5
HW		 353 LED_FREQ = 0x1a,
354 EEE_LED = 0x1b,
b646d900 355 ERIDR = 0x70,
356 ERIAR = 0x74,
357#define ERIAR_FLAG 0x80000000
358#define ERIAR_WRITE_CMD 0x80000000
359#define ERIAR_READ_CMD 0x00000000
360#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 361#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 362#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
363#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
364#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 365#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 366#define ERIAR_MASK_SHIFT 12
367#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
368#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 369#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 370#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 371#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 372 EPHY_RXER_NUM = 0x7c,
373 OCPDR = 0xb0, /* OCP GPHY access */
374#define OCPDR_WRITE_CMD 0x80000000
375#define OCPDR_READ_CMD 0x00000000
376#define OCPDR_REG_MASK 0x7f
377#define OCPDR_GPHY_REG_SHIFT 16
378#define OCPDR_DATA_MASK 0xffff
379 OCPAR = 0xb4,
380#define OCPAR_FLAG 0x80000000
381#define OCPAR_GPHY_WRITE_CMD 0x8000f060
382#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 383 GPHY_OCP = 0xb8,
01dc7fec 384 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
385 MISC = 0xf0, /* 8168e only. */
cecb5fd7 386#define TXPLA_RST (1 << 29)
5598bfe5 387#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 388#define PWM_EN (1 << 22)
c558386b 389#define RXDV_GATED_EN (1 << 19)
5598bfe5 390#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 391};
392
07d3f51f 393enum rtl_register_content {
1da177e4 394 /* InterruptStatusBits */
07d3f51f
FR		 395 SYSErr = 0x8000,
396 PCSTimeout = 0x4000,
397 SWInt = 0x0100,
398 TxDescUnavail = 0x0080,
399 RxFIFOOver = 0x0040,
400 LinkChg = 0x0020,
401 RxOverflow = 0x0010,
402 TxErr = 0x0008,
403 TxOK = 0x0004,
404 RxErr = 0x0002,
405 RxOK = 0x0001,
1da177e4
LT		 406
407 /* RxStatusDesc */
e03f33af 408 RxBOVF = (1 << 24),
9dccf611
FR		 409 RxFOVF = (1 << 23),
410 RxRWT = (1 << 22),
411 RxRES = (1 << 21),
412 RxRUNT = (1 << 20),
413 RxCRC = (1 << 19),
1da177e4
LT		 414
415 /* ChipCmdBits */
4f6b00e5 416 StopReq = 0x80,
07d3f51f
FR		 417 CmdReset = 0x10,
418 CmdRxEnb = 0x08,
419 CmdTxEnb = 0x04,
420 RxBufEmpty = 0x01,
1da177e4 421
275391a4
FR		 422 /* TXPoll register p.5 */
423 HPQ = 0x80, /* Poll cmd on the high prio queue */
424 NPQ = 0x40, /* Poll cmd on the low prio queue */
425 FSWInt = 0x01, /* Forced software interrupt */
426
1da177e4 427 /* Cfg9346Bits */
07d3f51f
FR		 428 Cfg9346_Lock = 0x00,
429 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 430
431 /* rx_mode_bits */
07d3f51f
FR		 432 AcceptErr = 0x20,
433 AcceptRunt = 0x10,
434 AcceptBroadcast = 0x08,
435 AcceptMulticast = 0x04,
436 AcceptMyPhys = 0x02,
437 AcceptAllPhys = 0x01,
1687b566 438#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 439
1da177e4
LT		 440 /* TxConfigBits */
441 TxInterFrameGapShift = 24,
442 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
443
5d06a99f 444 /* Config1 register p.24 */
f162a5d1
FR		 445 LEDS1 = (1 << 7),
446 LEDS0 = (1 << 6),
f162a5d1
FR		 447 Speed_down = (1 << 4),
448 MEMMAP = (1 << 3),
449 IOMAP = (1 << 2),
450 VPD = (1 << 1),
5d06a99f
FR		 451 PMEnable = (1 << 0), /* Power Management Enable */
452
6dccd16b 453 /* Config2 register p. 25 */
57538c4a 454 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 455 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 456 PCI_Clock_66MHz = 0x01,
457 PCI_Clock_33MHz = 0x00,
458
61a4dcc2
FR		 459 /* Config3 register p.25 */
460 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
461 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 462 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 463 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 464 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 465
d58d46b5
FR		 466 /* Config4 register */
467 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
468
5d06a99f 469 /* Config5 register p.27 */
61a4dcc2
FR		 470 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
471 MWF = (1 << 5), /* Accept Multicast wakeup frame */
472 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 473 Spi_en = (1 << 3),
61a4dcc2 474 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 475 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 476 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 477
1da177e4 478 /* CPlusCmd p.31 */
f162a5d1
FR		 479 EnableBist = (1 << 15), // 8168 8101
480 Mac_dbgo_oe = (1 << 14), // 8168 8101
481 Normal_mode = (1 << 13), // unused
482 Force_half_dup = (1 << 12), // 8168 8101
483 Force_rxflow_en = (1 << 11), // 8168 8101
484 Force_txflow_en = (1 << 10), // 8168 8101
485 Cxpl_dbg_sel = (1 << 9), // 8168 8101
486 ASF = (1 << 8), // 8168 8101
487 PktCntrDisable = (1 << 7), // 8168 8101
488 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 489 RxVlan = (1 << 6),
490 RxChkSum = (1 << 5),
491 PCIDAC = (1 << 4),
492 PCIMulRW = (1 << 3),
9a3c81fa 493#define INTT_MASK GENMASK(1, 0)
0e485150
FR		 494 INTT_0 = 0x0000, // 8168
495 INTT_1 = 0x0001, // 8168
496 INTT_2 = 0x0002, // 8168
497 INTT_3 = 0x0003, // 8168
1da177e4
LT		 498
499 /* rtl8169_PHYstatus */
07d3f51f
FR		 500 TBI_Enable = 0x80,
501 TxFlowCtrl = 0x40,
502 RxFlowCtrl = 0x20,
503 _1000bpsF = 0x10,
504 _100bps = 0x08,
505 _10bps = 0x04,
506 LinkStatus = 0x02,
507 FullDup = 0x01,
1da177e4 508
1da177e4 509 /* _TBICSRBit */
07d3f51f 510 TBILinkOK = 0x02000000,
d4a3a0fc 511
6e85d5ad
CV		 512 /* ResetCounterCommand */
513 CounterReset = 0x1,
514
d4a3a0fc 515 /* DumpCounterCommand */
07d3f51f 516 CounterDump = 0x8,
6e1d0b89
CHL		 517
518 /* magic enable v2 */
519 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 520};
521
2b7b4318
FR		 522enum rtl_desc_bit {
523 /* First doubleword. */
1da177e4
LT		 524 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
525 RingEnd = (1 << 30), /* End of descriptor ring */
526 FirstFrag = (1 << 29), /* First segment of a packet */
527 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 528};
529
530/* Generic case. */
531enum rtl_tx_desc_bit {
532 /* First doubleword. */
533 TD_LSO = (1 << 27), /* Large Send Offload */
534#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 535
2b7b4318
FR		 536 /* Second doubleword. */
537 TxVlanTag = (1 << 17), /* Add VLAN tag */
538};
539
540/* 8169, 8168b and 810x except 8102e. */
541enum rtl_tx_desc_bit_0 {
542 /* First doubleword. */
543#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
544 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
545 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
546 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
547};
548
549/* 8102e, 8168c and beyond. */
550enum rtl_tx_desc_bit_1 {
bdfa4ed6 551 /* First doubleword. */
552 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 553 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 554#define GTTCPHO_SHIFT 18
e974604b 555#define GTTCPHO_MAX 0x7fU
bdfa4ed6 556
2b7b4318 557 /* Second doubleword. */
e974604b 558#define TCPHO_SHIFT 18
559#define TCPHO_MAX 0x3ffU
2b7b4318 560#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 561 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
562 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 563 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
564 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
565};
1da177e4 566
2b7b4318 567enum rtl_rx_desc_bit {
1da177e4
LT		 568 /* Rx private */
569 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 570 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 571
572#define RxProtoUDP (PID1)
573#define RxProtoTCP (PID0)
574#define RxProtoIP (PID1 | PID0)
575#define RxProtoMask RxProtoIP
576
577 IPFail = (1 << 16), /* IP checksum failed */
578 UDPFail = (1 << 15), /* UDP/IP checksum failed */
579 TCPFail = (1 << 14), /* TCP/IP checksum failed */
580 RxVlanTag = (1 << 16), /* VLAN tag available */
581};
582
583#define RsvdMask 0x3fffc000
12d42c50 584#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 585
586struct TxDesc {
6cccd6e7
REB		 587 __le32 opts1;
588 __le32 opts2;
589 __le64 addr;
1da177e4
LT		 590};
591
592struct RxDesc {
6cccd6e7
REB		 593 __le32 opts1;
594 __le32 opts2;
595 __le64 addr;
1da177e4
LT		 596};
597
598struct ring_info {
599 struct sk_buff *skb;
600 u32 len;
1da177e4
LT		 601};
602
355423d0
IV		 603struct rtl8169_counters {
604 __le64 tx_packets;
605 __le64 rx_packets;
606 __le64 tx_errors;
607 __le32 rx_errors;
608 __le16 rx_missed;
609 __le16 align_errors;
610 __le32 tx_one_collision;
611 __le32 tx_multi_collision;
612 __le64 rx_unicast;
613 __le64 rx_broadcast;
614 __le32 rx_multicast;
615 __le16 tx_aborted;
616 __le16 tx_underun;
617};
618
6e85d5ad
CV		 619struct rtl8169_tc_offsets {
620 bool inited;
621 __le64 tx_errors;
622 __le32 tx_multi_collision;
6e85d5ad
CV		 623 __le16 tx_aborted;
624};
625
da78dbff 626enum rtl_flag {
6ad56901 627 RTL_FLAG_TASK_ENABLED = 0,
da78dbff 628 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 629 RTL_FLAG_MAX
630};
631
8027aa24
JW		 632struct rtl8169_stats {
633 u64 packets;
634 u64 bytes;
635 struct u64_stats_sync syncp;
636};
637
1da177e4
LT		 638struct rtl8169_private {
639 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 640 struct pci_dev *pci_dev;
c4028958 641 struct net_device *dev;
bea3348e 642 struct napi_struct napi;
b57b7e5a 643 u32 msg_enable;
2b7b4318 644 u16 mac_version;
1da177e4
LT		 645 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
646 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 647 u32 dirty_tx;
8027aa24
JW		 648 struct rtl8169_stats rx_stats;
649 struct rtl8169_stats tx_stats;
1da177e4
LT		 650 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
651 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
652 dma_addr_t TxPhyAddr;
653 dma_addr_t RxPhyAddr;
6f0333b8 654 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 655 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 656 u16 cp_cmd;
da78dbff 657
559c3c04 658 u16 irq_mask;
50970831 659 const struct rtl_coalesce_info *coalesce_info;
c2f6f3ee 660 struct clk *clk;
c0e45c1c 661
662 struct mdio_ops {
24192210
FR		 663 void (*write)(struct rtl8169_private *, int, int);
664 int (*read)(struct rtl8169_private *, int);
c0e45c1c 665 } mdio_ops;
666
d58d46b5
FR		 667 struct jumbo_ops {
668 void (*enable)(struct rtl8169_private *);
669 void (*disable)(struct rtl8169_private *);
670 } jumbo_ops;
671
61cb532d 672 void (*hw_start)(struct rtl8169_private *tp);
5888d3fc 673 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 674
675 struct {
da78dbff
FR		 676 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
677 struct mutex mutex;
4422bcd4
FR		 678 struct work_struct work;
679 } wk;
680
f7ffa9ae 681 unsigned supports_gmii:1;
f1e911d5 682 struct mii_bus *mii_bus;
42020320
CV		 683 dma_addr_t counters_phys_addr;
684 struct rtl8169_counters *counters;
6e85d5ad 685 struct rtl8169_tc_offsets tc_offset;
e1759441 686 u32 saved_wolopts;
f1e02ed1 687
b6ffd97f
FR		 688 struct rtl_fw {
689 const struct firmware *fw;
1c361efb
FR		 690
691#define RTL_VER_SIZE 32
692
693 char version[RTL_VER_SIZE];
694
695 struct rtl_fw_phy_action {
696 __le32 *code;
697 size_t size;
698 } phy_action;
b6ffd97f 699 } *rtl_fw;
497888cf 700#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 701
702 u32 ocp_base;
1da177e4
LT		 703};
704
979b6c13 705MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 706MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 707module_param(use_dac, int, 0);
4300e8c7 708MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 709module_param_named(debug, debug.msg_enable, int, 0);
710MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
11287b69 711MODULE_SOFTDEP("pre: realtek");
1da177e4 712MODULE_LICENSE("GPL");
bca03d5f 713MODULE_FIRMWARE(FIRMWARE_8168D_1);
714MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 715MODULE_FIRMWARE(FIRMWARE_8168E_1);
716MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 717MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 718MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 719MODULE_FIRMWARE(FIRMWARE_8168F_1);
720MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 721MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 722MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 723MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 724MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 725MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 726MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 727MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 728MODULE_FIRMWARE(FIRMWARE_8168H_1);
729MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 730MODULE_FIRMWARE(FIRMWARE_8107E_1);
731MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 732
1e1205b7
HK		 733static inline struct device *tp_to_dev(struct rtl8169_private *tp)
734{
735 return &tp->pci_dev->dev;
736}
737
da78dbff
FR		 738static void rtl_lock_work(struct rtl8169_private *tp)
739{
740 mutex_lock(&tp->wk.mutex);
741}
742
743static void rtl_unlock_work(struct rtl8169_private *tp)
744{
745 mutex_unlock(&tp->wk.mutex);
746}
747
cb73200c 748static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 749{
cb73200c 750 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 751 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 752}
753
ffc46952
FR		 754struct rtl_cond {
755 bool (*check)(struct rtl8169_private *);
756 const char *msg;
757};
758
759static void rtl_udelay(unsigned int d)
760{
761 udelay(d);
762}
763
764static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
765 void (*delay)(unsigned int), unsigned int d, int n,
766 bool high)
767{
768 int i;
769
770 for (i = 0; i < n; i++) {
771 delay(d);
772 if (c->check(tp) == high)
773 return true;
774 }
82e316ef
FR		 775 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
776 c->msg, !high, n, d);
ffc46952
FR		 777 return false;
778}
779
780static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
781 const struct rtl_cond *c,
782 unsigned int d, int n)
783{
784 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
785}
786
787static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
788 const struct rtl_cond *c,
789 unsigned int d, int n)
790{
791 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
792}
793
794static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
795 const struct rtl_cond *c,
796 unsigned int d, int n)
797{
798 return rtl_loop_wait(tp, c, msleep, d, n, true);
799}
800
801static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
802 const struct rtl_cond *c,
803 unsigned int d, int n)
804{
805 return rtl_loop_wait(tp, c, msleep, d, n, false);
806}
807
808#define DECLARE_RTL_COND(name) \
809static bool name ## _check(struct rtl8169_private *); \
810 \
811static const struct rtl_cond name = { \
812 .check = name ## _check, \
813 .msg = #name \
814}; \
815 \
816static bool name ## _check(struct rtl8169_private *tp)
817
c558386b
HW		 818static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
819{
820 if (reg & 0xffff0001) {
821 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
822 return true;
823 }
824 return false;
825}
826
827DECLARE_RTL_COND(rtl_ocp_gphy_cond)
828{
1ef7286e 829 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 830}
831
832static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
833{
c558386b
HW		 834 if (rtl_ocp_reg_failure(tp, reg))
835 return;
836
1ef7286e 837 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 838
839 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
840}
841
842static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
843{
c558386b
HW		 844 if (rtl_ocp_reg_failure(tp, reg))
845 return 0;
846
1ef7286e 847 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 848
849 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 850 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 851}
852
c558386b
HW		 853static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
854{
c558386b
HW		 855 if (rtl_ocp_reg_failure(tp, reg))
856 return;
857
1ef7286e 858 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 859}
860
861static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
862{
c558386b
HW		 863 if (rtl_ocp_reg_failure(tp, reg))
864 return 0;
865
1ef7286e 866 RTL_W32(tp, OCPDR, reg << 15);
c558386b 867
1ef7286e 868 return RTL_R32(tp, OCPDR);
c558386b
HW		 869}
870
871#define OCP_STD_PHY_BASE 0xa400
872
873static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
874{
875 if (reg == 0x1f) {
876 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
877 return;
878 }
879
880 if (tp->ocp_base != OCP_STD_PHY_BASE)
881 reg -= 0x10;
882
883 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
884}
885
886static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
887{
888 if (tp->ocp_base != OCP_STD_PHY_BASE)
889 reg -= 0x10;
890
891 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
892}
893
eee3786f 894static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
895{
896 if (reg == 0x1f) {
897 tp->ocp_base = value << 4;
898 return;
899 }
900
901 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
902}
903
904static int mac_mcu_read(struct rtl8169_private *tp, int reg)
905{
906 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
907}
908
ffc46952
FR		 909DECLARE_RTL_COND(rtl_phyar_cond)
910{
1ef7286e 911 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 912}
913
24192210 914static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 915{
1ef7286e 916 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 917
ffc46952 918 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 919 /*
81a95f04
TT		 920 * According to hardware specs a 20us delay is required after write
921 * complete indication, but before sending next command.
024a07ba 922 */
81a95f04 923 udelay(20);
1da177e4
LT		 924}
925
24192210 926static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 927{
ffc46952 928 int value;
1da177e4 929
1ef7286e 930 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 931
ffc46952 932 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 933 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 934
81a95f04
TT		 935 /*
936 * According to hardware specs a 20us delay is required after read
937 * complete indication, but before sending next command.
938 */
939 udelay(20);
940
1da177e4
LT		 941 return value;
942}
943
935e2218
CHL		 944DECLARE_RTL_COND(rtl_ocpar_cond)
945{
1ef7286e 946 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 947}
948
24192210 949static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 950{
1ef7286e
AS		 951 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
952 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
953 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 954
ffc46952 955 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 956}
957
24192210 958static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 959{
24192210
FR		 960 r8168dp_1_mdio_access(tp, reg,
961 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 962}
963
24192210 964static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 965{
24192210 966 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 967
968 mdelay(1);
1ef7286e
AS		 969 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
970 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 971
ffc46952 972 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 973 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 974}
975
e6de30d6 976#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
977
1ef7286e 978static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 979{
1ef7286e 980 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 981}
982
1ef7286e 983static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 984{
1ef7286e 985 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 986}
987
24192210 988static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 989{
1ef7286e 990 r8168dp_2_mdio_start(tp);
e6de30d6 991
24192210 992 r8169_mdio_write(tp, reg, value);
e6de30d6 993
1ef7286e 994 r8168dp_2_mdio_stop(tp);
e6de30d6 995}
996
24192210 997static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 998{
999 int value;
1000
1ef7286e 1001 r8168dp_2_mdio_start(tp);
e6de30d6 1002
24192210 1003 value = r8169_mdio_read(tp, reg);
e6de30d6 1004
1ef7286e 1005 r8168dp_2_mdio_stop(tp);
e6de30d6 1006
1007 return value;
1008}
1009
4da19633 1010static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1011{
24192210 1012 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1013}
1014
4da19633 1015static int rtl_readphy(struct rtl8169_private *tp, int location)
1016{
24192210 1017 return tp->mdio_ops.read(tp, location);
4da19633 1018}
1019
1020static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1021{
1022 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1023}
1024
76564428 1025static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1026{
1027 int val;
1028
4da19633 1029 val = rtl_readphy(tp, reg_addr);
76564428 1030 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1031}
1032
ffc46952
FR		 1033DECLARE_RTL_COND(rtl_ephyar_cond)
1034{
1ef7286e 1035 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1036}
1037
fdf6fc06 1038static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1039{
1ef7286e 1040 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1041 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1042
ffc46952
FR		 1043 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1044
1045 udelay(10);
dacf8154
FR		 1046}
1047
fdf6fc06 1048static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1049{
1ef7286e 1050 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1051
ffc46952 1052 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1053 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1054}
1055
935e2218
CHL		 1056DECLARE_RTL_COND(rtl_eriar_cond)
1057{
1ef7286e 1058 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1059}
1060
fdf6fc06
FR		 1061static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1062 u32 val, int type)
133ac40a 1063{
133ac40a 1064 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1065 RTL_W32(tp, ERIDR, val);
1066 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1067
ffc46952 1068 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1069}
1070
fdf6fc06 1071static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1072{
1ef7286e 1073 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1074
ffc46952 1075 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1076 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1077}
1078
706123d0 1079static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1080 u32 m, int type)
133ac40a
HW		 1081{
1082 u32 val;
1083
fdf6fc06
FR		 1084 val = rtl_eri_read(tp, addr, type);
1085 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1086}
1087
935e2218
CHL		 1088static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1089{
1ef7286e 1090 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1091 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1092 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1093}
1094
1095static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1096{
1097 return rtl_eri_read(tp, reg, ERIAR_OOB);
1098}
1099
935e2218
CHL		 1100static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1101 u32 data)
1102{
1ef7286e
AS		 1103 RTL_W32(tp, OCPDR, data);
1104 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1105 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1106}
1107
1108static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1109 u32 data)
1110{
1111 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1112 data, ERIAR_OOB);
1113}
1114
3c72bf71 1115static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
2a9b4d96
CHL		 1116{
1117 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1118
3c72bf71 1119 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
2a9b4d96
CHL		 1120}
1121
1122#define OOB_CMD_RESET 0x00
1123#define OOB_CMD_DRIVER_START 0x05
1124#define OOB_CMD_DRIVER_STOP 0x06
1125
1126static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1127{
1128 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1129}
1130
3c72bf71 1131DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
2a9b4d96
CHL		 1132{
1133 u16 reg;
1134
1135 reg = rtl8168_get_ocp_reg(tp);
1136
3c72bf71 1137 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
2a9b4d96
CHL		 1138}
1139
935e2218 1140DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1141{
3c72bf71 1142 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
935e2218
CHL		 1143}
1144
1145DECLARE_RTL_COND(rtl_ocp_tx_cond)
1146{
1ef7286e 1147 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1148}
2a9b4d96 1149
003609da
CHL		 1150static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1151{
1ef7286e 1152 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1153 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1154 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1155 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1156}
1157
935e2218
CHL		 1158static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1159{
3c72bf71
HK		 1160 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1161 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1162}
1163
935e2218 1164static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1165{
3c72bf71
HK		 1166 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1167 r8168ep_ocp_write(tp, 0x01, 0x30,
1168 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1169 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1170}
1171
1172static void rtl8168_driver_start(struct rtl8169_private *tp)
1173{
1174 switch (tp->mac_version) {
1175 case RTL_GIGA_MAC_VER_27:
1176 case RTL_GIGA_MAC_VER_28:
1177 case RTL_GIGA_MAC_VER_31:
1178 rtl8168dp_driver_start(tp);
1179 break;
1180 case RTL_GIGA_MAC_VER_49:
1181 case RTL_GIGA_MAC_VER_50:
1182 case RTL_GIGA_MAC_VER_51:
1183 rtl8168ep_driver_start(tp);
1184 break;
1185 default:
1186 BUG();
1187 break;
1188 }
1189}
2a9b4d96 1190
935e2218
CHL		 1191static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1192{
3c72bf71
HK		 1193 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1194 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1195}
1196
935e2218
CHL		 1197static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1198{
003609da 1199 rtl8168ep_stop_cmac(tp);
3c72bf71
HK		 1200 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1201 r8168ep_ocp_write(tp, 0x01, 0x30,
1202 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1203 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1204}
1205
1206static void rtl8168_driver_stop(struct rtl8169_private *tp)
1207{
1208 switch (tp->mac_version) {
1209 case RTL_GIGA_MAC_VER_27:
1210 case RTL_GIGA_MAC_VER_28:
1211 case RTL_GIGA_MAC_VER_31:
1212 rtl8168dp_driver_stop(tp);
1213 break;
1214 case RTL_GIGA_MAC_VER_49:
1215 case RTL_GIGA_MAC_VER_50:
1216 case RTL_GIGA_MAC_VER_51:
1217 rtl8168ep_driver_stop(tp);
1218 break;
1219 default:
1220 BUG();
1221 break;
1222 }
1223}
1224
9dbe7896 1225static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1226{
1227 u16 reg = rtl8168_get_ocp_reg(tp);
1228
3c72bf71 1229 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1230}
1231
9dbe7896 1232static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1233{
3c72bf71 1234 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1235}
1236
9dbe7896 1237static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1238{
1239 switch (tp->mac_version) {
1240 case RTL_GIGA_MAC_VER_27:
1241 case RTL_GIGA_MAC_VER_28:
1242 case RTL_GIGA_MAC_VER_31:
1243 return r8168dp_check_dash(tp);
1244 case RTL_GIGA_MAC_VER_49:
1245 case RTL_GIGA_MAC_VER_50:
1246 case RTL_GIGA_MAC_VER_51:
1247 return r8168ep_check_dash(tp);
1248 default:
9dbe7896 1249 return false;
935e2218
CHL		 1250 }
1251}
1252
c28aa385 1253struct exgmac_reg {
1254 u16 addr;
1255 u16 mask;
1256 u32 val;
1257};
1258
fdf6fc06 1259static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1260 const struct exgmac_reg *r, int len)
1261{
1262 while (len-- > 0) {
fdf6fc06 1263 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1264 r++;
1265 }
1266}
1267
ffc46952
FR		 1268DECLARE_RTL_COND(rtl_efusear_cond)
1269{
1ef7286e 1270 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1271}
1272
fdf6fc06 1273static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1274{
1ef7286e 1275 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1276
ffc46952 1277 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1278 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1279}
1280
9085cdfa
FR		 1281static u16 rtl_get_events(struct rtl8169_private *tp)
1282{
1ef7286e 1283 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1284}
1285
1286static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1287{
1ef7286e 1288 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1289}
1290
1291static void rtl_irq_disable(struct rtl8169_private *tp)
1292{
1ef7286e 1293 RTL_W16(tp, IntrMask, 0);
3e990ff5
FR		 1294}
1295
da78dbff
FR		 1296#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1297#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1298#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1299
fe716f8a 1300static void rtl_irq_enable(struct rtl8169_private *tp)
da78dbff 1301{
559c3c04 1302 RTL_W16(tp, IntrMask, tp->irq_mask);
da78dbff
FR		 1303}
1304
811fd301 1305static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1306{
9085cdfa 1307 rtl_irq_disable(tp);
de20e12f
HK		 1308 rtl_ack_events(tp, 0xffff);
1309 /* PCI commit */
1ef7286e 1310 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1311}
1312
70090424
HW		 1313static void rtl_link_chg_patch(struct rtl8169_private *tp)
1314{
70090424 1315 struct net_device *dev = tp->dev;
29a12b49 1316 struct phy_device *phydev = dev->phydev;
70090424
HW		 1317
1318 if (!netif_running(dev))
1319 return;
1320
b3d7b2f2
HW		 1321 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1322 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1323 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1324 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1325 ERIAR_EXGMAC);
1326 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1327 ERIAR_EXGMAC);
29a12b49 1328 } else if (phydev->speed == SPEED_100) {
fdf6fc06
FR		 1329 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1330 ERIAR_EXGMAC);
1331 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1332 ERIAR_EXGMAC);
70090424 1333 } else {
fdf6fc06
FR		 1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1335 ERIAR_EXGMAC);
1336 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1337 ERIAR_EXGMAC);
70090424
HW		 1338 }
1339 /* Reset packet filter */
706123d0 1340 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1341 ERIAR_EXGMAC);
706123d0 1342 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1343 ERIAR_EXGMAC);
c2218925
HW		 1344 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1345 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1346 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1348 ERIAR_EXGMAC);
1349 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1350 ERIAR_EXGMAC);
c2218925 1351 } else {
fdf6fc06
FR		 1352 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1353 ERIAR_EXGMAC);
1354 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1355 ERIAR_EXGMAC);
c2218925 1356 }
7e18dca1 1357 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1358 if (phydev->speed == SPEED_10) {
fdf6fc06
FR		 1359 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1360 ERIAR_EXGMAC);
1361 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1362 ERIAR_EXGMAC);
7e18dca1 1363 } else {
fdf6fc06
FR		 1364 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1365 ERIAR_EXGMAC);
7e18dca1 1366 }
70090424
HW		 1367 }
1368}
1369
e1759441
RW		 1370#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1371
1372static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1373{
61a4dcc2 1374 u8 options;
e1759441 1375 u32 wolopts = 0;
61a4dcc2 1376
1ef7286e 1377 options = RTL_R8(tp, Config1);
61a4dcc2 1378 if (!(options & PMEnable))
e1759441 1379 return 0;
61a4dcc2 1380
1ef7286e 1381 options = RTL_R8(tp, Config3);
61a4dcc2 1382 if (options & LinkUp)
e1759441 1383 wolopts |= WAKE_PHY;
6e1d0b89 1384 switch (tp->mac_version) {
2a71883c
HK		 1385 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1386 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1387 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1388 wolopts |= WAKE_MAGIC;
1389 break;
1390 default:
1391 if (options & MagicPacket)
1392 wolopts |= WAKE_MAGIC;
1393 break;
1394 }
61a4dcc2 1395
1ef7286e 1396 options = RTL_R8(tp, Config5);
61a4dcc2 1397 if (options & UWF)
e1759441 1398 wolopts |= WAKE_UCAST;
61a4dcc2 1399 if (options & BWF)
e1759441 1400 wolopts |= WAKE_BCAST;
61a4dcc2 1401 if (options & MWF)
e1759441 1402 wolopts |= WAKE_MCAST;
61a4dcc2 1403
e1759441 1404 return wolopts;
61a4dcc2
FR		 1405}
1406
e1759441 1407static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1408{
1409 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1410
da78dbff 1411 rtl_lock_work(tp);
e1759441 1412 wol->supported = WAKE_ANY;
433f9d0d 1413 wol->wolopts = tp->saved_wolopts;
da78dbff 1414 rtl_unlock_work(tp);
e1759441
RW		 1415}
1416
1417static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1418{
6e1d0b89 1419 unsigned int i, tmp;
350f7596 1420 static const struct {
61a4dcc2
FR		 1421 u32 opt;
1422 u16 reg;
1423 u8 mask;
1424 } cfg[] = {
61a4dcc2 1425 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1426 { WAKE_UCAST, Config5, UWF },
1427 { WAKE_BCAST, Config5, BWF },
1428 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1429 { WAKE_ANY, Config5, LanWake },
1430 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1431 };
851e6022 1432 u8 options;
61a4dcc2 1433
1ef7286e 1434 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1435
6e1d0b89 1436 switch (tp->mac_version) {
2a71883c
HK		 1437 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1438 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1439 tmp = ARRAY_SIZE(cfg) - 1;
1440 if (wolopts & WAKE_MAGIC)
706123d0 1441 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1442 0x0dc,
1443 ERIAR_MASK_0100,
1444 MagicPacket_v2,
1445 0x0000,
1446 ERIAR_EXGMAC);
1447 else
706123d0 1448 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1449 0x0dc,
1450 ERIAR_MASK_0100,
1451 0x0000,
1452 MagicPacket_v2,
1453 ERIAR_EXGMAC);
1454 break;
1455 default:
1456 tmp = ARRAY_SIZE(cfg);
1457 break;
1458 }
1459
1460 for (i = 0; i < tmp; i++) {
1ef7286e 1461 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1462 if (wolopts & cfg[i].opt)
61a4dcc2 1463 options |= cfg[i].mask;
1ef7286e 1464 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1465 }
1466
851e6022
FR		 1467 switch (tp->mac_version) {
1468 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1469 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1470 if (wolopts)
1471 options |= PMEnable;
1ef7286e 1472 RTL_W8(tp, Config1, options);
851e6022
FR		 1473 break;
1474 default:
1ef7286e 1475 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1476 if (wolopts)
1477 options |= PME_SIGNAL;
1ef7286e 1478 RTL_W8(tp, Config2, options);
851e6022
FR		 1479 break;
1480 }
1481
1ef7286e 1482 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
3bd82645
HK		 1483
1484 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
e1759441
RW		 1485}
1486
1487static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1488{
1489 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1490 struct device *d = tp_to_dev(tp);
5fa80a32 1491
2f533f6b
HK		 1492 if (wol->wolopts & ~WAKE_ANY)
1493 return -EINVAL;
1494
5fa80a32 1495 pm_runtime_get_noresume(d);
e1759441 1496
da78dbff 1497 rtl_lock_work(tp);
61a4dcc2 1498
2f533f6b 1499 tp->saved_wolopts = wol->wolopts;
433f9d0d 1500
5fa80a32 1501 if (pm_runtime_active(d))
433f9d0d 1502 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1503
1504 rtl_unlock_work(tp);
61a4dcc2 1505
5fa80a32
CHL		 1506 pm_runtime_put_noidle(d);
1507
61a4dcc2
FR		 1508 return 0;
1509}
1510
31bd204f
FR		 1511static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1512{
85bffe6c 1513 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1514}
1515
1da177e4
LT		 1516static void rtl8169_get_drvinfo(struct net_device *dev,
1517 struct ethtool_drvinfo *info)
1518{
1519 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1520 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1521
68aad78c 1522 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
68aad78c 1523 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1524 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1525 if (!IS_ERR_OR_NULL(rtl_fw))
1526 strlcpy(info->fw_version, rtl_fw->version,
1527 sizeof(info->fw_version));
1da177e4
LT		 1528}
1529
1530static int rtl8169_get_regs_len(struct net_device *dev)
1531{
1532 return R8169_REGS_SIZE;
1533}
1534
c8f44aff
MM		 1535static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1536 netdev_features_t features)
1da177e4 1537{
d58d46b5
FR		 1538 struct rtl8169_private *tp = netdev_priv(dev);
1539
2b7b4318 1540 if (dev->mtu > TD_MSS_MAX)
350fb32a 1541 features &= ~NETIF_F_ALL_TSO;
1da177e4 1542
d58d46b5 1543 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1544 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1545 features &= ~NETIF_F_IP_CSUM;
1546
350fb32a 1547 return features;
1da177e4
LT		 1548}
1549
a3984578
HK		 1550static int rtl8169_set_features(struct net_device *dev,
1551 netdev_features_t features)
1da177e4
LT		 1552{
1553 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1554 u32 rx_config;
1da177e4 1555
a3984578
HK		 1556 rtl_lock_work(tp);
1557
1ef7286e 1558 rx_config = RTL_R32(tp, RxConfig);
929a031d 1559 if (features & NETIF_F_RXALL)
1560 rx_config |= (AcceptErr | AcceptRunt);
1561 else
1562 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1563
1ef7286e 1564 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1565
929a031d 1566 if (features & NETIF_F_RXCSUM)
1567 tp->cp_cmd |= RxChkSum;
1568 else
1569 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1570
929a031d 1571 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1572 tp->cp_cmd |= RxVlan;
1573 else
1574 tp->cp_cmd &= ~RxVlan;
1575
1ef7286e
AS		 1576 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1577 RTL_R16(tp, CPlusCmd);
1da177e4 1578
da78dbff 1579 rtl_unlock_work(tp);
1da177e4
LT		 1580
1581 return 0;
1582}
1583
810f4893 1584static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1585{
df8a39de
JP		 1586 return (skb_vlan_tag_present(skb)) ?
1587 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1588}
1589
7a8fc77b 1590static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1591{
1592 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1593
7a8fc77b 1594 if (opts2 & RxVlanTag)
86a9bad3 1595 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1596}
1597
1da177e4
LT		 1598static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1599 void *p)
1600{
5b0384f4 1601 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1602 u32 __iomem *data = tp->mmio_addr;
1603 u32 *dw = p;
1604 int i;
1da177e4 1605
da78dbff 1606 rtl_lock_work(tp);
15edae91
PW		 1607 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1608 memcpy_fromio(dw++, data++, 4);
da78dbff 1609 rtl_unlock_work(tp);
1da177e4
LT		 1610}
1611
b57b7e5a
SH		 1612static u32 rtl8169_get_msglevel(struct net_device *dev)
1613{
1614 struct rtl8169_private *tp = netdev_priv(dev);
1615
1616 return tp->msg_enable;
1617}
1618
1619static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1620{
1621 struct rtl8169_private *tp = netdev_priv(dev);
1622
1623 tp->msg_enable = value;
1624}
1625
d4a3a0fc
SH		 1626static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1627 "tx_packets",
1628 "rx_packets",
1629 "tx_errors",
1630 "rx_errors",
1631 "rx_missed",
1632 "align_errors",
1633 "tx_single_collisions",
1634 "tx_multi_collisions",
1635 "unicast",
1636 "broadcast",
1637 "multicast",
1638 "tx_aborted",
1639 "tx_underrun",
1640};
1641
b9f2c044 1642static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1643{
b9f2c044
JG		 1644 switch (sset) {
1645 case ETH_SS_STATS:
1646 return ARRAY_SIZE(rtl8169_gstrings);
1647 default:
1648 return -EOPNOTSUPP;
1649 }
d4a3a0fc
SH		 1650}
1651
42020320 1652DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1653{
1ef7286e 1654 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1655}
1656
e71c9ce2 1657static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1658{
42020320
CV		 1659 dma_addr_t paddr = tp->counters_phys_addr;
1660 u32 cmd;
6e85d5ad 1661
1ef7286e
AS		 1662 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1663 RTL_R32(tp, CounterAddrHigh);
42020320 1664 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1665 RTL_W32(tp, CounterAddrLow, cmd);
1666 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1667
a78e9366 1668 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1669}
1670
e71c9ce2 1671static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1672{
6e85d5ad
CV		 1673 /*
1674 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1675 * tally counters.
1676 */
1677 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1678 return true;
1679
e71c9ce2 1680 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1681}
1682
e71c9ce2 1683static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1684{
10262b0b
HK		 1685 u8 val = RTL_R8(tp, ChipCmd);
1686
355423d0
IV		 1687 /*
1688 * Some chips are unable to dump tally counters when the receiver
10262b0b 1689 * is disabled. If 0xff chip may be in a PCI power-save state.
355423d0 1690 */
10262b0b 1691 if (!(val & CmdRxEnb) || val == 0xff)
6e85d5ad 1692 return true;
d4a3a0fc 1693
e71c9ce2 1694 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1695}
1696
e71c9ce2 1697static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1698{
42020320 1699 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1700 bool ret = false;
1701
1702 /*
1703 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1704 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1705 * reset by a power cycle, while the counter values collected by the
1706 * driver are reset at every driver unload/load cycle.
1707 *
1708 * To make sure the HW values returned by @get_stats64 match the SW
1709 * values, we collect the initial values at first open(*) and use them
1710 * as offsets to normalize the values returned by @get_stats64.
1711 *
1712 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1713 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1714 * set at open time by rtl_hw_start.
1715 */
1716
1717 if (tp->tc_offset.inited)
1718 return true;
1719
1720 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1721 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1722 ret = true;
1723
e71c9ce2 1724 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1725 ret = true;
1726
42020320
CV		 1727 tp->tc_offset.tx_errors = counters->tx_errors;
1728 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1729 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1730 tp->tc_offset.inited = true;
1731
1732 return ret;
d4a3a0fc
SH		 1733}
1734
355423d0
IV		 1735static void rtl8169_get_ethtool_stats(struct net_device *dev,
1736 struct ethtool_stats *stats, u64 *data)
1737{
1738 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1739 struct device *d = tp_to_dev(tp);
42020320 1740 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1741
1742 ASSERT_RTNL();
1743
e0636236
CHL		 1744 pm_runtime_get_noresume(d);
1745
1746 if (pm_runtime_active(d))
e71c9ce2 1747 rtl8169_update_counters(tp);
e0636236
CHL		 1748
1749 pm_runtime_put_noidle(d);
355423d0 1750
42020320
CV		 1751 data[0] = le64_to_cpu(counters->tx_packets);
1752 data[1] = le64_to_cpu(counters->rx_packets);
1753 data[2] = le64_to_cpu(counters->tx_errors);
1754 data[3] = le32_to_cpu(counters->rx_errors);
1755 data[4] = le16_to_cpu(counters->rx_missed);
1756 data[5] = le16_to_cpu(counters->align_errors);
1757 data[6] = le32_to_cpu(counters->tx_one_collision);
1758 data[7] = le32_to_cpu(counters->tx_multi_collision);
1759 data[8] = le64_to_cpu(counters->rx_unicast);
1760 data[9] = le64_to_cpu(counters->rx_broadcast);
1761 data[10] = le32_to_cpu(counters->rx_multicast);
1762 data[11] = le16_to_cpu(counters->tx_aborted);
1763 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1764}
1765
d4a3a0fc
SH		 1766static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1767{
1768 switch(stringset) {
1769 case ETH_SS_STATS:
1770 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1771 break;
1772 }
1773}
1774
50970831
FR		 1775/*
1776 * Interrupt coalescing
1777 *
1778 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1779 * > 8169, 8168 and 810x line of chipsets
1780 *
1781 * 8169, 8168, and 8136(810x) serial chipsets support it.
1782 *
1783 * > 2 - the Tx timer unit at gigabit speed
1784 *
1785 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1786 * (0xe0) bit 1 and bit 0.
1787 *
1788 * For 8169
1789 * bit[1:0] \ speed 1000M 100M 10M
1790 * 0 0 320ns 2.56us 40.96us
1791 * 0 1 2.56us 20.48us 327.7us
1792 * 1 0 5.12us 40.96us 655.4us
1793 * 1 1 10.24us 81.92us 1.31ms
1794 *
1795 * For the other
1796 * bit[1:0] \ speed 1000M 100M 10M
1797 * 0 0 5us 2.56us 40.96us
1798 * 0 1 40us 20.48us 327.7us
1799 * 1 0 80us 40.96us 655.4us
1800 * 1 1 160us 81.92us 1.31ms
1801 */
1802
1803/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1804struct rtl_coalesce_scale {
1805 /* Rx / Tx */
1806 u32 nsecs[2];
1807};
1808
1809/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1810struct rtl_coalesce_info {
1811 u32 speed;
1812 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1813};
1814
1815/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1816#define rxtx_x1822(r, t) { \
1817 {{(r), (t)}}, \
1818 {{(r)*8, (t)*8}}, \
1819 {{(r)*8*2, (t)*8*2}}, \
1820 {{(r)*8*2*2, (t)*8*2*2}}, \
1821}
1822static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1823 /* speed delays: rx00 tx00 */
1824 { SPEED_10, rxtx_x1822(40960, 40960) },
1825 { SPEED_100, rxtx_x1822( 2560, 2560) },
1826 { SPEED_1000, rxtx_x1822( 320, 320) },
1827 { 0 },
1828};
1829
1830static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1831 /* speed delays: rx00 tx00 */
1832 { SPEED_10, rxtx_x1822(40960, 40960) },
1833 { SPEED_100, rxtx_x1822( 2560, 2560) },
1834 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1835 { 0 },
1836};
1837#undef rxtx_x1822
1838
1839/* get rx/tx scale vector corresponding to current speed */
1840static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1841{
1842 struct rtl8169_private *tp = netdev_priv(dev);
1843 struct ethtool_link_ksettings ecmd;
1844 const struct rtl_coalesce_info *ci;
1845 int rc;
1846
45772433 1847 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
50970831
FR		 1848 if (rc < 0)
1849 return ERR_PTR(rc);
1850
1851 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1852 if (ecmd.base.speed == ci->speed) {
1853 return ci;
1854 }
1855 }
1856
1857 return ERR_PTR(-ELNRNG);
1858}
1859
1860static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1861{
1862 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1863 const struct rtl_coalesce_info *ci;
1864 const struct rtl_coalesce_scale *scale;
1865 struct {
1866 u32 *max_frames;
1867 u32 *usecs;
1868 } coal_settings [] = {
1869 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1870 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1871 }, *p = coal_settings;
1872 int i;
1873 u16 w;
1874
1875 memset(ec, 0, sizeof(*ec));
1876
1877 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1878 ci = rtl_coalesce_info(dev);
1879 if (IS_ERR(ci))
1880 return PTR_ERR(ci);
1881
0ae0974e 1882 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 1883
1884 /* read IntrMitigate and adjust according to scale */
1ef7286e 1885 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 1886 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1887 w >>= RTL_COALESCE_SHIFT;
1888 *p->usecs = w & RTL_COALESCE_MASK;
1889 }
1890
1891 for (i = 0; i < 2; i++) {
1892 p = coal_settings + i;
1893 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1894
1895 /*
1896 * ethtool_coalesce says it is illegal to set both usecs and
1897 * max_frames to 0.
1898 */
1899 if (!*p->usecs && !*p->max_frames)
1900 *p->max_frames = 1;
1901 }
1902
1903 return 0;
1904}
1905
1906/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1907static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1908 struct net_device *dev, u32 nsec, u16 *cp01)
1909{
1910 const struct rtl_coalesce_info *ci;
1911 u16 i;
1912
1913 ci = rtl_coalesce_info(dev);
1914 if (IS_ERR(ci))
1915 return ERR_CAST(ci);
1916
1917 for (i = 0; i < 4; i++) {
1918 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1919 ci->scalev[i].nsecs[1]);
1920 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1921 *cp01 = i;
1922 return &ci->scalev[i];
1923 }
1924 }
1925
1926 return ERR_PTR(-EINVAL);
1927}
1928
1929static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1930{
1931 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1932 const struct rtl_coalesce_scale *scale;
1933 struct {
1934 u32 frames;
1935 u32 usecs;
1936 } coal_settings [] = {
1937 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1938 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1939 }, *p = coal_settings;
1940 u16 w = 0, cp01;
1941 int i;
1942
1943 scale = rtl_coalesce_choose_scale(dev,
1944 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1945 if (IS_ERR(scale))
1946 return PTR_ERR(scale);
1947
1948 for (i = 0; i < 2; i++, p++) {
1949 u32 units;
1950
1951 /*
1952 * accept max_frames=1 we returned in rtl_get_coalesce.
1953 * accept it not only when usecs=0 because of e.g. the following scenario:
1954 *
1955 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1956 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1957 * - then user does `ethtool -C eth0 rx-usecs 100`
1958 *
1959 * since ethtool sends to kernel whole ethtool_coalesce
1960 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1961 * we'll reject it below in `frames % 4 != 0`.
1962 */
1963 if (p->frames == 1) {
1964 p->frames = 0;
1965 }
1966
1967 units = p->usecs * 1000 / scale->nsecs[i];
1968 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1969 return -EINVAL;
1970
1971 w <<= RTL_COALESCE_SHIFT;
1972 w |= units;
1973 w <<= RTL_COALESCE_SHIFT;
1974 w |= p->frames >> 2;
1975 }
1976
1977 rtl_lock_work(tp);
1978
1ef7286e 1979 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 1980
9a3c81fa 1981 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 1982 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1983 RTL_R16(tp, CPlusCmd);
50970831
FR		 1984
1985 rtl_unlock_work(tp);
1986
1987 return 0;
1988}
1989
7282d491 1990static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1991 .get_drvinfo = rtl8169_get_drvinfo,
1992 .get_regs_len = rtl8169_get_regs_len,
1993 .get_link = ethtool_op_get_link,
50970831
FR		 1994 .get_coalesce = rtl_get_coalesce,
1995 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 1996 .get_msglevel = rtl8169_get_msglevel,
1997 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1998 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1999 .get_wol = rtl8169_get_wol,
2000 .set_wol = rtl8169_set_wol,
d4a3a0fc 2001 .get_strings = rtl8169_get_strings,
b9f2c044 2002 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2003 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2004 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2005 .nway_reset = phy_ethtool_nway_reset,
45772433
HK		 2006 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2007 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1da177e4
LT		 2008};
2009
b4cc2dcc 2010static void rtl8169_get_mac_version(struct rtl8169_private *tp)
1da177e4 2011{
0e485150
FR		 2012 /*
2013 * The driver currently handles the 8168Bf and the 8168Be identically
2014 * but they can be identified more specifically through the test below
2015 * if needed:
2016 *
1ef7286e 2017 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2018 *
2019 * Same thing for the 8101Eb and the 8101Ec:
2020 *
1ef7286e 2021 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2022 */
3744100e 2023 static const struct rtl_mac_info {
55d2ad7b
HK		 2024 u16 mask;
2025 u16 val;
2026 u16 mac_version;
1da177e4 2027 } mac_info[] = {
935e2218 2028 /* 8168EP family. */
55d2ad7b
HK		 2029 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2030 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2031 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
935e2218 2032
6e1d0b89 2033 /* 8168H family. */
55d2ad7b
HK		 2034 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2035 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
6e1d0b89 2036
c558386b 2037 /* 8168G family. */
55d2ad7b
HK		 2038 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2039 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2040 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2041 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
c558386b 2042
c2218925 2043 /* 8168F family. */
55d2ad7b
HK		 2044 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2045 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2046 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
c2218925 2047
01dc7fec 2048 /* 8168E family. */
55d2ad7b
HK		 2049 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2050 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2051 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
01dc7fec 2052
5b538df9 2053 /* 8168D family. */
55d2ad7b
HK		 2054 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2055 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
5b538df9 2056
e6de30d6 2057 /* 8168DP family. */
55d2ad7b
HK		 2058 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2059 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2060 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
e6de30d6 2061
ef808d50 2062 /* 8168C family. */
55d2ad7b
HK		 2063 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2064 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2065 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2066 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2067 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2068 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2069 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2070
2071 /* 8168B family. */
55d2ad7b
HK		 2072 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2073 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2074 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
e3cf0cc0
FR		 2075
2076 /* 8101 family. */
55d2ad7b
HK		 2077 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2078 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2079 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2080 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2081 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2082 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2083 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2084 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2085 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2086 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2087 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2088 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2089 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2090 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
e3cf0cc0 2091 /* FIXME: where did these entries come from ? -- FR */
55d2ad7b
HK		 2092 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2093 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
e3cf0cc0
FR		 2094
2095 /* 8110 family. */
55d2ad7b
HK		 2096 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2097 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2098 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2099 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2100 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2101 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
e3cf0cc0 2102
f21b75e9 2103 /* Catch-all */
55d2ad7b 2104 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2105 };
2106 const struct rtl_mac_info *p = mac_info;
55d2ad7b 2107 u16 reg = RTL_R32(tp, TxConfig) >> 20;
1da177e4 2108
e3cf0cc0 2109 while ((reg & p->mask) != p->val)
1da177e4
LT		 2110 p++;
2111 tp->mac_version = p->mac_version;
5d320a20
FR		 2112
2113 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
b4cc2dcc 2114 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
45f1996f
HK		 2115 } else if (!tp->supports_gmii) {
2116 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2117 tp->mac_version = RTL_GIGA_MAC_VER_43;
2118 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2119 tp->mac_version = RTL_GIGA_MAC_VER_47;
2120 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2121 tp->mac_version = RTL_GIGA_MAC_VER_48;
5d320a20 2122 }
1da177e4
LT		 2123}
2124
867763c1
FR		 2125struct phy_reg {
2126 u16 reg;
2127 u16 val;
2128};
2129
4da19633 2130static void rtl_writephy_batch(struct rtl8169_private *tp,
2131 const struct phy_reg *regs, int len)
867763c1
FR		 2132{
2133 while (len-- > 0) {
4da19633 2134 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2135 regs++;
2136 }
2137}
2138
bca03d5f 2139#define PHY_READ 0x00000000
2140#define PHY_DATA_OR 0x10000000
2141#define PHY_DATA_AND 0x20000000
2142#define PHY_BJMPN 0x30000000
eee3786f 2143#define PHY_MDIO_CHG 0x40000000
bca03d5f 2144#define PHY_CLEAR_READCOUNT 0x70000000
2145#define PHY_WRITE 0x80000000
2146#define PHY_READCOUNT_EQ_SKIP 0x90000000
2147#define PHY_COMP_EQ_SKIPN 0xa0000000
2148#define PHY_COMP_NEQ_SKIPN 0xb0000000
2149#define PHY_WRITE_PREVIOUS 0xc0000000
2150#define PHY_SKIPN 0xd0000000
2151#define PHY_DELAY_MS 0xe0000000
bca03d5f 2152
960aee6c
HW		 2153struct fw_info {
2154 u32 magic;
2155 char version[RTL_VER_SIZE];
2156 __le32 fw_start;
2157 __le32 fw_len;
2158 u8 chksum;
2159} __packed;
2160
1c361efb
FR		 2161#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2162
2163static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2164{
b6ffd97f 2165 const struct firmware *fw = rtl_fw->fw;
960aee6c 2166 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2167 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2168 char *version = rtl_fw->version;
2169 bool rc = false;
2170
2171 if (fw->size < FW_OPCODE_SIZE)
2172 goto out;
960aee6c
HW		 2173
2174 if (!fw_info->magic) {
2175 size_t i, size, start;
2176 u8 checksum = 0;
2177
2178 if (fw->size < sizeof(*fw_info))
2179 goto out;
2180
2181 for (i = 0; i < fw->size; i++)
2182 checksum += fw->data[i];
2183 if (checksum != 0)
2184 goto out;
2185
2186 start = le32_to_cpu(fw_info->fw_start);
2187 if (start > fw->size)
2188 goto out;
2189
2190 size = le32_to_cpu(fw_info->fw_len);
2191 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2192 goto out;
2193
2194 memcpy(version, fw_info->version, RTL_VER_SIZE);
2195
2196 pa->code = (__le32 *)(fw->data + start);
2197 pa->size = size;
2198 } else {
1c361efb
FR		 2199 if (fw->size % FW_OPCODE_SIZE)
2200 goto out;
2201
2202 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2203
2204 pa->code = (__le32 *)fw->data;
2205 pa->size = fw->size / FW_OPCODE_SIZE;
2206 }
2207 version[RTL_VER_SIZE - 1] = 0;
2208
2209 rc = true;
2210out:
2211 return rc;
2212}
2213
fd112f2e
FR		 2214static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2215 struct rtl_fw_phy_action *pa)
1c361efb 2216{
fd112f2e 2217 bool rc = false;
1c361efb 2218 size_t index;
bca03d5f 2219
1c361efb
FR		 2220 for (index = 0; index < pa->size; index++) {
2221 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2222 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2223
42b82dc1 2224 switch(action & 0xf0000000) {
2225 case PHY_READ:
2226 case PHY_DATA_OR:
2227 case PHY_DATA_AND:
eee3786f 2228 case PHY_MDIO_CHG:
42b82dc1 2229 case PHY_CLEAR_READCOUNT:
2230 case PHY_WRITE:
2231 case PHY_WRITE_PREVIOUS:
2232 case PHY_DELAY_MS:
2233 break;
2234
2235 case PHY_BJMPN:
2236 if (regno > index) {
fd112f2e 2237 netif_err(tp, ifup, tp->dev,
cecb5fd7 2238 "Out of range of firmware\n");
fd112f2e 2239 goto out;
42b82dc1 2240 }
2241 break;
2242 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2243 if (index + 2 >= pa->size) {
fd112f2e 2244 netif_err(tp, ifup, tp->dev,
cecb5fd7 2245 "Out of range of firmware\n");
fd112f2e 2246 goto out;
42b82dc1 2247 }
2248 break;
2249 case PHY_COMP_EQ_SKIPN:
2250 case PHY_COMP_NEQ_SKIPN:
2251 case PHY_SKIPN:
1c361efb 2252 if (index + 1 + regno >= pa->size) {
fd112f2e 2253 netif_err(tp, ifup, tp->dev,
cecb5fd7 2254 "Out of range of firmware\n");
fd112f2e 2255 goto out;
42b82dc1 2256 }
bca03d5f 2257 break;
2258
42b82dc1 2259 default:
fd112f2e 2260 netif_err(tp, ifup, tp->dev,
42b82dc1 2261 "Invalid action 0x%08x\n", action);
fd112f2e 2262 goto out;
bca03d5f 2263 }
2264 }
fd112f2e
FR		 2265 rc = true;
2266out:
2267 return rc;
2268}
bca03d5f 2269
fd112f2e
FR		 2270static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2271{
2272 struct net_device *dev = tp->dev;
2273 int rc = -EINVAL;
2274
2275 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2276 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2277 goto out;
2278 }
2279
2280 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2281 rc = 0;
2282out:
2283 return rc;
2284}
2285
2286static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2287{
2288 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2289 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2290 u32 predata, count;
2291 size_t index;
2292
2293 predata = count = 0;
eee3786f 2294 org.write = ops->write;
2295 org.read = ops->read;
42b82dc1 2296
1c361efb
FR		 2297 for (index = 0; index < pa->size; ) {
2298 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2299 u32 data = action & 0x0000ffff;
42b82dc1 2300 u32 regno = (action & 0x0fff0000) >> 16;
2301
2302 if (!action)
2303 break;
bca03d5f 2304
2305 switch(action & 0xf0000000) {
42b82dc1 2306 case PHY_READ:
2307 predata = rtl_readphy(tp, regno);
2308 count++;
2309 index++;
2310 break;
2311 case PHY_DATA_OR:
2312 predata |= data;
2313 index++;
2314 break;
2315 case PHY_DATA_AND:
2316 predata &= data;
2317 index++;
2318 break;
2319 case PHY_BJMPN:
2320 index -= regno;
2321 break;
eee3786f 2322 case PHY_MDIO_CHG:
2323 if (data == 0) {
2324 ops->write = org.write;
2325 ops->read = org.read;
2326 } else if (data == 1) {
2327 ops->write = mac_mcu_write;
2328 ops->read = mac_mcu_read;
2329 }
2330
42b82dc1 2331 index++;
2332 break;
2333 case PHY_CLEAR_READCOUNT:
2334 count = 0;
2335 index++;
2336 break;
bca03d5f 2337 case PHY_WRITE:
42b82dc1 2338 rtl_writephy(tp, regno, data);
2339 index++;
2340 break;
2341 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2342 index += (count == data) ? 2 : 1;
bca03d5f 2343 break;
42b82dc1 2344 case PHY_COMP_EQ_SKIPN:
2345 if (predata == data)
2346 index += regno;
2347 index++;
2348 break;
2349 case PHY_COMP_NEQ_SKIPN:
2350 if (predata != data)
2351 index += regno;
2352 index++;
2353 break;
2354 case PHY_WRITE_PREVIOUS:
2355 rtl_writephy(tp, regno, predata);
2356 index++;
2357 break;
2358 case PHY_SKIPN:
2359 index += regno + 1;
2360 break;
2361 case PHY_DELAY_MS:
2362 mdelay(data);
2363 index++;
2364 break;
2365
bca03d5f 2366 default:
2367 BUG();
2368 }
2369 }
eee3786f 2370
2371 ops->write = org.write;
2372 ops->read = org.read;
bca03d5f 2373}
2374
f1e02ed1 2375static void rtl_release_firmware(struct rtl8169_private *tp)
2376{
b6ffd97f
FR		 2377 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2378 release_firmware(tp->rtl_fw->fw);
2379 kfree(tp->rtl_fw);
2380 }
2381 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2382}
2383
953a12cc 2384static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2385{
b6ffd97f 2386 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2387
2388 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2389 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2390 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2391}
2392
2393static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2394{
2395 if (rtl_readphy(tp, reg) != val)
2396 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2397 else
2398 rtl_apply_firmware(tp);
f1e02ed1 2399}
2400
4da19633 2401static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2402{
350f7596 2403 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2404 { 0x1f, 0x0001 },
2405 { 0x06, 0x006e },
2406 { 0x08, 0x0708 },
2407 { 0x15, 0x4000 },
2408 { 0x18, 0x65c7 },
1da177e4 2409
0b9b571d 2410 { 0x1f, 0x0001 },
2411 { 0x03, 0x00a1 },
2412 { 0x02, 0x0008 },
2413 { 0x01, 0x0120 },
2414 { 0x00, 0x1000 },
2415 { 0x04, 0x0800 },
2416 { 0x04, 0x0000 },
1da177e4 2417
0b9b571d 2418 { 0x03, 0xff41 },
2419 { 0x02, 0xdf60 },
2420 { 0x01, 0x0140 },
2421 { 0x00, 0x0077 },
2422 { 0x04, 0x7800 },
2423 { 0x04, 0x7000 },
2424
2425 { 0x03, 0x802f },
2426 { 0x02, 0x4f02 },
2427 { 0x01, 0x0409 },
2428 { 0x00, 0xf0f9 },
2429 { 0x04, 0x9800 },
2430 { 0x04, 0x9000 },
2431
2432 { 0x03, 0xdf01 },
2433 { 0x02, 0xdf20 },
2434 { 0x01, 0xff95 },
2435 { 0x00, 0xba00 },
2436 { 0x04, 0xa800 },
2437 { 0x04, 0xa000 },
2438
2439 { 0x03, 0xff41 },
2440 { 0x02, 0xdf20 },
2441 { 0x01, 0x0140 },
2442 { 0x00, 0x00bb },
2443 { 0x04, 0xb800 },
2444 { 0x04, 0xb000 },
2445
2446 { 0x03, 0xdf41 },
2447 { 0x02, 0xdc60 },
2448 { 0x01, 0x6340 },
2449 { 0x00, 0x007d },
2450 { 0x04, 0xd800 },
2451 { 0x04, 0xd000 },
2452
2453 { 0x03, 0xdf01 },
2454 { 0x02, 0xdf20 },
2455 { 0x01, 0x100a },
2456 { 0x00, 0xa0ff },
2457 { 0x04, 0xf800 },
2458 { 0x04, 0xf000 },
2459
2460 { 0x1f, 0x0000 },
2461 { 0x0b, 0x0000 },
2462 { 0x00, 0x9200 }
2463 };
1da177e4 2464
4da19633 2465 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2466}
2467
4da19633 2468static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2469{
350f7596 2470 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2471 { 0x1f, 0x0002 },
2472 { 0x01, 0x90d0 },
2473 { 0x1f, 0x0000 }
2474 };
2475
4da19633 2476 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2477}
2478
4da19633 2479static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2480{
2481 struct pci_dev *pdev = tp->pci_dev;
2e955856 2482
ccbae55e
SS		 2483 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2484 (pdev->subsystem_device != 0xe000))
2e955856 2485 return;
2486
4da19633 2487 rtl_writephy(tp, 0x1f, 0x0001);
2488 rtl_writephy(tp, 0x10, 0xf01b);
2489 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2490}
2491
4da19633 2492static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2493{
350f7596 2494 static const struct phy_reg phy_reg_init[] = {
2e955856 2495 { 0x1f, 0x0001 },
2496 { 0x04, 0x0000 },
2497 { 0x03, 0x00a1 },
2498 { 0x02, 0x0008 },
2499 { 0x01, 0x0120 },
2500 { 0x00, 0x1000 },
2501 { 0x04, 0x0800 },
2502 { 0x04, 0x9000 },
2503 { 0x03, 0x802f },
2504 { 0x02, 0x4f02 },
2505 { 0x01, 0x0409 },
2506 { 0x00, 0xf099 },
2507 { 0x04, 0x9800 },
2508 { 0x04, 0xa000 },
2509 { 0x03, 0xdf01 },
2510 { 0x02, 0xdf20 },
2511 { 0x01, 0xff95 },
2512 { 0x00, 0xba00 },
2513 { 0x04, 0xa800 },
2514 { 0x04, 0xf000 },
2515 { 0x03, 0xdf01 },
2516 { 0x02, 0xdf20 },
2517 { 0x01, 0x101a },
2518 { 0x00, 0xa0ff },
2519 { 0x04, 0xf800 },
2520 { 0x04, 0x0000 },
2521 { 0x1f, 0x0000 },
2522
2523 { 0x1f, 0x0001 },
2524 { 0x10, 0xf41b },
2525 { 0x14, 0xfb54 },
2526 { 0x18, 0xf5c7 },
2527 { 0x1f, 0x0000 },
2528
2529 { 0x1f, 0x0001 },
2530 { 0x17, 0x0cc0 },
2531 { 0x1f, 0x0000 }
2532 };
2533
4da19633 2534 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2535
4da19633 2536 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2537}
2538
4da19633 2539static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2540{
350f7596 2541 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2542 { 0x1f, 0x0001 },
2543 { 0x04, 0x0000 },
2544 { 0x03, 0x00a1 },
2545 { 0x02, 0x0008 },
2546 { 0x01, 0x0120 },
2547 { 0x00, 0x1000 },
2548 { 0x04, 0x0800 },
2549 { 0x04, 0x9000 },
2550 { 0x03, 0x802f },
2551 { 0x02, 0x4f02 },
2552 { 0x01, 0x0409 },
2553 { 0x00, 0xf099 },
2554 { 0x04, 0x9800 },
2555 { 0x04, 0xa000 },
2556 { 0x03, 0xdf01 },
2557 { 0x02, 0xdf20 },
2558 { 0x01, 0xff95 },
2559 { 0x00, 0xba00 },
2560 { 0x04, 0xa800 },
2561 { 0x04, 0xf000 },
2562 { 0x03, 0xdf01 },
2563 { 0x02, 0xdf20 },
2564 { 0x01, 0x101a },
2565 { 0x00, 0xa0ff },
2566 { 0x04, 0xf800 },
2567 { 0x04, 0x0000 },
2568 { 0x1f, 0x0000 },
2569
2570 { 0x1f, 0x0001 },
2571 { 0x0b, 0x8480 },
2572 { 0x1f, 0x0000 },
2573
2574 { 0x1f, 0x0001 },
2575 { 0x18, 0x67c7 },
2576 { 0x04, 0x2000 },
2577 { 0x03, 0x002f },
2578 { 0x02, 0x4360 },
2579 { 0x01, 0x0109 },
2580 { 0x00, 0x3022 },
2581 { 0x04, 0x2800 },
2582 { 0x1f, 0x0000 },
2583
2584 { 0x1f, 0x0001 },
2585 { 0x17, 0x0cc0 },
2586 { 0x1f, 0x0000 }
2587 };
2588
4da19633 2589 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2590}
2591
4da19633 2592static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2593{
350f7596 2594 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2595 { 0x10, 0xf41b },
2596 { 0x1f, 0x0000 }
2597 };
2598
4da19633 2599 rtl_writephy(tp, 0x1f, 0x0001);
2600 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2601
4da19633 2602 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2603}
2604
4da19633 2605static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2606{
350f7596 2607 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2608 { 0x1f, 0x0001 },
2609 { 0x10, 0xf41b },
2610 { 0x1f, 0x0000 }
2611 };
2612
4da19633 2613 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2614}
2615
4da19633 2616static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2617{
350f7596 2618 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2619 { 0x1f, 0x0000 },
2620 { 0x1d, 0x0f00 },
2621 { 0x1f, 0x0002 },
2622 { 0x0c, 0x1ec8 },
2623 { 0x1f, 0x0000 }
2624 };
2625
4da19633 2626 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2627}
2628
4da19633 2629static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2630{
350f7596 2631 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2632 { 0x1f, 0x0001 },
2633 { 0x1d, 0x3d98 },
2634 { 0x1f, 0x0000 }
2635 };
2636
4da19633 2637 rtl_writephy(tp, 0x1f, 0x0000);
2638 rtl_patchphy(tp, 0x14, 1 << 5);
2639 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2640
4da19633 2641 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2642}
2643
4da19633 2644static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2645{
350f7596 2646 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2647 { 0x1f, 0x0001 },
2648 { 0x12, 0x2300 },
867763c1
FR		 2649 { 0x1f, 0x0002 },
2650 { 0x00, 0x88d4 },
2651 { 0x01, 0x82b1 },
2652 { 0x03, 0x7002 },
2653 { 0x08, 0x9e30 },
2654 { 0x09, 0x01f0 },
2655 { 0x0a, 0x5500 },
2656 { 0x0c, 0x00c8 },
2657 { 0x1f, 0x0003 },
2658 { 0x12, 0xc096 },
2659 { 0x16, 0x000a },
f50d4275
FR		 2660 { 0x1f, 0x0000 },
2661 { 0x1f, 0x0000 },
2662 { 0x09, 0x2000 },
2663 { 0x09, 0x0000 }
867763c1
FR		 2664 };
2665
4da19633 2666 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2667
4da19633 2668 rtl_patchphy(tp, 0x14, 1 << 5);
2669 rtl_patchphy(tp, 0x0d, 1 << 5);
2670 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2671}
2672
4da19633 2673static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2674{
350f7596 2675 static const struct phy_reg phy_reg_init[] = {
f50d4275 2676 { 0x1f, 0x0001 },
7da97ec9 2677 { 0x12, 0x2300 },
f50d4275
FR		 2678 { 0x03, 0x802f },
2679 { 0x02, 0x4f02 },
2680 { 0x01, 0x0409 },
2681 { 0x00, 0xf099 },
2682 { 0x04, 0x9800 },
2683 { 0x04, 0x9000 },
2684 { 0x1d, 0x3d98 },
7da97ec9
FR		 2685 { 0x1f, 0x0002 },
2686 { 0x0c, 0x7eb8 },
f50d4275
FR		 2687 { 0x06, 0x0761 },
2688 { 0x1f, 0x0003 },
2689 { 0x16, 0x0f0a },
7da97ec9
FR		 2690 { 0x1f, 0x0000 }
2691 };
2692
4da19633 2693 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2694
4da19633 2695 rtl_patchphy(tp, 0x16, 1 << 0);
2696 rtl_patchphy(tp, 0x14, 1 << 5);
2697 rtl_patchphy(tp, 0x0d, 1 << 5);
2698 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2699}
2700
4da19633 2701static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2702{
350f7596 2703 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2704 { 0x1f, 0x0001 },
2705 { 0x12, 0x2300 },
2706 { 0x1d, 0x3d98 },
2707 { 0x1f, 0x0002 },
2708 { 0x0c, 0x7eb8 },
2709 { 0x06, 0x5461 },
2710 { 0x1f, 0x0003 },
2711 { 0x16, 0x0f0a },
2712 { 0x1f, 0x0000 }
2713 };
2714
4da19633 2715 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2716
4da19633 2717 rtl_patchphy(tp, 0x16, 1 << 0);
2718 rtl_patchphy(tp, 0x14, 1 << 5);
2719 rtl_patchphy(tp, 0x0d, 1 << 5);
2720 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2721}
2722
4da19633 2723static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2724{
4da19633 2725 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2726}
2727
bca03d5f 2728static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2729{
350f7596 2730 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2731 /* Channel Estimation */
5b538df9 2732 { 0x1f, 0x0001 },
daf9df6d 2733 { 0x06, 0x4064 },
2734 { 0x07, 0x2863 },
2735 { 0x08, 0x059c },
2736 { 0x09, 0x26b4 },
2737 { 0x0a, 0x6a19 },
2738 { 0x0b, 0xdcc8 },
2739 { 0x10, 0xf06d },
2740 { 0x14, 0x7f68 },
2741 { 0x18, 0x7fd9 },
2742 { 0x1c, 0xf0ff },
2743 { 0x1d, 0x3d9c },
5b538df9 2744 { 0x1f, 0x0003 },
daf9df6d 2745 { 0x12, 0xf49f },
2746 { 0x13, 0x070b },
2747 { 0x1a, 0x05ad },
bca03d5f 2748 { 0x14, 0x94c0 },
2749
2750 /*
2751 * Tx Error Issue
cecb5fd7 2752 * Enhance line driver power
bca03d5f 2753 */
5b538df9 2754 { 0x1f, 0x0002 },
daf9df6d 2755 { 0x06, 0x5561 },
2756 { 0x1f, 0x0005 },
2757 { 0x05, 0x8332 },
bca03d5f 2758 { 0x06, 0x5561 },
2759
2760 /*
2761 * Can not link to 1Gbps with bad cable
2762 * Decrease SNR threshold form 21.07dB to 19.04dB
2763 */
2764 { 0x1f, 0x0001 },
2765 { 0x17, 0x0cc0 },
daf9df6d 2766
5b538df9 2767 { 0x1f, 0x0000 },
bca03d5f 2768 { 0x0d, 0xf880 }
daf9df6d 2769 };
2770
4da19633 2771 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2772
bca03d5f 2773 /*
2774 * Rx Error Issue
2775 * Fine Tune Switching regulator parameter
2776 */
4da19633 2777 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2778 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2779 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2780
fdf6fc06 2781 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2782 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2783 { 0x1f, 0x0002 },
2784 { 0x05, 0x669a },
2785 { 0x1f, 0x0005 },
2786 { 0x05, 0x8330 },
2787 { 0x06, 0x669a },
2788 { 0x1f, 0x0002 }
2789 };
2790 int val;
2791
4da19633 2792 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2793
4da19633 2794 val = rtl_readphy(tp, 0x0d);
daf9df6d 2795
2796 if ((val & 0x00ff) != 0x006c) {
350f7596 2797 static const u32 set[] = {
daf9df6d 2798 0x0065, 0x0066, 0x0067, 0x0068,
2799 0x0069, 0x006a, 0x006b, 0x006c
2800 };
2801 int i;
2802
4da19633 2803 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2804
2805 val &= 0xff00;
2806 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2807 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2808 }
2809 } else {
350f7596 2810 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2811 { 0x1f, 0x0002 },
2812 { 0x05, 0x6662 },
2813 { 0x1f, 0x0005 },
2814 { 0x05, 0x8330 },
2815 { 0x06, 0x6662 }
2816 };
2817
4da19633 2818 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2819 }
2820
bca03d5f 2821 /* RSET couple improve */
4da19633 2822 rtl_writephy(tp, 0x1f, 0x0002);
2823 rtl_patchphy(tp, 0x0d, 0x0300);
2824 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2825
bca03d5f 2826 /* Fine tune PLL performance */
4da19633 2827 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2828 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2829 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2830
4da19633 2831 rtl_writephy(tp, 0x1f, 0x0005);
2832 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2833
2834 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2835
4da19633 2836 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2837}
2838
bca03d5f 2839static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2840{
350f7596 2841 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2842 /* Channel Estimation */
daf9df6d 2843 { 0x1f, 0x0001 },
2844 { 0x06, 0x4064 },
2845 { 0x07, 0x2863 },
2846 { 0x08, 0x059c },
2847 { 0x09, 0x26b4 },
2848 { 0x0a, 0x6a19 },
2849 { 0x0b, 0xdcc8 },
2850 { 0x10, 0xf06d },
2851 { 0x14, 0x7f68 },
2852 { 0x18, 0x7fd9 },
2853 { 0x1c, 0xf0ff },
2854 { 0x1d, 0x3d9c },
2855 { 0x1f, 0x0003 },
2856 { 0x12, 0xf49f },
2857 { 0x13, 0x070b },
2858 { 0x1a, 0x05ad },
2859 { 0x14, 0x94c0 },
2860
bca03d5f 2861 /*
2862 * Tx Error Issue
cecb5fd7 2863 * Enhance line driver power
bca03d5f 2864 */
daf9df6d 2865 { 0x1f, 0x0002 },
2866 { 0x06, 0x5561 },
2867 { 0x1f, 0x0005 },
2868 { 0x05, 0x8332 },
bca03d5f 2869 { 0x06, 0x5561 },
2870
2871 /*
2872 * Can not link to 1Gbps with bad cable
2873 * Decrease SNR threshold form 21.07dB to 19.04dB
2874 */
2875 { 0x1f, 0x0001 },
2876 { 0x17, 0x0cc0 },
daf9df6d 2877
2878 { 0x1f, 0x0000 },
bca03d5f 2879 { 0x0d, 0xf880 }
5b538df9
FR		 2880 };
2881
4da19633 2882 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2883
fdf6fc06 2884 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2885 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2886 { 0x1f, 0x0002 },
2887 { 0x05, 0x669a },
5b538df9 2888 { 0x1f, 0x0005 },
daf9df6d 2889 { 0x05, 0x8330 },
2890 { 0x06, 0x669a },
2891
2892 { 0x1f, 0x0002 }
2893 };
2894 int val;
2895
4da19633 2896 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2897
4da19633 2898 val = rtl_readphy(tp, 0x0d);
daf9df6d 2899 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2900 static const u32 set[] = {
daf9df6d 2901 0x0065, 0x0066, 0x0067, 0x0068,
2902 0x0069, 0x006a, 0x006b, 0x006c
2903 };
2904 int i;
2905
4da19633 2906 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2907
2908 val &= 0xff00;
2909 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2910 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2911 }
2912 } else {
350f7596 2913 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2914 { 0x1f, 0x0002 },
2915 { 0x05, 0x2642 },
5b538df9 2916 { 0x1f, 0x0005 },
daf9df6d 2917 { 0x05, 0x8330 },
2918 { 0x06, 0x2642 }
5b538df9
FR		 2919 };
2920
4da19633 2921 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2922 }
2923
bca03d5f 2924 /* Fine tune PLL performance */
4da19633 2925 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2926 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2927 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2928
bca03d5f 2929 /* Switching regulator Slew rate */
4da19633 2930 rtl_writephy(tp, 0x1f, 0x0002);
2931 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2932
4da19633 2933 rtl_writephy(tp, 0x1f, 0x0005);
2934 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2935
2936 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2937
4da19633 2938 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2939}
2940
4da19633 2941static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2942{
350f7596 2943 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2944 { 0x1f, 0x0002 },
2945 { 0x10, 0x0008 },
2946 { 0x0d, 0x006c },
2947
2948 { 0x1f, 0x0000 },
2949 { 0x0d, 0xf880 },
2950
2951 { 0x1f, 0x0001 },
2952 { 0x17, 0x0cc0 },
2953
2954 { 0x1f, 0x0001 },
2955 { 0x0b, 0xa4d8 },
2956 { 0x09, 0x281c },
2957 { 0x07, 0x2883 },
2958 { 0x0a, 0x6b35 },
2959 { 0x1d, 0x3da4 },
2960 { 0x1c, 0xeffd },
2961 { 0x14, 0x7f52 },
2962 { 0x18, 0x7fc6 },
2963 { 0x08, 0x0601 },
2964 { 0x06, 0x4063 },
2965 { 0x10, 0xf074 },
2966 { 0x1f, 0x0003 },
2967 { 0x13, 0x0789 },
2968 { 0x12, 0xf4bd },
2969 { 0x1a, 0x04fd },
2970 { 0x14, 0x84b0 },
2971 { 0x1f, 0x0000 },
2972 { 0x00, 0x9200 },
2973
2974 { 0x1f, 0x0005 },
2975 { 0x01, 0x0340 },
2976 { 0x1f, 0x0001 },
2977 { 0x04, 0x4000 },
2978 { 0x03, 0x1d21 },
2979 { 0x02, 0x0c32 },
2980 { 0x01, 0x0200 },
2981 { 0x00, 0x5554 },
2982 { 0x04, 0x4800 },
2983 { 0x04, 0x4000 },
2984 { 0x04, 0xf000 },
2985 { 0x03, 0xdf01 },
2986 { 0x02, 0xdf20 },
2987 { 0x01, 0x101a },
2988 { 0x00, 0xa0ff },
2989 { 0x04, 0xf800 },
2990 { 0x04, 0xf000 },
2991 { 0x1f, 0x0000 },
2992
2993 { 0x1f, 0x0007 },
2994 { 0x1e, 0x0023 },
2995 { 0x16, 0x0000 },
2996 { 0x1f, 0x0000 }
2997 };
2998
4da19633 2999 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3000}
3001
e6de30d6 3002static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3003{
3004 static const struct phy_reg phy_reg_init[] = {
3005 { 0x1f, 0x0001 },
3006 { 0x17, 0x0cc0 },
3007
3008 { 0x1f, 0x0007 },
3009 { 0x1e, 0x002d },
3010 { 0x18, 0x0040 },
3011 { 0x1f, 0x0000 }
3012 };
3013
3014 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3015 rtl_patchphy(tp, 0x0d, 1 << 5);
3016}
3017
70090424 3018static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3019{
3020 static const struct phy_reg phy_reg_init[] = {
3021 /* Enable Delay cap */
3022 { 0x1f, 0x0005 },
3023 { 0x05, 0x8b80 },
3024 { 0x06, 0xc896 },
3025 { 0x1f, 0x0000 },
3026
3027 /* Channel estimation fine tune */
3028 { 0x1f, 0x0001 },
3029 { 0x0b, 0x6c20 },
3030 { 0x07, 0x2872 },
3031 { 0x1c, 0xefff },
3032 { 0x1f, 0x0003 },
3033 { 0x14, 0x6420 },
3034 { 0x1f, 0x0000 },
3035
3036 /* Update PFM & 10M TX idle timer */
3037 { 0x1f, 0x0007 },
3038 { 0x1e, 0x002f },
3039 { 0x15, 0x1919 },
3040 { 0x1f, 0x0000 },
3041
3042 { 0x1f, 0x0007 },
3043 { 0x1e, 0x00ac },
3044 { 0x18, 0x0006 },
3045 { 0x1f, 0x0000 }
3046 };
3047
15ecd039
FR		 3048 rtl_apply_firmware(tp);
3049
01dc7fec 3050 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3051
3052 /* DCO enable for 10M IDLE Power */
3053 rtl_writephy(tp, 0x1f, 0x0007);
3054 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3055 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3056 rtl_writephy(tp, 0x1f, 0x0000);
3057
3058 /* For impedance matching */
3059 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3060 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3061 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3062
3063 /* PHY auto speed down */
3064 rtl_writephy(tp, 0x1f, 0x0007);
3065 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3066 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3067 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3068 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3069
3070 rtl_writephy(tp, 0x1f, 0x0005);
3071 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3072 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3073 rtl_writephy(tp, 0x1f, 0x0000);
3074
3075 rtl_writephy(tp, 0x1f, 0x0005);
3076 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3077 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3078 rtl_writephy(tp, 0x1f, 0x0007);
3079 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3080 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3081 rtl_writephy(tp, 0x1f, 0x0006);
3082 rtl_writephy(tp, 0x00, 0x5a00);
3083 rtl_writephy(tp, 0x1f, 0x0000);
3084 rtl_writephy(tp, 0x0d, 0x0007);
3085 rtl_writephy(tp, 0x0e, 0x003c);
3086 rtl_writephy(tp, 0x0d, 0x4007);
3087 rtl_writephy(tp, 0x0e, 0x0000);
3088 rtl_writephy(tp, 0x0d, 0x0000);
3089}
3090
9ecb9aab 3091static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3092{
3093 const u16 w[] = {
3094 addr[0] | (addr[1] << 8),
3095 addr[2] | (addr[3] << 8),
3096 addr[4] | (addr[5] << 8)
3097 };
3098 const struct exgmac_reg e[] = {
3099 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3100 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3101 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3102 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3103 };
3104
3105 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3106}
3107
70090424
HW		 3108static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3109{
3110 static const struct phy_reg phy_reg_init[] = {
3111 /* Enable Delay cap */
3112 { 0x1f, 0x0004 },
3113 { 0x1f, 0x0007 },
3114 { 0x1e, 0x00ac },
3115 { 0x18, 0x0006 },
3116 { 0x1f, 0x0002 },
3117 { 0x1f, 0x0000 },
3118 { 0x1f, 0x0000 },
3119
3120 /* Channel estimation fine tune */
3121 { 0x1f, 0x0003 },
3122 { 0x09, 0xa20f },
3123 { 0x1f, 0x0000 },
3124 { 0x1f, 0x0000 },
3125
3126 /* Green Setting */
3127 { 0x1f, 0x0005 },
3128 { 0x05, 0x8b5b },
3129 { 0x06, 0x9222 },
3130 { 0x05, 0x8b6d },
3131 { 0x06, 0x8000 },
3132 { 0x05, 0x8b76 },
3133 { 0x06, 0x8000 },
3134 { 0x1f, 0x0000 }
3135 };
3136
3137 rtl_apply_firmware(tp);
3138
3139 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3140
3141 /* For 4-corner performance improve */
3142 rtl_writephy(tp, 0x1f, 0x0005);
3143 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3144 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3145 rtl_writephy(tp, 0x1f, 0x0000);
3146
3147 /* PHY auto speed down */
3148 rtl_writephy(tp, 0x1f, 0x0004);
3149 rtl_writephy(tp, 0x1f, 0x0007);
3150 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3151 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3152 rtl_writephy(tp, 0x1f, 0x0002);
3153 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3154 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3155
3156 /* improve 10M EEE waveform */
3157 rtl_writephy(tp, 0x1f, 0x0005);
3158 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3159 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3160 rtl_writephy(tp, 0x1f, 0x0000);
3161
3162 /* Improve 2-pair detection performance */
3163 rtl_writephy(tp, 0x1f, 0x0005);
3164 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3165 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3166 rtl_writephy(tp, 0x1f, 0x0000);
3167
3168 /* EEE setting */
1814d6a8 3169 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3170 rtl_writephy(tp, 0x1f, 0x0005);
3171 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3172 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3173 rtl_writephy(tp, 0x1f, 0x0004);
3174 rtl_writephy(tp, 0x1f, 0x0007);
3175 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3176 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3177 rtl_writephy(tp, 0x1f, 0x0002);
3178 rtl_writephy(tp, 0x1f, 0x0000);
3179 rtl_writephy(tp, 0x0d, 0x0007);
3180 rtl_writephy(tp, 0x0e, 0x003c);
3181 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3182 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3183 rtl_writephy(tp, 0x0d, 0x0000);
3184
3185 /* Green feature */
3186 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3187 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3188 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3189 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3190 rtl_writephy(tp, 0x1f, 0x0005);
3191 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3192 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3193
9ecb9aab 3194 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3195 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3196}
3197
5f886e08
HW		 3198static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3199{
3200 /* For 4-corner performance improve */
3201 rtl_writephy(tp, 0x1f, 0x0005);
3202 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3203 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3204 rtl_writephy(tp, 0x1f, 0x0000);
3205
3206 /* PHY auto speed down */
3207 rtl_writephy(tp, 0x1f, 0x0007);
3208 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3209 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3210 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3211 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3212
3213 /* Improve 10M EEE waveform */
3214 rtl_writephy(tp, 0x1f, 0x0005);
3215 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3216 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3217 rtl_writephy(tp, 0x1f, 0x0000);
3218}
3219
c2218925
HW		 3220static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3221{
3222 static const struct phy_reg phy_reg_init[] = {
3223 /* Channel estimation fine tune */
3224 { 0x1f, 0x0003 },
3225 { 0x09, 0xa20f },
3226 { 0x1f, 0x0000 },
3227
3228 /* Modify green table for giga & fnet */
3229 { 0x1f, 0x0005 },
3230 { 0x05, 0x8b55 },
3231 { 0x06, 0x0000 },
3232 { 0x05, 0x8b5e },
3233 { 0x06, 0x0000 },
3234 { 0x05, 0x8b67 },
3235 { 0x06, 0x0000 },
3236 { 0x05, 0x8b70 },
3237 { 0x06, 0x0000 },
3238 { 0x1f, 0x0000 },
3239 { 0x1f, 0x0007 },
3240 { 0x1e, 0x0078 },
3241 { 0x17, 0x0000 },
3242 { 0x19, 0x00fb },
3243 { 0x1f, 0x0000 },
3244
3245 /* Modify green table for 10M */
3246 { 0x1f, 0x0005 },
3247 { 0x05, 0x8b79 },
3248 { 0x06, 0xaa00 },
3249 { 0x1f, 0x0000 },
3250
3251 /* Disable hiimpedance detection (RTCT) */
3252 { 0x1f, 0x0003 },
3253 { 0x01, 0x328a },
3254 { 0x1f, 0x0000 }
3255 };
3256
3257 rtl_apply_firmware(tp);
3258
3259 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3260
5f886e08 3261 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3262
3263 /* Improve 2-pair detection performance */
3264 rtl_writephy(tp, 0x1f, 0x0005);
3265 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3266 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3267 rtl_writephy(tp, 0x1f, 0x0000);
3268}
3269
3270static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3271{
3272 rtl_apply_firmware(tp);
3273
5f886e08 3274 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3275}
3276
b3d7b2f2
HW		 3277static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3278{
b3d7b2f2
HW		 3279 static const struct phy_reg phy_reg_init[] = {
3280 /* Channel estimation fine tune */
3281 { 0x1f, 0x0003 },
3282 { 0x09, 0xa20f },
3283 { 0x1f, 0x0000 },
3284
3285 /* Modify green table for giga & fnet */
3286 { 0x1f, 0x0005 },
3287 { 0x05, 0x8b55 },
3288 { 0x06, 0x0000 },
3289 { 0x05, 0x8b5e },
3290 { 0x06, 0x0000 },
3291 { 0x05, 0x8b67 },
3292 { 0x06, 0x0000 },
3293 { 0x05, 0x8b70 },
3294 { 0x06, 0x0000 },
3295 { 0x1f, 0x0000 },
3296 { 0x1f, 0x0007 },
3297 { 0x1e, 0x0078 },
3298 { 0x17, 0x0000 },
3299 { 0x19, 0x00aa },
3300 { 0x1f, 0x0000 },
3301
3302 /* Modify green table for 10M */
3303 { 0x1f, 0x0005 },
3304 { 0x05, 0x8b79 },
3305 { 0x06, 0xaa00 },
3306 { 0x1f, 0x0000 },
3307
3308 /* Disable hiimpedance detection (RTCT) */
3309 { 0x1f, 0x0003 },
3310 { 0x01, 0x328a },
3311 { 0x1f, 0x0000 }
3312 };
3313
3314
3315 rtl_apply_firmware(tp);
3316
3317 rtl8168f_hw_phy_config(tp);
3318
3319 /* Improve 2-pair detection performance */
3320 rtl_writephy(tp, 0x1f, 0x0005);
3321 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3322 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3323 rtl_writephy(tp, 0x1f, 0x0000);
3324
3325 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3326
3327 /* Modify green table for giga */
3328 rtl_writephy(tp, 0x1f, 0x0005);
3329 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3330 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3331 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3332 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3333 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3334 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3335 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3336 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3337 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3338 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3339 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3340 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3341 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3342 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3343 rtl_writephy(tp, 0x1f, 0x0000);
3344
3345 /* uc same-seed solution */
3346 rtl_writephy(tp, 0x1f, 0x0005);
3347 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3348 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3349 rtl_writephy(tp, 0x1f, 0x0000);
3350
3351 /* eee setting */
706123d0 3352 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3353 rtl_writephy(tp, 0x1f, 0x0005);
3354 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3355 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3356 rtl_writephy(tp, 0x1f, 0x0004);
3357 rtl_writephy(tp, 0x1f, 0x0007);
3358 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3359 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3360 rtl_writephy(tp, 0x1f, 0x0000);
3361 rtl_writephy(tp, 0x0d, 0x0007);
3362 rtl_writephy(tp, 0x0e, 0x003c);
3363 rtl_writephy(tp, 0x0d, 0x4007);
3364 rtl_writephy(tp, 0x0e, 0x0000);
3365 rtl_writephy(tp, 0x0d, 0x0000);
3366
3367 /* Green feature */
3368 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3369 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3370 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3371 rtl_writephy(tp, 0x1f, 0x0000);
3372}
3373
c558386b
HW		 3374static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3375{
c558386b
HW		 3376 rtl_apply_firmware(tp);
3377
41f44d13 3378 rtl_writephy(tp, 0x1f, 0x0a46);
3379 if (rtl_readphy(tp, 0x10) & 0x0100) {
3380 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3381 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3382 } else {
3383 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3384 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3385 }
c558386b 3386
41f44d13 3387 rtl_writephy(tp, 0x1f, 0x0a46);
3388 if (rtl_readphy(tp, 0x13) & 0x0100) {
3389 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3390 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3391 } else {
fe7524c0 3392 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3393 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3394 }
c558386b 3395
41f44d13 3396 /* Enable PHY auto speed down */
3397 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3398 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3399
fe7524c0 3400 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3401 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3402 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3403 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3404 rtl_writephy(tp, 0x1f, 0x0a43);
3405 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3406 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3407 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3408
41f44d13 3409 /* EEE auto-fallback function */
3410 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3411 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3412
41f44d13 3413 /* Enable UC LPF tune function */
3414 rtl_writephy(tp, 0x1f, 0x0a43);
3415 rtl_writephy(tp, 0x13, 0x8012);
76564428 3416 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3417
3418 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3419 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3420
fe7524c0 3421 /* Improve SWR Efficiency */
3422 rtl_writephy(tp, 0x1f, 0x0bcd);
3423 rtl_writephy(tp, 0x14, 0x5065);
3424 rtl_writephy(tp, 0x14, 0xd065);
3425 rtl_writephy(tp, 0x1f, 0x0bc8);
3426 rtl_writephy(tp, 0x11, 0x5655);
3427 rtl_writephy(tp, 0x1f, 0x0bcd);
3428 rtl_writephy(tp, 0x14, 0x1065);
3429 rtl_writephy(tp, 0x14, 0x9065);
3430 rtl_writephy(tp, 0x14, 0x1065);
3431
1bac1072
DC		 3432 /* Check ALDPS bit, disable it if enabled */
3433 rtl_writephy(tp, 0x1f, 0x0a43);
3434 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3435 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3436
41f44d13 3437 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3438}
3439
57538c4a 3440static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3441{
3442 rtl_apply_firmware(tp);
3443}
3444
6e1d0b89
CHL		 3445static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3446{
3447 u16 dout_tapbin;
3448 u32 data;
3449
3450 rtl_apply_firmware(tp);
3451
3452 /* CHN EST parameters adjust - giga master */
3453 rtl_writephy(tp, 0x1f, 0x0a43);
3454 rtl_writephy(tp, 0x13, 0x809b);
76564428 3455 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3456 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3457 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3458 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3459 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3460 rtl_writephy(tp, 0x13, 0x809c);
76564428 3461 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3462 rtl_writephy(tp, 0x1f, 0x0000);
3463
3464 /* CHN EST parameters adjust - giga slave */
3465 rtl_writephy(tp, 0x1f, 0x0a43);
3466 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3467 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3468 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3469 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3470 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3471 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3472 rtl_writephy(tp, 0x1f, 0x0000);
3473
3474 /* CHN EST parameters adjust - fnet */
3475 rtl_writephy(tp, 0x1f, 0x0a43);
3476 rtl_writephy(tp, 0x13, 0x808e);
76564428 3477 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3478 rtl_writephy(tp, 0x13, 0x8090);
76564428 3479 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3480 rtl_writephy(tp, 0x13, 0x8092);
76564428 3481 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3482 rtl_writephy(tp, 0x1f, 0x0000);
3483
3484 /* enable R-tune & PGA-retune function */
3485 dout_tapbin = 0;
3486 rtl_writephy(tp, 0x1f, 0x0a46);
3487 data = rtl_readphy(tp, 0x13);
3488 data &= 3;
3489 data <<= 2;
3490 dout_tapbin |= data;
3491 data = rtl_readphy(tp, 0x12);
3492 data &= 0xc000;
3493 data >>= 14;
3494 dout_tapbin |= data;
3495 dout_tapbin = ~(dout_tapbin^0x08);
3496 dout_tapbin <<= 12;
3497 dout_tapbin &= 0xf000;
3498 rtl_writephy(tp, 0x1f, 0x0a43);
3499 rtl_writephy(tp, 0x13, 0x827a);
76564428 3500 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3501 rtl_writephy(tp, 0x13, 0x827b);
76564428 3502 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3503 rtl_writephy(tp, 0x13, 0x827c);
76564428 3504 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3505 rtl_writephy(tp, 0x13, 0x827d);
76564428 3506 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3507
3508 rtl_writephy(tp, 0x1f, 0x0a43);
3509 rtl_writephy(tp, 0x13, 0x0811);
76564428 3510 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3511 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3512 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3513 rtl_writephy(tp, 0x1f, 0x0000);
3514
3515 /* enable GPHY 10M */
3516 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3517 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3518 rtl_writephy(tp, 0x1f, 0x0000);
3519
3520 /* SAR ADC performance */
3521 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3522 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3523 rtl_writephy(tp, 0x1f, 0x0000);
3524
3525 rtl_writephy(tp, 0x1f, 0x0a43);
3526 rtl_writephy(tp, 0x13, 0x803f);
76564428 3527 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3528 rtl_writephy(tp, 0x13, 0x8047);
76564428 3529 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3530 rtl_writephy(tp, 0x13, 0x804f);
76564428 3531 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3532 rtl_writephy(tp, 0x13, 0x8057);
76564428 3533 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3534 rtl_writephy(tp, 0x13, 0x805f);
76564428 3535 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3536 rtl_writephy(tp, 0x13, 0x8067);
76564428 3537 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3538 rtl_writephy(tp, 0x13, 0x806f);
76564428 3539 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3540 rtl_writephy(tp, 0x1f, 0x0000);
3541
3542 /* disable phy pfm mode */
3543 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3544 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3545 rtl_writephy(tp, 0x1f, 0x0000);
3546
3547 /* Check ALDPS bit, disable it if enabled */
3548 rtl_writephy(tp, 0x1f, 0x0a43);
3549 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3550 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3551
3552 rtl_writephy(tp, 0x1f, 0x0000);
3553}
3554
3555static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3556{
3557 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3558 u16 rlen;
3559 u32 data;
3560
3561 rtl_apply_firmware(tp);
3562
3563 /* CHIN EST parameter update */
3564 rtl_writephy(tp, 0x1f, 0x0a43);
3565 rtl_writephy(tp, 0x13, 0x808a);
76564428 3566 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3567 rtl_writephy(tp, 0x1f, 0x0000);
3568
3569 /* enable R-tune & PGA-retune function */
3570 rtl_writephy(tp, 0x1f, 0x0a43);
3571 rtl_writephy(tp, 0x13, 0x0811);
76564428 3572 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3573 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3574 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3575 rtl_writephy(tp, 0x1f, 0x0000);
3576
3577 /* enable GPHY 10M */
3578 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3579 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3580 rtl_writephy(tp, 0x1f, 0x0000);
3581
3582 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3583 data = r8168_mac_ocp_read(tp, 0xdd02);
3584 ioffset_p3 = ((data & 0x80)>>7);
3585 ioffset_p3 <<= 3;
3586
3587 data = r8168_mac_ocp_read(tp, 0xdd00);
3588 ioffset_p3 |= ((data & (0xe000))>>13);
3589 ioffset_p2 = ((data & (0x1e00))>>9);
3590 ioffset_p1 = ((data & (0x01e0))>>5);
3591 ioffset_p0 = ((data & 0x0010)>>4);
3592 ioffset_p0 <<= 3;
3593 ioffset_p0 |= (data & (0x07));
3594 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3595
05b9687b 3596 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3597 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3598 rtl_writephy(tp, 0x1f, 0x0bcf);
3599 rtl_writephy(tp, 0x16, data);
3600 rtl_writephy(tp, 0x1f, 0x0000);
3601 }
3602
3603 /* Modify rlen (TX LPF corner frequency) level */
3604 rtl_writephy(tp, 0x1f, 0x0bcd);
3605 data = rtl_readphy(tp, 0x16);
3606 data &= 0x000f;
3607 rlen = 0;
3608 if (data > 3)
3609 rlen = data - 3;
3610 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3611 rtl_writephy(tp, 0x17, data);
3612 rtl_writephy(tp, 0x1f, 0x0bcd);
3613 rtl_writephy(tp, 0x1f, 0x0000);
3614
3615 /* disable phy pfm mode */
3616 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3617 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3618 rtl_writephy(tp, 0x1f, 0x0000);
3619
3620 /* Check ALDPS bit, disable it if enabled */
3621 rtl_writephy(tp, 0x1f, 0x0a43);
3622 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3623 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3624
3625 rtl_writephy(tp, 0x1f, 0x0000);
3626}
3627
935e2218
CHL		 3628static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3629{
3630 /* Enable PHY auto speed down */
3631 rtl_writephy(tp, 0x1f, 0x0a44);
3632 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3633 rtl_writephy(tp, 0x1f, 0x0000);
3634
3635 /* patch 10M & ALDPS */
3636 rtl_writephy(tp, 0x1f, 0x0bcc);
3637 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3638 rtl_writephy(tp, 0x1f, 0x0a44);
3639 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3640 rtl_writephy(tp, 0x1f, 0x0a43);
3641 rtl_writephy(tp, 0x13, 0x8084);
3642 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3643 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3644 rtl_writephy(tp, 0x1f, 0x0000);
3645
3646 /* Enable EEE auto-fallback function */
3647 rtl_writephy(tp, 0x1f, 0x0a4b);
3648 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3649 rtl_writephy(tp, 0x1f, 0x0000);
3650
3651 /* Enable UC LPF tune function */
3652 rtl_writephy(tp, 0x1f, 0x0a43);
3653 rtl_writephy(tp, 0x13, 0x8012);
3654 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3655 rtl_writephy(tp, 0x1f, 0x0000);
3656
3657 /* set rg_sel_sdm_rate */
3658 rtl_writephy(tp, 0x1f, 0x0c42);
3659 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3660 rtl_writephy(tp, 0x1f, 0x0000);
3661
3662 /* Check ALDPS bit, disable it if enabled */
3663 rtl_writephy(tp, 0x1f, 0x0a43);
3664 if (rtl_readphy(tp, 0x10) & 0x0004)
3665 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3666
3667 rtl_writephy(tp, 0x1f, 0x0000);
3668}
3669
3670static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3671{
3672 /* patch 10M & ALDPS */
3673 rtl_writephy(tp, 0x1f, 0x0bcc);
3674 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3675 rtl_writephy(tp, 0x1f, 0x0a44);
3676 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3677 rtl_writephy(tp, 0x1f, 0x0a43);
3678 rtl_writephy(tp, 0x13, 0x8084);
3679 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3680 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3681 rtl_writephy(tp, 0x1f, 0x0000);
3682
3683 /* Enable UC LPF tune function */
3684 rtl_writephy(tp, 0x1f, 0x0a43);
3685 rtl_writephy(tp, 0x13, 0x8012);
3686 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3687 rtl_writephy(tp, 0x1f, 0x0000);
3688
3689 /* Set rg_sel_sdm_rate */
3690 rtl_writephy(tp, 0x1f, 0x0c42);
3691 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3692 rtl_writephy(tp, 0x1f, 0x0000);
3693
3694 /* Channel estimation parameters */
3695 rtl_writephy(tp, 0x1f, 0x0a43);
3696 rtl_writephy(tp, 0x13, 0x80f3);
3697 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3698 rtl_writephy(tp, 0x13, 0x80f0);
3699 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3700 rtl_writephy(tp, 0x13, 0x80ef);
3701 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3702 rtl_writephy(tp, 0x13, 0x80f6);
3703 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3704 rtl_writephy(tp, 0x13, 0x80ec);
3705 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3706 rtl_writephy(tp, 0x13, 0x80ed);
3707 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3708 rtl_writephy(tp, 0x13, 0x80f2);
3709 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3710 rtl_writephy(tp, 0x13, 0x80f4);
3711 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3712 rtl_writephy(tp, 0x1f, 0x0a43);
3713 rtl_writephy(tp, 0x13, 0x8110);
3714 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3715 rtl_writephy(tp, 0x13, 0x810f);
3716 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3717 rtl_writephy(tp, 0x13, 0x8111);
3718 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3719 rtl_writephy(tp, 0x13, 0x8113);
3720 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3721 rtl_writephy(tp, 0x13, 0x8115);
3722 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3723 rtl_writephy(tp, 0x13, 0x810e);
3724 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3725 rtl_writephy(tp, 0x13, 0x810c);
3726 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3727 rtl_writephy(tp, 0x13, 0x810b);
3728 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3729 rtl_writephy(tp, 0x1f, 0x0a43);
3730 rtl_writephy(tp, 0x13, 0x80d1);
3731 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3732 rtl_writephy(tp, 0x13, 0x80cd);
3733 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3734 rtl_writephy(tp, 0x13, 0x80d3);
3735 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3736 rtl_writephy(tp, 0x13, 0x80d5);
3737 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3738 rtl_writephy(tp, 0x13, 0x80d7);
3739 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3740
3741 /* Force PWM-mode */
3742 rtl_writephy(tp, 0x1f, 0x0bcd);
3743 rtl_writephy(tp, 0x14, 0x5065);
3744 rtl_writephy(tp, 0x14, 0xd065);
3745 rtl_writephy(tp, 0x1f, 0x0bc8);
3746 rtl_writephy(tp, 0x12, 0x00ed);
3747 rtl_writephy(tp, 0x1f, 0x0bcd);
3748 rtl_writephy(tp, 0x14, 0x1065);
3749 rtl_writephy(tp, 0x14, 0x9065);
3750 rtl_writephy(tp, 0x14, 0x1065);
3751 rtl_writephy(tp, 0x1f, 0x0000);
3752
3753 /* Check ALDPS bit, disable it if enabled */
3754 rtl_writephy(tp, 0x1f, 0x0a43);
3755 if (rtl_readphy(tp, 0x10) & 0x0004)
3756 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3757
3758 rtl_writephy(tp, 0x1f, 0x0000);
3759}
3760
4da19633 3761static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3762{
350f7596 3763 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3764 { 0x1f, 0x0003 },
3765 { 0x08, 0x441d },
3766 { 0x01, 0x9100 },
3767 { 0x1f, 0x0000 }
3768 };
3769
4da19633 3770 rtl_writephy(tp, 0x1f, 0x0000);
3771 rtl_patchphy(tp, 0x11, 1 << 12);
3772 rtl_patchphy(tp, 0x19, 1 << 13);
3773 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3774
4da19633 3775 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3776}
3777
5a5e4443
HW		 3778static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3779{
3780 static const struct phy_reg phy_reg_init[] = {
3781 { 0x1f, 0x0005 },
3782 { 0x1a, 0x0000 },
3783 { 0x1f, 0x0000 },
3784
3785 { 0x1f, 0x0004 },
3786 { 0x1c, 0x0000 },
3787 { 0x1f, 0x0000 },
3788
3789 { 0x1f, 0x0001 },
3790 { 0x15, 0x7701 },
3791 { 0x1f, 0x0000 }
3792 };
3793
3794 /* Disable ALDPS before ram code */
eef63cc1
FR		 3795 rtl_writephy(tp, 0x1f, 0x0000);
3796 rtl_writephy(tp, 0x18, 0x0310);
3797 msleep(100);
5a5e4443 3798
953a12cc 3799 rtl_apply_firmware(tp);
5a5e4443
HW		 3800
3801 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3802}
3803
7e18dca1
HW		 3804static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3805{
7e18dca1 3806 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3807 rtl_writephy(tp, 0x1f, 0x0000);
3808 rtl_writephy(tp, 0x18, 0x0310);
3809 msleep(20);
7e18dca1
HW		 3810
3811 rtl_apply_firmware(tp);
3812
3813 /* EEE setting */
fdf6fc06 3814 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3815 rtl_writephy(tp, 0x1f, 0x0004);
3816 rtl_writephy(tp, 0x10, 0x401f);
3817 rtl_writephy(tp, 0x19, 0x7030);
3818 rtl_writephy(tp, 0x1f, 0x0000);
3819}
3820
5598bfe5
HW		 3821static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3822{
5598bfe5
HW		 3823 static const struct phy_reg phy_reg_init[] = {
3824 { 0x1f, 0x0004 },
3825 { 0x10, 0xc07f },
3826 { 0x19, 0x7030 },
3827 { 0x1f, 0x0000 }
3828 };
3829
3830 /* Disable ALDPS before ram code */
eef63cc1
FR		 3831 rtl_writephy(tp, 0x1f, 0x0000);
3832 rtl_writephy(tp, 0x18, 0x0310);
3833 msleep(100);
5598bfe5
HW		 3834
3835 rtl_apply_firmware(tp);
3836
fdf6fc06 3837 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3838 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3839
fdf6fc06 3840 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3841}
3842
5615d9f1
FR		 3843static void rtl_hw_phy_config(struct net_device *dev)
3844{
3845 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1 3846
5615d9f1
FR		 3847 switch (tp->mac_version) {
3848 case RTL_GIGA_MAC_VER_01:
3849 break;
3850 case RTL_GIGA_MAC_VER_02:
3851 case RTL_GIGA_MAC_VER_03:
4da19633 3852 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3853 break;
3854 case RTL_GIGA_MAC_VER_04:
4da19633 3855 rtl8169sb_hw_phy_config(tp);
5615d9f1 3856 break;
2e955856 3857 case RTL_GIGA_MAC_VER_05:
4da19633 3858 rtl8169scd_hw_phy_config(tp);
2e955856 3859 break;
8c7006aa 3860 case RTL_GIGA_MAC_VER_06:
4da19633 3861 rtl8169sce_hw_phy_config(tp);
8c7006aa 3862 break;
2857ffb7
FR		 3863 case RTL_GIGA_MAC_VER_07:
3864 case RTL_GIGA_MAC_VER_08:
3865 case RTL_GIGA_MAC_VER_09:
4da19633 3866 rtl8102e_hw_phy_config(tp);
2857ffb7 3867 break;
236b8082 3868 case RTL_GIGA_MAC_VER_11:
4da19633 3869 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3870 break;
3871 case RTL_GIGA_MAC_VER_12:
4da19633 3872 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3873 break;
3874 case RTL_GIGA_MAC_VER_17:
4da19633 3875 rtl8168bef_hw_phy_config(tp);
236b8082 3876 break;
867763c1 3877 case RTL_GIGA_MAC_VER_18:
4da19633 3878 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3879 break;
3880 case RTL_GIGA_MAC_VER_19:
4da19633 3881 rtl8168c_1_hw_phy_config(tp);
867763c1 3882 break;
7da97ec9 3883 case RTL_GIGA_MAC_VER_20:
4da19633 3884 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3885 break;
197ff761 3886 case RTL_GIGA_MAC_VER_21:
4da19633 3887 rtl8168c_3_hw_phy_config(tp);
197ff761 3888 break;
6fb07058 3889 case RTL_GIGA_MAC_VER_22:
4da19633 3890 rtl8168c_4_hw_phy_config(tp);
6fb07058 3891 break;
ef3386f0 3892 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3893 case RTL_GIGA_MAC_VER_24:
4da19633 3894 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3895 break;
5b538df9 3896 case RTL_GIGA_MAC_VER_25:
bca03d5f 3897 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3898 break;
3899 case RTL_GIGA_MAC_VER_26:
bca03d5f 3900 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3901 break;
3902 case RTL_GIGA_MAC_VER_27:
4da19633 3903 rtl8168d_3_hw_phy_config(tp);
5b538df9 3904 break;
e6de30d6 3905 case RTL_GIGA_MAC_VER_28:
3906 rtl8168d_4_hw_phy_config(tp);
3907 break;
5a5e4443
HW		 3908 case RTL_GIGA_MAC_VER_29:
3909 case RTL_GIGA_MAC_VER_30:
3910 rtl8105e_hw_phy_config(tp);
3911 break;
cecb5fd7
FR		 3912 case RTL_GIGA_MAC_VER_31:
3913 /* None. */
3914 break;
01dc7fec 3915 case RTL_GIGA_MAC_VER_32:
01dc7fec 3916 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3917 rtl8168e_1_hw_phy_config(tp);
3918 break;
3919 case RTL_GIGA_MAC_VER_34:
3920 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3921 break;
c2218925
HW		 3922 case RTL_GIGA_MAC_VER_35:
3923 rtl8168f_1_hw_phy_config(tp);
3924 break;
3925 case RTL_GIGA_MAC_VER_36:
3926 rtl8168f_2_hw_phy_config(tp);
3927 break;
ef3386f0 3928
7e18dca1
HW		 3929 case RTL_GIGA_MAC_VER_37:
3930 rtl8402_hw_phy_config(tp);
3931 break;
3932
b3d7b2f2
HW		 3933 case RTL_GIGA_MAC_VER_38:
3934 rtl8411_hw_phy_config(tp);
3935 break;
3936
5598bfe5
HW		 3937 case RTL_GIGA_MAC_VER_39:
3938 rtl8106e_hw_phy_config(tp);
3939 break;
3940
c558386b
HW		 3941 case RTL_GIGA_MAC_VER_40:
3942 rtl8168g_1_hw_phy_config(tp);
3943 break;
57538c4a 3944 case RTL_GIGA_MAC_VER_42:
58152cd4 3945 case RTL_GIGA_MAC_VER_43:
45dd95c4 3946 case RTL_GIGA_MAC_VER_44:
57538c4a 3947 rtl8168g_2_hw_phy_config(tp);
3948 break;
6e1d0b89
CHL		 3949 case RTL_GIGA_MAC_VER_45:
3950 case RTL_GIGA_MAC_VER_47:
3951 rtl8168h_1_hw_phy_config(tp);
3952 break;
3953 case RTL_GIGA_MAC_VER_46:
3954 case RTL_GIGA_MAC_VER_48:
3955 rtl8168h_2_hw_phy_config(tp);
3956 break;
c558386b 3957
935e2218
CHL		 3958 case RTL_GIGA_MAC_VER_49:
3959 rtl8168ep_1_hw_phy_config(tp);
3960 break;
3961 case RTL_GIGA_MAC_VER_50:
3962 case RTL_GIGA_MAC_VER_51:
3963 rtl8168ep_2_hw_phy_config(tp);
3964 break;
3965
c558386b 3966 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3967 default:
3968 break;
3969 }
3970}
3971
da78dbff
FR		 3972static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3973{
da78dbff
FR		 3974 if (!test_and_set_bit(flag, tp->wk.flags))
3975 schedule_work(&tp->wk.work);
da78dbff
FR		 3976}
3977
2544bfc0
FR		 3978static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3979{
2544bfc0 3980 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
e397286b 3981 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 3982}
3983
4ff96fa6
FR		 3984static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3985{
5615d9f1 3986 rtl_hw_phy_config(dev);
4ff96fa6 3987
77332894 3988 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7a67e11d
HK		 3989 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3990 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
49d17512
HK		 3991 netif_dbg(tp, drv, dev,
3992 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 3993 RTL_W8(tp, 0x82, 0x01);
77332894 3994 }
4ff96fa6 3995
5b7ad4b7
HK		 3996 /* We may have called phy_speed_down before */
3997 phy_speed_up(dev->phydev);
3998
f75222bc 3999 genphy_soft_reset(dev->phydev);
10bc6a60 4000
9003b369 4001 /* It was reported that several chips end up with 10MBit/Half on a
10bc6a60 4002 * 1GBit link after resuming from S3. For whatever reason the PHY on
9003b369 4003 * these chips doesn't properly start a renegotiation when soft-reset.
10bc6a60
HK		 4004 * Explicitly requesting a renegotiation fixes this.
4005 */
9003b369 4006 if (dev->phydev->autoneg == AUTONEG_ENABLE)
10bc6a60 4007 phy_restart_aneg(dev->phydev);
4ff96fa6
FR		 4008}
4009
773d2021
FR		 4010static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4011{
da78dbff 4012 rtl_lock_work(tp);
773d2021 4013
1ef7286e 4014 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4015
1ef7286e
AS		 4016 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4017 RTL_R32(tp, MAC4);
908ba2bf 4018
1ef7286e
AS		 4019 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4020 RTL_R32(tp, MAC0);
908ba2bf 4021
9ecb9aab 4022 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4023 rtl_rar_exgmac_set(tp, addr);
c28aa385 4024
1ef7286e 4025 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4026
da78dbff 4027 rtl_unlock_work(tp);
773d2021
FR		 4028}
4029
4030static int rtl_set_mac_address(struct net_device *dev, void *p)
4031{
4032 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4033 struct device *d = tp_to_dev(tp);
1f7aa2bc 4034 int ret;
773d2021 4035
1f7aa2bc
HK		 4036 ret = eth_mac_addr(dev, p);
4037 if (ret)
4038 return ret;
773d2021 4039
f51d4a10
CHL		 4040 pm_runtime_get_noresume(d);
4041
4042 if (pm_runtime_active(d))
4043 rtl_rar_set(tp, dev->dev_addr);
4044
4045 pm_runtime_put_noidle(d);
773d2021
FR		 4046
4047 return 0;
4048}
4049
e397286b 4050static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 4051{
69b3c59f
HK		 4052 if (!netif_running(dev))
4053 return -ENODEV;
e397286b 4054
69b3c59f 4055 return phy_mii_ioctl(dev->phydev, ifr, cmd);
8b4ab28d
FR		 4056}
4057
baf63293 4058static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4059{
4060 struct mdio_ops *ops = &tp->mdio_ops;
4061
4062 switch (tp->mac_version) {
4063 case RTL_GIGA_MAC_VER_27:
4064 ops->write = r8168dp_1_mdio_write;
4065 ops->read = r8168dp_1_mdio_read;
4066 break;
e6de30d6 4067 case RTL_GIGA_MAC_VER_28:
4804b3b3 4068 case RTL_GIGA_MAC_VER_31:
e6de30d6 4069 ops->write = r8168dp_2_mdio_write;
4070 ops->read = r8168dp_2_mdio_read;
4071 break;
2a71883c 4072 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
c558386b
HW		 4073 ops->write = r8168g_mdio_write;
4074 ops->read = r8168g_mdio_read;
4075 break;
c0e45c1c 4076 default:
4077 ops->write = r8169_mdio_write;
4078 ops->read = r8169_mdio_read;
4079 break;
4080 }
4081}
4082
649b3b8c 4083static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4084{
649b3b8c 4085 switch (tp->mac_version) {
b00e69de
CB		 4086 case RTL_GIGA_MAC_VER_25:
4087 case RTL_GIGA_MAC_VER_26:
649b3b8c 4088 case RTL_GIGA_MAC_VER_29:
4089 case RTL_GIGA_MAC_VER_30:
4090 case RTL_GIGA_MAC_VER_32:
4091 case RTL_GIGA_MAC_VER_33:
4092 case RTL_GIGA_MAC_VER_34:
2a71883c 4093 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4094 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4095 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4096 break;
4097 default:
4098 break;
4099 }
4100}
4101
4102static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4103{
649f0837
HK		 4104 struct phy_device *phydev;
4105
4106 if (!__rtl8169_get_wol(tp))
649b3b8c 4107 return false;
4108
649f0837
HK		 4109 /* phydev may not be attached to netdevice */
4110 phydev = mdiobus_get_phy(tp->mii_bus, 0);
4111
4112 phy_speed_down(phydev, false);
649b3b8c 4113 rtl_wol_suspend_quirk(tp);
4114
4115 return true;
4116}
4117
065c27c1 4118static void r8168_pll_power_down(struct rtl8169_private *tp)
4119{
9dbe7896 4120 if (r8168_check_dash(tp))
065c27c1 4121 return;
4122
01dc7fec 4123 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4124 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4125 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4126
649b3b8c 4127 if (rtl_wol_pll_power_down(tp))
065c27c1 4128 return;
065c27c1 4129
065c27c1 4130 switch (tp->mac_version) {
2a71883c 4131 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4132 case RTL_GIGA_MAC_VER_37:
4133 case RTL_GIGA_MAC_VER_39:
4134 case RTL_GIGA_MAC_VER_43:
42fde737 4135 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4136 case RTL_GIGA_MAC_VER_45:
4137 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4138 case RTL_GIGA_MAC_VER_47:
4139 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4140 case RTL_GIGA_MAC_VER_50:
4141 case RTL_GIGA_MAC_VER_51:
1ef7286e 4142 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4143 break;
beb330a4 4144 case RTL_GIGA_MAC_VER_40:
4145 case RTL_GIGA_MAC_VER_41:
935e2218 4146 case RTL_GIGA_MAC_VER_49:
706123d0 4147 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4148 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4149 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4150 break;
065c27c1 4151 }
4152}
4153
4154static void r8168_pll_power_up(struct rtl8169_private *tp)
4155{
065c27c1 4156 switch (tp->mac_version) {
2a71883c 4157 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4158 case RTL_GIGA_MAC_VER_37:
4159 case RTL_GIGA_MAC_VER_39:
4160 case RTL_GIGA_MAC_VER_43:
1ef7286e 4161 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4162 break;
42fde737 4163 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4164 case RTL_GIGA_MAC_VER_45:
4165 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4166 case RTL_GIGA_MAC_VER_47:
4167 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4168 case RTL_GIGA_MAC_VER_50:
4169 case RTL_GIGA_MAC_VER_51:
1ef7286e 4170 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4171 break;
beb330a4 4172 case RTL_GIGA_MAC_VER_40:
4173 case RTL_GIGA_MAC_VER_41:
935e2218 4174 case RTL_GIGA_MAC_VER_49:
1ef7286e 4175 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4176 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4177 0x00000000, ERIAR_EXGMAC);
4178 break;
065c27c1 4179 }
4180
242cd9b5
HK		 4181 phy_resume(tp->dev->phydev);
4182 /* give MAC/PHY some time to resume */
4183 msleep(20);
065c27c1 4184}
4185
065c27c1 4186static void rtl_pll_power_down(struct rtl8169_private *tp)
4187{
4f447d29
HK		 4188 switch (tp->mac_version) {
4189 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4190 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4191 break;
4192 default:
4193 r8168_pll_power_down(tp);
4194 }
065c27c1 4195}
4196
4197static void rtl_pll_power_up(struct rtl8169_private *tp)
4198{
065c27c1 4199 switch (tp->mac_version) {
4f447d29
HK		 4200 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4201 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
065c27c1 4202 break;
065c27c1 4203 default:
4f447d29 4204 r8168_pll_power_up(tp);
065c27c1 4205 }
4206}
4207
e542a226
HW		 4208static void rtl_init_rxcfg(struct rtl8169_private *tp)
4209{
e542a226 4210 switch (tp->mac_version) {
2a71883c
HK		 4211 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4212 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 4213 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 4214 break;
2a71883c 4215 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
511cfd58
MS		 4216 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4217 case RTL_GIGA_MAC_VER_38:
1ef7286e 4218 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4219 break;
2a71883c 4220 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4221 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4222 break;
e542a226 4223 default:
1ef7286e 4224 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4225 break;
4226 }
4227}
4228
92fc43b4
HW		 4229static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4230{
9fba0812 4231 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4232}
4233
d58d46b5
FR		 4234static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4235{
eda40b8c
HK		 4236 if (tp->jumbo_ops.enable) {
4237 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4238 tp->jumbo_ops.enable(tp);
4239 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4240 }
d58d46b5
FR		 4241}
4242
4243static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4244{
eda40b8c
HK		 4245 if (tp->jumbo_ops.disable) {
4246 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4247 tp->jumbo_ops.disable(tp);
4248 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4249 }
d58d46b5
FR		 4250}
4251
4252static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4253{
1ef7286e
AS		 4254 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4255 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4256 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4257}
4258
4259static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4260{
1ef7286e
AS		 4261 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4262 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4263 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4264}
4265
4266static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4267{
1ef7286e 4268 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4269}
4270
4271static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4272{
1ef7286e 4273 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4274}
4275
4276static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4277{
1ef7286e
AS		 4278 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4279 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4280 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4281 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4282}
4283
4284static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4285{
1ef7286e
AS		 4286 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4287 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4288 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4289 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4290}
4291
4292static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4293{
cb73200c 4294 rtl_tx_performance_tweak(tp,
f65d539c 4295 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4296}
4297
4298static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4299{
cb73200c 4300 rtl_tx_performance_tweak(tp,
8d98aa39 4301 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4302}
4303
4304static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4305{
d58d46b5
FR		 4306 r8168b_0_hw_jumbo_enable(tp);
4307
1ef7286e 4308 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4309}
4310
4311static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4312{
d58d46b5
FR		 4313 r8168b_0_hw_jumbo_disable(tp);
4314
1ef7286e 4315 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4316}
4317
baf63293 4318static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4319{
4320 struct jumbo_ops *ops = &tp->jumbo_ops;
4321
4322 switch (tp->mac_version) {
4323 case RTL_GIGA_MAC_VER_11:
4324 ops->disable = r8168b_0_hw_jumbo_disable;
4325 ops->enable = r8168b_0_hw_jumbo_enable;
4326 break;
4327 case RTL_GIGA_MAC_VER_12:
4328 case RTL_GIGA_MAC_VER_17:
4329 ops->disable = r8168b_1_hw_jumbo_disable;
4330 ops->enable = r8168b_1_hw_jumbo_enable;
4331 break;
4332 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4333 case RTL_GIGA_MAC_VER_19:
4334 case RTL_GIGA_MAC_VER_20:
4335 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4336 case RTL_GIGA_MAC_VER_22:
4337 case RTL_GIGA_MAC_VER_23:
4338 case RTL_GIGA_MAC_VER_24:
4339 case RTL_GIGA_MAC_VER_25:
4340 case RTL_GIGA_MAC_VER_26:
4341 ops->disable = r8168c_hw_jumbo_disable;
4342 ops->enable = r8168c_hw_jumbo_enable;
4343 break;
4344 case RTL_GIGA_MAC_VER_27:
4345 case RTL_GIGA_MAC_VER_28:
4346 ops->disable = r8168dp_hw_jumbo_disable;
4347 ops->enable = r8168dp_hw_jumbo_enable;
4348 break;
4349 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4350 case RTL_GIGA_MAC_VER_32:
4351 case RTL_GIGA_MAC_VER_33:
4352 case RTL_GIGA_MAC_VER_34:
4353 ops->disable = r8168e_hw_jumbo_disable;
4354 ops->enable = r8168e_hw_jumbo_enable;
4355 break;
4356
4357 /*
4358 * No action needed for jumbo frames with 8169.
4359 * No jumbo for 810x at all.
4360 */
2a71883c 4361 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 4362 default:
4363 ops->disable = NULL;
4364 ops->enable = NULL;
4365 break;
4366 }
4367}
4368
ffc46952
FR		 4369DECLARE_RTL_COND(rtl_chipcmd_cond)
4370{
1ef7286e 4371 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4372}
4373
6f43adc8
FR		 4374static void rtl_hw_reset(struct rtl8169_private *tp)
4375{
1ef7286e 4376 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4377
ffc46952 4378 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4379}
4380
b6ffd97f 4381static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4382{
b6ffd97f
FR		 4383 struct rtl_fw *rtl_fw;
4384 const char *name;
4385 int rc = -ENOMEM;
953a12cc 4386
b6ffd97f
FR		 4387 name = rtl_lookup_firmware_name(tp);
4388 if (!name)
4389 goto out_no_firmware;
953a12cc 4390
b6ffd97f
FR		 4391 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4392 if (!rtl_fw)
4393 goto err_warn;
31bd204f 4394
1e1205b7 4395 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 4396 if (rc < 0)
4397 goto err_free;
4398
fd112f2e
FR		 4399 rc = rtl_check_firmware(tp, rtl_fw);
4400 if (rc < 0)
4401 goto err_release_firmware;
4402
b6ffd97f
FR		 4403 tp->rtl_fw = rtl_fw;
4404out:
4405 return;
4406
fd112f2e
FR		 4407err_release_firmware:
4408 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4409err_free:
4410 kfree(rtl_fw);
4411err_warn:
4412 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4413 name, rc);
4414out_no_firmware:
4415 tp->rtl_fw = NULL;
4416 goto out;
4417}
4418
4419static void rtl_request_firmware(struct rtl8169_private *tp)
4420{
4421 if (IS_ERR(tp->rtl_fw))
4422 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4423}
4424
92fc43b4
HW		 4425static void rtl_rx_close(struct rtl8169_private *tp)
4426{
1ef7286e 4427 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4428}
4429
ffc46952
FR		 4430DECLARE_RTL_COND(rtl_npq_cond)
4431{
1ef7286e 4432 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4433}
4434
4435DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4436{
1ef7286e 4437 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4438}
4439
e6de30d6 4440static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 4441{
4442 /* Disable interrupts */
811fd301 4443 rtl8169_irq_mask_and_ack(tp);
1da177e4 4444
92fc43b4
HW		 4445 rtl_rx_close(tp);
4446
b2d43e6e
HK		 4447 switch (tp->mac_version) {
4448 case RTL_GIGA_MAC_VER_27:
4449 case RTL_GIGA_MAC_VER_28:
4450 case RTL_GIGA_MAC_VER_31:
ffc46952 4451 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 4452 break;
4453 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4454 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4455 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 4456 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 4457 break;
4458 default:
1ef7286e 4459 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 4460 udelay(100);
b2d43e6e 4461 break;
e6de30d6 4462 }
4463
92fc43b4 4464 rtl_hw_reset(tp);
1da177e4
LT		 4465}
4466
05212ba8 4467static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 4468{
ad5f97fa
HK		 4469 u32 val = TX_DMA_BURST << TxDMAShift |
4470 InterFrameGap << TxInterFrameGapShift;
4471
4472 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4473 tp->mac_version != RTL_GIGA_MAC_VER_39)
4474 val |= TXCFG_AUTO_FIFO;
4475
4476 RTL_W32(tp, TxConfig, val);
9cb427b6
FR		 4477}
4478
4fd48c4a 4479static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4480{
4fd48c4a
HK		 4481 /* Low hurts. Let's disable the filtering. */
4482 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4483}
4484
1ef7286e 4485static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4486{
4487 /*
4488 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4489 * register to be written before TxDescAddrLow to work.
4490 * Switching from MMIO to I/O access fixes the issue as well.
4491 */
1ef7286e
AS		 4492 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4493 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4494 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4495 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4496}
4497
1ef7286e 4498static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4499{
34bc0095
HK		 4500 u32 val;
4501
4502 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4503 val = 0x000fff00;
4504 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4505 val = 0x00ffff00;
4506 else
4507 return;
4508
4509 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4510 val |= 0xff;
4511
4512 RTL_W32(tp, 0x7c, val);
6dccd16b
FR		 4513}
4514
e6b763ea
FR		 4515static void rtl_set_rx_mode(struct net_device *dev)
4516{
4517 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 4518 u32 mc_filter[2]; /* Multicast hash filter */
4519 int rx_mode;
4520 u32 tmp = 0;
4521
4522 if (dev->flags & IFF_PROMISC) {
4523 /* Unconditionally log net taps. */
4524 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4525 rx_mode =
4526 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4527 AcceptAllPhys;
4528 mc_filter[1] = mc_filter[0] = 0xffffffff;
4529 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4530 (dev->flags & IFF_ALLMULTI)) {
4531 /* Too many to filter perfectly -- accept all multicasts. */
4532 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4533 mc_filter[1] = mc_filter[0] = 0xffffffff;
4534 } else {
4535 struct netdev_hw_addr *ha;
4536
4537 rx_mode = AcceptBroadcast | AcceptMyPhys;
4538 mc_filter[1] = mc_filter[0] = 0;
4539 netdev_for_each_mc_addr(ha, dev) {
4540 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4541 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4542 rx_mode |= AcceptMulticast;
4543 }
4544 }
4545
4546 if (dev->features & NETIF_F_RXALL)
4547 rx_mode |= (AcceptErr | AcceptRunt);
4548
1ef7286e 4549 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 4550
4551 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4552 u32 data = mc_filter[0];
4553
4554 mc_filter[0] = swab32(mc_filter[1]);
4555 mc_filter[1] = swab32(data);
4556 }
4557
0481776b
NW		 4558 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4559 mc_filter[1] = mc_filter[0] = 0xffffffff;
4560
1ef7286e
AS		 4561 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4562 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4563
1ef7286e 4564 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 4565}
4566
52f8560e
HK		 4567static void rtl_hw_start(struct rtl8169_private *tp)
4568{
4569 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4570
4571 tp->hw_start(tp);
4572
4573 rtl_set_rx_max_size(tp);
4574 rtl_set_rx_tx_desc_registers(tp);
52f8560e
HK		 4575 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4576
4577 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4578 RTL_R8(tp, IntrMask);
4579 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
05212ba8 4580 rtl_init_rxcfg(tp);
f74dd480 4581 rtl_set_tx_config_registers(tp);
05212ba8 4582
52f8560e
HK		 4583 rtl_set_rx_mode(tp->dev);
4584 /* no early-rx interrupts */
4585 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
fe716f8a 4586 rtl_irq_enable(tp);
52f8560e
HK		 4587}
4588
61cb532d 4589static void rtl_hw_start_8169(struct rtl8169_private *tp)
07ce4064 4590{
0ae0974e 4591 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
61cb532d 4592 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
9cb427b6 4593
1ef7286e 4594 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 4595
0ae0974e 4596 tp->cp_cmd |= PCIMulRW;
1da177e4 4597
cecb5fd7
FR		 4598 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4599 tp->mac_version == RTL_GIGA_MAC_VER_03) {
49d17512
HK		 4600 netif_dbg(tp, drv, tp->dev,
4601 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
bcf0bf90 4602 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4603 }
4604
1ef7286e 4605 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 4606
1ef7286e 4607 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 4608
1da177e4
LT		 4609 /*
4610 * Undocumented corner. Supposedly:
4611 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4612 */
1ef7286e 4613 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 4614
1ef7286e 4615 RTL_W32(tp, RxMissed, 0);
07ce4064 4616}
1da177e4 4617
ffc46952
FR		 4618DECLARE_RTL_COND(rtl_csiar_cond)
4619{
1ef7286e 4620 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4621}
4622
ff1d7331 4623static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4624{
ff1d7331 4625 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4626
1ef7286e
AS		 4627 RTL_W32(tp, CSIDR, value);
4628 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4629 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4630
ffc46952 4631 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4632}
4633
ff1d7331 4634static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4635{
ff1d7331
HK		 4636 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4637
4638 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4639 CSIAR_BYTE_ENABLE);
7e18dca1 4640
ffc46952 4641 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4642 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4643}
4644
ff1d7331 4645static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4646{
ff1d7331
HK		 4647 struct pci_dev *pdev = tp->pci_dev;
4648 u32 csi;
45dd95c4 4649
ff1d7331
HK		 4650 /* According to Realtek the value at config space address 0x070f
4651 * controls the L0s/L1 entrance latency. We try standard ECAM access
4652 * first and if it fails fall back to CSI.
4653 */
4654 if (pdev->cfg_size > 0x070f &&
4655 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4656 return;
4657
4658 netdev_notice_once(tp->dev,
4659 "No native access to PCI extended config space, falling back to CSI\n");
4660 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4661 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4662}
4663
f37658da 4664static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 4665{
ff1d7331 4666 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 4667}
4668
4669struct ephy_info {
4670 unsigned int offset;
4671 u16 mask;
4672 u16 bits;
4673};
4674
fdf6fc06
FR		 4675static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4676 int len)
dacf8154
FR		 4677{
4678 u16 w;
4679
4680 while (len-- > 0) {
fdf6fc06
FR		 4681 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4682 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4683 e++;
4684 }
4685}
4686
73c86ee3 4687static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 4688{
73c86ee3 4689 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4690 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4691}
4692
73c86ee3 4693static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 4694{
73c86ee3 4695 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4696 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4697}
4698
b51ecea8 4699static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4700{
b51ecea8 4701 u8 data;
4702
1ef7286e 4703 data = RTL_R8(tp, Config3);
b51ecea8 4704
4705 if (enable)
4706 data |= Rdy_to_L23;
4707 else
4708 data &= ~Rdy_to_L23;
4709
1ef7286e 4710 RTL_W8(tp, Config3, data);
b51ecea8 4711}
4712
a99790bf
KHF		 4713static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4714{
4715 if (enable) {
a99790bf 4716 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
94235460 4717 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
a99790bf
KHF		 4718 } else {
4719 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4720 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4721 }
94235460
KHF		 4722
4723 udelay(10);
a99790bf
KHF		 4724}
4725
beb1fe18 4726static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4727{
1ef7286e 4728 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4729
12d42c50 4730 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4731 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
b726e493 4732
faf1e785 4733 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 4734 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 4735 PCI_EXP_DEVCTL_NOSNOOP_EN);
4736 }
219a1e9d
FR		 4737}
4738
beb1fe18 4739static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4740{
beb1fe18 4741 rtl_hw_start_8168bb(tp);
b726e493 4742
1ef7286e 4743 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 4744
1ef7286e 4745 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 4746}
4747
beb1fe18 4748static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4749{
1ef7286e 4750 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 4751
1ef7286e 4752 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4753
faf1e785 4754 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4755 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 4756
73c86ee3 4757 rtl_disable_clock_request(tp);
b726e493 4758
12d42c50 4759 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4760 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
219a1e9d
FR		 4761}
4762
beb1fe18 4763static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4764{
350f7596 4765 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4766 { 0x01, 0, 0x0001 },
4767 { 0x02, 0x0800, 0x1000 },
4768 { 0x03, 0, 0x0042 },
4769 { 0x06, 0x0080, 0x0000 },
4770 { 0x07, 0, 0x2000 }
4771 };
4772
f37658da 4773 rtl_set_def_aspm_entry_latency(tp);
b726e493 4774
fdf6fc06 4775 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4776
beb1fe18 4777 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4778}
4779
beb1fe18 4780static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4781{
f37658da 4782 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 4783
1ef7286e 4784 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 4785
faf1e785 4786 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4787 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 4788
12d42c50 4789 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4790 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
ef3386f0
FR		 4791}
4792
beb1fe18 4793static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4794{
f37658da 4795 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 4796
1ef7286e 4797 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 4798
4799 /* Magic. */
1ef7286e 4800 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 4801
1ef7286e 4802 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4803
faf1e785 4804 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4805 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 4806
12d42c50 4807 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4808 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7f3e3d3a
FR		 4809}
4810
beb1fe18 4811static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4812{
350f7596 4813 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4814 { 0x02, 0x0800, 0x1000 },
4815 { 0x03, 0, 0x0002 },
4816 { 0x06, 0x0080, 0x0000 }
4817 };
4818
f37658da 4819 rtl_set_def_aspm_entry_latency(tp);
b726e493 4820
1ef7286e 4821 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 4822
fdf6fc06 4823 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4824
beb1fe18 4825 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4826}
4827
beb1fe18 4828static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4829{
350f7596 4830 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4831 { 0x01, 0, 0x0001 },
4832 { 0x03, 0x0400, 0x0220 }
4833 };
4834
f37658da 4835 rtl_set_def_aspm_entry_latency(tp);
b726e493 4836
fdf6fc06 4837 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4838
beb1fe18 4839 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4840}
4841
beb1fe18 4842static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4843{
beb1fe18 4844 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4845}
4846
beb1fe18 4847static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4848{
f37658da 4849 rtl_set_def_aspm_entry_latency(tp);
6fb07058 4850
beb1fe18 4851 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4852}
4853
beb1fe18 4854static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4855{
f37658da 4856 rtl_set_def_aspm_entry_latency(tp);
5b538df9 4857
73c86ee3 4858 rtl_disable_clock_request(tp);
5b538df9 4859
1ef7286e 4860 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 4861
faf1e785 4862 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4863 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 4864
12d42c50 4865 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4866 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5b538df9
FR		 4867}
4868
beb1fe18 4869static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4870{
f37658da 4871 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 4872
faf1e785 4873 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4874 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 4875
1ef7286e 4876 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 4877
73c86ee3 4878 rtl_disable_clock_request(tp);
4804b3b3 4879}
4880
beb1fe18 4881static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4882{
4883 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 4884 { 0x0b, 0x0000, 0x0048 },
4885 { 0x19, 0x0020, 0x0050 },
4886 { 0x0c, 0x0100, 0x0020 }
e6de30d6 4887 };
e6de30d6 4888
f37658da 4889 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 4890
8d98aa39 4891 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 4892
1ef7286e 4893 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 4894
1016a4a1 4895 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 4896
73c86ee3 4897 rtl_enable_clock_request(tp);
e6de30d6 4898}
4899
beb1fe18 4900static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4901{
70090424 4902 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4903 { 0x00, 0x0200, 0x0100 },
4904 { 0x00, 0x0000, 0x0004 },
4905 { 0x06, 0x0002, 0x0001 },
4906 { 0x06, 0x0000, 0x0030 },
4907 { 0x07, 0x0000, 0x2000 },
4908 { 0x00, 0x0000, 0x0020 },
4909 { 0x03, 0x5800, 0x2000 },
4910 { 0x03, 0x0000, 0x0001 },
4911 { 0x01, 0x0800, 0x1000 },
4912 { 0x07, 0x0000, 0x4000 },
4913 { 0x1e, 0x0000, 0x2000 },
4914 { 0x19, 0xffff, 0xfe6c },
4915 { 0x0a, 0x0000, 0x0040 }
4916 };
4917
f37658da 4918 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 4919
fdf6fc06 4920 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4921
faf1e785 4922 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4923 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 4924
1ef7286e 4925 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 4926
73c86ee3 4927 rtl_disable_clock_request(tp);
01dc7fec 4928
4929 /* Reset tx FIFO pointer */
1ef7286e
AS		 4930 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4931 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 4932
1ef7286e 4933 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 4934}
4935
beb1fe18 4936static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 4937{
4938 static const struct ephy_info e_info_8168e_2[] = {
4939 { 0x09, 0x0000, 0x0080 },
4940 { 0x19, 0x0000, 0x0224 }
4941 };
4942
f37658da 4943 rtl_set_def_aspm_entry_latency(tp);
70090424 4944
fdf6fc06 4945 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 4946
faf1e785 4947 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4948 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 4949
fdf6fc06
FR		 4950 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4951 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4952 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4953 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4954 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4955 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 4956 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4957 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 4958
1ef7286e 4959 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 4960
73c86ee3 4961 rtl_disable_clock_request(tp);
4521e1a9 4962
1ef7286e 4963 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 4964
4965 /* Adjust EEE LED frequency */
1ef7286e 4966 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 4967
1ef7286e
AS		 4968 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4969 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4970 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 4971
4972 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 4973}
4974
5f886e08 4975static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 4976{
f37658da 4977 rtl_set_def_aspm_entry_latency(tp);
c2218925 4978
8d98aa39 4979 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 4980
fdf6fc06
FR		 4981 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4982 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4983 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4984 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 4985 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4986 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4987 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4988 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 4989 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4990 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 4991
1ef7286e 4992 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 4993
73c86ee3 4994 rtl_disable_clock_request(tp);
4521e1a9 4995
1ef7286e
AS		 4996 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4997 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4998 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4999 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 5000}
5001
5f886e08
HW		 5002static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5003{
5f886e08
HW		 5004 static const struct ephy_info e_info_8168f_1[] = {
5005 { 0x06, 0x00c0, 0x0020 },
5006 { 0x08, 0x0001, 0x0002 },
5007 { 0x09, 0x0000, 0x0080 },
5008 { 0x19, 0x0000, 0x0224 }
5009 };
5010
5011 rtl_hw_start_8168f(tp);
5012
fdf6fc06 5013 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5014
706123d0 5015 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5016
5017 /* Adjust EEE LED frequency */
1ef7286e 5018 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 5019}
5020
b3d7b2f2
HW		 5021static void rtl_hw_start_8411(struct rtl8169_private *tp)
5022{
b3d7b2f2
HW		 5023 static const struct ephy_info e_info_8168f_1[] = {
5024 { 0x06, 0x00c0, 0x0020 },
5025 { 0x0f, 0xffff, 0x5200 },
5026 { 0x1e, 0x0000, 0x4000 },
5027 { 0x19, 0x0000, 0x0224 }
5028 };
5029
5030 rtl_hw_start_8168f(tp);
b51ecea8 5031 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5032
fdf6fc06 5033 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5034
706123d0 5035 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5036}
5037
5fbea337 5038static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 5039{
c558386b
HW		 5040 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5041 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5042 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5043 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5044
f37658da 5045 rtl_set_def_aspm_entry_latency(tp);
c558386b 5046
8d98aa39 5047 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 5048
706123d0
CHL		 5049 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5050 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5051 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5052
1ef7286e
AS		 5053 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5054 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 5055
5056 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5057 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5058
5059 /* Adjust EEE LED frequency */
1ef7286e 5060 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 5061
706123d0
CHL		 5062 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5063 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5064
5065 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5066}
5067
5fbea337
CHL		 5068static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5069{
5fbea337
CHL		 5070 static const struct ephy_info e_info_8168g_1[] = {
5071 { 0x00, 0x0000, 0x0008 },
5072 { 0x0c, 0x37d0, 0x0820 },
5073 { 0x1e, 0x0000, 0x0001 },
5074 { 0x19, 0x8000, 0x0000 }
5075 };
5076
5077 rtl_hw_start_8168g(tp);
5078
5079 /* disable aspm and clock request before access ephy */
a99790bf 5080 rtl_hw_aspm_clkreq_enable(tp, false);
5fbea337 5081 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
a99790bf 5082 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 5083}
5084
57538c4a 5085static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5086{
57538c4a 5087 static const struct ephy_info e_info_8168g_2[] = {
5088 { 0x00, 0x0000, 0x0008 },
5089 { 0x0c, 0x3df0, 0x0200 },
5090 { 0x19, 0xffff, 0xfc00 },
5091 { 0x1e, 0xffff, 0x20eb }
5092 };
5093
5fbea337 5094 rtl_hw_start_8168g(tp);
57538c4a 5095
5096 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 5097 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5098 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 5099 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5100}
5101
45dd95c4 5102static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5103{
45dd95c4 5104 static const struct ephy_info e_info_8411_2[] = {
5105 { 0x00, 0x0000, 0x0008 },
5106 { 0x0c, 0x3df0, 0x0200 },
5107 { 0x0f, 0xffff, 0x5200 },
5108 { 0x19, 0x0020, 0x0000 },
5109 { 0x1e, 0x0000, 0x2000 }
5110 };
5111
5fbea337 5112 rtl_hw_start_8168g(tp);
45dd95c4 5113
5114 /* disable aspm and clock request before access ephy */
a99790bf 5115 rtl_hw_aspm_clkreq_enable(tp, false);
45dd95c4 5116 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
a99790bf 5117 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 5118}
5119
6e1d0b89
CHL		 5120static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5121{
72521ea0 5122 int rg_saw_cnt;
6e1d0b89
CHL		 5123 u32 data;
5124 static const struct ephy_info e_info_8168h_1[] = {
5125 { 0x1e, 0x0800, 0x0001 },
5126 { 0x1d, 0x0000, 0x0800 },
5127 { 0x05, 0xffff, 0x2089 },
5128 { 0x06, 0xffff, 0x5881 },
5129 { 0x04, 0xffff, 0x154a },
5130 { 0x01, 0xffff, 0x068b }
5131 };
5132
5133 /* disable aspm and clock request before access ephy */
a99790bf 5134 rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b89
CHL		 5135 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5136
6e1d0b89
CHL		 5137 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5138 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5139 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5140 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5141
f37658da 5142 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 5143
8d98aa39 5144 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 5145
706123d0
CHL		 5146 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5147 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5148
706123d0 5149 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5150
706123d0 5151 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5152
5153 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5154
1ef7286e
AS		 5155 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5156 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 5157
5158 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5159 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5160
5161 /* Adjust EEE LED frequency */
1ef7286e 5162 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 5163
1ef7286e
AS		 5164 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5165 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 5166
1ef7286e 5167 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 5168
706123d0 5169 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5170
5171 rtl_pcie_state_l2l3_enable(tp, false);
5172
5173 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 5174 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 5175 rtl_writephy(tp, 0x1f, 0x0000);
5176 if (rg_saw_cnt > 0) {
5177 u16 sw_cnt_1ms_ini;
5178
5179 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5180 sw_cnt_1ms_ini &= 0x0fff;
5181 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 5182 data &= ~0x0fff;
6e1d0b89
CHL		 5183 data |= sw_cnt_1ms_ini;
5184 r8168_mac_ocp_write(tp, 0xd412, data);
5185 }
5186
5187 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 5188 data &= ~0xf0;
5189 data |= 0x70;
6e1d0b89
CHL		 5190 r8168_mac_ocp_write(tp, 0xe056, data);
5191
5192 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 5193 data &= ~0x6000;
5194 data |= 0x8008;
6e1d0b89
CHL		 5195 r8168_mac_ocp_write(tp, 0xe052, data);
5196
5197 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 5198 data &= ~0x01ff;
6e1d0b89
CHL		 5199 data |= 0x017f;
5200 r8168_mac_ocp_write(tp, 0xe0d6, data);
5201
5202 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 5203 data &= ~0x0fff;
6e1d0b89
CHL		 5204 data |= 0x047f;
5205 r8168_mac_ocp_write(tp, 0xd420, data);
5206
5207 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5208 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5209 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5210 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 5211
5212 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 5213}
5214
935e2218
CHL		 5215static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5216{
003609da
CHL		 5217 rtl8168ep_stop_cmac(tp);
5218
935e2218
CHL		 5219 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5220 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5221 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5222 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5223
f37658da 5224 rtl_set_def_aspm_entry_latency(tp);
935e2218 5225
8d98aa39 5226 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 5227
5228 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5229 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5230
5231 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5232
5233 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5234
1ef7286e
AS		 5235 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5236 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 5237
5238 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5239 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5240
5241 /* Adjust EEE LED frequency */
1ef7286e 5242 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 5243
5244 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5245
1ef7286e 5246 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 5247
5248 rtl_pcie_state_l2l3_enable(tp, false);
5249}
5250
5251static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5252{
935e2218
CHL		 5253 static const struct ephy_info e_info_8168ep_1[] = {
5254 { 0x00, 0xffff, 0x10ab },
5255 { 0x06, 0xffff, 0xf030 },
5256 { 0x08, 0xffff, 0x2006 },
5257 { 0x0d, 0xffff, 0x1666 },
5258 { 0x0c, 0x3ff0, 0x0000 }
5259 };
5260
5261 /* disable aspm and clock request before access ephy */
a99790bf 5262 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5263 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5264
5265 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5266
5267 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5268}
5269
5270static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5271{
935e2218
CHL		 5272 static const struct ephy_info e_info_8168ep_2[] = {
5273 { 0x00, 0xffff, 0x10a3 },
5274 { 0x19, 0xffff, 0xfc00 },
5275 { 0x1e, 0xffff, 0x20ea }
5276 };
5277
5278 /* disable aspm and clock request before access ephy */
a99790bf 5279 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5280 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5281
5282 rtl_hw_start_8168ep(tp);
5283
1ef7286e
AS		 5284 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5285 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5286
5287 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5288}
5289
5290static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5291{
935e2218
CHL		 5292 u32 data;
5293 static const struct ephy_info e_info_8168ep_3[] = {
5294 { 0x00, 0xffff, 0x10a3 },
5295 { 0x19, 0xffff, 0x7c00 },
5296 { 0x1e, 0xffff, 0x20eb },
5297 { 0x0d, 0xffff, 0x1666 }
5298 };
5299
5300 /* disable aspm and clock request before access ephy */
a99790bf 5301 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5302 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5303
5304 rtl_hw_start_8168ep(tp);
5305
1ef7286e
AS		 5306 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5307 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 5308
5309 data = r8168_mac_ocp_read(tp, 0xd3e2);
5310 data &= 0xf000;
5311 data |= 0x0271;
5312 r8168_mac_ocp_write(tp, 0xd3e2, data);
5313
5314 data = r8168_mac_ocp_read(tp, 0xd3e4);
5315 data &= 0xff00;
5316 r8168_mac_ocp_write(tp, 0xd3e4, data);
5317
5318 data = r8168_mac_ocp_read(tp, 0xe860);
5319 data |= 0x0080;
5320 r8168_mac_ocp_write(tp, 0xe860, data);
a99790bf
KHF		 5321
5322 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5323}
5324
61cb532d 5325static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5326{
1ef7286e 5327 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 5328
0ae0974e
HK		 5329 tp->cp_cmd &= ~INTT_MASK;
5330 tp->cp_cmd |= PktCntrDisable | INTT_1;
1ef7286e 5331 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 5332
1ef7286e 5333 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 5334
0e485150 5335 /* Work around for RxFIFO overflow. */
811fd301 5336 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
559c3c04
HK		 5337 tp->irq_mask |= RxFIFOOver;
5338 tp->irq_mask &= ~RxOverflow;
0e485150
FR		 5339 }
5340
219a1e9d
FR		 5341 switch (tp->mac_version) {
5342 case RTL_GIGA_MAC_VER_11:
beb1fe18 5343 rtl_hw_start_8168bb(tp);
4804b3b3 5344 break;
219a1e9d
FR		 5345
5346 case RTL_GIGA_MAC_VER_12:
5347 case RTL_GIGA_MAC_VER_17:
beb1fe18 5348 rtl_hw_start_8168bef(tp);
4804b3b3 5349 break;
219a1e9d
FR		 5350
5351 case RTL_GIGA_MAC_VER_18:
beb1fe18 5352 rtl_hw_start_8168cp_1(tp);
4804b3b3 5353 break;
219a1e9d
FR		 5354
5355 case RTL_GIGA_MAC_VER_19:
beb1fe18 5356 rtl_hw_start_8168c_1(tp);
4804b3b3 5357 break;
219a1e9d
FR		 5358
5359 case RTL_GIGA_MAC_VER_20:
beb1fe18 5360 rtl_hw_start_8168c_2(tp);
4804b3b3 5361 break;
219a1e9d 5362
197ff761 5363 case RTL_GIGA_MAC_VER_21:
beb1fe18 5364 rtl_hw_start_8168c_3(tp);
4804b3b3 5365 break;
197ff761 5366
6fb07058 5367 case RTL_GIGA_MAC_VER_22:
beb1fe18 5368 rtl_hw_start_8168c_4(tp);
4804b3b3 5369 break;
6fb07058 5370
ef3386f0 5371 case RTL_GIGA_MAC_VER_23:
beb1fe18 5372 rtl_hw_start_8168cp_2(tp);
4804b3b3 5373 break;
ef3386f0 5374
7f3e3d3a 5375 case RTL_GIGA_MAC_VER_24:
beb1fe18 5376 rtl_hw_start_8168cp_3(tp);
4804b3b3 5377 break;
7f3e3d3a 5378
5b538df9 5379 case RTL_GIGA_MAC_VER_25:
daf9df6d 5380 case RTL_GIGA_MAC_VER_26:
5381 case RTL_GIGA_MAC_VER_27:
beb1fe18 5382 rtl_hw_start_8168d(tp);
4804b3b3 5383 break;
5b538df9 5384
e6de30d6 5385 case RTL_GIGA_MAC_VER_28:
beb1fe18 5386 rtl_hw_start_8168d_4(tp);
4804b3b3 5387 break;
cecb5fd7 5388
4804b3b3 5389 case RTL_GIGA_MAC_VER_31:
beb1fe18 5390 rtl_hw_start_8168dp(tp);
4804b3b3 5391 break;
5392
01dc7fec 5393 case RTL_GIGA_MAC_VER_32:
5394 case RTL_GIGA_MAC_VER_33:
beb1fe18 5395 rtl_hw_start_8168e_1(tp);
70090424
HW		 5396 break;
5397 case RTL_GIGA_MAC_VER_34:
beb1fe18 5398 rtl_hw_start_8168e_2(tp);
01dc7fec 5399 break;
e6de30d6 5400
c2218925
HW		 5401 case RTL_GIGA_MAC_VER_35:
5402 case RTL_GIGA_MAC_VER_36:
beb1fe18 5403 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5404 break;
5405
b3d7b2f2
HW		 5406 case RTL_GIGA_MAC_VER_38:
5407 rtl_hw_start_8411(tp);
5408 break;
5409
c558386b
HW		 5410 case RTL_GIGA_MAC_VER_40:
5411 case RTL_GIGA_MAC_VER_41:
5412 rtl_hw_start_8168g_1(tp);
5413 break;
57538c4a 5414 case RTL_GIGA_MAC_VER_42:
5415 rtl_hw_start_8168g_2(tp);
5416 break;
c558386b 5417
45dd95c4 5418 case RTL_GIGA_MAC_VER_44:
5419 rtl_hw_start_8411_2(tp);
5420 break;
5421
6e1d0b89
CHL		 5422 case RTL_GIGA_MAC_VER_45:
5423 case RTL_GIGA_MAC_VER_46:
5424 rtl_hw_start_8168h_1(tp);
5425 break;
5426
935e2218
CHL		 5427 case RTL_GIGA_MAC_VER_49:
5428 rtl_hw_start_8168ep_1(tp);
5429 break;
5430
5431 case RTL_GIGA_MAC_VER_50:
5432 rtl_hw_start_8168ep_2(tp);
5433 break;
5434
5435 case RTL_GIGA_MAC_VER_51:
5436 rtl_hw_start_8168ep_3(tp);
5437 break;
5438
219a1e9d 5439 default:
49d17512
HK		 5440 netif_err(tp, drv, tp->dev,
5441 "unknown chipset (mac_version = %d)\n",
5442 tp->mac_version);
4804b3b3 5443 break;
219a1e9d 5444 }
07ce4064 5445}
1da177e4 5446
beb1fe18 5447static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5448{
350f7596 5449 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5450 { 0x01, 0, 0x6e65 },
5451 { 0x02, 0, 0x091f },
5452 { 0x03, 0, 0xc2f9 },
5453 { 0x06, 0, 0xafb5 },
5454 { 0x07, 0, 0x0e00 },
5455 { 0x19, 0, 0xec80 },
5456 { 0x01, 0, 0x2e65 },
5457 { 0x01, 0, 0x6e65 }
5458 };
5459 u8 cfg1;
5460
f37658da 5461 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5462
1ef7286e 5463 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 5464
8d98aa39 5465 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5466
1ef7286e 5467 RTL_W8(tp, Config1,
2857ffb7 5468 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 5469 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 5470
1ef7286e 5471 cfg1 = RTL_R8(tp, Config1);
2857ffb7 5472 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 5473 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 5474
fdf6fc06 5475 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5476}
5477
beb1fe18 5478static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5479{
f37658da 5480 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5481
8d98aa39 5482 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5483
1ef7286e
AS		 5484 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5485 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 5486}
5487
beb1fe18 5488static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5489{
beb1fe18 5490 rtl_hw_start_8102e_2(tp);
2857ffb7 5491
fdf6fc06 5492 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5493}
5494
beb1fe18 5495static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 5496{
5497 static const struct ephy_info e_info_8105e_1[] = {
5498 { 0x07, 0, 0x4000 },
5499 { 0x19, 0, 0x0200 },
5500 { 0x19, 0, 0x0020 },
5501 { 0x1e, 0, 0x2000 },
5502 { 0x03, 0, 0x0001 },
5503 { 0x19, 0, 0x0100 },
5504 { 0x19, 0, 0x0004 },
5505 { 0x0a, 0, 0x0020 }
5506 };
5507
cecb5fd7 5508 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5509 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 5510
cecb5fd7 5511 /* Disable Early Tally Counter */
1ef7286e 5512 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 5513
1ef7286e
AS		 5514 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5515 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 5516
fdf6fc06 5517 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5518
5519 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5520}
5521
beb1fe18 5522static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5523{
beb1fe18 5524 rtl_hw_start_8105e_1(tp);
fdf6fc06 5525 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5526}
5527
7e18dca1
HW		 5528static void rtl_hw_start_8402(struct rtl8169_private *tp)
5529{
7e18dca1
HW		 5530 static const struct ephy_info e_info_8402[] = {
5531 { 0x19, 0xffff, 0xff64 },
5532 { 0x1e, 0, 0x4000 }
5533 };
5534
f37658da 5535 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 5536
5537 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5538 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 5539
1ef7286e 5540 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 5541
fdf6fc06 5542 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 5543
8d98aa39 5544 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 5545
fdf6fc06
FR		 5546 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5547 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 5548 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5549 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5550 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5551 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 5552 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 5553
5554 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 5555}
5556
5598bfe5
HW		 5557static void rtl_hw_start_8106(struct rtl8169_private *tp)
5558{
0866cd15
KHF		 5559 rtl_hw_aspm_clkreq_enable(tp, false);
5560
5598bfe5 5561 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5562 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5563
1ef7286e
AS		 5564 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5565 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5566 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5567
5568 rtl_pcie_state_l2l3_enable(tp, false);
0866cd15 5569 rtl_hw_aspm_clkreq_enable(tp, true);
5598bfe5
HW		 5570}
5571
61cb532d 5572static void rtl_hw_start_8101(struct rtl8169_private *tp)
07ce4064 5573{
da78dbff 5574 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
559c3c04 5575 tp->irq_mask &= ~RxFIFOOver;
811fd301 5576
cecb5fd7 5577 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5578 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 5579 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 5580 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5581
1ef7286e 5582 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5583
12d42c50 5584 tp->cp_cmd &= CPCMD_QUIRK_MASK;
1ef7286e 5585 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 5586
2857ffb7
FR		 5587 switch (tp->mac_version) {
5588 case RTL_GIGA_MAC_VER_07:
beb1fe18 5589 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5590 break;
5591
5592 case RTL_GIGA_MAC_VER_08:
beb1fe18 5593 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5594 break;
5595
5596 case RTL_GIGA_MAC_VER_09:
beb1fe18 5597 rtl_hw_start_8102e_2(tp);
2857ffb7 5598 break;
5a5e4443
HW		 5599
5600 case RTL_GIGA_MAC_VER_29:
beb1fe18 5601 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5602 break;
5603 case RTL_GIGA_MAC_VER_30:
beb1fe18 5604 rtl_hw_start_8105e_2(tp);
5a5e4443 5605 break;
7e18dca1
HW		 5606
5607 case RTL_GIGA_MAC_VER_37:
5608 rtl_hw_start_8402(tp);
5609 break;
5598bfe5
HW		 5610
5611 case RTL_GIGA_MAC_VER_39:
5612 rtl_hw_start_8106(tp);
5613 break;
58152cd4 5614 case RTL_GIGA_MAC_VER_43:
5615 rtl_hw_start_8168g_2(tp);
5616 break;
6e1d0b89
CHL		 5617 case RTL_GIGA_MAC_VER_47:
5618 case RTL_GIGA_MAC_VER_48:
5619 rtl_hw_start_8168h_1(tp);
5620 break;
cdf1a608
FR		 5621 }
5622
1ef7286e 5623 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5624}
5625
5626static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5627{
d58d46b5
FR		 5628 struct rtl8169_private *tp = netdev_priv(dev);
5629
d58d46b5
FR		 5630 if (new_mtu > ETH_DATA_LEN)
5631 rtl_hw_jumbo_enable(tp);
5632 else
5633 rtl_hw_jumbo_disable(tp);
5634
1da177e4 5635 dev->mtu = new_mtu;
350fb32a
MM		 5636 netdev_update_features(dev);
5637
323bb685 5638 return 0;
1da177e4
LT		 5639}
5640
5641static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5642{
95e0918d 5643 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5644 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5645}
5646
6f0333b8
ED		 5647static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5648 void **data_buff, struct RxDesc *desc)
1da177e4 5649{
1d0254dd
HK		 5650 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5651 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 5652
6f0333b8
ED		 5653 kfree(*data_buff);
5654 *data_buff = NULL;
1da177e4
LT		 5655 rtl8169_make_unusable_by_asic(desc);
5656}
5657
1d0254dd 5658static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5659{
5660 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5661
a0750138
AD		 5662 /* Force memory writes to complete before releasing descriptor */
5663 dma_wmb();
5664
1d0254dd 5665 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 5666}
5667
6f0333b8
ED		 5668static inline void *rtl8169_align(void *data)
5669{
5670 return (void *)ALIGN((long)data, 16);
5671}
5672
0ecbe1ca
SG		 5673static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5674 struct RxDesc *desc)
1da177e4 5675{
6f0333b8 5676 void *data;
1da177e4 5677 dma_addr_t mapping;
1e1205b7 5678 struct device *d = tp_to_dev(tp);
d3b404c2 5679 int node = dev_to_node(d);
1da177e4 5680
1d0254dd 5681 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 5682 if (!data)
5683 return NULL;
e9f63f30 5684
6f0333b8
ED		 5685 if (rtl8169_align(data) != data) {
5686 kfree(data);
1d0254dd 5687 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 5688 if (!data)
5689 return NULL;
5690 }
3eafe507 5691
1d0254dd 5692 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 5693 DMA_FROM_DEVICE);
d827d86b
SG		 5694 if (unlikely(dma_mapping_error(d, mapping))) {
5695 if (net_ratelimit())
5696 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5697 goto err_out;
d827d86b 5698 }
1da177e4 5699
d731af78
HK		 5700 desc->addr = cpu_to_le64(mapping);
5701 rtl8169_mark_to_asic(desc);
6f0333b8 5702 return data;
3eafe507
SG		 5703
5704err_out:
5705 kfree(data);
5706 return NULL;
1da177e4
LT		 5707}
5708
5709static void rtl8169_rx_clear(struct rtl8169_private *tp)
5710{
07d3f51f 5711 unsigned int i;
1da177e4
LT		 5712
5713 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5714 if (tp->Rx_databuff[i]) {
5715 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5716 tp->RxDescArray + i);
5717 }
5718 }
5719}
5720
0ecbe1ca 5721static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5722{
0ecbe1ca
SG		 5723 desc->opts1 |= cpu_to_le32(RingEnd);
5724}
5b0384f4 5725
0ecbe1ca
SG		 5726static int rtl8169_rx_fill(struct rtl8169_private *tp)
5727{
5728 unsigned int i;
1da177e4 5729
0ecbe1ca
SG		 5730 for (i = 0; i < NUM_RX_DESC; i++) {
5731 void *data;
4ae47c2d 5732
0ecbe1ca 5733 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5734 if (!data) {
5735 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5736 goto err_out;
6f0333b8
ED		 5737 }
5738 tp->Rx_databuff[i] = data;
1da177e4 5739 }
1da177e4 5740
0ecbe1ca
SG		 5741 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5742 return 0;
5743
5744err_out:
5745 rtl8169_rx_clear(tp);
5746 return -ENOMEM;
1da177e4
LT		 5747}
5748
b1127e64 5749static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 5750{
1da177e4
LT		 5751 rtl8169_init_ring_indexes(tp);
5752
b1127e64
HK		 5753 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5754 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 5755
0ecbe1ca 5756 return rtl8169_rx_fill(tp);
1da177e4
LT		 5757}
5758
48addcc9 5759static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5760 struct TxDesc *desc)
5761{
5762 unsigned int len = tx_skb->len;
5763
48addcc9
SG		 5764 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5765
1da177e4
LT		 5766 desc->opts1 = 0x00;
5767 desc->opts2 = 0x00;
5768 desc->addr = 0x00;
5769 tx_skb->len = 0;
5770}
5771
3eafe507
SG		 5772static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5773 unsigned int n)
1da177e4
LT		 5774{
5775 unsigned int i;
5776
3eafe507
SG		 5777 for (i = 0; i < n; i++) {
5778 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5779 struct ring_info *tx_skb = tp->tx_skb + entry;
5780 unsigned int len = tx_skb->len;
5781
5782 if (len) {
5783 struct sk_buff *skb = tx_skb->skb;
5784
1e1205b7 5785 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 5786 tp->TxDescArray + entry);
5787 if (skb) {
7a4b813c 5788 dev_consume_skb_any(skb);
1da177e4
LT		 5789 tx_skb->skb = NULL;
5790 }
1da177e4
LT		 5791 }
5792 }
3eafe507
SG		 5793}
5794
5795static void rtl8169_tx_clear(struct rtl8169_private *tp)
5796{
5797 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4 5798 tp->cur_tx = tp->dirty_tx = 0;
d92060bc 5799 netdev_reset_queue(tp->dev);
1da177e4
LT		 5800}
5801
4422bcd4 5802static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5803{
c4028958 5804 struct net_device *dev = tp->dev;
56de414c 5805 int i;
1da177e4 5806
da78dbff
FR		 5807 napi_disable(&tp->napi);
5808 netif_stop_queue(dev);
16f11500 5809 synchronize_rcu();
1da177e4 5810
c7c2c39b 5811 rtl8169_hw_reset(tp);
5812
56de414c 5813 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 5814 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 5815
1da177e4 5816 rtl8169_tx_clear(tp);
c7c2c39b 5817 rtl8169_init_ring_indexes(tp);
1da177e4 5818
da78dbff 5819 napi_enable(&tp->napi);
61cb532d 5820 rtl_hw_start(tp);
56de414c 5821 netif_wake_queue(dev);
1da177e4
LT		 5822}
5823
5824static void rtl8169_tx_timeout(struct net_device *dev)
5825{
da78dbff
FR		 5826 struct rtl8169_private *tp = netdev_priv(dev);
5827
5828 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5829}
5830
734c1409
HK		 5831static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5832{
5833 u32 status = opts0 | len;
5834
5835 if (entry == NUM_TX_DESC - 1)
5836 status |= RingEnd;
5837
5838 return cpu_to_le32(status);
5839}
5840
1da177e4 5841static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5842 u32 *opts)
1da177e4
LT		 5843{
5844 struct skb_shared_info *info = skb_shinfo(skb);
5845 unsigned int cur_frag, entry;
6e1d0b89 5846 struct TxDesc *uninitialized_var(txd);
1e1205b7 5847 struct device *d = tp_to_dev(tp);
1da177e4
LT		 5848
5849 entry = tp->cur_tx;
5850 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5851 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4 5852 dma_addr_t mapping;
734c1409 5853 u32 len;
1da177e4
LT		 5854 void *addr;
5855
5856 entry = (entry + 1) % NUM_TX_DESC;
5857
5858 txd = tp->TxDescArray + entry;
9e903e08 5859 len = skb_frag_size(frag);
929f6189 5860 addr = skb_frag_address(frag);
48addcc9 5861 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5862 if (unlikely(dma_mapping_error(d, mapping))) {
5863 if (net_ratelimit())
5864 netif_err(tp, drv, tp->dev,
5865 "Failed to map TX fragments DMA!\n");
3eafe507 5866 goto err_out;
d827d86b 5867 }
1da177e4 5868
734c1409 5869 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
2b7b4318 5870 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5871 txd->addr = cpu_to_le64(mapping);
5872
5873 tp->tx_skb[entry].len = len;
5874 }
5875
5876 if (cur_frag) {
5877 tp->tx_skb[entry].skb = skb;
5878 txd->opts1 |= cpu_to_le32(LastFrag);
5879 }
5880
5881 return cur_frag;
3eafe507
SG		 5882
5883err_out:
5884 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5885 return -EIO;
1da177e4
LT		 5886}
5887
b423e9ae 5888static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5889{
5890 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5891}
5892
e974604b 5893static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5894 struct net_device *dev);
5895/* r8169_csum_workaround()
5896 * The hw limites the value the transport offset. When the offset is out of the
5897 * range, calculate the checksum by sw.
5898 */
5899static void r8169_csum_workaround(struct rtl8169_private *tp,
5900 struct sk_buff *skb)
5901{
5902 if (skb_shinfo(skb)->gso_size) {
5903 netdev_features_t features = tp->dev->features;
5904 struct sk_buff *segs, *nskb;
5905
5906 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5907 segs = skb_gso_segment(skb, features);
5908 if (IS_ERR(segs) || !segs)
5909 goto drop;
5910
5911 do {
5912 nskb = segs;
5913 segs = segs->next;
5914 nskb->next = NULL;
5915 rtl8169_start_xmit(nskb, tp->dev);
5916 } while (segs);
5917
eb781397 5918 dev_consume_skb_any(skb);
e974604b 5919 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5920 if (skb_checksum_help(skb) < 0)
5921 goto drop;
5922
5923 rtl8169_start_xmit(skb, tp->dev);
5924 } else {
5925 struct net_device_stats *stats;
5926
5927drop:
5928 stats = &tp->dev->stats;
5929 stats->tx_dropped++;
eb781397 5930 dev_kfree_skb_any(skb);
e974604b 5931 }
5932}
5933
5934/* msdn_giant_send_check()
5935 * According to the document of microsoft, the TCP Pseudo Header excludes the
5936 * packet length for IPv6 TCP large packets.
5937 */
5938static int msdn_giant_send_check(struct sk_buff *skb)
5939{
5940 const struct ipv6hdr *ipv6h;
5941 struct tcphdr *th;
5942 int ret;
5943
5944 ret = skb_cow_head(skb, 0);
5945 if (ret)
5946 return ret;
5947
5948 ipv6h = ipv6_hdr(skb);
5949 th = tcp_hdr(skb);
5950
5951 th->check = 0;
5952 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5953
5954 return ret;
5955}
5956
5888d3fc 5957static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5958 struct sk_buff *skb, u32 *opts)
1da177e4 5959{
350fb32a
MM		 5960 u32 mss = skb_shinfo(skb)->gso_size;
5961
2b7b4318
FR		 5962 if (mss) {
5963 opts[0] |= TD_LSO;
5888d3fc 5964 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5965 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5966 const struct iphdr *ip = ip_hdr(skb);
5967
5968 if (ip->protocol == IPPROTO_TCP)
5969 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5970 else if (ip->protocol == IPPROTO_UDP)
5971 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5972 else
5973 WARN_ON_ONCE(1);
5974 }
5975
5976 return true;
5977}
5978
5979static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5980 struct sk_buff *skb, u32 *opts)
5981{
bdfa4ed6 5982 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 5983 u32 mss = skb_shinfo(skb)->gso_size;
5984
5985 if (mss) {
e974604b 5986 if (transport_offset > GTTCPHO_MAX) {
5987 netif_warn(tp, tx_err, tp->dev,
5988 "Invalid transport offset 0x%x for TSO\n",
5989 transport_offset);
5990 return false;
5991 }
5992
4ff36466 5993 switch (vlan_get_protocol(skb)) {
e974604b 5994 case htons(ETH_P_IP):
5995 opts[0] |= TD1_GTSENV4;
5996 break;
5997
5998 case htons(ETH_P_IPV6):
5999 if (msdn_giant_send_check(skb))
6000 return false;
6001
6002 opts[0] |= TD1_GTSENV6;
6003 break;
6004
6005 default:
6006 WARN_ON_ONCE(1);
6007 break;
6008 }
6009
bdfa4ed6 6010 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6011 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6012 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6013 u8 ip_protocol;
1da177e4 6014
b423e9ae 6015 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6016 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 6017
e974604b 6018 if (transport_offset > TCPHO_MAX) {
6019 netif_warn(tp, tx_err, tp->dev,
6020 "Invalid transport offset 0x%x\n",
6021 transport_offset);
6022 return false;
6023 }
6024
4ff36466 6025 switch (vlan_get_protocol(skb)) {
e974604b 6026 case htons(ETH_P_IP):
6027 opts[1] |= TD1_IPv4_CS;
6028 ip_protocol = ip_hdr(skb)->protocol;
6029 break;
6030
6031 case htons(ETH_P_IPV6):
6032 opts[1] |= TD1_IPv6_CS;
6033 ip_protocol = ipv6_hdr(skb)->nexthdr;
6034 break;
6035
6036 default:
6037 ip_protocol = IPPROTO_RAW;
6038 break;
6039 }
6040
6041 if (ip_protocol == IPPROTO_TCP)
6042 opts[1] |= TD1_TCP_CS;
6043 else if (ip_protocol == IPPROTO_UDP)
6044 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6045 else
6046 WARN_ON_ONCE(1);
e974604b 6047
6048 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6049 } else {
6050 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6051 return !eth_skb_pad(skb);
1da177e4 6052 }
5888d3fc 6053
b423e9ae 6054 return true;
1da177e4
LT		 6055}
6056
76085c9e
HK		 6057static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
6058 unsigned int nr_frags)
6059{
6060 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
6061
6062 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
6063 return slots_avail > nr_frags;
6064}
6065
61357325
SH		 6066static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6067 struct net_device *dev)
1da177e4
LT		 6068{
6069 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6070 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 6071 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 6072 struct device *d = tp_to_dev(tp);
1da177e4 6073 dma_addr_t mapping;
734c1409 6074 u32 opts[2], len;
2e6eedb4 6075 bool stop_queue;
3eafe507 6076 int frags;
5b0384f4 6077
76085c9e 6078 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6079 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6080 goto err_stop_0;
1da177e4
LT		 6081 }
6082
6083 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6084 goto err_stop_0;
6085
b423e9ae 6086 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6087 opts[0] = DescOwn;
6088
e974604b 6089 if (!tp->tso_csum(tp, skb, opts)) {
6090 r8169_csum_workaround(tp, skb);
6091 return NETDEV_TX_OK;
6092 }
b423e9ae 6093
3eafe507 6094 len = skb_headlen(skb);
48addcc9 6095 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6096 if (unlikely(dma_mapping_error(d, mapping))) {
6097 if (net_ratelimit())
6098 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6099 goto err_dma_0;
d827d86b 6100 }
3eafe507
SG		 6101
6102 tp->tx_skb[entry].len = len;
6103 txd->addr = cpu_to_le64(mapping);
1da177e4 6104
2b7b4318 6105 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6106 if (frags < 0)
6107 goto err_dma_1;
6108 else if (frags)
2b7b4318 6109 opts[0] |= FirstFrag;
3eafe507 6110 else {
2b7b4318 6111 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6112 tp->tx_skb[entry].skb = skb;
6113 }
6114
2b7b4318
FR		 6115 txd->opts2 = cpu_to_le32(opts[1]);
6116
5047fb5d
RC		 6117 skb_tx_timestamp(skb);
6118
a0750138
AD		 6119 /* Force memory writes to complete before releasing descriptor */
6120 dma_wmb();
1da177e4 6121
734c1409 6122 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
1da177e4 6123
a0750138 6124 /* Force all memory writes to complete before notifying device */
4c020a96 6125 wmb();
1da177e4 6126
a0750138
AD		 6127 tp->cur_tx += frags + 1;
6128
2e6eedb4
HK		 6129 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
6130 if (unlikely(stop_queue))
6131 netif_stop_queue(dev);
1da177e4 6132
bd7153bd 6133 if (__netdev_sent_queue(dev, skb->len, skb->xmit_more))
2e6eedb4 6134 RTL_W8(tp, TxPoll, NPQ);
da78dbff 6135
2e6eedb4 6136 if (unlikely(stop_queue)) {
ae1f23fb
FR		 6137 /* Sync with rtl_tx:
6138 * - publish queue status and cur_tx ring index (write barrier)
6139 * - refresh dirty_tx ring index (read barrier).
6140 * May the current thread have a pessimistic view of the ring
6141 * status and forget to wake up queue, a racing rtl_tx thread
6142 * can't.
6143 */
1e874e04 6144 smp_mb();
76085c9e 6145 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6146 netif_wake_queue(dev);
6147 }
6148
61357325 6149 return NETDEV_TX_OK;
1da177e4 6150
3eafe507 6151err_dma_1:
48addcc9 6152 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6153err_dma_0:
989c9ba1 6154 dev_kfree_skb_any(skb);
3eafe507
SG		 6155 dev->stats.tx_dropped++;
6156 return NETDEV_TX_OK;
6157
6158err_stop_0:
1da177e4 6159 netif_stop_queue(dev);
cebf8cc7 6160 dev->stats.tx_dropped++;
61357325 6161 return NETDEV_TX_BUSY;
1da177e4
LT		 6162}
6163
6164static void rtl8169_pcierr_interrupt(struct net_device *dev)
6165{
6166 struct rtl8169_private *tp = netdev_priv(dev);
6167 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6168 u16 pci_status, pci_cmd;
6169
6170 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6171 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6172
bf82c189
JP		 6173 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6174 pci_cmd, pci_status);
1da177e4
LT		 6175
6176 /*
6177 * The recovery sequence below admits a very elaborated explanation:
6178 * - it seems to work;
d03902b8
FR		 6179 * - I did not see what else could be done;
6180 * - it makes iop3xx happy.
1da177e4
LT		 6181 *
6182 * Feel free to adjust to your needs.
6183 */
a27993f3 6184 if (pdev->broken_parity_status)
d03902b8
FR		 6185 pci_cmd &= ~PCI_COMMAND_PARITY;
6186 else
6187 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6188
6189 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6190
6191 pci_write_config_word(pdev, PCI_STATUS,
6192 pci_status & (PCI_STATUS_DETECTED_PARITY |
6193 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6194 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6195
6196 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6197 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 6198 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 6199 tp->cp_cmd &= ~PCIDAC;
1ef7286e 6200 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 6201 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6202 }
6203
e6de30d6 6204 rtl8169_hw_reset(tp);
d03902b8 6205
98ddf986 6206 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6207}
6208
5317d5c6
HK		 6209static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6210 int budget)
1da177e4 6211{
d92060bc 6212 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
1da177e4 6213
1da177e4
LT		 6214 dirty_tx = tp->dirty_tx;
6215 smp_rmb();
6216 tx_left = tp->cur_tx - dirty_tx;
6217
6218 while (tx_left > 0) {
6219 unsigned int entry = dirty_tx % NUM_TX_DESC;
6220 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6221 u32 status;
6222
1da177e4
LT		 6223 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6224 if (status & DescOwn)
6225 break;
6226
a0750138
AD		 6227 /* This barrier is needed to keep us from reading
6228 * any other fields out of the Tx descriptor until
6229 * we know the status of DescOwn
6230 */
6231 dma_rmb();
6232
1e1205b7 6233 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6234 tp->TxDescArray + entry);
1da177e4 6235 if (status & LastFrag) {
d92060bc
FW		 6236 pkts_compl++;
6237 bytes_compl += tx_skb->skb->len;
5317d5c6 6238 napi_consume_skb(tx_skb->skb, budget);
1da177e4
LT		 6239 tx_skb->skb = NULL;
6240 }
6241 dirty_tx++;
6242 tx_left--;
6243 }
6244
6245 if (tp->dirty_tx != dirty_tx) {
d92060bc
FW		 6246 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6247
6248 u64_stats_update_begin(&tp->tx_stats.syncp);
6249 tp->tx_stats.packets += pkts_compl;
6250 tp->tx_stats.bytes += bytes_compl;
6251 u64_stats_update_end(&tp->tx_stats.syncp);
6252
1da177e4 6253 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6254 /* Sync with rtl8169_start_xmit:
6255 * - publish dirty_tx ring index (write barrier)
6256 * - refresh cur_tx ring index and queue status (read barrier)
6257 * May the current thread miss the stopped queue condition,
6258 * a racing xmit thread can only have a right view of the
6259 * ring status.
6260 */
1e874e04 6261 smp_mb();
1da177e4 6262 if (netif_queue_stopped(dev) &&
76085c9e 6263 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6264 netif_wake_queue(dev);
6265 }
d78ae2dc
FR		 6266 /*
6267 * 8168 hack: TxPoll requests are lost when the Tx packets are
6268 * too close. Let's kick an extra TxPoll request when a burst
6269 * of start_xmit activity is detected (if it is not detected,
6270 * it is slow enough). -- FR
6271 */
1ef7286e
AS		 6272 if (tp->cur_tx != dirty_tx)
6273 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 6274 }
6275}
6276
126fa4b9
FR		 6277static inline int rtl8169_fragmented_frame(u32 status)
6278{
6279 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6280}
6281
adea1ac7 6282static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6283{
1da177e4
LT		 6284 u32 status = opts1 & RxProtoMask;
6285
6286 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6287 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6288 skb->ip_summed = CHECKSUM_UNNECESSARY;
6289 else
bc8acf2c 6290 skb_checksum_none_assert(skb);
1da177e4
LT		 6291}
6292
6f0333b8
ED		 6293static struct sk_buff *rtl8169_try_rx_copy(void *data,
6294 struct rtl8169_private *tp,
6295 int pkt_size,
6296 dma_addr_t addr)
1da177e4 6297{
b449655f 6298 struct sk_buff *skb;
1e1205b7 6299 struct device *d = tp_to_dev(tp);
b449655f 6300
6f0333b8 6301 data = rtl8169_align(data);
48addcc9 6302 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 6303 prefetch(data);
e2338f86 6304 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 6305 if (skb)
8a67aa86 6306 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 6307 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6308
6f0333b8 6309 return skb;
1da177e4
LT		 6310}
6311
da78dbff 6312static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6313{
6314 unsigned int cur_rx, rx_left;
6f0333b8 6315 unsigned int count;
1da177e4 6316
1da177e4 6317 cur_rx = tp->cur_rx;
1da177e4 6318
9fba0812 6319 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6320 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6321 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6322 u32 status;
6323
6202806e 6324 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6325 if (status & DescOwn)
6326 break;
a0750138
AD		 6327
6328 /* This barrier is needed to keep us from reading
6329 * any other fields out of the Rx descriptor until
6330 * we know the status of DescOwn
6331 */
6332 dma_rmb();
6333
4dcb7d33 6334 if (unlikely(status & RxRES)) {
bf82c189
JP		 6335 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6336 status);
cebf8cc7 6337 dev->stats.rx_errors++;
1da177e4 6338 if (status & (RxRWT | RxRUNT))
cebf8cc7 6339 dev->stats.rx_length_errors++;
1da177e4 6340 if (status & RxCRC)
cebf8cc7 6341 dev->stats.rx_crc_errors++;
6202806e
HK		 6342 /* RxFOVF is a reserved bit on later chip versions */
6343 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6344 status & RxFOVF) {
da78dbff 6345 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6346 dev->stats.rx_fifo_errors++;
6202806e
HK		 6347 } else if (status & (RxRUNT | RxCRC) &&
6348 !(status & RxRWT) &&
6349 dev->features & NETIF_F_RXALL) {
6bbe021d 6350 goto process_pkt;
6202806e 6351 }
1da177e4 6352 } else {
6f0333b8 6353 struct sk_buff *skb;
6bbe021d
BG		 6354 dma_addr_t addr;
6355 int pkt_size;
6356
6357process_pkt:
6358 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6359 if (likely(!(dev->features & NETIF_F_RXFCS)))
6360 pkt_size = (status & 0x00003fff) - 4;
6361 else
6362 pkt_size = status & 0x00003fff;
1da177e4 6363
126fa4b9
FR		 6364 /*
6365 * The driver does not support incoming fragmented
6366 * frames. They are seen as a symptom of over-mtu
6367 * sized frames.
6368 */
6369 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6370 dev->stats.rx_dropped++;
6371 dev->stats.rx_length_errors++;
ce11ff5e 6372 goto release_descriptor;
126fa4b9
FR		 6373 }
6374
6f0333b8
ED		 6375 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6376 tp, pkt_size, addr);
6f0333b8
ED		 6377 if (!skb) {
6378 dev->stats.rx_dropped++;
ce11ff5e 6379 goto release_descriptor;
1da177e4
LT		 6380 }
6381
adea1ac7 6382 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6383 skb_put(skb, pkt_size);
6384 skb->protocol = eth_type_trans(skb, dev);
6385
7a8fc77b
FR		 6386 rtl8169_rx_vlan_tag(desc, skb);
6387
39174291 6388 if (skb->pkt_type == PACKET_MULTICAST)
6389 dev->stats.multicast++;
6390
56de414c 6391 napi_gro_receive(&tp->napi, skb);
1da177e4 6392
8027aa24
JW		 6393 u64_stats_update_begin(&tp->rx_stats.syncp);
6394 tp->rx_stats.packets++;
6395 tp->rx_stats.bytes += pkt_size;
6396 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6397 }
ce11ff5e 6398release_descriptor:
6399 desc->opts2 = 0;
1d0254dd 6400 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6401 }
6402
6403 count = cur_rx - tp->cur_rx;
6404 tp->cur_rx = cur_rx;
6405
1da177e4
LT		 6406 return count;
6407}
6408
07d3f51f 6409static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6410{
ebcd5daa 6411 struct rtl8169_private *tp = dev_instance;
05bbe558 6412 u16 status = rtl_get_events(tp);
e782410e 6413 u16 irq_mask = RTL_R16(tp, IntrMask);
1da177e4 6414
e782410e 6415 if (status == 0xffff || !(status & irq_mask))
05bbe558 6416 return IRQ_NONE;
1da177e4 6417
38caff5a
HK		 6418 if (unlikely(status & SYSErr)) {
6419 rtl8169_pcierr_interrupt(tp->dev);
6420 goto out;
6421 }
da78dbff 6422
ee28b30c 6423 if (status & LinkChg && tp->dev->phydev)
38caff5a 6424 phy_mac_interrupt(tp->dev->phydev);
1da177e4 6425
38caff5a
HK		 6426 if (unlikely(status & RxFIFOOver &&
6427 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6428 netif_stop_queue(tp->dev);
6429 /* XXX - Hack alert. See rtl_task(). */
6430 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6431 }
1da177e4 6432
38caff5a
HK		 6433 if (status & RTL_EVENT_NAPI) {
6434 rtl_irq_disable(tp);
6435 napi_schedule_irqoff(&tp->napi);
6436 }
6437out:
6438 rtl_ack_events(tp, status);
1da177e4 6439
38caff5a 6440 return IRQ_HANDLED;
1da177e4
LT		 6441}
6442
4422bcd4
FR		 6443static void rtl_task(struct work_struct *work)
6444{
da78dbff
FR		 6445 static const struct {
6446 int bitnr;
6447 void (*action)(struct rtl8169_private *);
6448 } rtl_work[] = {
da78dbff 6449 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6450 };
4422bcd4
FR		 6451 struct rtl8169_private *tp =
6452 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6453 struct net_device *dev = tp->dev;
6454 int i;
6455
6456 rtl_lock_work(tp);
6457
6c4a70c5
FR		 6458 if (!netif_running(dev) ||
6459 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6460 goto out_unlock;
6461
6462 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6463 bool pending;
6464
da78dbff 6465 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6466 if (pending)
6467 rtl_work[i].action(tp);
6468 }
4422bcd4 6469
da78dbff
FR		 6470out_unlock:
6471 rtl_unlock_work(tp);
4422bcd4
FR		 6472}
6473
bea3348e 6474static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6475{
bea3348e
SH		 6476 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6477 struct net_device *dev = tp->dev;
6b839b6c 6478 int work_done;
da78dbff 6479
6b839b6c 6480 work_done = rtl_rx(dev, tp, (u32) budget);
da78dbff 6481
5317d5c6 6482 rtl_tx(dev, tp, budget);
1da177e4 6483
bea3348e 6484 if (work_done < budget) {
6ad20165 6485 napi_complete_done(napi, work_done);
fe716f8a 6486 rtl_irq_enable(tp);
1da177e4
LT		 6487 }
6488
bea3348e 6489 return work_done;
1da177e4 6490}
1da177e4 6491
1ef7286e 6492static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6493{
6494 struct rtl8169_private *tp = netdev_priv(dev);
6495
6496 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6497 return;
6498
1ef7286e
AS		 6499 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6500 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6501}
6502
f1e911d5
HK		 6503static void r8169_phylink_handler(struct net_device *ndev)
6504{
6505 struct rtl8169_private *tp = netdev_priv(ndev);
6506
6507 if (netif_carrier_ok(ndev)) {
6508 rtl_link_chg_patch(tp);
6509 pm_request_resume(&tp->pci_dev->dev);
6510 } else {
6511 pm_runtime_idle(&tp->pci_dev->dev);
6512 }
6513
6514 if (net_ratelimit())
6515 phy_print_status(ndev->phydev);
6516}
6517
6518static int r8169_phy_connect(struct rtl8169_private *tp)
6519{
6520 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6521 phy_interface_t phy_mode;
6522 int ret;
6523
f7ffa9ae 6524 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 6525 PHY_INTERFACE_MODE_MII;
6526
6527 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6528 phy_mode);
6529 if (ret)
6530 return ret;
6531
f7ffa9ae 6532 if (!tp->supports_gmii)
f1e911d5
HK		 6533 phy_set_max_speed(phydev, SPEED_100);
6534
6535 /* Ensure to advertise everything, incl. pause */
3c1bcc86 6536 linkmode_copy(phydev->advertising, phydev->supported);
f1e911d5
HK		 6537
6538 phy_attached_info(phydev);
6539
6540 return 0;
6541}
6542
1da177e4
LT		 6543static void rtl8169_down(struct net_device *dev)
6544{
6545 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6546
f1e911d5
HK		 6547 phy_stop(dev->phydev);
6548
93dd79e8 6549 napi_disable(&tp->napi);
da78dbff 6550 netif_stop_queue(dev);
1da177e4 6551
92fc43b4 6552 rtl8169_hw_reset(tp);
323bb685
SG		 6553 /*
6554 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6555 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6556 * and napi is disabled (rtl8169_poll).
323bb685 6557 */
1ef7286e 6558 rtl8169_rx_missed(dev);
1da177e4 6559
1da177e4 6560 /* Give a racing hard_start_xmit a few cycles to complete. */
16f11500 6561 synchronize_rcu();
1da177e4 6562
1da177e4
LT		 6563 rtl8169_tx_clear(tp);
6564
6565 rtl8169_rx_clear(tp);
065c27c1 6566
6567 rtl_pll_power_down(tp);
1da177e4
LT		 6568}
6569
6570static int rtl8169_close(struct net_device *dev)
6571{
6572 struct rtl8169_private *tp = netdev_priv(dev);
6573 struct pci_dev *pdev = tp->pci_dev;
6574
e1759441
RW		 6575 pm_runtime_get_sync(&pdev->dev);
6576
cecb5fd7 6577 /* Update counters before going down */
e71c9ce2 6578 rtl8169_update_counters(tp);
355423d0 6579
da78dbff 6580 rtl_lock_work(tp);
6ad56901
KHF		 6581 /* Clear all task flags */
6582 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
da78dbff 6583
1da177e4 6584 rtl8169_down(dev);
da78dbff 6585 rtl_unlock_work(tp);
1da177e4 6586
4ea72445
L		 6587 cancel_work_sync(&tp->wk.work);
6588
f1e911d5
HK		 6589 phy_disconnect(dev->phydev);
6590
ebcd5daa 6591 pci_free_irq(pdev, 0, tp);
1da177e4 6592
82553bb6
SG		 6593 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6594 tp->RxPhyAddr);
6595 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6596 tp->TxPhyAddr);
1da177e4
LT		 6597 tp->TxDescArray = NULL;
6598 tp->RxDescArray = NULL;
6599
e1759441
RW		 6600 pm_runtime_put_sync(&pdev->dev);
6601
1da177e4
LT		 6602 return 0;
6603}
6604
dc1c00ce
FR		 6605#ifdef CONFIG_NET_POLL_CONTROLLER
6606static void rtl8169_netpoll(struct net_device *dev)
6607{
6608 struct rtl8169_private *tp = netdev_priv(dev);
6609
6d8b8349 6610 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6611}
6612#endif
6613
df43ac78
FR		 6614static int rtl_open(struct net_device *dev)
6615{
6616 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6617 struct pci_dev *pdev = tp->pci_dev;
6618 int retval = -ENOMEM;
6619
6620 pm_runtime_get_sync(&pdev->dev);
6621
6622 /*
e75d6606 6623 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6624 * dma_alloc_coherent provides more.
6625 */
6626 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6627 &tp->TxPhyAddr, GFP_KERNEL);
6628 if (!tp->TxDescArray)
6629 goto err_pm_runtime_put;
6630
6631 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6632 &tp->RxPhyAddr, GFP_KERNEL);
6633 if (!tp->RxDescArray)
6634 goto err_free_tx_0;
6635
b1127e64 6636 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6637 if (retval < 0)
6638 goto err_free_rx_1;
6639
6640 INIT_WORK(&tp->wk.work, rtl_task);
6641
6642 smp_mb();
6643
6644 rtl_request_firmware(tp);
6645
ebcd5daa 6646 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 6647 dev->name);
df43ac78
FR		 6648 if (retval < 0)
6649 goto err_release_fw_2;
6650
f1e911d5
HK		 6651 retval = r8169_phy_connect(tp);
6652 if (retval)
6653 goto err_free_irq;
6654
df43ac78
FR		 6655 rtl_lock_work(tp);
6656
6657 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6658
6659 napi_enable(&tp->napi);
6660
6661 rtl8169_init_phy(dev, tp);
6662
df43ac78
FR		 6663 rtl_pll_power_up(tp);
6664
61cb532d 6665 rtl_hw_start(tp);
df43ac78 6666
e71c9ce2 6667 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 6668 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6669
f1e911d5 6670 phy_start(dev->phydev);
df43ac78
FR		 6671 netif_start_queue(dev);
6672
6673 rtl_unlock_work(tp);
6674
a92a0849 6675 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 6676out:
6677 return retval;
6678
f1e911d5
HK		 6679err_free_irq:
6680 pci_free_irq(pdev, 0, tp);
df43ac78
FR		 6681err_release_fw_2:
6682 rtl_release_firmware(tp);
6683 rtl8169_rx_clear(tp);
6684err_free_rx_1:
6685 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6686 tp->RxPhyAddr);
6687 tp->RxDescArray = NULL;
6688err_free_tx_0:
6689 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6690 tp->TxPhyAddr);
6691 tp->TxDescArray = NULL;
6692err_pm_runtime_put:
6693 pm_runtime_put_noidle(&pdev->dev);
6694 goto out;
6695}
6696
bc1f4470 6697static void
8027aa24 6698rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6699{
6700 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 6701 struct pci_dev *pdev = tp->pci_dev;
42020320 6702 struct rtl8169_counters *counters = tp->counters;
8027aa24 6703 unsigned int start;
1da177e4 6704
f09cf4b7
CHL		 6705 pm_runtime_get_noresume(&pdev->dev);
6706
6707 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 6708 rtl8169_rx_missed(dev);
5b0384f4 6709
8027aa24 6710 do {
57a7744e 6711 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6712 stats->rx_packets = tp->rx_stats.packets;
6713 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6714 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 6715
8027aa24 6716 do {
57a7744e 6717 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6718 stats->tx_packets = tp->tx_stats.packets;
6719 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6720 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6721
6722 stats->rx_dropped = dev->stats.rx_dropped;
6723 stats->tx_dropped = dev->stats.tx_dropped;
6724 stats->rx_length_errors = dev->stats.rx_length_errors;
6725 stats->rx_errors = dev->stats.rx_errors;
6726 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6727 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6728 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 6729 stats->multicast = dev->stats.multicast;
8027aa24 6730
6e85d5ad
CV		 6731 /*
6732 * Fetch additonal counter values missing in stats collected by driver
6733 * from tally counters.
6734 */
f09cf4b7 6735 if (pm_runtime_active(&pdev->dev))
e71c9ce2 6736 rtl8169_update_counters(tp);
6e85d5ad
CV		 6737
6738 /*
6739 * Subtract values fetched during initalization.
6740 * See rtl8169_init_counter_offsets for a description why we do that.
6741 */
42020320 6742 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 6743 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 6744 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 6745 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 6746 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 6747 le16_to_cpu(tp->tc_offset.tx_aborted);
6748
f09cf4b7 6749 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 6750}
6751
861ab440 6752static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6753{
065c27c1 6754 struct rtl8169_private *tp = netdev_priv(dev);
6755
5d06a99f 6756 if (!netif_running(dev))
861ab440 6757 return;
5d06a99f 6758
f1e911d5 6759 phy_stop(dev->phydev);
5d06a99f 6760 netif_device_detach(dev);
da78dbff
FR		 6761
6762 rtl_lock_work(tp);
6763 napi_disable(&tp->napi);
6ad56901
KHF		 6764 /* Clear all task flags */
6765 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6766
da78dbff
FR		 6767 rtl_unlock_work(tp);
6768
6769 rtl_pll_power_down(tp);
861ab440
RW		 6770}
6771
6772#ifdef CONFIG_PM
6773
6774static int rtl8169_suspend(struct device *device)
6775{
0f07bd85 6776 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1 6777 struct rtl8169_private *tp = netdev_priv(dev);
5d06a99f 6778
861ab440 6779 rtl8169_net_suspend(dev);
ac8bd9e1 6780 clk_disable_unprepare(tp->clk);
1371fa6d 6781
5d06a99f
FR		 6782 return 0;
6783}
6784
e1759441
RW		 6785static void __rtl8169_resume(struct net_device *dev)
6786{
065c27c1 6787 struct rtl8169_private *tp = netdev_priv(dev);
6788
e1759441 6789 netif_device_attach(dev);
065c27c1 6790
6791 rtl_pll_power_up(tp);
92bad850 6792 rtl8169_init_phy(dev, tp);
065c27c1 6793
f1e911d5
HK		 6794 phy_start(tp->dev->phydev);
6795
cff4c162
AS		 6796 rtl_lock_work(tp);
6797 napi_enable(&tp->napi);
6c4a70c5 6798 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6799 rtl_unlock_work(tp);
da78dbff 6800
98ddf986 6801 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6802}
6803
861ab440 6804static int rtl8169_resume(struct device *device)
5d06a99f 6805{
0f07bd85 6806 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1
HG		 6807 struct rtl8169_private *tp = netdev_priv(dev);
6808
6809 clk_prepare_enable(tp->clk);
5d06a99f 6810
e1759441
RW		 6811 if (netif_running(dev))
6812 __rtl8169_resume(dev);
5d06a99f 6813
e1759441
RW		 6814 return 0;
6815}
6816
6817static int rtl8169_runtime_suspend(struct device *device)
6818{
0f07bd85 6819 struct net_device *dev = dev_get_drvdata(device);
e1759441
RW		 6820 struct rtl8169_private *tp = netdev_priv(dev);
6821
07df5bd8 6822 if (!tp->TxDescArray)
e1759441
RW		 6823 return 0;
6824
da78dbff 6825 rtl_lock_work(tp);
e1759441 6826 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6827 rtl_unlock_work(tp);
e1759441
RW		 6828
6829 rtl8169_net_suspend(dev);
6830
f09cf4b7 6831 /* Update counters before going runtime suspend */
1ef7286e 6832 rtl8169_rx_missed(dev);
e71c9ce2 6833 rtl8169_update_counters(tp);
f09cf4b7 6834
e1759441
RW		 6835 return 0;
6836}
6837
6838static int rtl8169_runtime_resume(struct device *device)
6839{
0f07bd85 6840 struct net_device *dev = dev_get_drvdata(device);
e1759441 6841 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 6842 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 6843
6844 if (!tp->TxDescArray)
6845 return 0;
6846
da78dbff 6847 rtl_lock_work(tp);
e1759441 6848 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 6849 rtl_unlock_work(tp);
e1759441
RW		 6850
6851 __rtl8169_resume(dev);
5d06a99f 6852
5d06a99f
FR		 6853 return 0;
6854}
6855
e1759441
RW		 6856static int rtl8169_runtime_idle(struct device *device)
6857{
0f07bd85 6858 struct net_device *dev = dev_get_drvdata(device);
e1759441 6859
a92a0849
HK		 6860 if (!netif_running(dev) || !netif_carrier_ok(dev))
6861 pm_schedule_suspend(device, 10000);
6862
6863 return -EBUSY;
e1759441
RW		 6864}
6865
47145210 6866static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6867 .suspend = rtl8169_suspend,
6868 .resume = rtl8169_resume,
6869 .freeze = rtl8169_suspend,
6870 .thaw = rtl8169_resume,
6871 .poweroff = rtl8169_suspend,
6872 .restore = rtl8169_resume,
6873 .runtime_suspend = rtl8169_runtime_suspend,
6874 .runtime_resume = rtl8169_runtime_resume,
6875 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6876};
6877
6878#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6879
6880#else /* !CONFIG_PM */
6881
6882#define RTL8169_PM_OPS NULL
6883
6884#endif /* !CONFIG_PM */
6885
649b3b8c 6886static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6887{
649b3b8c 6888 /* WoL fails with 8168b when the receiver is disabled. */
6889 switch (tp->mac_version) {
6890 case RTL_GIGA_MAC_VER_11:
6891 case RTL_GIGA_MAC_VER_12:
6892 case RTL_GIGA_MAC_VER_17:
6893 pci_clear_master(tp->pci_dev);
6894
1ef7286e 6895 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 6896 /* PCI commit */
1ef7286e 6897 RTL_R8(tp, ChipCmd);
649b3b8c 6898 break;
6899 default:
6900 break;
6901 }
6902}
6903
1765f95d
FR		 6904static void rtl_shutdown(struct pci_dev *pdev)
6905{
861ab440 6906 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6907 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6908
6909 rtl8169_net_suspend(dev);
1765f95d 6910
cecb5fd7 6911 /* Restore original MAC address */
cc098dc7
IV		 6912 rtl_rar_set(tp, dev->perm_addr);
6913
92fc43b4 6914 rtl8169_hw_reset(tp);
4bb3f522 6915
861ab440 6916 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 6917 if (tp->saved_wolopts) {
649b3b8c 6918 rtl_wol_suspend_quirk(tp);
6919 rtl_wol_shutdown_quirk(tp);
ca52efd5 6920 }
6921
861ab440
RW		 6922 pci_wake_from_d3(pdev, true);
6923 pci_set_power_state(pdev, PCI_D3hot);
6924 }
6925}
5d06a99f 6926
baf63293 6927static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6928{
6929 struct net_device *dev = pci_get_drvdata(pdev);
6930 struct rtl8169_private *tp = netdev_priv(dev);
6931
9dbe7896 6932 if (r8168_check_dash(tp))
e27566ed 6933 rtl8168_driver_stop(tp);
e27566ed 6934
ad1be8d3
DN		 6935 netif_napi_del(&tp->napi);
6936
e27566ed 6937 unregister_netdev(dev);
f1e911d5 6938 mdiobus_unregister(tp->mii_bus);
e27566ed
FR		 6939
6940 rtl_release_firmware(tp);
6941
6942 if (pci_dev_run_wake(pdev))
6943 pm_runtime_get_noresume(&pdev->dev);
6944
6945 /* restore original MAC address */
6946 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 6947}
6948
fa9c385e 6949static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6950 .ndo_open = rtl_open,
fa9c385e
FR		 6951 .ndo_stop = rtl8169_close,
6952 .ndo_get_stats64 = rtl8169_get_stats64,
6953 .ndo_start_xmit = rtl8169_start_xmit,
6954 .ndo_tx_timeout = rtl8169_tx_timeout,
6955 .ndo_validate_addr = eth_validate_addr,
6956 .ndo_change_mtu = rtl8169_change_mtu,
6957 .ndo_fix_features = rtl8169_fix_features,
6958 .ndo_set_features = rtl8169_set_features,
6959 .ndo_set_mac_address = rtl_set_mac_address,
6960 .ndo_do_ioctl = rtl8169_ioctl,
6961 .ndo_set_rx_mode = rtl_set_rx_mode,
6962#ifdef CONFIG_NET_POLL_CONTROLLER
6963 .ndo_poll_controller = rtl8169_netpoll,
6964#endif
6965
6966};
6967
31fa8b18 6968static const struct rtl_cfg_info {
61cb532d 6969 void (*hw_start)(struct rtl8169_private *tp);
559c3c04 6970 u16 irq_mask;
14967f94 6971 unsigned int has_gmii:1;
50970831 6972 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 6973} rtl_cfg_infos [] = {
6974 [RTL_CFG_0] = {
6975 .hw_start = rtl_hw_start_8169,
559c3c04 6976 .irq_mask = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 6977 .has_gmii = 1,
50970831 6978 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 6979 },
6980 [RTL_CFG_1] = {
6981 .hw_start = rtl_hw_start_8168,
559c3c04 6982 .irq_mask = LinkChg | RxOverflow,
14967f94 6983 .has_gmii = 1,
50970831 6984 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 6985 },
6986 [RTL_CFG_2] = {
6987 .hw_start = rtl_hw_start_8101,
559c3c04 6988 .irq_mask = LinkChg | RxOverflow | RxFIFOOver,
50970831 6989 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 6990 }
6991};
6992
6c6aa15f 6993static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 6994{
6c6aa15f 6995 unsigned int flags;
31fa8b18 6996
d49c88d7 6997 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1ef7286e
AS		 6998 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6999 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7000 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f 7001 flags = PCI_IRQ_LEGACY;
d49c88d7 7002 } else {
6c6aa15f 7003 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 7004 }
6c6aa15f
HK		 7005
7006 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 7007}
7008
c558386b
HW		 7009DECLARE_RTL_COND(rtl_link_list_ready_cond)
7010{
1ef7286e 7011 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 7012}
7013
7014DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7015{
1ef7286e 7016 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 7017}
7018
f1e911d5
HK		 7019static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7020{
7021 struct rtl8169_private *tp = mii_bus->priv;
7022
7023 if (phyaddr > 0)
7024 return -ENODEV;
7025
7026 return rtl_readphy(tp, phyreg);
7027}
7028
7029static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7030 int phyreg, u16 val)
7031{
7032 struct rtl8169_private *tp = mii_bus->priv;
7033
7034 if (phyaddr > 0)
7035 return -ENODEV;
7036
7037 rtl_writephy(tp, phyreg, val);
7038
7039 return 0;
7040}
7041
7042static int r8169_mdio_register(struct rtl8169_private *tp)
7043{
7044 struct pci_dev *pdev = tp->pci_dev;
7045 struct phy_device *phydev;
7046 struct mii_bus *new_bus;
7047 int ret;
7048
7049 new_bus = devm_mdiobus_alloc(&pdev->dev);
7050 if (!new_bus)
7051 return -ENOMEM;
7052
7053 new_bus->name = "r8169";
7054 new_bus->priv = tp;
7055 new_bus->parent = &pdev->dev;
7056 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7057 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7058 PCI_DEVID(pdev->bus->number, pdev->devfn));
7059
7060 new_bus->read = r8169_mdio_read_reg;
7061 new_bus->write = r8169_mdio_write_reg;
7062
7063 ret = mdiobus_register(new_bus);
7064 if (ret)
7065 return ret;
7066
7067 phydev = mdiobus_get_phy(new_bus, 0);
7068 if (!phydev) {
7069 mdiobus_unregister(new_bus);
7070 return -ENODEV;
7071 }
7072
242cd9b5
HK		 7073 /* PHY will be woken up in rtl_open() */
7074 phy_suspend(phydev);
7075
f1e911d5
HK		 7076 tp->mii_bus = new_bus;
7077
7078 return 0;
7079}
7080
baf63293 7081static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 7082{
c558386b
HW		 7083 u32 data;
7084
7085 tp->ocp_base = OCP_STD_PHY_BASE;
7086
1ef7286e 7087 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 7088
7089 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7090 return;
7091
7092 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7093 return;
7094
1ef7286e 7095 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 7096 msleep(1);
1ef7286e 7097 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 7098
5f8bcce9 7099 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7100 data &= ~(1 << 14);
7101 r8168_mac_ocp_write(tp, 0xe8de, data);
7102
7103 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7104 return;
7105
5f8bcce9 7106 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7107 data |= (1 << 15);
7108 r8168_mac_ocp_write(tp, 0xe8de, data);
7109
7110 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7111 return;
7112}
7113
003609da
CHL		 7114static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7115{
7116 rtl8168ep_stop_cmac(tp);
7117 rtl_hw_init_8168g(tp);
7118}
7119
baf63293 7120static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7121{
7122 switch (tp->mac_version) {
2a71883c 7123 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7124 rtl_hw_init_8168g(tp);
7125 break;
2a71883c 7126 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
003609da 7127 rtl_hw_init_8168ep(tp);
c558386b 7128 break;
c558386b
HW		 7129 default:
7130 break;
7131 }
7132}
7133
eb88f5f7
HK		 7134/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7135static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7136{
7137 switch (tp->mac_version) {
7138 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7139 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7140 return false;
7141 default:
7142 return true;
7143 }
7144}
7145
abe8b2f7
HK		 7146static int rtl_jumbo_max(struct rtl8169_private *tp)
7147{
7148 /* Non-GBit versions don't support jumbo frames */
7149 if (!tp->supports_gmii)
7150 return JUMBO_1K;
7151
7152 switch (tp->mac_version) {
7153 /* RTL8169 */
7154 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7155 return JUMBO_7K;
7156 /* RTL8168b */
7157 case RTL_GIGA_MAC_VER_11:
7158 case RTL_GIGA_MAC_VER_12:
7159 case RTL_GIGA_MAC_VER_17:
7160 return JUMBO_4K;
7161 /* RTL8168c */
7162 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7163 return JUMBO_6K;
7164 default:
7165 return JUMBO_9K;
7166 }
7167}
7168
c2f6f3ee
HG		 7169static void rtl_disable_clk(void *data)
7170{
7171 clk_disable_unprepare(data);
7172}
7173
929a031d 7174static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7175{
7176 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3b6cf25d 7177 struct rtl8169_private *tp;
3b6cf25d 7178 struct net_device *dev;
c8d48d9c 7179 int chipset, region, i;
abe8b2f7 7180 int jumbo_max, rc;
3b6cf25d 7181
4c45d24a
HK		 7182 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7183 if (!dev)
7184 return -ENOMEM;
3b6cf25d
FR		 7185
7186 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7187 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7188 tp = netdev_priv(dev);
7189 tp->dev = dev;
7190 tp->pci_dev = pdev;
7191 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
f7ffa9ae 7192 tp->supports_gmii = cfg->has_gmii;
3b6cf25d 7193
c2f6f3ee
HG		 7194 /* Get the *optional* external "ether_clk" used on some boards */
7195 tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7196 if (IS_ERR(tp->clk)) {
7197 rc = PTR_ERR(tp->clk);
7198 if (rc == -ENOENT) {
7199 /* clk-core allows NULL (for suspend / resume) */
7200 tp->clk = NULL;
7201 } else if (rc == -EPROBE_DEFER) {
7202 return rc;
7203 } else {
7204 dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7205 return rc;
7206 }
7207 } else {
7208 rc = clk_prepare_enable(tp->clk);
7209 if (rc) {
7210 dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7211 return rc;
7212 }
7213
7214 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7215 tp->clk);
7216 if (rc)
7217 return rc;
7218 }
7219
3b6cf25d 7220 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7221 rc = pcim_enable_device(pdev);
3b6cf25d 7222 if (rc < 0) {
22148df0 7223 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7224 return rc;
3b6cf25d
FR		 7225 }
7226
4c45d24a 7227 if (pcim_set_mwi(pdev) < 0)
22148df0 7228 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7229
c8d48d9c
HK		 7230 /* use first MMIO region */
7231 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7232 if (region < 0) {
22148df0 7233 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7234 return -ENODEV;
3b6cf25d
FR		 7235 }
7236
7237 /* check for weird/broken PCI region reporting */
7238 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7239 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7240 return -ENODEV;
3b6cf25d
FR		 7241 }
7242
93a00d4d 7243 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7244 if (rc < 0) {
22148df0 7245 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7246 return rc;
3b6cf25d
FR		 7247 }
7248
93a00d4d 7249 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d 7250
3b6cf25d 7251 /* Identify chip attached to board */
b4cc2dcc
HK		 7252 rtl8169_get_mac_version(tp);
7253 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7254 return -ENODEV;
3b6cf25d 7255
e397286b
HK		 7256 if (rtl_tbi_enabled(tp)) {
7257 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7258 return -ENODEV;
7259 }
7260
0ae0974e 7261 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83 7262
a0456790
HK		 7263 if (sizeof(dma_addr_t) > 4 && (use_dac == 1 || (use_dac == -1 &&
7264 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7265 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
27896c83
AB		 7266
7267 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7268 if (!pci_is_pcie(pdev))
7269 tp->cp_cmd |= PCIDAC;
7270 dev->features |= NETIF_F_HIGHDMA;
7271 } else {
7272 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7273 if (rc < 0) {
22148df0 7274 dev_err(&pdev->dev, "DMA configuration failed\n");
4c45d24a 7275 return rc;
27896c83
AB		 7276 }
7277 }
7278
3b6cf25d
FR		 7279 rtl_init_rxcfg(tp);
7280
de20e12f 7281 rtl8169_irq_mask_and_ack(tp);
3b6cf25d 7282
c558386b
HW		 7283 rtl_hw_initialize(tp);
7284
3b6cf25d
FR		 7285 rtl_hw_reset(tp);
7286
3b6cf25d
FR		 7287 pci_set_master(pdev);
7288
3b6cf25d 7289 rtl_init_mdio_ops(tp);
3b6cf25d
FR		 7290 rtl_init_jumbo_ops(tp);
7291
3b6cf25d 7292 chipset = tp->mac_version;
3b6cf25d 7293
6c6aa15f
HK		 7294 rc = rtl_alloc_irq(tp);
7295 if (rc < 0) {
22148df0 7296 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7297 return rc;
7298 }
3b6cf25d 7299
18041b52 7300 tp->saved_wolopts = __rtl8169_get_wol(tp);
7edf6d31 7301
3b6cf25d 7302 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7303 u64_stats_init(&tp->rx_stats.syncp);
7304 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7305
7306 /* Get MAC address */
b2d43e6e 7307 switch (tp->mac_version) {
353af85e 7308 u8 mac_addr[ETH_ALEN] __aligned(4);
b2d43e6e
HK		 7309 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7310 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
05b9687b 7311 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
353af85e 7312 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89 7313
353af85e
HK		 7314 if (is_valid_ether_addr(mac_addr))
7315 rtl_rar_set(tp, mac_addr);
b2d43e6e
HK		 7316 break;
7317 default:
7318 break;
6e1d0b89 7319 }
3b6cf25d 7320 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 7321 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 7322
7ad24ea4 7323 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7324
37621493 7325 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 7326
7327 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7328 * properly for all devices */
7329 dev->features |= NETIF_F_RXCSUM |
f646968f 7330 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7331
7332 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7333 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7334 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7335 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7336 NETIF_F_HIGHDMA;
2d0ec544 7337 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 7338
929a031d 7339 tp->cp_cmd |= RxChkSum | RxVlan;
7340
7341 /*
7342 * Pretend we are using VLANs; This bypasses a nasty bug where
7343 * Interrupts stop flowing on high load on 8110SCd controllers.
7344 */
3b6cf25d 7345 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7346 /* Disallow toggling */
f646968f 7347 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7348
eb88f5f7 7349 if (rtl_chip_supports_csum_v2(tp)) {
5888d3fc 7350 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7351 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
eb88f5f7
HK		 7352 } else {
7353 tp->tso_csum = rtl8169_tso_csum_v1;
a4328ddb 7354 }
5888d3fc 7355
3b6cf25d
FR		 7356 dev->hw_features |= NETIF_F_RXALL;
7357 dev->hw_features |= NETIF_F_RXFCS;
7358
c7315a95
JW		 7359 /* MTU range: 60 - hw-specific max */
7360 dev->min_mtu = ETH_ZLEN;
abe8b2f7
HK		 7361 jumbo_max = rtl_jumbo_max(tp);
7362 dev->max_mtu = jumbo_max;
c7315a95 7363
3b6cf25d 7364 tp->hw_start = cfg->hw_start;
559c3c04 7365 tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
50970831 7366 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d 7367
3b6cf25d
FR		 7368 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7369
4c45d24a
HK		 7370 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7371 &tp->counters_phys_addr,
7372 GFP_KERNEL);
4cf964af
HK		 7373 if (!tp->counters)
7374 return -ENOMEM;
42020320 7375
19c9ea36
HK		 7376 pci_set_drvdata(pdev, dev);
7377
f1e911d5
HK		 7378 rc = r8169_mdio_register(tp);
7379 if (rc)
4cf964af 7380 return rc;
3b6cf25d 7381
07df5bd8
HK		 7382 /* chip gets powered up in rtl_open() */
7383 rtl_pll_power_down(tp);
7384
f1e911d5
HK		 7385 rc = register_netdev(dev);
7386 if (rc)
7387 goto err_mdio_unregister;
7388
55d2ad7b 7389 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
2d6c5a61 7390 rtl_chip_infos[chipset].name, dev->dev_addr,
55d2ad7b 7391 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
29274991 7392 pci_irq_vector(pdev, 0));
abe8b2f7
HK		 7393
7394 if (jumbo_max > JUMBO_1K)
7395 netif_info(tp, probe, dev,
7396 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7397 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7398 "ok" : "ko");
3b6cf25d 7399
9dbe7896 7400 if (r8168_check_dash(tp))
3b6cf25d 7401 rtl8168_driver_start(tp);
3b6cf25d 7402
a92a0849
HK		 7403 if (pci_dev_run_wake(pdev))
7404 pm_runtime_put_sync(&pdev->dev);
7405
4c45d24a 7406 return 0;
f1e911d5
HK		 7407
7408err_mdio_unregister:
7409 mdiobus_unregister(tp->mii_bus);
7410 return rc;
3b6cf25d
FR		 7411}
7412
1da177e4
LT		 7413static struct pci_driver rtl8169_pci_driver = {
7414 .name = MODULENAME,
7415 .id_table = rtl8169_pci_tbl,
3b6cf25d 7416 .probe = rtl_init_one,
baf63293 7417 .remove = rtl_remove_one,
1765f95d 7418 .shutdown = rtl_shutdown,
861ab440 7419 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7420};
7421
3eeb7da9 7422module_pci_driver(rtl8169_pci_driver);
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