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5b435de0 AS |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/printk.h> | |
21 | #include <linux/pci_ids.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/mmc/sdio.h> | |
26 | #include <linux/mmc/sdio_func.h> | |
27 | #include <linux/mmc/card.h> | |
28 | #include <linux/semaphore.h> | |
29 | #include <linux/firmware.h> | |
b7a57e76 | 30 | #include <linux/module.h> |
99ba15cd | 31 | #include <linux/bcma/bcma.h> |
4fc0d016 | 32 | #include <linux/debugfs.h> |
8dc01811 | 33 | #include <linux/vmalloc.h> |
668761ac | 34 | #include <linux/platform_data/brcmfmac-sdio.h> |
8da9d2c8 | 35 | #include <linux/moduleparam.h> |
5b435de0 AS |
36 | #include <asm/unaligned.h> |
37 | #include <defs.h> | |
38 | #include <brcmu_wifi.h> | |
39 | #include <brcmu_utils.h> | |
40 | #include <brcm_hw_ids.h> | |
41 | #include <soc.h> | |
42 | #include "sdio_host.h" | |
a83369b6 | 43 | #include "sdio_chip.h" |
5b435de0 AS |
44 | |
45 | #define DCMD_RESP_TIMEOUT 2000 /* In milli second */ | |
46 | ||
8ae74654 | 47 | #ifdef DEBUG |
5b435de0 AS |
48 | |
49 | #define BRCMF_TRAP_INFO_SIZE 80 | |
50 | ||
51 | #define CBUF_LEN (128) | |
52 | ||
4fc0d016 AS |
53 | /* Device console log buffer state */ |
54 | #define CONSOLE_BUFFER_MAX 2024 | |
55 | ||
5b435de0 AS |
56 | struct rte_log_le { |
57 | __le32 buf; /* Can't be pointer on (64-bit) hosts */ | |
58 | __le32 buf_size; | |
59 | __le32 idx; | |
60 | char *_buf_compat; /* Redundant pointer for backward compat. */ | |
61 | }; | |
62 | ||
63 | struct rte_console { | |
64 | /* Virtual UART | |
65 | * When there is no UART (e.g. Quickturn), | |
66 | * the host should write a complete | |
67 | * input line directly into cbuf and then write | |
68 | * the length into vcons_in. | |
69 | * This may also be used when there is a real UART | |
70 | * (at risk of conflicting with | |
71 | * the real UART). vcons_out is currently unused. | |
72 | */ | |
73 | uint vcons_in; | |
74 | uint vcons_out; | |
75 | ||
76 | /* Output (logging) buffer | |
77 | * Console output is written to a ring buffer log_buf at index log_idx. | |
78 | * The host may read the output when it sees log_idx advance. | |
79 | * Output will be lost if the output wraps around faster than the host | |
80 | * polls. | |
81 | */ | |
82 | struct rte_log_le log_le; | |
83 | ||
84 | /* Console input line buffer | |
85 | * Characters are read one at a time into cbuf | |
86 | * until <CR> is received, then | |
87 | * the buffer is processed as a command line. | |
88 | * Also used for virtual UART. | |
89 | */ | |
90 | uint cbuf_idx; | |
91 | char cbuf[CBUF_LEN]; | |
92 | }; | |
93 | ||
8ae74654 | 94 | #endif /* DEBUG */ |
5b435de0 AS |
95 | #include <chipcommon.h> |
96 | ||
5b435de0 | 97 | #include "dhd_bus.h" |
5b435de0 | 98 | #include "dhd_dbg.h" |
40c1c249 | 99 | #include "tracepoint.h" |
5b435de0 AS |
100 | |
101 | #define TXQLEN 2048 /* bulk tx queue length */ | |
102 | #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ | |
103 | #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ | |
104 | #define PRIOMASK 7 | |
105 | ||
106 | #define TXRETRIES 2 /* # of retries for tx frames */ | |
107 | ||
108 | #define BRCMF_RXBOUND 50 /* Default for max rx frames in | |
109 | one scheduling */ | |
110 | ||
111 | #define BRCMF_TXBOUND 20 /* Default for max tx frames in | |
112 | one scheduling */ | |
113 | ||
8da9d2c8 FL |
114 | #define BRCMF_DEFAULT_TXGLOM_SIZE 32 /* max tx frames in glom chain */ |
115 | ||
5b435de0 AS |
116 | #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ |
117 | ||
118 | #define MEMBLOCK 2048 /* Block size used for downloading | |
119 | of dongle image */ | |
120 | #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold | |
121 | biggest possible glom */ | |
122 | ||
123 | #define BRCMF_FIRSTREAD (1 << 6) | |
124 | ||
125 | ||
126 | /* SBSDIO_DEVICE_CTL */ | |
127 | ||
128 | /* 1: device will assert busy signal when receiving CMD53 */ | |
129 | #define SBSDIO_DEVCTL_SETBUSY 0x01 | |
130 | /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ | |
131 | #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 | |
132 | /* 1: mask all interrupts to host except the chipActive (rev 8) */ | |
133 | #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 | |
134 | /* 1: isolate internal sdio signals, put external pads in tri-state; requires | |
135 | * sdio bus power cycle to clear (rev 9) */ | |
136 | #define SBSDIO_DEVCTL_PADS_ISO 0x08 | |
137 | /* Force SD->SB reset mapping (rev 11) */ | |
138 | #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 | |
139 | /* Determined by CoreControl bit */ | |
140 | #define SBSDIO_DEVCTL_RST_CORECTL 0x00 | |
141 | /* Force backplane reset */ | |
142 | #define SBSDIO_DEVCTL_RST_BPRESET 0x10 | |
143 | /* Force no backplane reset */ | |
144 | #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 | |
145 | ||
5b435de0 AS |
146 | /* direct(mapped) cis space */ |
147 | ||
148 | /* MAPPED common CIS address */ | |
149 | #define SBSDIO_CIS_BASE_COMMON 0x1000 | |
150 | /* maximum bytes in one CIS */ | |
151 | #define SBSDIO_CIS_SIZE_LIMIT 0x200 | |
152 | /* cis offset addr is < 17 bits */ | |
153 | #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF | |
154 | ||
155 | /* manfid tuple length, include tuple, link bytes */ | |
156 | #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 | |
157 | ||
158 | /* intstatus */ | |
159 | #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ | |
160 | #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ | |
161 | #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ | |
162 | #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ | |
163 | #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ | |
164 | #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ | |
165 | #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ | |
166 | #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ | |
167 | #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ | |
168 | #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ | |
169 | #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ | |
170 | #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ | |
171 | #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ | |
172 | #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ | |
173 | #define I_PC (1 << 10) /* descriptor error */ | |
174 | #define I_PD (1 << 11) /* data error */ | |
175 | #define I_DE (1 << 12) /* Descriptor protocol Error */ | |
176 | #define I_RU (1 << 13) /* Receive descriptor Underflow */ | |
177 | #define I_RO (1 << 14) /* Receive fifo Overflow */ | |
178 | #define I_XU (1 << 15) /* Transmit fifo Underflow */ | |
179 | #define I_RI (1 << 16) /* Receive Interrupt */ | |
180 | #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ | |
181 | #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ | |
182 | #define I_XI (1 << 24) /* Transmit Interrupt */ | |
183 | #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ | |
184 | #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ | |
185 | #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ | |
186 | #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ | |
187 | #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ | |
188 | #define I_SRESET (1 << 30) /* CCCR RES interrupt */ | |
189 | #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ | |
190 | #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) | |
191 | #define I_DMA (I_RI | I_XI | I_ERRORS) | |
192 | ||
193 | /* corecontrol */ | |
194 | #define CC_CISRDY (1 << 0) /* CIS Ready */ | |
195 | #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ | |
196 | #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ | |
197 | #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ | |
198 | #define CC_XMTDATAAVAIL_MODE (1 << 4) | |
199 | #define CC_XMTDATAAVAIL_CTRL (1 << 5) | |
200 | ||
201 | /* SDA_FRAMECTRL */ | |
202 | #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | |
203 | #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | |
204 | #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ | |
205 | #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ | |
206 | ||
5b435de0 AS |
207 | /* |
208 | * Software allocation of To SB Mailbox resources | |
209 | */ | |
210 | ||
211 | /* tosbmailbox bits corresponding to intstatus bits */ | |
212 | #define SMB_NAK (1 << 0) /* Frame NAK */ | |
213 | #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ | |
214 | #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ | |
215 | #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ | |
216 | ||
217 | /* tosbmailboxdata */ | |
218 | #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ | |
219 | ||
220 | /* | |
221 | * Software allocation of To Host Mailbox resources | |
222 | */ | |
223 | ||
224 | /* intstatus bits */ | |
225 | #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ | |
226 | #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ | |
227 | #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ | |
228 | #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ | |
229 | ||
230 | /* tohostmailboxdata */ | |
231 | #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ | |
232 | #define HMB_DATA_DEVREADY 2 /* talk to host after enable */ | |
233 | #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ | |
234 | #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ | |
235 | ||
236 | #define HMB_DATA_FCDATA_MASK 0xff000000 | |
237 | #define HMB_DATA_FCDATA_SHIFT 24 | |
238 | ||
239 | #define HMB_DATA_VERSION_MASK 0x00ff0000 | |
240 | #define HMB_DATA_VERSION_SHIFT 16 | |
241 | ||
242 | /* | |
243 | * Software-defined protocol header | |
244 | */ | |
245 | ||
246 | /* Current protocol version */ | |
247 | #define SDPCM_PROT_VERSION 4 | |
248 | ||
5b435de0 AS |
249 | /* |
250 | * Shared structure between dongle and the host. | |
251 | * The structure contains pointers to trap or assert information. | |
252 | */ | |
4fc0d016 | 253 | #define SDPCM_SHARED_VERSION 0x0003 |
5b435de0 AS |
254 | #define SDPCM_SHARED_VERSION_MASK 0x00FF |
255 | #define SDPCM_SHARED_ASSERT_BUILT 0x0100 | |
256 | #define SDPCM_SHARED_ASSERT 0x0200 | |
257 | #define SDPCM_SHARED_TRAP 0x0400 | |
258 | ||
259 | /* Space for header read, limit for data packets */ | |
260 | #define MAX_HDR_READ (1 << 6) | |
261 | #define MAX_RX_DATASZ 2048 | |
262 | ||
263 | /* Maximum milliseconds to wait for F2 to come up */ | |
264 | #define BRCMF_WAIT_F2RDY 3000 | |
265 | ||
266 | /* Bump up limit on waiting for HT to account for first startup; | |
267 | * if the image is doing a CRC calculation before programming the PMU | |
268 | * for HT availability, it could take a couple hundred ms more, so | |
269 | * max out at a 1 second (1000000us). | |
270 | */ | |
271 | #undef PMU_MAX_TRANSITION_DLY | |
272 | #define PMU_MAX_TRANSITION_DLY 1000000 | |
273 | ||
274 | /* Value for ChipClockCSR during initial setup */ | |
275 | #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ | |
276 | SBSDIO_ALP_AVAIL_REQ) | |
277 | ||
278 | /* Flags for SDH calls */ | |
279 | #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) | |
280 | ||
382a9e0f FL |
281 | #define BRCMF_IDLE_IMMEDIATE (-1) /* Enter idle immediately */ |
282 | #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change | |
283 | * when idle | |
284 | */ | |
285 | #define BRCMF_IDLE_INTERVAL 1 | |
286 | ||
4a3da990 PH |
287 | #define KSO_WAIT_US 50 |
288 | #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) | |
289 | ||
5b435de0 AS |
290 | /* |
291 | * Conversion of 802.1D priority to precedence level | |
292 | */ | |
293 | static uint prio2prec(u32 prio) | |
294 | { | |
295 | return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? | |
296 | (prio^2) : prio; | |
297 | } | |
298 | ||
8ae74654 | 299 | #ifdef DEBUG |
5b435de0 AS |
300 | /* Device console log buffer state */ |
301 | struct brcmf_console { | |
302 | uint count; /* Poll interval msec counter */ | |
303 | uint log_addr; /* Log struct address (fixed) */ | |
304 | struct rte_log_le log_le; /* Log struct (host copy) */ | |
305 | uint bufsize; /* Size of log buffer */ | |
306 | u8 *buf; /* Log buffer (host copy) */ | |
307 | uint last; /* Last buffer read index */ | |
308 | }; | |
4fc0d016 AS |
309 | |
310 | struct brcmf_trap_info { | |
311 | __le32 type; | |
312 | __le32 epc; | |
313 | __le32 cpsr; | |
314 | __le32 spsr; | |
315 | __le32 r0; /* a1 */ | |
316 | __le32 r1; /* a2 */ | |
317 | __le32 r2; /* a3 */ | |
318 | __le32 r3; /* a4 */ | |
319 | __le32 r4; /* v1 */ | |
320 | __le32 r5; /* v2 */ | |
321 | __le32 r6; /* v3 */ | |
322 | __le32 r7; /* v4 */ | |
323 | __le32 r8; /* v5 */ | |
324 | __le32 r9; /* sb/v6 */ | |
325 | __le32 r10; /* sl/v7 */ | |
326 | __le32 r11; /* fp/v8 */ | |
327 | __le32 r12; /* ip */ | |
328 | __le32 r13; /* sp */ | |
329 | __le32 r14; /* lr */ | |
330 | __le32 pc; /* r15 */ | |
331 | }; | |
8ae74654 | 332 | #endif /* DEBUG */ |
5b435de0 AS |
333 | |
334 | struct sdpcm_shared { | |
335 | u32 flags; | |
336 | u32 trap_addr; | |
337 | u32 assert_exp_addr; | |
338 | u32 assert_file_addr; | |
339 | u32 assert_line; | |
340 | u32 console_addr; /* Address of struct rte_console */ | |
341 | u32 msgtrace_addr; | |
342 | u8 tag[32]; | |
4fc0d016 | 343 | u32 brpt_addr; |
5b435de0 AS |
344 | }; |
345 | ||
346 | struct sdpcm_shared_le { | |
347 | __le32 flags; | |
348 | __le32 trap_addr; | |
349 | __le32 assert_exp_addr; | |
350 | __le32 assert_file_addr; | |
351 | __le32 assert_line; | |
352 | __le32 console_addr; /* Address of struct rte_console */ | |
353 | __le32 msgtrace_addr; | |
354 | u8 tag[32]; | |
4fc0d016 | 355 | __le32 brpt_addr; |
5b435de0 AS |
356 | }; |
357 | ||
6bc52319 FL |
358 | /* dongle SDIO bus specific header info */ |
359 | struct brcmf_sdio_hdrinfo { | |
4754fcee FL |
360 | u8 seq_num; |
361 | u8 channel; | |
362 | u16 len; | |
363 | u16 len_left; | |
364 | u16 len_nxtfrm; | |
365 | u8 dat_offset; | |
8da9d2c8 FL |
366 | bool lastfrm; |
367 | u16 tail_pad; | |
4754fcee | 368 | }; |
5b435de0 AS |
369 | |
370 | /* misc chip info needed by some of the routines */ | |
5b435de0 | 371 | /* Private data for SDIO bus interaction */ |
e92eedf4 | 372 | struct brcmf_sdio { |
5b435de0 AS |
373 | struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ |
374 | struct chip_info *ci; /* Chip info struct */ | |
375 | char *vars; /* Variables (from CIS and/or other) */ | |
376 | uint varsz; /* Size of variables buffer */ | |
377 | ||
378 | u32 ramsize; /* Size of RAM in SOCRAM (bytes) */ | |
379 | ||
380 | u32 hostintmask; /* Copy of Host Interrupt Mask */ | |
4531603a FL |
381 | atomic_t intstatus; /* Intstatus bits (events) pending */ |
382 | atomic_t fcstate; /* State of dongle flow-control */ | |
5b435de0 AS |
383 | |
384 | uint blocksize; /* Block size of SDIO transfers */ | |
385 | uint roundup; /* Max roundup limit */ | |
386 | ||
387 | struct pktq txq; /* Queue length used for flow-control */ | |
388 | u8 flowcontrol; /* per prio flow control bitmask */ | |
389 | u8 tx_seq; /* Transmit sequence number (next) */ | |
390 | u8 tx_max; /* Maximum transmit sequence allowed */ | |
391 | ||
392 | u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN]; | |
393 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ | |
5b435de0 | 394 | u8 rx_seq; /* Receive sequence number (expected) */ |
6bc52319 | 395 | struct brcmf_sdio_hdrinfo cur_read; |
4754fcee | 396 | /* info of current read frame */ |
5b435de0 | 397 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ |
4754fcee | 398 | bool rxpending; /* Data frame pending in dongle */ |
5b435de0 AS |
399 | |
400 | uint rxbound; /* Rx frames to read before resched */ | |
401 | uint txbound; /* Tx frames to send before resched */ | |
402 | uint txminmax; | |
403 | ||
404 | struct sk_buff *glomd; /* Packet containing glomming descriptor */ | |
b83db862 | 405 | struct sk_buff_head glom; /* Packet list for glommed superframe */ |
5b435de0 AS |
406 | uint glomerr; /* Glom packet read errors */ |
407 | ||
408 | u8 *rxbuf; /* Buffer for receiving control packets */ | |
409 | uint rxblen; /* Allocated length of rxbuf */ | |
410 | u8 *rxctl; /* Aligned pointer into rxbuf */ | |
dd43a01c | 411 | u8 *rxctl_orig; /* pointer for freeing rxctl */ |
5b435de0 | 412 | uint rxlen; /* Length of valid data in buffer */ |
dd43a01c | 413 | spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ |
5b435de0 AS |
414 | |
415 | u8 sdpcm_ver; /* Bus protocol reported by dongle */ | |
416 | ||
417 | bool intr; /* Use interrupts */ | |
418 | bool poll; /* Use polling */ | |
1d382273 | 419 | atomic_t ipend; /* Device interrupt is pending */ |
5b435de0 AS |
420 | uint spurious; /* Count of spurious interrupts */ |
421 | uint pollrate; /* Ticks between device polls */ | |
422 | uint polltick; /* Tick counter */ | |
5b435de0 | 423 | |
8ae74654 | 424 | #ifdef DEBUG |
5b435de0 AS |
425 | uint console_interval; |
426 | struct brcmf_console console; /* Console output polling support */ | |
427 | uint console_addr; /* Console address from shared struct */ | |
8ae74654 | 428 | #endif /* DEBUG */ |
5b435de0 | 429 | |
5b435de0 AS |
430 | uint clkstate; /* State of sd and backplane clock(s) */ |
431 | bool activity; /* Activity flag for clock down */ | |
432 | s32 idletime; /* Control for activity timeout */ | |
433 | s32 idlecount; /* Activity timeout counter */ | |
434 | s32 idleclock; /* How to set bus driver when idle */ | |
5b435de0 AS |
435 | bool rxflow_mode; /* Rx flow control mode */ |
436 | bool rxflow; /* Is rx flow control on */ | |
437 | bool alp_only; /* Don't use HT clock (ALP only) */ | |
5b435de0 | 438 | |
5b435de0 AS |
439 | u8 *ctrl_frame_buf; |
440 | u32 ctrl_frame_len; | |
441 | bool ctrl_frame_stat; | |
442 | ||
443 | spinlock_t txqlock; | |
444 | wait_queue_head_t ctrl_wait; | |
445 | wait_queue_head_t dcmd_resp_wait; | |
446 | ||
447 | struct timer_list timer; | |
448 | struct completion watchdog_wait; | |
449 | struct task_struct *watchdog_tsk; | |
450 | bool wd_timer_valid; | |
451 | uint save_ms; | |
452 | ||
f1e68c2e FL |
453 | struct workqueue_struct *brcmf_wq; |
454 | struct work_struct datawork; | |
fccfe930 | 455 | atomic_t dpc_tskcnt; |
5b435de0 | 456 | |
c8bf3484 | 457 | bool txoff; /* Transmit flow-controlled */ |
80969836 | 458 | struct brcmf_sdio_count sdcnt; |
4a3da990 PH |
459 | bool sr_enabled; /* SaveRestore enabled */ |
460 | bool sleeping; /* SDIO bus sleeping */ | |
706478cb FL |
461 | |
462 | u8 tx_hdrlen; /* sdio bus header length for tx packet */ | |
8da9d2c8 FL |
463 | bool txglom; /* host tx glomming enable flag */ |
464 | struct sk_buff *txglom_sgpad; /* scatter-gather padding buffer */ | |
e217d1c8 AS |
465 | u16 head_align; /* buffer pointer alignment */ |
466 | u16 sgentry_align; /* scatter-gather buffer alignment */ | |
5b435de0 AS |
467 | }; |
468 | ||
5b435de0 AS |
469 | /* clkstate */ |
470 | #define CLK_NONE 0 | |
471 | #define CLK_SDONLY 1 | |
4a3da990 | 472 | #define CLK_PENDING 2 |
5b435de0 AS |
473 | #define CLK_AVAIL 3 |
474 | ||
8ae74654 | 475 | #ifdef DEBUG |
5b435de0 | 476 | static int qcount[NUMPRIO]; |
8ae74654 | 477 | #endif /* DEBUG */ |
5b435de0 | 478 | |
668761ac | 479 | #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ |
5b435de0 AS |
480 | |
481 | #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) | |
482 | ||
483 | /* Retry count for register access failures */ | |
484 | static const uint retry_limit = 2; | |
485 | ||
486 | /* Limit on rounding up frames */ | |
487 | static const uint max_roundup = 512; | |
488 | ||
489 | #define ALIGNMENT 4 | |
490 | ||
8da9d2c8 FL |
491 | static int brcmf_sdio_txglomsz = BRCMF_DEFAULT_TXGLOM_SIZE; |
492 | module_param_named(txglomsz, brcmf_sdio_txglomsz, int, 0); | |
493 | MODULE_PARM_DESC(txglomsz, "maximum tx packet chain size [SDIO]"); | |
494 | ||
9d7d6f95 FL |
495 | enum brcmf_sdio_frmtype { |
496 | BRCMF_SDIO_FT_NORMAL, | |
497 | BRCMF_SDIO_FT_SUPER, | |
498 | BRCMF_SDIO_FT_SUB, | |
499 | }; | |
500 | ||
f2c44fe7 HM |
501 | #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin" |
502 | #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt" | |
503 | #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin" | |
504 | #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt" | |
505 | #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin" | |
506 | #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt" | |
507 | #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin" | |
508 | #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt" | |
509 | #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin" | |
510 | #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt" | |
511 | #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin" | |
512 | #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt" | |
513 | #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin" | |
514 | #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt" | |
bed89b64 FL |
515 | #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin" |
516 | #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt" | |
f2c44fe7 HM |
517 | |
518 | MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME); | |
519 | MODULE_FIRMWARE(BCM43143_NVRAM_NAME); | |
520 | MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME); | |
521 | MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME); | |
522 | MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME); | |
523 | MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME); | |
524 | MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME); | |
525 | MODULE_FIRMWARE(BCM4329_NVRAM_NAME); | |
526 | MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME); | |
527 | MODULE_FIRMWARE(BCM4330_NVRAM_NAME); | |
528 | MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME); | |
529 | MODULE_FIRMWARE(BCM4334_NVRAM_NAME); | |
530 | MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME); | |
531 | MODULE_FIRMWARE(BCM4335_NVRAM_NAME); | |
bed89b64 FL |
532 | MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME); |
533 | MODULE_FIRMWARE(BCM4339_NVRAM_NAME); | |
f2c44fe7 HM |
534 | |
535 | struct brcmf_firmware_names { | |
536 | u32 chipid; | |
537 | u32 revmsk; | |
538 | const char *bin; | |
539 | const char *nv; | |
540 | }; | |
541 | ||
542 | enum brcmf_firmware_type { | |
543 | BRCMF_FIRMWARE_BIN, | |
544 | BRCMF_FIRMWARE_NVRAM | |
545 | }; | |
546 | ||
547 | #define BRCMF_FIRMWARE_NVRAM(name) \ | |
548 | name ## _FIRMWARE_NAME, name ## _NVRAM_NAME | |
549 | ||
550 | static const struct brcmf_firmware_names brcmf_fwname_data[] = { | |
551 | { BCM43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) }, | |
552 | { BCM43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) }, | |
553 | { BCM43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) }, | |
554 | { BCM4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) }, | |
555 | { BCM4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) }, | |
556 | { BCM4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) }, | |
bed89b64 FL |
557 | { BCM4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) }, |
558 | { BCM4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) } | |
f2c44fe7 HM |
559 | }; |
560 | ||
561 | ||
562 | static const struct firmware *brcmf_sdbrcm_get_fw(struct brcmf_sdio *bus, | |
563 | enum brcmf_firmware_type type) | |
564 | { | |
565 | const struct firmware *fw; | |
566 | const char *name; | |
567 | int err, i; | |
568 | ||
569 | for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) { | |
570 | if (brcmf_fwname_data[i].chipid == bus->ci->chip && | |
571 | brcmf_fwname_data[i].revmsk & BIT(bus->ci->chiprev)) { | |
572 | switch (type) { | |
573 | case BRCMF_FIRMWARE_BIN: | |
574 | name = brcmf_fwname_data[i].bin; | |
575 | break; | |
576 | case BRCMF_FIRMWARE_NVRAM: | |
577 | name = brcmf_fwname_data[i].nv; | |
578 | break; | |
579 | default: | |
580 | brcmf_err("invalid firmware type (%d)\n", type); | |
581 | return NULL; | |
582 | } | |
583 | goto found; | |
584 | } | |
585 | } | |
586 | brcmf_err("Unknown chipid %d [%d]\n", | |
587 | bus->ci->chip, bus->ci->chiprev); | |
588 | return NULL; | |
589 | ||
590 | found: | |
591 | err = request_firmware(&fw, name, &bus->sdiodev->func[2]->dev); | |
592 | if ((err) || (!fw)) { | |
593 | brcmf_err("fail to request firmware %s (%d)\n", name, err); | |
594 | return NULL; | |
595 | } | |
596 | ||
597 | return fw; | |
598 | } | |
599 | ||
5b435de0 AS |
600 | static void pkt_align(struct sk_buff *p, int len, int align) |
601 | { | |
602 | uint datalign; | |
603 | datalign = (unsigned long)(p->data); | |
604 | datalign = roundup(datalign, (align)) - datalign; | |
605 | if (datalign) | |
606 | skb_pull(p, datalign); | |
607 | __skb_trim(p, len); | |
608 | } | |
609 | ||
610 | /* To check if there's window offered */ | |
e92eedf4 | 611 | static bool data_ok(struct brcmf_sdio *bus) |
5b435de0 AS |
612 | { |
613 | return (u8)(bus->tx_max - bus->tx_seq) != 0 && | |
614 | ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; | |
615 | } | |
616 | ||
617 | /* | |
618 | * Reads a register in the SDIO hardware block. This block occupies a series of | |
619 | * adresses on the 32 bit backplane bus. | |
620 | */ | |
58692750 FL |
621 | static int |
622 | r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset) | |
5b435de0 | 623 | { |
99ba15cd | 624 | u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); |
79ae3957 | 625 | int ret; |
58692750 FL |
626 | |
627 | *regvar = brcmf_sdio_regrl(bus->sdiodev, | |
628 | bus->ci->c_inf[idx].base + offset, &ret); | |
629 | ||
630 | return ret; | |
5b435de0 AS |
631 | } |
632 | ||
58692750 FL |
633 | static int |
634 | w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) | |
5b435de0 | 635 | { |
99ba15cd | 636 | u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); |
e13ce26b | 637 | int ret; |
58692750 FL |
638 | |
639 | brcmf_sdio_regwl(bus->sdiodev, | |
640 | bus->ci->c_inf[idx].base + reg_offset, | |
641 | regval, &ret); | |
642 | ||
643 | return ret; | |
5b435de0 AS |
644 | } |
645 | ||
4a3da990 PH |
646 | static int |
647 | brcmf_sdbrcm_kso_control(struct brcmf_sdio *bus, bool on) | |
648 | { | |
649 | u8 wr_val = 0, rd_val, cmp_val, bmask; | |
650 | int err = 0; | |
651 | int try_cnt = 0; | |
652 | ||
653 | brcmf_dbg(TRACE, "Enter\n"); | |
654 | ||
655 | wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
656 | /* 1st KSO write goes to AOS wake up core if device is asleep */ | |
657 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
658 | wr_val, &err); | |
659 | if (err) { | |
660 | brcmf_err("SDIO_AOS KSO write error: %d\n", err); | |
661 | return err; | |
662 | } | |
663 | ||
664 | if (on) { | |
665 | /* device WAKEUP through KSO: | |
666 | * write bit 0 & read back until | |
667 | * both bits 0 (kso bit) & 1 (dev on status) are set | |
668 | */ | |
669 | cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | | |
670 | SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; | |
671 | bmask = cmp_val; | |
672 | usleep_range(2000, 3000); | |
673 | } else { | |
674 | /* Put device to sleep, turn off KSO */ | |
675 | cmp_val = 0; | |
676 | /* only check for bit0, bit1(dev on status) may not | |
677 | * get cleared right away | |
678 | */ | |
679 | bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; | |
680 | } | |
681 | ||
682 | do { | |
683 | /* reliable KSO bit set/clr: | |
684 | * the sdiod sleep write access is synced to PMU 32khz clk | |
685 | * just one write attempt may fail, | |
686 | * read it back until it matches written value | |
687 | */ | |
688 | rd_val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
689 | &err); | |
690 | if (((rd_val & bmask) == cmp_val) && !err) | |
691 | break; | |
692 | brcmf_dbg(SDIO, "KSO wr/rd retry:%d (max: %d) ERR:%x\n", | |
693 | try_cnt, MAX_KSO_ATTEMPTS, err); | |
694 | udelay(KSO_WAIT_US); | |
695 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
696 | wr_val, &err); | |
697 | } while (try_cnt++ < MAX_KSO_ATTEMPTS); | |
698 | ||
699 | return err; | |
700 | } | |
701 | ||
5b435de0 AS |
702 | #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND) |
703 | ||
704 | #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) | |
705 | ||
5b435de0 | 706 | /* Turn backplane clock on or off */ |
e92eedf4 | 707 | static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok) |
5b435de0 AS |
708 | { |
709 | int err; | |
710 | u8 clkctl, clkreq, devctl; | |
711 | unsigned long timeout; | |
712 | ||
c3203374 | 713 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
714 | |
715 | clkctl = 0; | |
716 | ||
4a3da990 PH |
717 | if (bus->sr_enabled) { |
718 | bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); | |
719 | return 0; | |
720 | } | |
721 | ||
5b435de0 AS |
722 | if (on) { |
723 | /* Request HT Avail */ | |
724 | clkreq = | |
725 | bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; | |
726 | ||
3bba829f FL |
727 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
728 | clkreq, &err); | |
5b435de0 | 729 | if (err) { |
5e8149f5 | 730 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
731 | return -EBADE; |
732 | } | |
733 | ||
5b435de0 | 734 | /* Check current status */ |
45db339c FL |
735 | clkctl = brcmf_sdio_regrb(bus->sdiodev, |
736 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 737 | if (err) { |
5e8149f5 | 738 | brcmf_err("HT Avail read error: %d\n", err); |
5b435de0 AS |
739 | return -EBADE; |
740 | } | |
741 | ||
742 | /* Go to pending and await interrupt if appropriate */ | |
743 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { | |
744 | /* Allow only clock-available interrupt */ | |
45db339c FL |
745 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
746 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 747 | if (err) { |
5e8149f5 | 748 | brcmf_err("Devctl error setting CA: %d\n", |
5b435de0 AS |
749 | err); |
750 | return -EBADE; | |
751 | } | |
752 | ||
753 | devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; | |
3bba829f FL |
754 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
755 | devctl, &err); | |
c3203374 | 756 | brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); |
5b435de0 AS |
757 | bus->clkstate = CLK_PENDING; |
758 | ||
759 | return 0; | |
760 | } else if (bus->clkstate == CLK_PENDING) { | |
761 | /* Cancel CA-only interrupt filter */ | |
45db339c | 762 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
5b435de0 AS |
763 | SBSDIO_DEVICE_CTL, &err); |
764 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
3bba829f FL |
765 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
766 | devctl, &err); | |
5b435de0 AS |
767 | } |
768 | ||
769 | /* Otherwise, wait here (polling) for HT Avail */ | |
770 | timeout = jiffies + | |
771 | msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); | |
772 | while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
45db339c FL |
773 | clkctl = brcmf_sdio_regrb(bus->sdiodev, |
774 | SBSDIO_FUNC1_CHIPCLKCSR, | |
775 | &err); | |
5b435de0 AS |
776 | if (time_after(jiffies, timeout)) |
777 | break; | |
778 | else | |
779 | usleep_range(5000, 10000); | |
780 | } | |
781 | if (err) { | |
5e8149f5 | 782 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
783 | return -EBADE; |
784 | } | |
785 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
5e8149f5 | 786 | brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", |
5b435de0 AS |
787 | PMU_MAX_TRANSITION_DLY, clkctl); |
788 | return -EBADE; | |
789 | } | |
790 | ||
791 | /* Mark clock available */ | |
792 | bus->clkstate = CLK_AVAIL; | |
c3203374 | 793 | brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); |
5b435de0 | 794 | |
8ae74654 | 795 | #if defined(DEBUG) |
23677ce3 | 796 | if (!bus->alp_only) { |
5b435de0 | 797 | if (SBSDIO_ALPONLY(clkctl)) |
5e8149f5 | 798 | brcmf_err("HT Clock should be on\n"); |
5b435de0 | 799 | } |
8ae74654 | 800 | #endif /* defined (DEBUG) */ |
5b435de0 AS |
801 | |
802 | bus->activity = true; | |
803 | } else { | |
804 | clkreq = 0; | |
805 | ||
806 | if (bus->clkstate == CLK_PENDING) { | |
807 | /* Cancel CA-only interrupt filter */ | |
45db339c FL |
808 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
809 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 810 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
3bba829f FL |
811 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
812 | devctl, &err); | |
5b435de0 AS |
813 | } |
814 | ||
815 | bus->clkstate = CLK_SDONLY; | |
3bba829f FL |
816 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
817 | clkreq, &err); | |
c3203374 | 818 | brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); |
5b435de0 | 819 | if (err) { |
5e8149f5 | 820 | brcmf_err("Failed access turning clock off: %d\n", |
5b435de0 AS |
821 | err); |
822 | return -EBADE; | |
823 | } | |
824 | } | |
825 | return 0; | |
826 | } | |
827 | ||
828 | /* Change idle/active SD state */ | |
e92eedf4 | 829 | static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on) |
5b435de0 | 830 | { |
c3203374 | 831 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
832 | |
833 | if (on) | |
834 | bus->clkstate = CLK_SDONLY; | |
835 | else | |
836 | bus->clkstate = CLK_NONE; | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
841 | /* Transition SD and backplane clock readiness */ | |
e92eedf4 | 842 | static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) |
5b435de0 | 843 | { |
8ae74654 | 844 | #ifdef DEBUG |
5b435de0 | 845 | uint oldstate = bus->clkstate; |
8ae74654 | 846 | #endif /* DEBUG */ |
5b435de0 | 847 | |
c3203374 | 848 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
849 | |
850 | /* Early exit if we're already there */ | |
851 | if (bus->clkstate == target) { | |
852 | if (target == CLK_AVAIL) { | |
853 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
854 | bus->activity = true; | |
855 | } | |
856 | return 0; | |
857 | } | |
858 | ||
859 | switch (target) { | |
860 | case CLK_AVAIL: | |
861 | /* Make sure SD clock is available */ | |
862 | if (bus->clkstate == CLK_NONE) | |
863 | brcmf_sdbrcm_sdclk(bus, true); | |
864 | /* Now request HT Avail on the backplane */ | |
865 | brcmf_sdbrcm_htclk(bus, true, pendok); | |
866 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
867 | bus->activity = true; | |
868 | break; | |
869 | ||
870 | case CLK_SDONLY: | |
871 | /* Remove HT request, or bring up SD clock */ | |
872 | if (bus->clkstate == CLK_NONE) | |
873 | brcmf_sdbrcm_sdclk(bus, true); | |
874 | else if (bus->clkstate == CLK_AVAIL) | |
875 | brcmf_sdbrcm_htclk(bus, false, false); | |
876 | else | |
5e8149f5 | 877 | brcmf_err("request for %d -> %d\n", |
5b435de0 AS |
878 | bus->clkstate, target); |
879 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
880 | break; | |
881 | ||
882 | case CLK_NONE: | |
883 | /* Make sure to remove HT request */ | |
884 | if (bus->clkstate == CLK_AVAIL) | |
885 | brcmf_sdbrcm_htclk(bus, false, false); | |
886 | /* Now remove the SD clock */ | |
887 | brcmf_sdbrcm_sdclk(bus, false); | |
888 | brcmf_sdbrcm_wd_timer(bus, 0); | |
889 | break; | |
890 | } | |
8ae74654 | 891 | #ifdef DEBUG |
c3203374 | 892 | brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); |
8ae74654 | 893 | #endif /* DEBUG */ |
5b435de0 AS |
894 | |
895 | return 0; | |
896 | } | |
897 | ||
4a3da990 PH |
898 | static int |
899 | brcmf_sdbrcm_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) | |
900 | { | |
901 | int err = 0; | |
902 | brcmf_dbg(TRACE, "Enter\n"); | |
903 | brcmf_dbg(SDIO, "request %s currently %s\n", | |
904 | (sleep ? "SLEEP" : "WAKE"), | |
905 | (bus->sleeping ? "SLEEP" : "WAKE")); | |
906 | ||
907 | /* If SR is enabled control bus state with KSO */ | |
908 | if (bus->sr_enabled) { | |
909 | /* Done if we're already in the requested state */ | |
910 | if (sleep == bus->sleeping) | |
911 | goto end; | |
912 | ||
913 | /* Going to sleep */ | |
914 | if (sleep) { | |
915 | /* Don't sleep if something is pending */ | |
916 | if (atomic_read(&bus->intstatus) || | |
917 | atomic_read(&bus->ipend) > 0 || | |
918 | (!atomic_read(&bus->fcstate) && | |
919 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
920 | data_ok(bus))) | |
921 | return -EBUSY; | |
922 | err = brcmf_sdbrcm_kso_control(bus, false); | |
923 | /* disable watchdog */ | |
924 | if (!err) | |
925 | brcmf_sdbrcm_wd_timer(bus, 0); | |
926 | } else { | |
927 | bus->idlecount = 0; | |
928 | err = brcmf_sdbrcm_kso_control(bus, true); | |
929 | } | |
930 | if (!err) { | |
931 | /* Change state */ | |
932 | bus->sleeping = sleep; | |
933 | brcmf_dbg(SDIO, "new state %s\n", | |
934 | (sleep ? "SLEEP" : "WAKE")); | |
935 | } else { | |
936 | brcmf_err("error while changing bus sleep state %d\n", | |
937 | err); | |
938 | return err; | |
939 | } | |
940 | } | |
941 | ||
942 | end: | |
943 | /* control clocks */ | |
944 | if (sleep) { | |
945 | if (!bus->sr_enabled) | |
946 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, pendok); | |
947 | } else { | |
948 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, pendok); | |
949 | } | |
950 | ||
951 | return err; | |
952 | ||
953 | } | |
954 | ||
e92eedf4 | 955 | static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus) |
5b435de0 AS |
956 | { |
957 | u32 intstatus = 0; | |
958 | u32 hmb_data; | |
959 | u8 fcbits; | |
58692750 | 960 | int ret; |
5b435de0 | 961 | |
c3203374 | 962 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
963 | |
964 | /* Read mailbox data and ack that we did so */ | |
58692750 FL |
965 | ret = r_sdreg32(bus, &hmb_data, |
966 | offsetof(struct sdpcmd_regs, tohostmailboxdata)); | |
5b435de0 | 967 | |
58692750 | 968 | if (ret == 0) |
5b435de0 | 969 | w_sdreg32(bus, SMB_INT_ACK, |
58692750 | 970 | offsetof(struct sdpcmd_regs, tosbmailbox)); |
80969836 | 971 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
972 | |
973 | /* Dongle recomposed rx frames, accept them again */ | |
974 | if (hmb_data & HMB_DATA_NAKHANDLED) { | |
c3203374 | 975 | brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", |
5b435de0 AS |
976 | bus->rx_seq); |
977 | if (!bus->rxskip) | |
5e8149f5 | 978 | brcmf_err("unexpected NAKHANDLED!\n"); |
5b435de0 AS |
979 | |
980 | bus->rxskip = false; | |
981 | intstatus |= I_HMB_FRAME_IND; | |
982 | } | |
983 | ||
984 | /* | |
985 | * DEVREADY does not occur with gSPI. | |
986 | */ | |
987 | if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { | |
988 | bus->sdpcm_ver = | |
989 | (hmb_data & HMB_DATA_VERSION_MASK) >> | |
990 | HMB_DATA_VERSION_SHIFT; | |
991 | if (bus->sdpcm_ver != SDPCM_PROT_VERSION) | |
5e8149f5 | 992 | brcmf_err("Version mismatch, dongle reports %d, " |
5b435de0 AS |
993 | "expecting %d\n", |
994 | bus->sdpcm_ver, SDPCM_PROT_VERSION); | |
995 | else | |
c3203374 | 996 | brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", |
5b435de0 AS |
997 | bus->sdpcm_ver); |
998 | } | |
999 | ||
1000 | /* | |
1001 | * Flow Control has been moved into the RX headers and this out of band | |
1002 | * method isn't used any more. | |
1003 | * remaining backward compatible with older dongles. | |
1004 | */ | |
1005 | if (hmb_data & HMB_DATA_FC) { | |
1006 | fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> | |
1007 | HMB_DATA_FCDATA_SHIFT; | |
1008 | ||
1009 | if (fcbits & ~bus->flowcontrol) | |
80969836 | 1010 | bus->sdcnt.fc_xoff++; |
5b435de0 AS |
1011 | |
1012 | if (bus->flowcontrol & ~fcbits) | |
80969836 | 1013 | bus->sdcnt.fc_xon++; |
5b435de0 | 1014 | |
80969836 | 1015 | bus->sdcnt.fc_rcvd++; |
5b435de0 AS |
1016 | bus->flowcontrol = fcbits; |
1017 | } | |
1018 | ||
1019 | /* Shouldn't be any others */ | |
1020 | if (hmb_data & ~(HMB_DATA_DEVREADY | | |
1021 | HMB_DATA_NAKHANDLED | | |
1022 | HMB_DATA_FC | | |
1023 | HMB_DATA_FWREADY | | |
1024 | HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) | |
5e8149f5 | 1025 | brcmf_err("Unknown mailbox data content: 0x%02x\n", |
5b435de0 AS |
1026 | hmb_data); |
1027 | ||
1028 | return intstatus; | |
1029 | } | |
1030 | ||
e92eedf4 | 1031 | static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) |
5b435de0 AS |
1032 | { |
1033 | uint retries = 0; | |
1034 | u16 lastrbc; | |
1035 | u8 hi, lo; | |
1036 | int err; | |
1037 | ||
5e8149f5 | 1038 | brcmf_err("%sterminate frame%s\n", |
5b435de0 AS |
1039 | abort ? "abort command, " : "", |
1040 | rtx ? ", send NAK" : ""); | |
1041 | ||
1042 | if (abort) | |
1043 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
1044 | ||
3bba829f FL |
1045 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
1046 | SFC_RF_TERM, &err); | |
80969836 | 1047 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
1048 | |
1049 | /* Wait until the packet has been flushed (device/FIFO stable) */ | |
1050 | for (lastrbc = retries = 0xffff; retries > 0; retries--) { | |
45db339c | 1051 | hi = brcmf_sdio_regrb(bus->sdiodev, |
5c15c23a | 1052 | SBSDIO_FUNC1_RFRAMEBCHI, &err); |
45db339c | 1053 | lo = brcmf_sdio_regrb(bus->sdiodev, |
5c15c23a | 1054 | SBSDIO_FUNC1_RFRAMEBCLO, &err); |
80969836 | 1055 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1056 | |
1057 | if ((hi == 0) && (lo == 0)) | |
1058 | break; | |
1059 | ||
1060 | if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { | |
5e8149f5 | 1061 | brcmf_err("count growing: last 0x%04x now 0x%04x\n", |
5b435de0 AS |
1062 | lastrbc, (hi << 8) + lo); |
1063 | } | |
1064 | lastrbc = (hi << 8) + lo; | |
1065 | } | |
1066 | ||
1067 | if (!retries) | |
5e8149f5 | 1068 | brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); |
5b435de0 | 1069 | else |
c3203374 | 1070 | brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); |
5b435de0 AS |
1071 | |
1072 | if (rtx) { | |
80969836 | 1073 | bus->sdcnt.rxrtx++; |
58692750 FL |
1074 | err = w_sdreg32(bus, SMB_NAK, |
1075 | offsetof(struct sdpcmd_regs, tosbmailbox)); | |
5b435de0 | 1076 | |
80969836 | 1077 | bus->sdcnt.f1regdata++; |
58692750 | 1078 | if (err == 0) |
5b435de0 AS |
1079 | bus->rxskip = true; |
1080 | } | |
1081 | ||
1082 | /* Clear partial in any case */ | |
4754fcee | 1083 | bus->cur_read.len = 0; |
5b435de0 AS |
1084 | |
1085 | /* If we can't reach the device, signal failure */ | |
5c15c23a | 1086 | if (err) |
712ac5b3 | 1087 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
1088 | } |
1089 | ||
9a95e60e | 1090 | /* return total length of buffer chain */ |
e92eedf4 | 1091 | static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus) |
9a95e60e AS |
1092 | { |
1093 | struct sk_buff *p; | |
1094 | uint total; | |
1095 | ||
1096 | total = 0; | |
1097 | skb_queue_walk(&bus->glom, p) | |
1098 | total += p->len; | |
1099 | return total; | |
1100 | } | |
1101 | ||
e92eedf4 | 1102 | static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus) |
046808da AS |
1103 | { |
1104 | struct sk_buff *cur, *next; | |
1105 | ||
1106 | skb_queue_walk_safe(&bus->glom, cur, next) { | |
1107 | skb_unlink(cur, &bus->glom); | |
1108 | brcmu_pkt_buf_free_skb(cur); | |
1109 | } | |
1110 | } | |
1111 | ||
6bc52319 FL |
1112 | /** |
1113 | * brcmfmac sdio bus specific header | |
1114 | * This is the lowest layer header wrapped on the packets transmitted between | |
1115 | * host and WiFi dongle which contains information needed for SDIO core and | |
1116 | * firmware | |
1117 | * | |
8da9d2c8 FL |
1118 | * It consists of 3 parts: hardware header, hardware extension header and |
1119 | * software header | |
6bc52319 FL |
1120 | * hardware header (frame tag) - 4 bytes |
1121 | * Byte 0~1: Frame length | |
1122 | * Byte 2~3: Checksum, bit-wise inverse of frame length | |
8da9d2c8 FL |
1123 | * hardware extension header - 8 bytes |
1124 | * Tx glom mode only, N/A for Rx or normal Tx | |
1125 | * Byte 0~1: Packet length excluding hw frame tag | |
1126 | * Byte 2: Reserved | |
1127 | * Byte 3: Frame flags, bit 0: last frame indication | |
1128 | * Byte 4~5: Reserved | |
1129 | * Byte 6~7: Tail padding length | |
6bc52319 FL |
1130 | * software header - 8 bytes |
1131 | * Byte 0: Rx/Tx sequence number | |
1132 | * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag | |
1133 | * Byte 2: Length of next data frame, reserved for Tx | |
1134 | * Byte 3: Data offset | |
1135 | * Byte 4: Flow control bits, reserved for Tx | |
1136 | * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet | |
1137 | * Byte 6~7: Reserved | |
1138 | */ | |
1139 | #define SDPCM_HWHDR_LEN 4 | |
8da9d2c8 | 1140 | #define SDPCM_HWEXT_LEN 8 |
6bc52319 FL |
1141 | #define SDPCM_SWHDR_LEN 8 |
1142 | #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) | |
6bc52319 FL |
1143 | /* software header */ |
1144 | #define SDPCM_SEQ_MASK 0x000000ff | |
1145 | #define SDPCM_SEQ_WRAP 256 | |
1146 | #define SDPCM_CHANNEL_MASK 0x00000f00 | |
1147 | #define SDPCM_CHANNEL_SHIFT 8 | |
1148 | #define SDPCM_CONTROL_CHANNEL 0 /* Control */ | |
1149 | #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ | |
1150 | #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ | |
1151 | #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ | |
1152 | #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ | |
1153 | #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) | |
1154 | #define SDPCM_NEXTLEN_MASK 0x00ff0000 | |
1155 | #define SDPCM_NEXTLEN_SHIFT 16 | |
1156 | #define SDPCM_DOFFSET_MASK 0xff000000 | |
1157 | #define SDPCM_DOFFSET_SHIFT 24 | |
1158 | #define SDPCM_FCMASK_MASK 0x000000ff | |
1159 | #define SDPCM_WINDOW_MASK 0x0000ff00 | |
1160 | #define SDPCM_WINDOW_SHIFT 8 | |
1161 | ||
1162 | static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) | |
1163 | { | |
1164 | u32 hdrvalue; | |
1165 | hdrvalue = *(u32 *)swheader; | |
1166 | return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); | |
1167 | } | |
1168 | ||
1169 | static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, | |
1170 | struct brcmf_sdio_hdrinfo *rd, | |
1171 | enum brcmf_sdio_frmtype type) | |
4754fcee FL |
1172 | { |
1173 | u16 len, checksum; | |
1174 | u8 rx_seq, fc, tx_seq_max; | |
6bc52319 | 1175 | u32 swheader; |
4754fcee | 1176 | |
4b776961 | 1177 | trace_brcmf_sdpcm_hdr(SDPCM_RX, header); |
76584ece | 1178 | |
6bc52319 | 1179 | /* hw header */ |
4754fcee FL |
1180 | len = get_unaligned_le16(header); |
1181 | checksum = get_unaligned_le16(header + sizeof(u16)); | |
1182 | /* All zero means no more to read */ | |
1183 | if (!(len | checksum)) { | |
1184 | bus->rxpending = false; | |
10510589 | 1185 | return -ENODATA; |
4754fcee FL |
1186 | } |
1187 | if ((u16)(~(len ^ checksum))) { | |
5e8149f5 | 1188 | brcmf_err("HW header checksum error\n"); |
4754fcee FL |
1189 | bus->sdcnt.rx_badhdr++; |
1190 | brcmf_sdbrcm_rxfail(bus, false, false); | |
10510589 | 1191 | return -EIO; |
4754fcee FL |
1192 | } |
1193 | if (len < SDPCM_HDRLEN) { | |
5e8149f5 | 1194 | brcmf_err("HW header length error\n"); |
10510589 | 1195 | return -EPROTO; |
4754fcee | 1196 | } |
9d7d6f95 FL |
1197 | if (type == BRCMF_SDIO_FT_SUPER && |
1198 | (roundup(len, bus->blocksize) != rd->len)) { | |
5e8149f5 | 1199 | brcmf_err("HW superframe header length error\n"); |
10510589 | 1200 | return -EPROTO; |
9d7d6f95 FL |
1201 | } |
1202 | if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { | |
5e8149f5 | 1203 | brcmf_err("HW subframe header length error\n"); |
10510589 | 1204 | return -EPROTO; |
9d7d6f95 | 1205 | } |
4754fcee FL |
1206 | rd->len = len; |
1207 | ||
6bc52319 FL |
1208 | /* software header */ |
1209 | header += SDPCM_HWHDR_LEN; | |
1210 | swheader = le32_to_cpu(*(__le32 *)header); | |
1211 | if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { | |
5e8149f5 | 1212 | brcmf_err("Glom descriptor found in superframe head\n"); |
9d7d6f95 | 1213 | rd->len = 0; |
10510589 | 1214 | return -EINVAL; |
9d7d6f95 | 1215 | } |
6bc52319 FL |
1216 | rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); |
1217 | rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; | |
9d7d6f95 FL |
1218 | if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && |
1219 | type != BRCMF_SDIO_FT_SUPER) { | |
5e8149f5 | 1220 | brcmf_err("HW header length too long\n"); |
4754fcee FL |
1221 | bus->sdcnt.rx_toolong++; |
1222 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1223 | rd->len = 0; | |
10510589 | 1224 | return -EPROTO; |
4754fcee | 1225 | } |
9d7d6f95 | 1226 | if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { |
5e8149f5 | 1227 | brcmf_err("Wrong channel for superframe\n"); |
9d7d6f95 | 1228 | rd->len = 0; |
10510589 | 1229 | return -EINVAL; |
9d7d6f95 FL |
1230 | } |
1231 | if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && | |
1232 | rd->channel != SDPCM_EVENT_CHANNEL) { | |
5e8149f5 | 1233 | brcmf_err("Wrong channel for subframe\n"); |
9d7d6f95 | 1234 | rd->len = 0; |
10510589 | 1235 | return -EINVAL; |
9d7d6f95 | 1236 | } |
6bc52319 | 1237 | rd->dat_offset = brcmf_sdio_getdatoffset(header); |
4754fcee | 1238 | if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { |
5e8149f5 | 1239 | brcmf_err("seq %d: bad data offset\n", rx_seq); |
4754fcee FL |
1240 | bus->sdcnt.rx_badhdr++; |
1241 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1242 | rd->len = 0; | |
10510589 | 1243 | return -ENXIO; |
4754fcee FL |
1244 | } |
1245 | if (rd->seq_num != rx_seq) { | |
5e8149f5 | 1246 | brcmf_err("seq %d: sequence number error, expect %d\n", |
4754fcee FL |
1247 | rx_seq, rd->seq_num); |
1248 | bus->sdcnt.rx_badseq++; | |
1249 | rd->seq_num = rx_seq; | |
1250 | } | |
9d7d6f95 FL |
1251 | /* no need to check the reset for subframe */ |
1252 | if (type == BRCMF_SDIO_FT_SUB) | |
10510589 | 1253 | return 0; |
6bc52319 | 1254 | rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; |
4754fcee FL |
1255 | if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { |
1256 | /* only warm for NON glom packet */ | |
1257 | if (rd->channel != SDPCM_GLOM_CHANNEL) | |
5e8149f5 | 1258 | brcmf_err("seq %d: next length error\n", rx_seq); |
4754fcee FL |
1259 | rd->len_nxtfrm = 0; |
1260 | } | |
6bc52319 FL |
1261 | swheader = le32_to_cpu(*(__le32 *)(header + 4)); |
1262 | fc = swheader & SDPCM_FCMASK_MASK; | |
4754fcee FL |
1263 | if (bus->flowcontrol != fc) { |
1264 | if (~bus->flowcontrol & fc) | |
1265 | bus->sdcnt.fc_xoff++; | |
1266 | if (bus->flowcontrol & ~fc) | |
1267 | bus->sdcnt.fc_xon++; | |
1268 | bus->sdcnt.fc_rcvd++; | |
1269 | bus->flowcontrol = fc; | |
1270 | } | |
6bc52319 | 1271 | tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; |
4754fcee | 1272 | if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { |
5e8149f5 | 1273 | brcmf_err("seq %d: max tx seq number error\n", rx_seq); |
4754fcee FL |
1274 | tx_seq_max = bus->tx_seq + 2; |
1275 | } | |
1276 | bus->tx_max = tx_seq_max; | |
1277 | ||
10510589 | 1278 | return 0; |
4754fcee FL |
1279 | } |
1280 | ||
6bc52319 FL |
1281 | static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) |
1282 | { | |
1283 | *(__le16 *)header = cpu_to_le16(frm_length); | |
1284 | *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); | |
1285 | } | |
1286 | ||
1287 | static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, | |
1288 | struct brcmf_sdio_hdrinfo *hd_info) | |
1289 | { | |
8da9d2c8 FL |
1290 | u32 hdrval; |
1291 | u8 hdr_offset; | |
6bc52319 FL |
1292 | |
1293 | brcmf_sdio_update_hwhdr(header, hd_info->len); | |
8da9d2c8 FL |
1294 | hdr_offset = SDPCM_HWHDR_LEN; |
1295 | ||
1296 | if (bus->txglom) { | |
1297 | hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); | |
1298 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1299 | hdrval = (u16)hd_info->tail_pad << 16; | |
1300 | *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); | |
1301 | hdr_offset += SDPCM_HWEXT_LEN; | |
1302 | } | |
6bc52319 | 1303 | |
8da9d2c8 FL |
1304 | hdrval = hd_info->seq_num; |
1305 | hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & | |
1306 | SDPCM_CHANNEL_MASK; | |
1307 | hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & | |
1308 | SDPCM_DOFFSET_MASK; | |
1309 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1310 | *(((__le32 *)(header + hdr_offset)) + 1) = 0; | |
1311 | trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); | |
6bc52319 FL |
1312 | } |
1313 | ||
e92eedf4 | 1314 | static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq) |
5b435de0 AS |
1315 | { |
1316 | u16 dlen, totlen; | |
1317 | u8 *dptr, num = 0; | |
9d7d6f95 | 1318 | u16 sublen; |
0b45bf74 | 1319 | struct sk_buff *pfirst, *pnext; |
5b435de0 AS |
1320 | |
1321 | int errcode; | |
9d7d6f95 | 1322 | u8 doff, sfdoff; |
5b435de0 | 1323 | |
6bc52319 | 1324 | struct brcmf_sdio_hdrinfo rd_new; |
5b435de0 AS |
1325 | |
1326 | /* If packets, issue read(s) and send up packet chain */ | |
1327 | /* Return sequence numbers consumed? */ | |
1328 | ||
c3203374 | 1329 | brcmf_dbg(SDIO, "start: glomd %p glom %p\n", |
b83db862 | 1330 | bus->glomd, skb_peek(&bus->glom)); |
5b435de0 AS |
1331 | |
1332 | /* If there's a descriptor, generate the packet chain */ | |
1333 | if (bus->glomd) { | |
0b45bf74 | 1334 | pfirst = pnext = NULL; |
5b435de0 AS |
1335 | dlen = (u16) (bus->glomd->len); |
1336 | dptr = bus->glomd->data; | |
1337 | if (!dlen || (dlen & 1)) { | |
5e8149f5 | 1338 | brcmf_err("bad glomd len(%d), ignore descriptor\n", |
5b435de0 AS |
1339 | dlen); |
1340 | dlen = 0; | |
1341 | } | |
1342 | ||
1343 | for (totlen = num = 0; dlen; num++) { | |
1344 | /* Get (and move past) next length */ | |
1345 | sublen = get_unaligned_le16(dptr); | |
1346 | dlen -= sizeof(u16); | |
1347 | dptr += sizeof(u16); | |
1348 | if ((sublen < SDPCM_HDRLEN) || | |
1349 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | |
5e8149f5 | 1350 | brcmf_err("descriptor len %d bad: %d\n", |
5b435de0 AS |
1351 | num, sublen); |
1352 | pnext = NULL; | |
1353 | break; | |
1354 | } | |
e217d1c8 | 1355 | if (sublen % bus->sgentry_align) { |
5e8149f5 | 1356 | brcmf_err("sublen %d not multiple of %d\n", |
e217d1c8 | 1357 | sublen, bus->sgentry_align); |
5b435de0 AS |
1358 | } |
1359 | totlen += sublen; | |
1360 | ||
1361 | /* For last frame, adjust read len so total | |
1362 | is a block multiple */ | |
1363 | if (!dlen) { | |
1364 | sublen += | |
1365 | (roundup(totlen, bus->blocksize) - totlen); | |
1366 | totlen = roundup(totlen, bus->blocksize); | |
1367 | } | |
1368 | ||
1369 | /* Allocate/chain packet for next subframe */ | |
e217d1c8 | 1370 | pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); |
5b435de0 | 1371 | if (pnext == NULL) { |
5e8149f5 | 1372 | brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", |
5b435de0 AS |
1373 | num, sublen); |
1374 | break; | |
1375 | } | |
b83db862 | 1376 | skb_queue_tail(&bus->glom, pnext); |
5b435de0 AS |
1377 | |
1378 | /* Adhere to start alignment requirements */ | |
e217d1c8 | 1379 | pkt_align(pnext, sublen, bus->sgentry_align); |
5b435de0 AS |
1380 | } |
1381 | ||
1382 | /* If all allocations succeeded, save packet chain | |
1383 | in bus structure */ | |
1384 | if (pnext) { | |
1385 | brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", | |
1386 | totlen, num); | |
4754fcee FL |
1387 | if (BRCMF_GLOM_ON() && bus->cur_read.len && |
1388 | totlen != bus->cur_read.len) { | |
5b435de0 | 1389 | brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", |
4754fcee | 1390 | bus->cur_read.len, totlen, rxseq); |
5b435de0 | 1391 | } |
5b435de0 AS |
1392 | pfirst = pnext = NULL; |
1393 | } else { | |
046808da | 1394 | brcmf_sdbrcm_free_glom(bus); |
5b435de0 AS |
1395 | num = 0; |
1396 | } | |
1397 | ||
1398 | /* Done with descriptor packet */ | |
1399 | brcmu_pkt_buf_free_skb(bus->glomd); | |
1400 | bus->glomd = NULL; | |
4754fcee | 1401 | bus->cur_read.len = 0; |
5b435de0 AS |
1402 | } |
1403 | ||
1404 | /* Ok -- either we just generated a packet chain, | |
1405 | or had one from before */ | |
b83db862 | 1406 | if (!skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1407 | if (BRCMF_GLOM_ON()) { |
1408 | brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); | |
b83db862 | 1409 | skb_queue_walk(&bus->glom, pnext) { |
5b435de0 AS |
1410 | brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", |
1411 | pnext, (u8 *) (pnext->data), | |
1412 | pnext->len, pnext->len); | |
1413 | } | |
1414 | } | |
1415 | ||
b83db862 | 1416 | pfirst = skb_peek(&bus->glom); |
9a95e60e | 1417 | dlen = (u16) brcmf_sdbrcm_glom_len(bus); |
5b435de0 AS |
1418 | |
1419 | /* Do an SDIO read for the superframe. Configurable iovar to | |
1420 | * read directly into the chained packet, or allocate a large | |
1421 | * packet and and copy into the chain. | |
1422 | */ | |
38b0b0dd | 1423 | sdio_claim_host(bus->sdiodev->func[1]); |
354b75bf FL |
1424 | errcode = brcmf_sdcard_recv_chain(bus->sdiodev, |
1425 | bus->sdiodev->sbwad, | |
a413e39a | 1426 | SDIO_FUNC_2, F2SYNC, &bus->glom, dlen); |
38b0b0dd | 1427 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 1428 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1429 | |
1430 | /* On failure, kill the superframe, allow a couple retries */ | |
1431 | if (errcode < 0) { | |
5e8149f5 | 1432 | brcmf_err("glom read of %d bytes failed: %d\n", |
5b435de0 | 1433 | dlen, errcode); |
5b435de0 | 1434 | |
38b0b0dd | 1435 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1436 | if (bus->glomerr++ < 3) { |
1437 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1438 | } else { | |
1439 | bus->glomerr = 0; | |
1440 | brcmf_sdbrcm_rxfail(bus, true, false); | |
80969836 | 1441 | bus->sdcnt.rxglomfail++; |
046808da | 1442 | brcmf_sdbrcm_free_glom(bus); |
5b435de0 | 1443 | } |
38b0b0dd | 1444 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1445 | return 0; |
1446 | } | |
1e023829 JP |
1447 | |
1448 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), | |
1449 | pfirst->data, min_t(int, pfirst->len, 48), | |
1450 | "SUPERFRAME:\n"); | |
5b435de0 | 1451 | |
9d7d6f95 FL |
1452 | rd_new.seq_num = rxseq; |
1453 | rd_new.len = dlen; | |
38b0b0dd | 1454 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1455 | errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, |
1456 | BRCMF_SDIO_FT_SUPER); | |
38b0b0dd | 1457 | sdio_release_host(bus->sdiodev->func[1]); |
9d7d6f95 | 1458 | bus->cur_read.len = rd_new.len_nxtfrm << 4; |
5b435de0 AS |
1459 | |
1460 | /* Remove superframe header, remember offset */ | |
9d7d6f95 FL |
1461 | skb_pull(pfirst, rd_new.dat_offset); |
1462 | sfdoff = rd_new.dat_offset; | |
0b45bf74 | 1463 | num = 0; |
5b435de0 AS |
1464 | |
1465 | /* Validate all the subframe headers */ | |
0b45bf74 AS |
1466 | skb_queue_walk(&bus->glom, pnext) { |
1467 | /* leave when invalid subframe is found */ | |
1468 | if (errcode) | |
1469 | break; | |
1470 | ||
9d7d6f95 FL |
1471 | rd_new.len = pnext->len; |
1472 | rd_new.seq_num = rxseq++; | |
38b0b0dd | 1473 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1474 | errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, |
1475 | BRCMF_SDIO_FT_SUB); | |
38b0b0dd | 1476 | sdio_release_host(bus->sdiodev->func[1]); |
1e023829 | 1477 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
9d7d6f95 | 1478 | pnext->data, 32, "subframe:\n"); |
5b435de0 | 1479 | |
0b45bf74 | 1480 | num++; |
5b435de0 AS |
1481 | } |
1482 | ||
1483 | if (errcode) { | |
1484 | /* Terminate frame on error, request | |
1485 | a couple retries */ | |
38b0b0dd | 1486 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1487 | if (bus->glomerr++ < 3) { |
1488 | /* Restore superframe header space */ | |
1489 | skb_push(pfirst, sfdoff); | |
1490 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1491 | } else { | |
1492 | bus->glomerr = 0; | |
1493 | brcmf_sdbrcm_rxfail(bus, true, false); | |
80969836 | 1494 | bus->sdcnt.rxglomfail++; |
046808da | 1495 | brcmf_sdbrcm_free_glom(bus); |
5b435de0 | 1496 | } |
38b0b0dd | 1497 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee | 1498 | bus->cur_read.len = 0; |
5b435de0 AS |
1499 | return 0; |
1500 | } | |
1501 | ||
1502 | /* Basic SD framing looks ok - process each packet (header) */ | |
5b435de0 | 1503 | |
0b45bf74 | 1504 | skb_queue_walk_safe(&bus->glom, pfirst, pnext) { |
5b435de0 AS |
1505 | dptr = (u8 *) (pfirst->data); |
1506 | sublen = get_unaligned_le16(dptr); | |
6bc52319 | 1507 | doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); |
5b435de0 | 1508 | |
1e023829 | 1509 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
9d7d6f95 FL |
1510 | dptr, pfirst->len, |
1511 | "Rx Subframe Data:\n"); | |
5b435de0 AS |
1512 | |
1513 | __skb_trim(pfirst, sublen); | |
1514 | skb_pull(pfirst, doff); | |
1515 | ||
1516 | if (pfirst->len == 0) { | |
0b45bf74 | 1517 | skb_unlink(pfirst, &bus->glom); |
5b435de0 | 1518 | brcmu_pkt_buf_free_skb(pfirst); |
5b435de0 | 1519 | continue; |
5b435de0 AS |
1520 | } |
1521 | ||
1e023829 JP |
1522 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
1523 | pfirst->data, | |
1524 | min_t(int, pfirst->len, 32), | |
1525 | "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", | |
1526 | bus->glom.qlen, pfirst, pfirst->data, | |
1527 | pfirst->len, pfirst->next, | |
1528 | pfirst->prev); | |
05f3820b AS |
1529 | skb_unlink(pfirst, &bus->glom); |
1530 | brcmf_rx_frame(bus->sdiodev->dev, pfirst); | |
1531 | bus->sdcnt.rxglompkts++; | |
5b435de0 | 1532 | } |
5b435de0 | 1533 | |
80969836 | 1534 | bus->sdcnt.rxglomframes++; |
5b435de0 AS |
1535 | } |
1536 | return num; | |
1537 | } | |
1538 | ||
e92eedf4 | 1539 | static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, |
5b435de0 AS |
1540 | bool *pending) |
1541 | { | |
1542 | DECLARE_WAITQUEUE(wait, current); | |
1543 | int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT); | |
1544 | ||
1545 | /* Wait until control frame is available */ | |
1546 | add_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1547 | set_current_state(TASK_INTERRUPTIBLE); | |
1548 | ||
1549 | while (!(*condition) && (!signal_pending(current) && timeout)) | |
1550 | timeout = schedule_timeout(timeout); | |
1551 | ||
1552 | if (signal_pending(current)) | |
1553 | *pending = true; | |
1554 | ||
1555 | set_current_state(TASK_RUNNING); | |
1556 | remove_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1557 | ||
1558 | return timeout; | |
1559 | } | |
1560 | ||
e92eedf4 | 1561 | static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus) |
5b435de0 AS |
1562 | { |
1563 | if (waitqueue_active(&bus->dcmd_resp_wait)) | |
1564 | wake_up_interruptible(&bus->dcmd_resp_wait); | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | static void | |
e92eedf4 | 1569 | brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) |
5b435de0 AS |
1570 | { |
1571 | uint rdlen, pad; | |
dd43a01c | 1572 | u8 *buf = NULL, *rbuf; |
5b435de0 AS |
1573 | int sdret; |
1574 | ||
1575 | brcmf_dbg(TRACE, "Enter\n"); | |
1576 | ||
dd43a01c FL |
1577 | if (bus->rxblen) |
1578 | buf = vzalloc(bus->rxblen); | |
14f8dc49 | 1579 | if (!buf) |
dd43a01c | 1580 | goto done; |
14f8dc49 | 1581 | |
dd43a01c FL |
1582 | rbuf = bus->rxbuf; |
1583 | pad = ((unsigned long)rbuf % BRCMF_SDALIGN); | |
5b435de0 | 1584 | if (pad) |
dd43a01c | 1585 | rbuf += (BRCMF_SDALIGN - pad); |
5b435de0 AS |
1586 | |
1587 | /* Copy the already-read portion over */ | |
dd43a01c | 1588 | memcpy(buf, hdr, BRCMF_FIRSTREAD); |
5b435de0 AS |
1589 | if (len <= BRCMF_FIRSTREAD) |
1590 | goto gotpkt; | |
1591 | ||
1592 | /* Raise rdlen to next SDIO block to avoid tail command */ | |
1593 | rdlen = len - BRCMF_FIRSTREAD; | |
1594 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
1595 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
1596 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
b01a6b3c | 1597 | ((len + pad) < bus->sdiodev->bus_if->maxctl)) |
5b435de0 AS |
1598 | rdlen += pad; |
1599 | } else if (rdlen % BRCMF_SDALIGN) { | |
1600 | rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN); | |
1601 | } | |
1602 | ||
1603 | /* Satisfy length-alignment requirements */ | |
1604 | if (rdlen & (ALIGNMENT - 1)) | |
1605 | rdlen = roundup(rdlen, ALIGNMENT); | |
1606 | ||
1607 | /* Drop if the read is too big or it exceeds our maximum */ | |
b01a6b3c | 1608 | if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1609 | brcmf_err("%d-byte control read exceeds %d-byte buffer\n", |
b01a6b3c | 1610 | rdlen, bus->sdiodev->bus_if->maxctl); |
5b435de0 AS |
1611 | brcmf_sdbrcm_rxfail(bus, false, false); |
1612 | goto done; | |
1613 | } | |
1614 | ||
b01a6b3c | 1615 | if ((len - doff) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1616 | brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", |
b01a6b3c | 1617 | len, len - doff, bus->sdiodev->bus_if->maxctl); |
80969836 | 1618 | bus->sdcnt.rx_toolong++; |
5b435de0 AS |
1619 | brcmf_sdbrcm_rxfail(bus, false, false); |
1620 | goto done; | |
1621 | } | |
1622 | ||
dd43a01c | 1623 | /* Read remain of frame body */ |
5b435de0 AS |
1624 | sdret = brcmf_sdcard_recv_buf(bus->sdiodev, |
1625 | bus->sdiodev->sbwad, | |
1626 | SDIO_FUNC_2, | |
dd43a01c | 1627 | F2SYNC, rbuf, rdlen); |
80969836 | 1628 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1629 | |
1630 | /* Control frame failures need retransmission */ | |
1631 | if (sdret < 0) { | |
5e8149f5 | 1632 | brcmf_err("read %d control bytes failed: %d\n", |
5b435de0 | 1633 | rdlen, sdret); |
80969836 | 1634 | bus->sdcnt.rxc_errors++; |
5b435de0 AS |
1635 | brcmf_sdbrcm_rxfail(bus, true, true); |
1636 | goto done; | |
dd43a01c FL |
1637 | } else |
1638 | memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); | |
5b435de0 AS |
1639 | |
1640 | gotpkt: | |
1641 | ||
1e023829 | 1642 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
dd43a01c | 1643 | buf, len, "RxCtrl:\n"); |
5b435de0 AS |
1644 | |
1645 | /* Point to valid data and indicate its length */ | |
dd43a01c FL |
1646 | spin_lock_bh(&bus->rxctl_lock); |
1647 | if (bus->rxctl) { | |
5e8149f5 | 1648 | brcmf_err("last control frame is being processed.\n"); |
dd43a01c FL |
1649 | spin_unlock_bh(&bus->rxctl_lock); |
1650 | vfree(buf); | |
1651 | goto done; | |
1652 | } | |
1653 | bus->rxctl = buf + doff; | |
1654 | bus->rxctl_orig = buf; | |
5b435de0 | 1655 | bus->rxlen = len - doff; |
dd43a01c | 1656 | spin_unlock_bh(&bus->rxctl_lock); |
5b435de0 AS |
1657 | |
1658 | done: | |
1659 | /* Awake any waiters */ | |
1660 | brcmf_sdbrcm_dcmd_resp_wake(bus); | |
1661 | } | |
1662 | ||
1663 | /* Pad read to blocksize for efficiency */ | |
e92eedf4 | 1664 | static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) |
5b435de0 AS |
1665 | { |
1666 | if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { | |
1667 | *pad = bus->blocksize - (*rdlen % bus->blocksize); | |
1668 | if (*pad <= bus->roundup && *pad < bus->blocksize && | |
1669 | *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) | |
1670 | *rdlen += *pad; | |
1671 | } else if (*rdlen % BRCMF_SDALIGN) { | |
1672 | *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN); | |
1673 | } | |
1674 | } | |
1675 | ||
4754fcee | 1676 | static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 | 1677 | { |
5b435de0 AS |
1678 | struct sk_buff *pkt; /* Packet for event or data frames */ |
1679 | u16 pad; /* Number of pad bytes to read */ | |
5b435de0 | 1680 | uint rxleft = 0; /* Remaining number of frames allowed */ |
349e7104 | 1681 | int ret; /* Return code from calls */ |
5b435de0 | 1682 | uint rxcount = 0; /* Total frames read */ |
6bc52319 | 1683 | struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; |
4754fcee | 1684 | u8 head_read = 0; |
5b435de0 AS |
1685 | |
1686 | brcmf_dbg(TRACE, "Enter\n"); | |
1687 | ||
1688 | /* Not finished unless we encounter no more frames indication */ | |
4754fcee | 1689 | bus->rxpending = true; |
5b435de0 | 1690 | |
4754fcee | 1691 | for (rd->seq_num = bus->rx_seq, rxleft = maxframes; |
8d169aa0 | 1692 | !bus->rxskip && rxleft && |
712ac5b3 | 1693 | bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN; |
4754fcee | 1694 | rd->seq_num++, rxleft--) { |
5b435de0 AS |
1695 | |
1696 | /* Handle glomming separately */ | |
b83db862 | 1697 | if (bus->glomd || !skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1698 | u8 cnt; |
1699 | brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", | |
b83db862 | 1700 | bus->glomd, skb_peek(&bus->glom)); |
4754fcee | 1701 | cnt = brcmf_sdbrcm_rxglom(bus, rd->seq_num); |
5b435de0 | 1702 | brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); |
4754fcee | 1703 | rd->seq_num += cnt - 1; |
5b435de0 AS |
1704 | rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; |
1705 | continue; | |
1706 | } | |
1707 | ||
4754fcee FL |
1708 | rd->len_left = rd->len; |
1709 | /* read header first for unknow frame length */ | |
38b0b0dd | 1710 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee | 1711 | if (!rd->len) { |
349e7104 | 1712 | ret = brcmf_sdcard_recv_buf(bus->sdiodev, |
4754fcee FL |
1713 | bus->sdiodev->sbwad, |
1714 | SDIO_FUNC_2, F2SYNC, | |
1715 | bus->rxhdr, | |
1716 | BRCMF_FIRSTREAD); | |
1717 | bus->sdcnt.f2rxhdrs++; | |
349e7104 | 1718 | if (ret < 0) { |
5e8149f5 | 1719 | brcmf_err("RXHEADER FAILED: %d\n", |
349e7104 | 1720 | ret); |
4754fcee FL |
1721 | bus->sdcnt.rx_hdrfail++; |
1722 | brcmf_sdbrcm_rxfail(bus, true, true); | |
38b0b0dd | 1723 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1724 | continue; |
5b435de0 | 1725 | } |
5b435de0 | 1726 | |
4754fcee | 1727 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), |
1e023829 JP |
1728 | bus->rxhdr, SDPCM_HDRLEN, |
1729 | "RxHdr:\n"); | |
5b435de0 | 1730 | |
6bc52319 FL |
1731 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, |
1732 | BRCMF_SDIO_FT_NORMAL)) { | |
38b0b0dd | 1733 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1734 | if (!bus->rxpending) |
1735 | break; | |
1736 | else | |
1737 | continue; | |
5b435de0 AS |
1738 | } |
1739 | ||
4754fcee FL |
1740 | if (rd->channel == SDPCM_CONTROL_CHANNEL) { |
1741 | brcmf_sdbrcm_read_control(bus, bus->rxhdr, | |
1742 | rd->len, | |
1743 | rd->dat_offset); | |
1744 | /* prepare the descriptor for the next read */ | |
1745 | rd->len = rd->len_nxtfrm << 4; | |
1746 | rd->len_nxtfrm = 0; | |
1747 | /* treat all packet as event if we don't know */ | |
1748 | rd->channel = SDPCM_EVENT_CHANNEL; | |
38b0b0dd | 1749 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1750 | continue; |
1751 | } | |
4754fcee FL |
1752 | rd->len_left = rd->len > BRCMF_FIRSTREAD ? |
1753 | rd->len - BRCMF_FIRSTREAD : 0; | |
1754 | head_read = BRCMF_FIRSTREAD; | |
5b435de0 AS |
1755 | } |
1756 | ||
4754fcee | 1757 | brcmf_pad(bus, &pad, &rd->len_left); |
5b435de0 | 1758 | |
4754fcee FL |
1759 | pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + |
1760 | BRCMF_SDALIGN); | |
5b435de0 AS |
1761 | if (!pkt) { |
1762 | /* Give up on data, request rtx of events */ | |
5e8149f5 | 1763 | brcmf_err("brcmu_pkt_buf_get_skb failed\n"); |
4754fcee FL |
1764 | brcmf_sdbrcm_rxfail(bus, false, |
1765 | RETRYCHAN(rd->channel)); | |
38b0b0dd | 1766 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1767 | continue; |
1768 | } | |
4754fcee FL |
1769 | skb_pull(pkt, head_read); |
1770 | pkt_align(pkt, rd->len_left, BRCMF_SDALIGN); | |
5b435de0 | 1771 | |
349e7104 | 1772 | ret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad, |
5adfeb63 | 1773 | SDIO_FUNC_2, F2SYNC, pkt); |
80969836 | 1774 | bus->sdcnt.f2rxdata++; |
38b0b0dd | 1775 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1776 | |
349e7104 | 1777 | if (ret < 0) { |
5e8149f5 | 1778 | brcmf_err("read %d bytes from channel %d failed: %d\n", |
349e7104 | 1779 | rd->len, rd->channel, ret); |
5b435de0 | 1780 | brcmu_pkt_buf_free_skb(pkt); |
38b0b0dd | 1781 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee FL |
1782 | brcmf_sdbrcm_rxfail(bus, true, |
1783 | RETRYCHAN(rd->channel)); | |
38b0b0dd | 1784 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1785 | continue; |
1786 | } | |
1787 | ||
4754fcee FL |
1788 | if (head_read) { |
1789 | skb_push(pkt, head_read); | |
1790 | memcpy(pkt->data, bus->rxhdr, head_read); | |
1791 | head_read = 0; | |
1792 | } else { | |
1793 | memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); | |
1794 | rd_new.seq_num = rd->seq_num; | |
38b0b0dd | 1795 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1796 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, |
1797 | BRCMF_SDIO_FT_NORMAL)) { | |
4754fcee FL |
1798 | rd->len = 0; |
1799 | brcmu_pkt_buf_free_skb(pkt); | |
1800 | } | |
1801 | bus->sdcnt.rx_readahead_cnt++; | |
1802 | if (rd->len != roundup(rd_new.len, 16)) { | |
5e8149f5 | 1803 | brcmf_err("frame length mismatch:read %d, should be %d\n", |
4754fcee FL |
1804 | rd->len, |
1805 | roundup(rd_new.len, 16) >> 4); | |
1806 | rd->len = 0; | |
1807 | brcmf_sdbrcm_rxfail(bus, true, true); | |
38b0b0dd | 1808 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1809 | brcmu_pkt_buf_free_skb(pkt); |
1810 | continue; | |
1811 | } | |
38b0b0dd | 1812 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1813 | rd->len_nxtfrm = rd_new.len_nxtfrm; |
1814 | rd->channel = rd_new.channel; | |
1815 | rd->dat_offset = rd_new.dat_offset; | |
1816 | ||
1817 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && | |
1818 | BRCMF_DATA_ON()) && | |
1819 | BRCMF_HDRS_ON(), | |
1820 | bus->rxhdr, SDPCM_HDRLEN, | |
1821 | "RxHdr:\n"); | |
1822 | ||
1823 | if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { | |
5e8149f5 | 1824 | brcmf_err("readahead on control packet %d?\n", |
4754fcee FL |
1825 | rd_new.seq_num); |
1826 | /* Force retry w/normal header read */ | |
1827 | rd->len = 0; | |
38b0b0dd | 1828 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee | 1829 | brcmf_sdbrcm_rxfail(bus, false, true); |
38b0b0dd | 1830 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1831 | brcmu_pkt_buf_free_skb(pkt); |
1832 | continue; | |
1833 | } | |
1834 | } | |
5b435de0 | 1835 | |
1e023829 | 1836 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
4754fcee | 1837 | pkt->data, rd->len, "Rx Data:\n"); |
5b435de0 | 1838 | |
5b435de0 | 1839 | /* Save superframe descriptor and allocate packet frame */ |
4754fcee | 1840 | if (rd->channel == SDPCM_GLOM_CHANNEL) { |
6bc52319 | 1841 | if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { |
5b435de0 | 1842 | brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", |
4754fcee | 1843 | rd->len); |
1e023829 | 1844 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
4754fcee | 1845 | pkt->data, rd->len, |
1e023829 | 1846 | "Glom Data:\n"); |
4754fcee | 1847 | __skb_trim(pkt, rd->len); |
5b435de0 AS |
1848 | skb_pull(pkt, SDPCM_HDRLEN); |
1849 | bus->glomd = pkt; | |
1850 | } else { | |
5e8149f5 | 1851 | brcmf_err("%s: glom superframe w/o " |
5b435de0 | 1852 | "descriptor!\n", __func__); |
38b0b0dd | 1853 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 1854 | brcmf_sdbrcm_rxfail(bus, false, false); |
38b0b0dd | 1855 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1856 | } |
4754fcee FL |
1857 | /* prepare the descriptor for the next read */ |
1858 | rd->len = rd->len_nxtfrm << 4; | |
1859 | rd->len_nxtfrm = 0; | |
1860 | /* treat all packet as event if we don't know */ | |
1861 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
1862 | continue; |
1863 | } | |
1864 | ||
1865 | /* Fill in packet len and prio, deliver upward */ | |
4754fcee FL |
1866 | __skb_trim(pkt, rd->len); |
1867 | skb_pull(pkt, rd->dat_offset); | |
1868 | ||
1869 | /* prepare the descriptor for the next read */ | |
1870 | rd->len = rd->len_nxtfrm << 4; | |
1871 | rd->len_nxtfrm = 0; | |
1872 | /* treat all packet as event if we don't know */ | |
1873 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
1874 | |
1875 | if (pkt->len == 0) { | |
1876 | brcmu_pkt_buf_free_skb(pkt); | |
1877 | continue; | |
5b435de0 AS |
1878 | } |
1879 | ||
05f3820b | 1880 | brcmf_rx_frame(bus->sdiodev->dev, pkt); |
5b435de0 | 1881 | } |
4754fcee | 1882 | |
5b435de0 | 1883 | rxcount = maxframes - rxleft; |
5b435de0 AS |
1884 | /* Message if we hit the limit */ |
1885 | if (!rxleft) | |
4754fcee | 1886 | brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); |
5b435de0 | 1887 | else |
5b435de0 AS |
1888 | brcmf_dbg(DATA, "processed %d frames\n", rxcount); |
1889 | /* Back off rxseq if awaiting rtx, update rx_seq */ | |
1890 | if (bus->rxskip) | |
4754fcee FL |
1891 | rd->seq_num--; |
1892 | bus->rx_seq = rd->seq_num; | |
5b435de0 AS |
1893 | |
1894 | return rxcount; | |
1895 | } | |
1896 | ||
5b435de0 | 1897 | static void |
e92eedf4 | 1898 | brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus) |
5b435de0 AS |
1899 | { |
1900 | if (waitqueue_active(&bus->ctrl_wait)) | |
1901 | wake_up_interruptible(&bus->ctrl_wait); | |
1902 | return; | |
1903 | } | |
1904 | ||
8da9d2c8 FL |
1905 | static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) |
1906 | { | |
e217d1c8 | 1907 | u16 head_pad; |
8da9d2c8 FL |
1908 | u8 *dat_buf; |
1909 | ||
8da9d2c8 FL |
1910 | dat_buf = (u8 *)(pkt->data); |
1911 | ||
1912 | /* Check head padding */ | |
e217d1c8 | 1913 | head_pad = ((unsigned long)dat_buf % bus->head_align); |
8da9d2c8 FL |
1914 | if (head_pad) { |
1915 | if (skb_headroom(pkt) < head_pad) { | |
1916 | bus->sdiodev->bus_if->tx_realloc++; | |
1917 | head_pad = 0; | |
1918 | if (skb_cow(pkt, head_pad)) | |
1919 | return -ENOMEM; | |
1920 | } | |
1921 | skb_push(pkt, head_pad); | |
1922 | dat_buf = (u8 *)(pkt->data); | |
1923 | memset(dat_buf, 0, head_pad + bus->tx_hdrlen); | |
1924 | } | |
1925 | return head_pad; | |
1926 | } | |
1927 | ||
5491c11c FL |
1928 | /** |
1929 | * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for | |
1930 | * bus layer usage. | |
1931 | */ | |
b05e9254 | 1932 | /* flag marking a dummy skb added for DMA alignment requirement */ |
5491c11c | 1933 | #define ALIGN_SKB_FLAG 0x8000 |
b05e9254 | 1934 | /* bit mask of data length chopped from the previous packet */ |
5491c11c FL |
1935 | #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff |
1936 | ||
8da9d2c8 | 1937 | static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, |
a64304f0 | 1938 | struct sk_buff_head *pktq, |
8da9d2c8 | 1939 | struct sk_buff *pkt, u16 total_len) |
a64304f0 | 1940 | { |
8da9d2c8 | 1941 | struct brcmf_sdio_dev *sdiodev; |
a64304f0 | 1942 | struct sk_buff *pkt_pad; |
e217d1c8 | 1943 | u16 tail_pad, tail_chop, chain_pad; |
a64304f0 | 1944 | unsigned int blksize; |
8da9d2c8 FL |
1945 | bool lastfrm; |
1946 | int ntail, ret; | |
a64304f0 | 1947 | |
8da9d2c8 | 1948 | sdiodev = bus->sdiodev; |
a64304f0 | 1949 | blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize; |
a64304f0 | 1950 | /* sg entry alignment should be a divisor of block size */ |
e217d1c8 | 1951 | WARN_ON(blksize % bus->sgentry_align); |
a64304f0 AS |
1952 | |
1953 | /* Check tail padding */ | |
8da9d2c8 FL |
1954 | lastfrm = skb_queue_is_last(pktq, pkt); |
1955 | tail_pad = 0; | |
e217d1c8 | 1956 | tail_chop = pkt->len % bus->sgentry_align; |
8da9d2c8 | 1957 | if (tail_chop) |
e217d1c8 | 1958 | tail_pad = bus->sgentry_align - tail_chop; |
8da9d2c8 FL |
1959 | chain_pad = (total_len + tail_pad) % blksize; |
1960 | if (lastfrm && chain_pad) | |
1961 | tail_pad += blksize - chain_pad; | |
a64304f0 | 1962 | if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { |
8da9d2c8 FL |
1963 | pkt_pad = bus->txglom_sgpad; |
1964 | if (pkt_pad == NULL) | |
1965 | brcmu_pkt_buf_get_skb(tail_pad + tail_chop); | |
a64304f0 AS |
1966 | if (pkt_pad == NULL) |
1967 | return -ENOMEM; | |
8da9d2c8 FL |
1968 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); |
1969 | if (unlikely(ret < 0)) | |
1970 | return ret; | |
a64304f0 AS |
1971 | memcpy(pkt_pad->data, |
1972 | pkt->data + pkt->len - tail_chop, | |
1973 | tail_chop); | |
1974 | *(u32 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; | |
1975 | skb_trim(pkt, pkt->len - tail_chop); | |
1976 | __skb_queue_after(pktq, pkt, pkt_pad); | |
1977 | } else { | |
1978 | ntail = pkt->data_len + tail_pad - | |
1979 | (pkt->end - pkt->tail); | |
1980 | if (skb_cloned(pkt) || ntail > 0) | |
1981 | if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) | |
1982 | return -ENOMEM; | |
1983 | if (skb_linearize(pkt)) | |
1984 | return -ENOMEM; | |
a64304f0 AS |
1985 | __skb_put(pkt, tail_pad); |
1986 | } | |
1987 | ||
8da9d2c8 | 1988 | return tail_pad; |
a64304f0 AS |
1989 | } |
1990 | ||
b05e9254 FL |
1991 | /** |
1992 | * brcmf_sdio_txpkt_prep - packet preparation for transmit | |
1993 | * @bus: brcmf_sdio structure pointer | |
1994 | * @pktq: packet list pointer | |
1995 | * @chan: virtual channel to transmit the packet | |
1996 | * | |
1997 | * Processes to be applied to the packet | |
1998 | * - Align data buffer pointer | |
1999 | * - Align data buffer length | |
2000 | * - Prepare header | |
2001 | * Return: negative value if there is error | |
2002 | */ | |
2003 | static int | |
2004 | brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, | |
2005 | uint chan) | |
5b435de0 | 2006 | { |
8da9d2c8 | 2007 | u16 head_pad, total_len; |
a64304f0 | 2008 | struct sk_buff *pkt_next; |
8da9d2c8 FL |
2009 | u8 txseq; |
2010 | int ret; | |
6bc52319 | 2011 | struct brcmf_sdio_hdrinfo hd_info = {0}; |
b05e9254 | 2012 | |
8da9d2c8 FL |
2013 | txseq = bus->tx_seq; |
2014 | total_len = 0; | |
2015 | skb_queue_walk(pktq, pkt_next) { | |
2016 | /* alignment packet inserted in previous | |
2017 | * loop cycle can be skipped as it is | |
2018 | * already properly aligned and does not | |
2019 | * need an sdpcm header. | |
2020 | */ | |
2021 | if (*(u32 *)(pkt_next->cb) & ALIGN_SKB_FLAG) | |
2022 | continue; | |
5b435de0 | 2023 | |
8da9d2c8 FL |
2024 | /* align packet data pointer */ |
2025 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); | |
2026 | if (ret < 0) | |
2027 | return ret; | |
2028 | head_pad = (u16)ret; | |
2029 | if (head_pad) | |
2030 | memset(pkt_next->data, 0, head_pad + bus->tx_hdrlen); | |
5b435de0 | 2031 | |
8da9d2c8 | 2032 | total_len += pkt_next->len; |
5b435de0 | 2033 | |
a64304f0 | 2034 | hd_info.len = pkt_next->len; |
8da9d2c8 FL |
2035 | hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); |
2036 | if (bus->txglom && pktq->qlen > 1) { | |
2037 | ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, | |
2038 | pkt_next, total_len); | |
2039 | if (ret < 0) | |
2040 | return ret; | |
2041 | hd_info.tail_pad = (u16)ret; | |
2042 | total_len += (u16)ret; | |
2043 | } | |
5b435de0 | 2044 | |
8da9d2c8 FL |
2045 | hd_info.channel = chan; |
2046 | hd_info.dat_offset = head_pad + bus->tx_hdrlen; | |
2047 | hd_info.seq_num = txseq++; | |
2048 | ||
2049 | /* Now fill the header */ | |
2050 | brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); | |
2051 | ||
2052 | if (BRCMF_BYTES_ON() && | |
2053 | ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || | |
2054 | (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) | |
2055 | brcmf_dbg_hex_dump(true, pkt_next, hd_info.len, | |
2056 | "Tx Frame:\n"); | |
2057 | else if (BRCMF_HDRS_ON()) | |
2058 | brcmf_dbg_hex_dump(true, pkt_next, | |
2059 | head_pad + bus->tx_hdrlen, | |
2060 | "Tx Header:\n"); | |
2061 | } | |
2062 | /* Hardware length tag of the first packet should be total | |
2063 | * length of the chain (including padding) | |
2064 | */ | |
2065 | if (bus->txglom) | |
2066 | brcmf_sdio_update_hwhdr(pktq->next->data, total_len); | |
b05e9254 FL |
2067 | return 0; |
2068 | } | |
5b435de0 | 2069 | |
b05e9254 FL |
2070 | /** |
2071 | * brcmf_sdio_txpkt_postp - packet post processing for transmit | |
2072 | * @bus: brcmf_sdio structure pointer | |
2073 | * @pktq: packet list pointer | |
2074 | * | |
2075 | * Processes to be applied to the packet | |
2076 | * - Remove head padding | |
2077 | * - Remove tail padding | |
2078 | */ | |
2079 | static void | |
2080 | brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) | |
2081 | { | |
2082 | u8 *hdr; | |
2083 | u32 dat_offset; | |
8da9d2c8 | 2084 | u16 tail_pad; |
b05e9254 FL |
2085 | u32 dummy_flags, chop_len; |
2086 | struct sk_buff *pkt_next, *tmp, *pkt_prev; | |
2087 | ||
2088 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
2089 | dummy_flags = *(u32 *)(pkt_next->cb); | |
5491c11c FL |
2090 | if (dummy_flags & ALIGN_SKB_FLAG) { |
2091 | chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; | |
b05e9254 FL |
2092 | if (chop_len) { |
2093 | pkt_prev = pkt_next->prev; | |
b05e9254 FL |
2094 | skb_put(pkt_prev, chop_len); |
2095 | } | |
2096 | __skb_unlink(pkt_next, pktq); | |
2097 | brcmu_pkt_buf_free_skb(pkt_next); | |
2098 | } else { | |
8da9d2c8 | 2099 | hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; |
b05e9254 FL |
2100 | dat_offset = le32_to_cpu(*(__le32 *)hdr); |
2101 | dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> | |
2102 | SDPCM_DOFFSET_SHIFT; | |
2103 | skb_pull(pkt_next, dat_offset); | |
8da9d2c8 FL |
2104 | if (bus->txglom) { |
2105 | tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); | |
2106 | skb_trim(pkt_next, pkt_next->len - tail_pad); | |
2107 | } | |
b05e9254 | 2108 | } |
5b435de0 | 2109 | } |
b05e9254 | 2110 | } |
5b435de0 | 2111 | |
b05e9254 FL |
2112 | /* Writes a HW/SW header into the packet and sends it. */ |
2113 | /* Assumes: (a) header space already there, (b) caller holds lock */ | |
8da9d2c8 | 2114 | static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, |
b05e9254 FL |
2115 | uint chan) |
2116 | { | |
2117 | int ret; | |
2118 | int i; | |
8da9d2c8 | 2119 | struct sk_buff *pkt_next, *tmp; |
b05e9254 FL |
2120 | |
2121 | brcmf_dbg(TRACE, "Enter\n"); | |
2122 | ||
8da9d2c8 | 2123 | ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); |
b05e9254 FL |
2124 | if (ret) |
2125 | goto done; | |
5b435de0 | 2126 | |
38b0b0dd | 2127 | sdio_claim_host(bus->sdiodev->func[1]); |
5adfeb63 | 2128 | ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad, |
8da9d2c8 | 2129 | SDIO_FUNC_2, F2SYNC, pktq); |
80969836 | 2130 | bus->sdcnt.f2txdata++; |
5b435de0 AS |
2131 | |
2132 | if (ret < 0) { | |
2133 | /* On failure, abort the command and terminate the frame */ | |
2134 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2135 | ret); | |
80969836 | 2136 | bus->sdcnt.tx_sderrs++; |
5b435de0 AS |
2137 | |
2138 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
3bba829f FL |
2139 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
2140 | SFC_WF_TERM, NULL); | |
80969836 | 2141 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
2142 | |
2143 | for (i = 0; i < 3; i++) { | |
2144 | u8 hi, lo; | |
45db339c FL |
2145 | hi = brcmf_sdio_regrb(bus->sdiodev, |
2146 | SBSDIO_FUNC1_WFRAMEBCHI, NULL); | |
2147 | lo = brcmf_sdio_regrb(bus->sdiodev, | |
2148 | SBSDIO_FUNC1_WFRAMEBCLO, NULL); | |
80969836 | 2149 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
2150 | if ((hi == 0) && (lo == 0)) |
2151 | break; | |
2152 | } | |
5b435de0 | 2153 | } |
38b0b0dd | 2154 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2155 | |
2156 | done: | |
8da9d2c8 FL |
2157 | brcmf_sdio_txpkt_postp(bus, pktq); |
2158 | if (ret == 0) | |
2159 | bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; | |
2160 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
2161 | __skb_unlink(pkt_next, pktq); | |
2162 | brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0); | |
2163 | } | |
5b435de0 AS |
2164 | return ret; |
2165 | } | |
2166 | ||
e92eedf4 | 2167 | static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 AS |
2168 | { |
2169 | struct sk_buff *pkt; | |
8da9d2c8 | 2170 | struct sk_buff_head pktq; |
5b435de0 | 2171 | u32 intstatus = 0; |
8da9d2c8 | 2172 | int ret = 0, prec_out, i; |
5b435de0 | 2173 | uint cnt = 0; |
8da9d2c8 | 2174 | u8 tx_prec_map, pkt_num; |
5b435de0 | 2175 | |
5b435de0 AS |
2176 | brcmf_dbg(TRACE, "Enter\n"); |
2177 | ||
2178 | tx_prec_map = ~bus->flowcontrol; | |
2179 | ||
2180 | /* Send frames until the limit or some other event */ | |
8da9d2c8 FL |
2181 | for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { |
2182 | pkt_num = 1; | |
2183 | __skb_queue_head_init(&pktq); | |
2184 | if (bus->txglom) | |
2185 | pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, | |
2186 | brcmf_sdio_txglomsz); | |
2187 | pkt_num = min_t(u32, pkt_num, | |
2188 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); | |
5b435de0 | 2189 | spin_lock_bh(&bus->txqlock); |
8da9d2c8 FL |
2190 | for (i = 0; i < pkt_num; i++) { |
2191 | pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, | |
2192 | &prec_out); | |
2193 | if (pkt == NULL) | |
2194 | break; | |
2195 | __skb_queue_tail(&pktq, pkt); | |
5b435de0 AS |
2196 | } |
2197 | spin_unlock_bh(&bus->txqlock); | |
8da9d2c8 FL |
2198 | if (i == 0) |
2199 | break; | |
5b435de0 | 2200 | |
8da9d2c8 FL |
2201 | ret = brcmf_sdbrcm_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); |
2202 | cnt += i; | |
5b435de0 AS |
2203 | |
2204 | /* In poll mode, need to check for other events */ | |
2205 | if (!bus->intr && cnt) { | |
2206 | /* Check device status, signal pending interrupt */ | |
38b0b0dd | 2207 | sdio_claim_host(bus->sdiodev->func[1]); |
5c15c23a FL |
2208 | ret = r_sdreg32(bus, &intstatus, |
2209 | offsetof(struct sdpcmd_regs, | |
2210 | intstatus)); | |
38b0b0dd | 2211 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 2212 | bus->sdcnt.f2txdata++; |
5c15c23a | 2213 | if (ret != 0) |
5b435de0 AS |
2214 | break; |
2215 | if (intstatus & bus->hostintmask) | |
1d382273 | 2216 | atomic_set(&bus->ipend, 1); |
5b435de0 AS |
2217 | } |
2218 | } | |
2219 | ||
2220 | /* Deflow-control stack if needed */ | |
05dde977 | 2221 | if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) && |
c8bf3484 | 2222 | bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { |
90d03ff7 HM |
2223 | bus->txoff = false; |
2224 | brcmf_txflowblock(bus->sdiodev->dev, false); | |
c8bf3484 | 2225 | } |
5b435de0 AS |
2226 | |
2227 | return cnt; | |
2228 | } | |
2229 | ||
a9ffda88 FL |
2230 | static void brcmf_sdbrcm_bus_stop(struct device *dev) |
2231 | { | |
2232 | u32 local_hostintmask; | |
2233 | u8 saveclk; | |
a9ffda88 FL |
2234 | int err; |
2235 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
0a332e46 | 2236 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
a9ffda88 FL |
2237 | struct brcmf_sdio *bus = sdiodev->bus; |
2238 | ||
2239 | brcmf_dbg(TRACE, "Enter\n"); | |
2240 | ||
2241 | if (bus->watchdog_tsk) { | |
2242 | send_sig(SIGTERM, bus->watchdog_tsk, 1); | |
2243 | kthread_stop(bus->watchdog_tsk); | |
2244 | bus->watchdog_tsk = NULL; | |
2245 | } | |
2246 | ||
38b0b0dd | 2247 | sdio_claim_host(bus->sdiodev->func[1]); |
a9ffda88 | 2248 | |
a9ffda88 | 2249 | /* Enable clock for device interrupts */ |
4a3da990 | 2250 | brcmf_sdbrcm_bus_sleep(bus, false, false); |
a9ffda88 FL |
2251 | |
2252 | /* Disable and clear interrupts at the chip level also */ | |
58692750 | 2253 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask)); |
a9ffda88 FL |
2254 | local_hostintmask = bus->hostintmask; |
2255 | bus->hostintmask = 0; | |
2256 | ||
2257 | /* Change our idea of bus state */ | |
2258 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; | |
2259 | ||
2260 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
45db339c FL |
2261 | saveclk = brcmf_sdio_regrb(bus->sdiodev, |
2262 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
a9ffda88 | 2263 | if (!err) { |
3bba829f FL |
2264 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
2265 | (saveclk | SBSDIO_FORCE_HT), &err); | |
a9ffda88 FL |
2266 | } |
2267 | if (err) | |
5e8149f5 | 2268 | brcmf_err("Failed to force clock for F2: err %d\n", err); |
a9ffda88 FL |
2269 | |
2270 | /* Turn off the bus (F2), free any pending packets */ | |
2271 | brcmf_dbg(INTR, "disable SDIO interrupts\n"); | |
3bba829f FL |
2272 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1, |
2273 | NULL); | |
a9ffda88 FL |
2274 | |
2275 | /* Clear any pending interrupts now that F2 is disabled */ | |
2276 | w_sdreg32(bus, local_hostintmask, | |
58692750 | 2277 | offsetof(struct sdpcmd_regs, intstatus)); |
a9ffda88 FL |
2278 | |
2279 | /* Turn off the backplane clock (only) */ | |
2280 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
38b0b0dd | 2281 | sdio_release_host(bus->sdiodev->func[1]); |
a9ffda88 FL |
2282 | |
2283 | /* Clear the data packet queues */ | |
2284 | brcmu_pktq_flush(&bus->txq, true, NULL, NULL); | |
2285 | ||
2286 | /* Clear any held glomming stuff */ | |
2287 | if (bus->glomd) | |
2288 | brcmu_pkt_buf_free_skb(bus->glomd); | |
2289 | brcmf_sdbrcm_free_glom(bus); | |
2290 | ||
2291 | /* Clear rx control and wake any waiters */ | |
dd43a01c | 2292 | spin_lock_bh(&bus->rxctl_lock); |
a9ffda88 | 2293 | bus->rxlen = 0; |
dd43a01c | 2294 | spin_unlock_bh(&bus->rxctl_lock); |
a9ffda88 FL |
2295 | brcmf_sdbrcm_dcmd_resp_wake(bus); |
2296 | ||
2297 | /* Reset some F2 state stuff */ | |
2298 | bus->rxskip = false; | |
2299 | bus->tx_seq = bus->rx_seq = 0; | |
a9ffda88 FL |
2300 | } |
2301 | ||
ba89bf19 FL |
2302 | static inline void brcmf_sdbrcm_clrintr(struct brcmf_sdio *bus) |
2303 | { | |
2304 | unsigned long flags; | |
2305 | ||
668761ac HM |
2306 | if (bus->sdiodev->oob_irq_requested) { |
2307 | spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags); | |
2308 | if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) { | |
2309 | enable_irq(bus->sdiodev->pdata->oob_irq_nr); | |
2310 | bus->sdiodev->irq_en = true; | |
2311 | } | |
2312 | spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags); | |
ba89bf19 | 2313 | } |
ba89bf19 | 2314 | } |
ba89bf19 | 2315 | |
4531603a FL |
2316 | static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) |
2317 | { | |
2318 | u8 idx; | |
2319 | u32 addr; | |
2320 | unsigned long val; | |
2321 | int n, ret; | |
2322 | ||
2323 | idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); | |
2324 | addr = bus->ci->c_inf[idx].base + | |
2325 | offsetof(struct sdpcmd_regs, intstatus); | |
2326 | ||
2327 | ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, false); | |
2328 | bus->sdcnt.f1regdata++; | |
2329 | if (ret != 0) | |
2330 | val = 0; | |
2331 | ||
2332 | val &= bus->hostintmask; | |
2333 | atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); | |
2334 | ||
2335 | /* Clear interrupts */ | |
2336 | if (val) { | |
2337 | ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, true); | |
2338 | bus->sdcnt.f1regdata++; | |
2339 | } | |
2340 | ||
2341 | if (ret) { | |
2342 | atomic_set(&bus->intstatus, 0); | |
2343 | } else if (val) { | |
2344 | for_each_set_bit(n, &val, 32) | |
2345 | set_bit(n, (unsigned long *)&bus->intstatus.counter); | |
2346 | } | |
2347 | ||
2348 | return ret; | |
2349 | } | |
2350 | ||
f1e68c2e | 2351 | static void brcmf_sdbrcm_dpc(struct brcmf_sdio *bus) |
5b435de0 | 2352 | { |
4531603a FL |
2353 | u32 newstatus = 0; |
2354 | unsigned long intstatus; | |
5b435de0 AS |
2355 | uint rxlimit = bus->rxbound; /* Rx frames to read before resched */ |
2356 | uint txlimit = bus->txbound; /* Tx frames to send before resched */ | |
2357 | uint framecnt = 0; /* Temporary counter of tx/rx frames */ | |
4531603a | 2358 | int err = 0, n; |
5b435de0 AS |
2359 | |
2360 | brcmf_dbg(TRACE, "Enter\n"); | |
2361 | ||
38b0b0dd | 2362 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2363 | |
2364 | /* If waiting for HTAVAIL, check status */ | |
4a3da990 | 2365 | if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { |
5b435de0 AS |
2366 | u8 clkctl, devctl = 0; |
2367 | ||
8ae74654 | 2368 | #ifdef DEBUG |
5b435de0 | 2369 | /* Check for inconsistent device control */ |
45db339c FL |
2370 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
2371 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 2372 | if (err) { |
5e8149f5 | 2373 | brcmf_err("error reading DEVCTL: %d\n", err); |
712ac5b3 | 2374 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 | 2375 | } |
8ae74654 | 2376 | #endif /* DEBUG */ |
5b435de0 AS |
2377 | |
2378 | /* Read CSR, if clock on switch to AVAIL, else ignore */ | |
45db339c FL |
2379 | clkctl = brcmf_sdio_regrb(bus->sdiodev, |
2380 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 2381 | if (err) { |
5e8149f5 | 2382 | brcmf_err("error reading CSR: %d\n", |
5b435de0 | 2383 | err); |
712ac5b3 | 2384 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2385 | } |
2386 | ||
c3203374 | 2387 | brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", |
5b435de0 AS |
2388 | devctl, clkctl); |
2389 | ||
2390 | if (SBSDIO_HTAV(clkctl)) { | |
45db339c FL |
2391 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
2392 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 2393 | if (err) { |
5e8149f5 | 2394 | brcmf_err("error reading DEVCTL: %d\n", |
5b435de0 | 2395 | err); |
712ac5b3 | 2396 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2397 | } |
2398 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
3bba829f FL |
2399 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
2400 | devctl, &err); | |
5b435de0 | 2401 | if (err) { |
5e8149f5 | 2402 | brcmf_err("error writing DEVCTL: %d\n", |
5b435de0 | 2403 | err); |
712ac5b3 | 2404 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2405 | } |
2406 | bus->clkstate = CLK_AVAIL; | |
5b435de0 AS |
2407 | } |
2408 | } | |
2409 | ||
5b435de0 | 2410 | /* Make sure backplane clock is on */ |
4a3da990 | 2411 | brcmf_sdbrcm_bus_sleep(bus, false, true); |
5b435de0 AS |
2412 | |
2413 | /* Pending interrupt indicates new device status */ | |
1d382273 FL |
2414 | if (atomic_read(&bus->ipend) > 0) { |
2415 | atomic_set(&bus->ipend, 0); | |
4531603a | 2416 | err = brcmf_sdio_intr_rstatus(bus); |
5b435de0 AS |
2417 | } |
2418 | ||
4531603a FL |
2419 | /* Start with leftover status bits */ |
2420 | intstatus = atomic_xchg(&bus->intstatus, 0); | |
5b435de0 AS |
2421 | |
2422 | /* Handle flow-control change: read new state in case our ack | |
2423 | * crossed another change interrupt. If change still set, assume | |
2424 | * FC ON for safety, let next loop through do the debounce. | |
2425 | */ | |
2426 | if (intstatus & I_HMB_FC_CHANGE) { | |
2427 | intstatus &= ~I_HMB_FC_CHANGE; | |
5c15c23a FL |
2428 | err = w_sdreg32(bus, I_HMB_FC_CHANGE, |
2429 | offsetof(struct sdpcmd_regs, intstatus)); | |
5b435de0 | 2430 | |
5c15c23a FL |
2431 | err = r_sdreg32(bus, &newstatus, |
2432 | offsetof(struct sdpcmd_regs, intstatus)); | |
80969836 | 2433 | bus->sdcnt.f1regdata += 2; |
4531603a FL |
2434 | atomic_set(&bus->fcstate, |
2435 | !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); | |
5b435de0 AS |
2436 | intstatus |= (newstatus & bus->hostintmask); |
2437 | } | |
2438 | ||
2439 | /* Handle host mailbox indication */ | |
2440 | if (intstatus & I_HMB_HOST_INT) { | |
2441 | intstatus &= ~I_HMB_HOST_INT; | |
2442 | intstatus |= brcmf_sdbrcm_hostmail(bus); | |
2443 | } | |
2444 | ||
38b0b0dd | 2445 | sdio_release_host(bus->sdiodev->func[1]); |
7cdf57d3 | 2446 | |
5b435de0 AS |
2447 | /* Generally don't ask for these, can get CRC errors... */ |
2448 | if (intstatus & I_WR_OOSYNC) { | |
5e8149f5 | 2449 | brcmf_err("Dongle reports WR_OOSYNC\n"); |
5b435de0 AS |
2450 | intstatus &= ~I_WR_OOSYNC; |
2451 | } | |
2452 | ||
2453 | if (intstatus & I_RD_OOSYNC) { | |
5e8149f5 | 2454 | brcmf_err("Dongle reports RD_OOSYNC\n"); |
5b435de0 AS |
2455 | intstatus &= ~I_RD_OOSYNC; |
2456 | } | |
2457 | ||
2458 | if (intstatus & I_SBINT) { | |
5e8149f5 | 2459 | brcmf_err("Dongle reports SBINT\n"); |
5b435de0 AS |
2460 | intstatus &= ~I_SBINT; |
2461 | } | |
2462 | ||
2463 | /* Would be active due to wake-wlan in gSPI */ | |
2464 | if (intstatus & I_CHIPACTIVE) { | |
2465 | brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); | |
2466 | intstatus &= ~I_CHIPACTIVE; | |
2467 | } | |
2468 | ||
2469 | /* Ignore frame indications if rxskip is set */ | |
2470 | if (bus->rxskip) | |
2471 | intstatus &= ~I_HMB_FRAME_IND; | |
2472 | ||
2473 | /* On frame indication, read available frames */ | |
03d5c360 | 2474 | if (PKT_AVAILABLE() && bus->clkstate == CLK_AVAIL) { |
4754fcee FL |
2475 | framecnt = brcmf_sdio_readframes(bus, rxlimit); |
2476 | if (!bus->rxpending) | |
5b435de0 AS |
2477 | intstatus &= ~I_HMB_FRAME_IND; |
2478 | rxlimit -= min(framecnt, rxlimit); | |
2479 | } | |
2480 | ||
2481 | /* Keep still-pending events for next scheduling */ | |
4531603a FL |
2482 | if (intstatus) { |
2483 | for_each_set_bit(n, &intstatus, 32) | |
2484 | set_bit(n, (unsigned long *)&bus->intstatus.counter); | |
2485 | } | |
5b435de0 | 2486 | |
ba89bf19 FL |
2487 | brcmf_sdbrcm_clrintr(bus); |
2488 | ||
5b435de0 AS |
2489 | if (data_ok(bus) && bus->ctrl_frame_stat && |
2490 | (bus->clkstate == CLK_AVAIL)) { | |
03d5c360 | 2491 | int i; |
5b435de0 | 2492 | |
38b0b0dd | 2493 | sdio_claim_host(bus->sdiodev->func[1]); |
03d5c360 | 2494 | err = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad, |
2c208890 | 2495 | SDIO_FUNC_2, F2SYNC, bus->ctrl_frame_buf, |
5adfeb63 | 2496 | (u32) bus->ctrl_frame_len); |
5b435de0 | 2497 | |
03d5c360 | 2498 | if (err < 0) { |
5b435de0 AS |
2499 | /* On failure, abort the command and |
2500 | terminate the frame */ | |
2501 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
03d5c360 | 2502 | err); |
80969836 | 2503 | bus->sdcnt.tx_sderrs++; |
5b435de0 AS |
2504 | |
2505 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2506 | ||
3bba829f | 2507 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
5c15c23a | 2508 | SFC_WF_TERM, &err); |
80969836 | 2509 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
2510 | |
2511 | for (i = 0; i < 3; i++) { | |
2512 | u8 hi, lo; | |
45db339c FL |
2513 | hi = brcmf_sdio_regrb(bus->sdiodev, |
2514 | SBSDIO_FUNC1_WFRAMEBCHI, | |
5c15c23a | 2515 | &err); |
45db339c FL |
2516 | lo = brcmf_sdio_regrb(bus->sdiodev, |
2517 | SBSDIO_FUNC1_WFRAMEBCLO, | |
5c15c23a | 2518 | &err); |
80969836 | 2519 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
2520 | if ((hi == 0) && (lo == 0)) |
2521 | break; | |
2522 | } | |
2523 | ||
03d5c360 | 2524 | } else { |
6bc52319 | 2525 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; |
03d5c360 | 2526 | } |
38b0b0dd | 2527 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2528 | bus->ctrl_frame_stat = false; |
2529 | brcmf_sdbrcm_wait_event_wakeup(bus); | |
2530 | } | |
2531 | /* Send queued frames (limit 1 if rx may still be pending) */ | |
4531603a | 2532 | else if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && |
5b435de0 AS |
2533 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit |
2534 | && data_ok(bus)) { | |
4754fcee FL |
2535 | framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : |
2536 | txlimit; | |
5b435de0 AS |
2537 | framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt); |
2538 | txlimit -= framecnt; | |
2539 | } | |
2540 | ||
5c15c23a | 2541 | if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) || (err != 0)) { |
5e8149f5 | 2542 | brcmf_err("failed backplane access over SDIO, halting operation\n"); |
712ac5b3 | 2543 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
4531603a FL |
2544 | atomic_set(&bus->intstatus, 0); |
2545 | } else if (atomic_read(&bus->intstatus) || | |
2546 | atomic_read(&bus->ipend) > 0 || | |
2547 | (!atomic_read(&bus->fcstate) && | |
2548 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
2549 | data_ok(bus)) || PKT_AVAILABLE()) { | |
fccfe930 | 2550 | atomic_inc(&bus->dpc_tskcnt); |
5b435de0 AS |
2551 | } |
2552 | ||
5b435de0 AS |
2553 | /* If we're done for now, turn off clock request. */ |
2554 | if ((bus->clkstate != CLK_PENDING) | |
2555 | && bus->idletime == BRCMF_IDLE_IMMEDIATE) { | |
2556 | bus->activity = false; | |
4a3da990 | 2557 | brcmf_dbg(SDIO, "idle state\n"); |
38b0b0dd | 2558 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 2559 | brcmf_sdbrcm_bus_sleep(bus, true, false); |
38b0b0dd | 2560 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 2561 | } |
5b435de0 AS |
2562 | } |
2563 | ||
e2432b67 AS |
2564 | static struct pktq *brcmf_sdbrcm_bus_gettxq(struct device *dev) |
2565 | { | |
2566 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
2567 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
2568 | struct brcmf_sdio *bus = sdiodev->bus; | |
2569 | ||
2570 | return &bus->txq; | |
2571 | } | |
2572 | ||
b9692d17 | 2573 | static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt) |
5b435de0 AS |
2574 | { |
2575 | int ret = -EBADE; | |
2576 | uint datalen, prec; | |
bf347bb9 | 2577 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2578 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
bf347bb9 | 2579 | struct brcmf_sdio *bus = sdiodev->bus; |
4061f895 | 2580 | ulong flags; |
5b435de0 AS |
2581 | |
2582 | brcmf_dbg(TRACE, "Enter\n"); | |
2583 | ||
2584 | datalen = pkt->len; | |
2585 | ||
2586 | /* Add space for the header */ | |
706478cb | 2587 | skb_push(pkt, bus->tx_hdrlen); |
5b435de0 AS |
2588 | /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ |
2589 | ||
2590 | prec = prio2prec((pkt->priority & PRIOMASK)); | |
2591 | ||
2592 | /* Check for existing queue, current flow-control, | |
2593 | pending event, or pending clock */ | |
2594 | brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); | |
80969836 | 2595 | bus->sdcnt.fcqueued++; |
5b435de0 AS |
2596 | |
2597 | /* Priority based enq */ | |
4061f895 | 2598 | spin_lock_irqsave(&bus->txqlock, flags); |
23677ce3 | 2599 | if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) { |
706478cb | 2600 | skb_pull(pkt, bus->tx_hdrlen); |
5e8149f5 | 2601 | brcmf_err("out of bus->txq !!!\n"); |
5b435de0 AS |
2602 | ret = -ENOSR; |
2603 | } else { | |
2604 | ret = 0; | |
2605 | } | |
5b435de0 | 2606 | |
c8bf3484 | 2607 | if (pktq_len(&bus->txq) >= TXHI) { |
90d03ff7 HM |
2608 | bus->txoff = true; |
2609 | brcmf_txflowblock(bus->sdiodev->dev, true); | |
c8bf3484 | 2610 | } |
4061f895 | 2611 | spin_unlock_irqrestore(&bus->txqlock, flags); |
5b435de0 | 2612 | |
8ae74654 | 2613 | #ifdef DEBUG |
5b435de0 AS |
2614 | if (pktq_plen(&bus->txq, prec) > qcount[prec]) |
2615 | qcount[prec] = pktq_plen(&bus->txq, prec); | |
2616 | #endif | |
f1e68c2e | 2617 | |
fccfe930 AS |
2618 | if (atomic_read(&bus->dpc_tskcnt) == 0) { |
2619 | atomic_inc(&bus->dpc_tskcnt); | |
f1e68c2e | 2620 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
2621 | } |
2622 | ||
2623 | return ret; | |
2624 | } | |
2625 | ||
8ae74654 | 2626 | #ifdef DEBUG |
5b435de0 AS |
2627 | #define CONSOLE_LINE_MAX 192 |
2628 | ||
e92eedf4 | 2629 | static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus) |
5b435de0 AS |
2630 | { |
2631 | struct brcmf_console *c = &bus->console; | |
2632 | u8 line[CONSOLE_LINE_MAX], ch; | |
2633 | u32 n, idx, addr; | |
2634 | int rv; | |
2635 | ||
2636 | /* Don't do anything until FWREADY updates console address */ | |
2637 | if (bus->console_addr == 0) | |
2638 | return 0; | |
2639 | ||
2640 | /* Read console log struct */ | |
2641 | addr = bus->console_addr + offsetof(struct rte_console, log_le); | |
ba540b01 FL |
2642 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, |
2643 | sizeof(c->log_le)); | |
5b435de0 AS |
2644 | if (rv < 0) |
2645 | return rv; | |
2646 | ||
2647 | /* Allocate console buffer (one time only) */ | |
2648 | if (c->buf == NULL) { | |
2649 | c->bufsize = le32_to_cpu(c->log_le.buf_size); | |
2650 | c->buf = kmalloc(c->bufsize, GFP_ATOMIC); | |
2651 | if (c->buf == NULL) | |
2652 | return -ENOMEM; | |
2653 | } | |
2654 | ||
2655 | idx = le32_to_cpu(c->log_le.idx); | |
2656 | ||
2657 | /* Protect against corrupt value */ | |
2658 | if (idx > c->bufsize) | |
2659 | return -EBADE; | |
2660 | ||
2661 | /* Skip reading the console buffer if the index pointer | |
2662 | has not moved */ | |
2663 | if (idx == c->last) | |
2664 | return 0; | |
2665 | ||
2666 | /* Read the console buffer */ | |
2667 | addr = le32_to_cpu(c->log_le.buf); | |
ba540b01 | 2668 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); |
5b435de0 AS |
2669 | if (rv < 0) |
2670 | return rv; | |
2671 | ||
2672 | while (c->last != idx) { | |
2673 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
2674 | if (c->last == idx) { | |
2675 | /* This would output a partial line. | |
2676 | * Instead, back up | |
2677 | * the buffer pointer and output this | |
2678 | * line next time around. | |
2679 | */ | |
2680 | if (c->last >= n) | |
2681 | c->last -= n; | |
2682 | else | |
2683 | c->last = c->bufsize - n; | |
2684 | goto break2; | |
2685 | } | |
2686 | ch = c->buf[c->last]; | |
2687 | c->last = (c->last + 1) % c->bufsize; | |
2688 | if (ch == '\n') | |
2689 | break; | |
2690 | line[n] = ch; | |
2691 | } | |
2692 | ||
2693 | if (n > 0) { | |
2694 | if (line[n - 1] == '\r') | |
2695 | n--; | |
2696 | line[n] = 0; | |
18aad4f8 | 2697 | pr_debug("CONSOLE: %s\n", line); |
5b435de0 AS |
2698 | } |
2699 | } | |
2700 | break2: | |
2701 | ||
2702 | return 0; | |
2703 | } | |
8ae74654 | 2704 | #endif /* DEBUG */ |
5b435de0 | 2705 | |
e92eedf4 | 2706 | static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len) |
5b435de0 AS |
2707 | { |
2708 | int i; | |
2709 | int ret; | |
2710 | ||
2711 | bus->ctrl_frame_stat = false; | |
5adfeb63 AS |
2712 | ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad, |
2713 | SDIO_FUNC_2, F2SYNC, frame, len); | |
5b435de0 AS |
2714 | |
2715 | if (ret < 0) { | |
2716 | /* On failure, abort the command and terminate the frame */ | |
2717 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2718 | ret); | |
80969836 | 2719 | bus->sdcnt.tx_sderrs++; |
5b435de0 AS |
2720 | |
2721 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2722 | ||
3bba829f FL |
2723 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
2724 | SFC_WF_TERM, NULL); | |
80969836 | 2725 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
2726 | |
2727 | for (i = 0; i < 3; i++) { | |
2728 | u8 hi, lo; | |
45db339c FL |
2729 | hi = brcmf_sdio_regrb(bus->sdiodev, |
2730 | SBSDIO_FUNC1_WFRAMEBCHI, NULL); | |
2731 | lo = brcmf_sdio_regrb(bus->sdiodev, | |
2732 | SBSDIO_FUNC1_WFRAMEBCLO, NULL); | |
80969836 | 2733 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
2734 | if (hi == 0 && lo == 0) |
2735 | break; | |
2736 | } | |
2737 | return ret; | |
2738 | } | |
2739 | ||
6bc52319 | 2740 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; |
5b435de0 AS |
2741 | |
2742 | return ret; | |
2743 | } | |
2744 | ||
fcf094f4 | 2745 | static int |
47a1ce78 | 2746 | brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
2747 | { |
2748 | u8 *frame; | |
8da9d2c8 | 2749 | u16 len, pad; |
5b435de0 AS |
2750 | uint retries = 0; |
2751 | u8 doff = 0; | |
2752 | int ret = -1; | |
47a1ce78 | 2753 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2754 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
47a1ce78 | 2755 | struct brcmf_sdio *bus = sdiodev->bus; |
6bc52319 | 2756 | struct brcmf_sdio_hdrinfo hd_info = {0}; |
5b435de0 AS |
2757 | |
2758 | brcmf_dbg(TRACE, "Enter\n"); | |
2759 | ||
2760 | /* Back the pointer to make a room for bus header */ | |
706478cb FL |
2761 | frame = msg - bus->tx_hdrlen; |
2762 | len = (msglen += bus->tx_hdrlen); | |
5b435de0 AS |
2763 | |
2764 | /* Add alignment padding (optional for ctl frames) */ | |
2765 | doff = ((unsigned long)frame % BRCMF_SDALIGN); | |
2766 | if (doff) { | |
2767 | frame -= doff; | |
2768 | len += doff; | |
2769 | msglen += doff; | |
706478cb | 2770 | memset(frame, 0, doff + bus->tx_hdrlen); |
5b435de0 AS |
2771 | } |
2772 | /* precondition: doff < BRCMF_SDALIGN */ | |
706478cb | 2773 | doff += bus->tx_hdrlen; |
5b435de0 AS |
2774 | |
2775 | /* Round send length to next SDIO block */ | |
8da9d2c8 | 2776 | pad = 0; |
5b435de0 | 2777 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { |
8da9d2c8 FL |
2778 | pad = bus->blocksize - (len % bus->blocksize); |
2779 | if ((pad > bus->roundup) || (pad >= bus->blocksize)) | |
2780 | pad = 0; | |
5b435de0 | 2781 | } else if (len % BRCMF_SDALIGN) { |
8da9d2c8 | 2782 | pad = BRCMF_SDALIGN - (len % BRCMF_SDALIGN); |
5b435de0 | 2783 | } |
8da9d2c8 | 2784 | len += pad; |
5b435de0 AS |
2785 | |
2786 | /* Satisfy length-alignment requirements */ | |
2787 | if (len & (ALIGNMENT - 1)) | |
2788 | len = roundup(len, ALIGNMENT); | |
2789 | ||
2790 | /* precondition: IS_ALIGNED((unsigned long)frame, 2) */ | |
2791 | ||
5b435de0 | 2792 | /* Make sure backplane clock is on */ |
38b0b0dd | 2793 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 2794 | brcmf_sdbrcm_bus_sleep(bus, false, false); |
38b0b0dd | 2795 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 2796 | |
6bc52319 FL |
2797 | hd_info.len = (u16)msglen; |
2798 | hd_info.channel = SDPCM_CONTROL_CHANNEL; | |
2799 | hd_info.dat_offset = doff; | |
8da9d2c8 FL |
2800 | hd_info.seq_num = bus->tx_seq; |
2801 | if (bus->txglom) { | |
2802 | hd_info.lastfrm = true; | |
2803 | hd_info.tail_pad = pad; | |
2804 | } | |
6bc52319 | 2805 | brcmf_sdio_hdpack(bus, frame, &hd_info); |
5b435de0 | 2806 | |
8da9d2c8 FL |
2807 | if (bus->txglom) |
2808 | brcmf_sdio_update_hwhdr(frame, len); | |
2809 | ||
5b435de0 AS |
2810 | if (!data_ok(bus)) { |
2811 | brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n", | |
2812 | bus->tx_max, bus->tx_seq); | |
2813 | bus->ctrl_frame_stat = true; | |
2814 | /* Send from dpc */ | |
2815 | bus->ctrl_frame_buf = frame; | |
2816 | bus->ctrl_frame_len = len; | |
2817 | ||
fd67dc83 FL |
2818 | wait_event_interruptible_timeout(bus->ctrl_wait, |
2819 | !bus->ctrl_frame_stat, | |
2820 | msecs_to_jiffies(2000)); | |
5b435de0 | 2821 | |
23677ce3 | 2822 | if (!bus->ctrl_frame_stat) { |
c3203374 | 2823 | brcmf_dbg(SDIO, "ctrl_frame_stat == false\n"); |
5b435de0 AS |
2824 | ret = 0; |
2825 | } else { | |
c3203374 | 2826 | brcmf_dbg(SDIO, "ctrl_frame_stat == true\n"); |
5b435de0 AS |
2827 | ret = -1; |
2828 | } | |
2829 | } | |
2830 | ||
2831 | if (ret == -1) { | |
1e023829 JP |
2832 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
2833 | frame, len, "Tx Frame:\n"); | |
2834 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && | |
2835 | BRCMF_HDRS_ON(), | |
2836 | frame, min_t(u16, len, 16), "TxHdr:\n"); | |
5b435de0 AS |
2837 | |
2838 | do { | |
38b0b0dd | 2839 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 2840 | ret = brcmf_tx_frame(bus, frame, len); |
38b0b0dd | 2841 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2842 | } while (ret < 0 && retries++ < TXRETRIES); |
2843 | } | |
2844 | ||
f1e68c2e | 2845 | if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && |
fccfe930 | 2846 | atomic_read(&bus->dpc_tskcnt) == 0) { |
5b435de0 | 2847 | bus->activity = false; |
38b0b0dd | 2848 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 2849 | brcmf_dbg(INFO, "idle\n"); |
5b435de0 | 2850 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, true); |
38b0b0dd | 2851 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2852 | } |
2853 | ||
5b435de0 | 2854 | if (ret) |
80969836 | 2855 | bus->sdcnt.tx_ctlerrs++; |
5b435de0 | 2856 | else |
80969836 | 2857 | bus->sdcnt.tx_ctlpkts++; |
5b435de0 AS |
2858 | |
2859 | return ret ? -EIO : 0; | |
2860 | } | |
2861 | ||
80969836 | 2862 | #ifdef DEBUG |
4fc0d016 AS |
2863 | static inline bool brcmf_sdio_valid_shared_address(u32 addr) |
2864 | { | |
2865 | return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); | |
2866 | } | |
2867 | ||
2868 | static int brcmf_sdio_readshared(struct brcmf_sdio *bus, | |
2869 | struct sdpcm_shared *sh) | |
2870 | { | |
2871 | u32 addr; | |
2872 | int rv; | |
2873 | u32 shaddr = 0; | |
2874 | struct sdpcm_shared_le sh_le; | |
2875 | __le32 addr_le; | |
2876 | ||
1640f28f | 2877 | shaddr = bus->ci->rambase + bus->ramsize - 4; |
4fc0d016 AS |
2878 | |
2879 | /* | |
2880 | * Read last word in socram to determine | |
2881 | * address of sdpcm_shared structure | |
2882 | */ | |
38b0b0dd | 2883 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 2884 | brcmf_sdbrcm_bus_sleep(bus, false, false); |
ba540b01 | 2885 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4); |
b55de97f | 2886 | sdio_release_host(bus->sdiodev->func[1]); |
4fc0d016 AS |
2887 | if (rv < 0) |
2888 | return rv; | |
2889 | ||
2890 | addr = le32_to_cpu(addr_le); | |
2891 | ||
c3203374 | 2892 | brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr); |
4fc0d016 AS |
2893 | |
2894 | /* | |
2895 | * Check if addr is valid. | |
2896 | * NVRAM length at the end of memory should have been overwritten. | |
2897 | */ | |
2898 | if (!brcmf_sdio_valid_shared_address(addr)) { | |
5e8149f5 | 2899 | brcmf_err("invalid sdpcm_shared address 0x%08X\n", |
4fc0d016 AS |
2900 | addr); |
2901 | return -EINVAL; | |
2902 | } | |
2903 | ||
2904 | /* Read hndrte_shared structure */ | |
ba540b01 FL |
2905 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, |
2906 | sizeof(struct sdpcm_shared_le)); | |
4fc0d016 AS |
2907 | if (rv < 0) |
2908 | return rv; | |
2909 | ||
2910 | /* Endianness */ | |
2911 | sh->flags = le32_to_cpu(sh_le.flags); | |
2912 | sh->trap_addr = le32_to_cpu(sh_le.trap_addr); | |
2913 | sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); | |
2914 | sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); | |
2915 | sh->assert_line = le32_to_cpu(sh_le.assert_line); | |
2916 | sh->console_addr = le32_to_cpu(sh_le.console_addr); | |
2917 | sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); | |
2918 | ||
86dcd937 PH |
2919 | if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { |
2920 | brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", | |
4fc0d016 AS |
2921 | SDPCM_SHARED_VERSION, |
2922 | sh->flags & SDPCM_SHARED_VERSION_MASK); | |
2923 | return -EPROTO; | |
2924 | } | |
2925 | ||
2926 | return 0; | |
2927 | } | |
2928 | ||
2929 | static int brcmf_sdio_dump_console(struct brcmf_sdio *bus, | |
2930 | struct sdpcm_shared *sh, char __user *data, | |
2931 | size_t count) | |
2932 | { | |
2933 | u32 addr, console_ptr, console_size, console_index; | |
2934 | char *conbuf = NULL; | |
2935 | __le32 sh_val; | |
2936 | int rv; | |
2937 | loff_t pos = 0; | |
2938 | int nbytes = 0; | |
2939 | ||
2940 | /* obtain console information from device memory */ | |
2941 | addr = sh->console_addr + offsetof(struct rte_console, log_le); | |
ba540b01 FL |
2942 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, |
2943 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2944 | if (rv < 0) |
2945 | return rv; | |
2946 | console_ptr = le32_to_cpu(sh_val); | |
2947 | ||
2948 | addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); | |
ba540b01 FL |
2949 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, |
2950 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2951 | if (rv < 0) |
2952 | return rv; | |
2953 | console_size = le32_to_cpu(sh_val); | |
2954 | ||
2955 | addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); | |
ba540b01 FL |
2956 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, |
2957 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2958 | if (rv < 0) |
2959 | return rv; | |
2960 | console_index = le32_to_cpu(sh_val); | |
2961 | ||
2962 | /* allocate buffer for console data */ | |
2963 | if (console_size <= CONSOLE_BUFFER_MAX) | |
2964 | conbuf = vzalloc(console_size+1); | |
2965 | ||
2966 | if (!conbuf) | |
2967 | return -ENOMEM; | |
2968 | ||
2969 | /* obtain the console data from device */ | |
2970 | conbuf[console_size] = '\0'; | |
ba540b01 FL |
2971 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, |
2972 | console_size); | |
4fc0d016 AS |
2973 | if (rv < 0) |
2974 | goto done; | |
2975 | ||
2976 | rv = simple_read_from_buffer(data, count, &pos, | |
2977 | conbuf + console_index, | |
2978 | console_size - console_index); | |
2979 | if (rv < 0) | |
2980 | goto done; | |
2981 | ||
2982 | nbytes = rv; | |
2983 | if (console_index > 0) { | |
2984 | pos = 0; | |
2985 | rv = simple_read_from_buffer(data+nbytes, count, &pos, | |
2986 | conbuf, console_index - 1); | |
2987 | if (rv < 0) | |
2988 | goto done; | |
2989 | rv += nbytes; | |
2990 | } | |
2991 | done: | |
2992 | vfree(conbuf); | |
2993 | return rv; | |
2994 | } | |
2995 | ||
2996 | static int brcmf_sdio_trap_info(struct brcmf_sdio *bus, struct sdpcm_shared *sh, | |
2997 | char __user *data, size_t count) | |
2998 | { | |
2999 | int error, res; | |
3000 | char buf[350]; | |
3001 | struct brcmf_trap_info tr; | |
4fc0d016 AS |
3002 | loff_t pos = 0; |
3003 | ||
baa9e609 PH |
3004 | if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { |
3005 | brcmf_dbg(INFO, "no trap in firmware\n"); | |
4fc0d016 | 3006 | return 0; |
baa9e609 | 3007 | } |
4fc0d016 | 3008 | |
ba540b01 FL |
3009 | error = brcmf_sdio_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, |
3010 | sizeof(struct brcmf_trap_info)); | |
4fc0d016 AS |
3011 | if (error < 0) |
3012 | return error; | |
3013 | ||
4fc0d016 AS |
3014 | res = scnprintf(buf, sizeof(buf), |
3015 | "dongle trap info: type 0x%x @ epc 0x%08x\n" | |
3016 | " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" | |
3017 | " lr 0x%08x pc 0x%08x offset 0x%x\n" | |
3018 | " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" | |
3019 | " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", | |
3020 | le32_to_cpu(tr.type), le32_to_cpu(tr.epc), | |
3021 | le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), | |
3022 | le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), | |
9bd02c6b | 3023 | le32_to_cpu(tr.pc), sh->trap_addr, |
4fc0d016 AS |
3024 | le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), |
3025 | le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), | |
3026 | le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), | |
3027 | le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); | |
3028 | ||
baa9e609 | 3029 | return simple_read_from_buffer(data, count, &pos, buf, res); |
4fc0d016 AS |
3030 | } |
3031 | ||
3032 | static int brcmf_sdio_assert_info(struct brcmf_sdio *bus, | |
3033 | struct sdpcm_shared *sh, char __user *data, | |
3034 | size_t count) | |
3035 | { | |
3036 | int error = 0; | |
3037 | char buf[200]; | |
3038 | char file[80] = "?"; | |
3039 | char expr[80] = "<???>"; | |
3040 | int res; | |
3041 | loff_t pos = 0; | |
3042 | ||
3043 | if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { | |
3044 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
3045 | return 0; | |
3046 | } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { | |
3047 | brcmf_dbg(INFO, "no assert in dongle\n"); | |
3048 | return 0; | |
3049 | } | |
3050 | ||
38b0b0dd | 3051 | sdio_claim_host(bus->sdiodev->func[1]); |
4fc0d016 | 3052 | if (sh->assert_file_addr != 0) { |
ba540b01 FL |
3053 | error = brcmf_sdio_ramrw(bus->sdiodev, false, |
3054 | sh->assert_file_addr, (u8 *)file, 80); | |
4fc0d016 AS |
3055 | if (error < 0) |
3056 | return error; | |
3057 | } | |
3058 | if (sh->assert_exp_addr != 0) { | |
ba540b01 FL |
3059 | error = brcmf_sdio_ramrw(bus->sdiodev, false, |
3060 | sh->assert_exp_addr, (u8 *)expr, 80); | |
4fc0d016 AS |
3061 | if (error < 0) |
3062 | return error; | |
3063 | } | |
38b0b0dd | 3064 | sdio_release_host(bus->sdiodev->func[1]); |
4fc0d016 AS |
3065 | |
3066 | res = scnprintf(buf, sizeof(buf), | |
3067 | "dongle assert: %s:%d: assert(%s)\n", | |
3068 | file, sh->assert_line, expr); | |
3069 | return simple_read_from_buffer(data, count, &pos, buf, res); | |
3070 | } | |
3071 | ||
3072 | static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus) | |
3073 | { | |
3074 | int error; | |
3075 | struct sdpcm_shared sh; | |
3076 | ||
4fc0d016 | 3077 | error = brcmf_sdio_readshared(bus, &sh); |
4fc0d016 AS |
3078 | |
3079 | if (error < 0) | |
3080 | return error; | |
3081 | ||
3082 | if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) | |
3083 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
3084 | else if (sh.flags & SDPCM_SHARED_ASSERT) | |
5e8149f5 | 3085 | brcmf_err("assertion in dongle\n"); |
4fc0d016 AS |
3086 | |
3087 | if (sh.flags & SDPCM_SHARED_TRAP) | |
5e8149f5 | 3088 | brcmf_err("firmware trap in dongle\n"); |
4fc0d016 AS |
3089 | |
3090 | return 0; | |
3091 | } | |
3092 | ||
3093 | static int brcmf_sdbrcm_died_dump(struct brcmf_sdio *bus, char __user *data, | |
3094 | size_t count, loff_t *ppos) | |
3095 | { | |
3096 | int error = 0; | |
3097 | struct sdpcm_shared sh; | |
3098 | int nbytes = 0; | |
3099 | loff_t pos = *ppos; | |
3100 | ||
3101 | if (pos != 0) | |
3102 | return 0; | |
3103 | ||
4fc0d016 AS |
3104 | error = brcmf_sdio_readshared(bus, &sh); |
3105 | if (error < 0) | |
3106 | goto done; | |
3107 | ||
3108 | error = brcmf_sdio_assert_info(bus, &sh, data, count); | |
3109 | if (error < 0) | |
3110 | goto done; | |
4fc0d016 | 3111 | nbytes = error; |
baa9e609 PH |
3112 | |
3113 | error = brcmf_sdio_trap_info(bus, &sh, data+nbytes, count); | |
4fc0d016 AS |
3114 | if (error < 0) |
3115 | goto done; | |
baa9e609 PH |
3116 | nbytes += error; |
3117 | ||
3118 | error = brcmf_sdio_dump_console(bus, &sh, data+nbytes, count); | |
3119 | if (error < 0) | |
3120 | goto done; | |
3121 | nbytes += error; | |
4fc0d016 | 3122 | |
baa9e609 PH |
3123 | error = nbytes; |
3124 | *ppos += nbytes; | |
4fc0d016 | 3125 | done: |
4fc0d016 AS |
3126 | return error; |
3127 | } | |
3128 | ||
3129 | static ssize_t brcmf_sdio_forensic_read(struct file *f, char __user *data, | |
3130 | size_t count, loff_t *ppos) | |
3131 | { | |
3132 | struct brcmf_sdio *bus = f->private_data; | |
3133 | int res; | |
3134 | ||
3135 | res = brcmf_sdbrcm_died_dump(bus, data, count, ppos); | |
3136 | if (res > 0) | |
3137 | *ppos += res; | |
3138 | return (ssize_t)res; | |
3139 | } | |
3140 | ||
3141 | static const struct file_operations brcmf_sdio_forensic_ops = { | |
3142 | .owner = THIS_MODULE, | |
3143 | .open = simple_open, | |
3144 | .read = brcmf_sdio_forensic_read | |
3145 | }; | |
3146 | ||
80969836 AS |
3147 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3148 | { | |
3149 | struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; | |
4fc0d016 | 3150 | struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); |
80969836 | 3151 | |
4fc0d016 AS |
3152 | if (IS_ERR_OR_NULL(dentry)) |
3153 | return; | |
3154 | ||
3155 | debugfs_create_file("forensics", S_IRUGO, dentry, bus, | |
3156 | &brcmf_sdio_forensic_ops); | |
80969836 AS |
3157 | brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt); |
3158 | } | |
3159 | #else | |
4fc0d016 AS |
3160 | static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus) |
3161 | { | |
3162 | return 0; | |
3163 | } | |
3164 | ||
80969836 AS |
3165 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3166 | { | |
3167 | } | |
3168 | #endif /* DEBUG */ | |
3169 | ||
fcf094f4 | 3170 | static int |
532cdd3b | 3171 | brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
3172 | { |
3173 | int timeleft; | |
3174 | uint rxlen = 0; | |
3175 | bool pending; | |
dd43a01c | 3176 | u8 *buf; |
532cdd3b | 3177 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3178 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
532cdd3b | 3179 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
3180 | |
3181 | brcmf_dbg(TRACE, "Enter\n"); | |
3182 | ||
3183 | /* Wait until control frame is available */ | |
3184 | timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending); | |
3185 | ||
dd43a01c | 3186 | spin_lock_bh(&bus->rxctl_lock); |
5b435de0 AS |
3187 | rxlen = bus->rxlen; |
3188 | memcpy(msg, bus->rxctl, min(msglen, rxlen)); | |
dd43a01c FL |
3189 | bus->rxctl = NULL; |
3190 | buf = bus->rxctl_orig; | |
3191 | bus->rxctl_orig = NULL; | |
5b435de0 | 3192 | bus->rxlen = 0; |
dd43a01c FL |
3193 | spin_unlock_bh(&bus->rxctl_lock); |
3194 | vfree(buf); | |
5b435de0 AS |
3195 | |
3196 | if (rxlen) { | |
3197 | brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", | |
3198 | rxlen, msglen); | |
3199 | } else if (timeleft == 0) { | |
5e8149f5 | 3200 | brcmf_err("resumed on timeout\n"); |
4fc0d016 | 3201 | brcmf_sdbrcm_checkdied(bus); |
23677ce3 | 3202 | } else if (pending) { |
5b435de0 AS |
3203 | brcmf_dbg(CTL, "cancelled\n"); |
3204 | return -ERESTARTSYS; | |
3205 | } else { | |
3206 | brcmf_dbg(CTL, "resumed for unknown reason?\n"); | |
4fc0d016 | 3207 | brcmf_sdbrcm_checkdied(bus); |
5b435de0 AS |
3208 | } |
3209 | ||
3210 | if (rxlen) | |
80969836 | 3211 | bus->sdcnt.rx_ctlpkts++; |
5b435de0 | 3212 | else |
80969836 | 3213 | bus->sdcnt.rx_ctlerrs++; |
5b435de0 AS |
3214 | |
3215 | return rxlen ? (int)rxlen : -ETIMEDOUT; | |
3216 | } | |
3217 | ||
069eddd9 | 3218 | static bool brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter) |
5b435de0 | 3219 | { |
99ba15cd | 3220 | struct chip_info *ci = bus->ci; |
5b435de0 AS |
3221 | |
3222 | /* To enter download state, disable ARM and reset SOCRAM. | |
3223 | * To exit download state, simply reset ARM (default is RAM boot). | |
3224 | */ | |
3225 | if (enter) { | |
3226 | bus->alp_only = true; | |
3227 | ||
069eddd9 | 3228 | brcmf_sdio_chip_enter_download(bus->sdiodev, ci); |
5b435de0 | 3229 | } else { |
069eddd9 FL |
3230 | if (!brcmf_sdio_chip_exit_download(bus->sdiodev, ci, bus->vars, |
3231 | bus->varsz)) | |
3232 | return false; | |
5b435de0 AS |
3233 | |
3234 | /* Allow HT Clock now that the ARM is running. */ | |
3235 | bus->alp_only = false; | |
3236 | ||
712ac5b3 | 3237 | bus->sdiodev->bus_if->state = BRCMF_BUS_LOAD; |
5b435de0 | 3238 | } |
069eddd9 FL |
3239 | |
3240 | return true; | |
5b435de0 AS |
3241 | } |
3242 | ||
e92eedf4 | 3243 | static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus) |
5b435de0 | 3244 | { |
f2c44fe7 HM |
3245 | const struct firmware *fw; |
3246 | int err; | |
1640f28f | 3247 | int offset; |
f2c44fe7 HM |
3248 | int address; |
3249 | int len; | |
3250 | ||
3251 | fw = brcmf_sdbrcm_get_fw(bus, BRCMF_FIRMWARE_BIN); | |
3252 | if (fw == NULL) | |
3253 | return -ENOENT; | |
3254 | ||
3255 | if (brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_ARM_CR4) != | |
3256 | BRCMF_MAX_CORENUM) | |
3257 | memcpy(&bus->ci->rst_vec, fw->data, sizeof(bus->ci->rst_vec)); | |
3258 | ||
3259 | err = 0; | |
3260 | offset = 0; | |
3261 | address = bus->ci->rambase; | |
3262 | while (offset < fw->size) { | |
3263 | len = ((offset + MEMBLOCK) < fw->size) ? MEMBLOCK : | |
3264 | fw->size - offset; | |
3265 | err = brcmf_sdio_ramrw(bus->sdiodev, true, address, | |
3266 | (u8 *)&fw->data[offset], len); | |
3267 | if (err) { | |
5e8149f5 | 3268 | brcmf_err("error %d on writing %d membytes at 0x%08x\n", |
f2c44fe7 HM |
3269 | err, len, address); |
3270 | goto failure; | |
5b435de0 | 3271 | } |
f2c44fe7 HM |
3272 | offset += len; |
3273 | address += len; | |
5b435de0 AS |
3274 | } |
3275 | ||
f2c44fe7 HM |
3276 | failure: |
3277 | release_firmware(fw); | |
5b435de0 | 3278 | |
f2c44fe7 | 3279 | return err; |
5b435de0 AS |
3280 | } |
3281 | ||
3282 | /* | |
3283 | * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file | |
3284 | * and ending in a NUL. | |
3285 | * Removes carriage returns, empty lines, comment lines, and converts | |
3286 | * newlines to NULs. | |
3287 | * Shortens buffer as needed and pads with NULs. End of buffer is marked | |
3288 | * by two NULs. | |
3289 | */ | |
3290 | ||
f2c44fe7 HM |
3291 | static int brcmf_process_nvram_vars(struct brcmf_sdio *bus, |
3292 | const struct firmware *nv) | |
5b435de0 | 3293 | { |
d610cde3 | 3294 | char *varbuf; |
5b435de0 AS |
3295 | char *dp; |
3296 | bool findNewline; | |
3297 | int column; | |
d610cde3 FL |
3298 | int ret = 0; |
3299 | uint buf_len, n, len; | |
3300 | ||
f2c44fe7 | 3301 | len = nv->size; |
d610cde3 FL |
3302 | varbuf = vmalloc(len); |
3303 | if (!varbuf) | |
3304 | return -ENOMEM; | |
5b435de0 | 3305 | |
f2c44fe7 | 3306 | memcpy(varbuf, nv->data, len); |
5b435de0 AS |
3307 | dp = varbuf; |
3308 | ||
3309 | findNewline = false; | |
3310 | column = 0; | |
3311 | ||
3312 | for (n = 0; n < len; n++) { | |
3313 | if (varbuf[n] == 0) | |
3314 | break; | |
3315 | if (varbuf[n] == '\r') | |
3316 | continue; | |
3317 | if (findNewline && varbuf[n] != '\n') | |
3318 | continue; | |
3319 | findNewline = false; | |
3320 | if (varbuf[n] == '#') { | |
3321 | findNewline = true; | |
3322 | continue; | |
3323 | } | |
3324 | if (varbuf[n] == '\n') { | |
3325 | if (column == 0) | |
3326 | continue; | |
3327 | *dp++ = 0; | |
3328 | column = 0; | |
3329 | continue; | |
3330 | } | |
3331 | *dp++ = varbuf[n]; | |
3332 | column++; | |
3333 | } | |
3334 | buf_len = dp - varbuf; | |
5b435de0 AS |
3335 | while (dp < varbuf + n) |
3336 | *dp++ = 0; | |
3337 | ||
d610cde3 | 3338 | kfree(bus->vars); |
6d4ef680 AS |
3339 | /* roundup needed for download to device */ |
3340 | bus->varsz = roundup(buf_len + 1, 4); | |
d610cde3 FL |
3341 | bus->vars = kmalloc(bus->varsz, GFP_KERNEL); |
3342 | if (bus->vars == NULL) { | |
3343 | bus->varsz = 0; | |
3344 | ret = -ENOMEM; | |
3345 | goto err; | |
3346 | } | |
3347 | ||
3348 | /* copy the processed variables and add null termination */ | |
3349 | memcpy(bus->vars, varbuf, buf_len); | |
3350 | bus->vars[buf_len] = 0; | |
3351 | err: | |
3352 | vfree(varbuf); | |
3353 | return ret; | |
5b435de0 AS |
3354 | } |
3355 | ||
e92eedf4 | 3356 | static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus) |
5b435de0 | 3357 | { |
f2c44fe7 | 3358 | const struct firmware *nv; |
5b435de0 AS |
3359 | int ret; |
3360 | ||
f2c44fe7 HM |
3361 | nv = brcmf_sdbrcm_get_fw(bus, BRCMF_FIRMWARE_NVRAM); |
3362 | if (nv == NULL) | |
3363 | return -ENOENT; | |
5b435de0 | 3364 | |
f2c44fe7 | 3365 | ret = brcmf_process_nvram_vars(bus, nv); |
5b435de0 | 3366 | |
f2c44fe7 | 3367 | release_firmware(nv); |
5b435de0 AS |
3368 | |
3369 | return ret; | |
3370 | } | |
3371 | ||
e92eedf4 | 3372 | static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus) |
5b435de0 AS |
3373 | { |
3374 | int bcmerror = -1; | |
3375 | ||
3376 | /* Keep arm in reset */ | |
069eddd9 | 3377 | if (!brcmf_sdbrcm_download_state(bus, true)) { |
5e8149f5 | 3378 | brcmf_err("error placing ARM core in reset\n"); |
5b435de0 AS |
3379 | goto err; |
3380 | } | |
3381 | ||
5b435de0 | 3382 | if (brcmf_sdbrcm_download_code_file(bus)) { |
5e8149f5 | 3383 | brcmf_err("dongle image file download failed\n"); |
5b435de0 AS |
3384 | goto err; |
3385 | } | |
3386 | ||
3eaa956c | 3387 | if (brcmf_sdbrcm_download_nvram(bus)) { |
5e8149f5 | 3388 | brcmf_err("dongle nvram file download failed\n"); |
3eaa956c FL |
3389 | goto err; |
3390 | } | |
5b435de0 AS |
3391 | |
3392 | /* Take arm out of reset */ | |
069eddd9 | 3393 | if (!brcmf_sdbrcm_download_state(bus, false)) { |
5e8149f5 | 3394 | brcmf_err("error getting out of ARM core reset\n"); |
5b435de0 AS |
3395 | goto err; |
3396 | } | |
3397 | ||
3398 | bcmerror = 0; | |
3399 | ||
3400 | err: | |
3401 | return bcmerror; | |
3402 | } | |
3403 | ||
4a3da990 PH |
3404 | static bool brcmf_sdbrcm_sr_capable(struct brcmf_sdio *bus) |
3405 | { | |
3406 | u32 addr, reg; | |
3407 | ||
3408 | brcmf_dbg(TRACE, "Enter\n"); | |
3409 | ||
3410 | /* old chips with PMU version less than 17 don't support save restore */ | |
3411 | if (bus->ci->pmurev < 17) | |
3412 | return false; | |
3413 | ||
3414 | /* read PMU chipcontrol register 3*/ | |
3415 | addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr); | |
3416 | brcmf_sdio_regwl(bus->sdiodev, addr, 3, NULL); | |
3417 | addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data); | |
3418 | reg = brcmf_sdio_regrl(bus->sdiodev, addr, NULL); | |
3419 | ||
3420 | return (bool)reg; | |
3421 | } | |
3422 | ||
3423 | static void brcmf_sdbrcm_sr_init(struct brcmf_sdio *bus) | |
3424 | { | |
3425 | int err = 0; | |
3426 | u8 val; | |
3427 | ||
3428 | brcmf_dbg(TRACE, "Enter\n"); | |
3429 | ||
3430 | val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, | |
3431 | &err); | |
3432 | if (err) { | |
3433 | brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3434 | return; | |
3435 | } | |
3436 | ||
3437 | val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; | |
3438 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, | |
3439 | val, &err); | |
3440 | if (err) { | |
3441 | brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3442 | return; | |
3443 | } | |
3444 | ||
3445 | /* Add CMD14 Support */ | |
3446 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, | |
3447 | (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | | |
3448 | SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT), | |
3449 | &err); | |
3450 | if (err) { | |
3451 | brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); | |
3452 | return; | |
3453 | } | |
3454 | ||
3455 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
3456 | SBSDIO_FORCE_HT, &err); | |
3457 | if (err) { | |
3458 | brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); | |
3459 | return; | |
3460 | } | |
3461 | ||
3462 | /* set flag */ | |
3463 | bus->sr_enabled = true; | |
3464 | brcmf_dbg(INFO, "SR enabled\n"); | |
3465 | } | |
3466 | ||
3467 | /* enable KSO bit */ | |
3468 | static int brcmf_sdbrcm_kso_init(struct brcmf_sdio *bus) | |
3469 | { | |
3470 | u8 val; | |
3471 | int err = 0; | |
3472 | ||
3473 | brcmf_dbg(TRACE, "Enter\n"); | |
3474 | ||
3475 | /* KSO bit added in SDIO core rev 12 */ | |
3476 | if (bus->ci->c_inf[1].rev < 12) | |
3477 | return 0; | |
3478 | ||
3479 | val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
3480 | &err); | |
3481 | if (err) { | |
3482 | brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); | |
3483 | return err; | |
3484 | } | |
3485 | ||
3486 | if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { | |
3487 | val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << | |
3488 | SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
3489 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
3490 | val, &err); | |
3491 | if (err) { | |
3492 | brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); | |
3493 | return err; | |
3494 | } | |
3495 | } | |
3496 | ||
3497 | return 0; | |
3498 | } | |
3499 | ||
3500 | ||
5b435de0 | 3501 | static bool |
e92eedf4 | 3502 | brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus) |
5b435de0 AS |
3503 | { |
3504 | bool ret; | |
3505 | ||
38b0b0dd FL |
3506 | sdio_claim_host(bus->sdiodev->func[1]); |
3507 | ||
5b435de0 AS |
3508 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); |
3509 | ||
3510 | ret = _brcmf_sdbrcm_download_firmware(bus) == 0; | |
3511 | ||
3512 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
3513 | ||
38b0b0dd FL |
3514 | sdio_release_host(bus->sdiodev->func[1]); |
3515 | ||
5b435de0 AS |
3516 | return ret; |
3517 | } | |
3518 | ||
cf458287 AS |
3519 | static int brcmf_sdbrcm_bus_preinit(struct device *dev) |
3520 | { | |
3521 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3522 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3523 | struct brcmf_sdio *bus = sdiodev->bus; | |
8da9d2c8 | 3524 | uint pad_size; |
cf458287 AS |
3525 | u32 value; |
3526 | u8 idx; | |
3527 | int err; | |
3528 | ||
8da9d2c8 FL |
3529 | /* the commands below use the terms tx and rx from |
3530 | * a device perspective, ie. bus:txglom affects the | |
3531 | * bus transfers from device to host. | |
3532 | */ | |
cf458287 AS |
3533 | idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); |
3534 | if (bus->ci->c_inf[idx].rev < 12) { | |
3535 | /* for sdio core rev < 12, disable txgloming */ | |
3536 | value = 0; | |
3537 | err = brcmf_iovar_data_set(dev, "bus:txglom", &value, | |
3538 | sizeof(u32)); | |
3539 | } else { | |
3540 | /* otherwise, set txglomalign */ | |
3541 | value = 4; | |
3542 | if (sdiodev->pdata) | |
3543 | value = sdiodev->pdata->sd_sgentry_align; | |
3544 | /* SDIO ADMA requires at least 32 bit alignment */ | |
3545 | value = max_t(u32, value, 4); | |
3546 | err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value, | |
3547 | sizeof(u32)); | |
3548 | } | |
8da9d2c8 FL |
3549 | |
3550 | if (err < 0) | |
3551 | goto done; | |
3552 | ||
3553 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
3554 | if (sdiodev->sg_support) { | |
3555 | bus->txglom = false; | |
3556 | value = 1; | |
3557 | pad_size = bus->sdiodev->func[2]->cur_blksize << 1; | |
3558 | bus->txglom_sgpad = brcmu_pkt_buf_get_skb(pad_size); | |
3559 | if (!bus->txglom_sgpad) | |
3560 | brcmf_err("allocating txglom padding skb failed, reduced performance\n"); | |
3561 | ||
3562 | err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", | |
3563 | &value, sizeof(u32)); | |
3564 | if (err < 0) { | |
3565 | /* bus:rxglom is allowed to fail */ | |
3566 | err = 0; | |
3567 | } else { | |
3568 | bus->txglom = true; | |
3569 | bus->tx_hdrlen += SDPCM_HWEXT_LEN; | |
3570 | } | |
3571 | } | |
3572 | brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); | |
3573 | ||
3574 | done: | |
cf458287 AS |
3575 | return err; |
3576 | } | |
3577 | ||
99a0b8ff | 3578 | static int brcmf_sdbrcm_bus_init(struct device *dev) |
5b435de0 | 3579 | { |
fa20b911 | 3580 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3581 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
fa20b911 | 3582 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 | 3583 | unsigned long timeout; |
5b435de0 AS |
3584 | u8 ready, enable; |
3585 | int err, ret = 0; | |
3586 | u8 saveclk; | |
3587 | ||
3588 | brcmf_dbg(TRACE, "Enter\n"); | |
3589 | ||
3590 | /* try to download image and nvram to the dongle */ | |
fa20b911 | 3591 | if (bus_if->state == BRCMF_BUS_DOWN) { |
5b435de0 AS |
3592 | if (!(brcmf_sdbrcm_download_firmware(bus))) |
3593 | return -1; | |
3594 | } | |
3595 | ||
712ac5b3 | 3596 | if (!bus->sdiodev->bus_if->drvr) |
5b435de0 AS |
3597 | return 0; |
3598 | ||
3599 | /* Start the watchdog timer */ | |
80969836 | 3600 | bus->sdcnt.tickcnt = 0; |
5b435de0 AS |
3601 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); |
3602 | ||
38b0b0dd | 3603 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3604 | |
3605 | /* Make sure backplane clock is on, needed to generate F2 interrupt */ | |
3606 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3607 | if (bus->clkstate != CLK_AVAIL) | |
3608 | goto exit; | |
3609 | ||
3610 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
45db339c FL |
3611 | saveclk = brcmf_sdio_regrb(bus->sdiodev, |
3612 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 3613 | if (!err) { |
3bba829f FL |
3614 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3615 | (saveclk | SBSDIO_FORCE_HT), &err); | |
5b435de0 AS |
3616 | } |
3617 | if (err) { | |
5e8149f5 | 3618 | brcmf_err("Failed to force clock for F2: err %d\n", err); |
5b435de0 AS |
3619 | goto exit; |
3620 | } | |
3621 | ||
3622 | /* Enable function 2 (frame transfers) */ | |
3623 | w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, | |
58692750 | 3624 | offsetof(struct sdpcmd_regs, tosbmailboxdata)); |
5b435de0 AS |
3625 | enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2); |
3626 | ||
3bba829f | 3627 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL); |
5b435de0 AS |
3628 | |
3629 | timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY); | |
3630 | ready = 0; | |
3631 | while (enable != ready) { | |
45db339c FL |
3632 | ready = brcmf_sdio_regrb(bus->sdiodev, |
3633 | SDIO_CCCR_IORx, NULL); | |
5b435de0 AS |
3634 | if (time_after(jiffies, timeout)) |
3635 | break; | |
3636 | else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50)) | |
3637 | /* prevent busy waiting if it takes too long */ | |
3638 | msleep_interruptible(20); | |
3639 | } | |
3640 | ||
3641 | brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready); | |
3642 | ||
3643 | /* If F2 successfully enabled, set core and enable interrupts */ | |
3644 | if (ready == enable) { | |
3645 | /* Set up the interrupt mask and enable interrupts */ | |
3646 | bus->hostintmask = HOSTINTMASK; | |
3647 | w_sdreg32(bus, bus->hostintmask, | |
58692750 | 3648 | offsetof(struct sdpcmd_regs, hostintmask)); |
5b435de0 | 3649 | |
3bba829f | 3650 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_WATERMARK, 8, &err); |
c0e89f08 | 3651 | } else { |
5b435de0 AS |
3652 | /* Disable F2 again */ |
3653 | enable = SDIO_FUNC_ENABLE_1; | |
3bba829f | 3654 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL); |
c0e89f08 | 3655 | ret = -ENODEV; |
5b435de0 AS |
3656 | } |
3657 | ||
4a3da990 PH |
3658 | if (brcmf_sdbrcm_sr_capable(bus)) { |
3659 | brcmf_sdbrcm_sr_init(bus); | |
3660 | } else { | |
3661 | /* Restore previous clock setting */ | |
3662 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
3663 | saveclk, &err); | |
3664 | } | |
5b435de0 | 3665 | |
e2f93cc3 | 3666 | if (ret == 0) { |
ba89bf19 | 3667 | ret = brcmf_sdio_intr_register(bus->sdiodev); |
e2f93cc3 | 3668 | if (ret != 0) |
5e8149f5 | 3669 | brcmf_err("intr register failed:%d\n", ret); |
e2f93cc3 FL |
3670 | } |
3671 | ||
5b435de0 | 3672 | /* If we didn't come up, turn off backplane clock */ |
d9126e0c | 3673 | if (bus_if->state != BRCMF_BUS_DATA) |
5b435de0 AS |
3674 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); |
3675 | ||
3676 | exit: | |
38b0b0dd | 3677 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3678 | |
3679 | return ret; | |
3680 | } | |
3681 | ||
3682 | void brcmf_sdbrcm_isr(void *arg) | |
3683 | { | |
e92eedf4 | 3684 | struct brcmf_sdio *bus = (struct brcmf_sdio *) arg; |
5b435de0 AS |
3685 | |
3686 | brcmf_dbg(TRACE, "Enter\n"); | |
3687 | ||
3688 | if (!bus) { | |
5e8149f5 | 3689 | brcmf_err("bus is null pointer, exiting\n"); |
5b435de0 AS |
3690 | return; |
3691 | } | |
3692 | ||
712ac5b3 | 3693 | if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) { |
5e8149f5 | 3694 | brcmf_err("bus is down. we have nothing to do\n"); |
5b435de0 AS |
3695 | return; |
3696 | } | |
3697 | /* Count the interrupt call */ | |
80969836 | 3698 | bus->sdcnt.intrcount++; |
4531603a FL |
3699 | if (in_interrupt()) |
3700 | atomic_set(&bus->ipend, 1); | |
3701 | else | |
3702 | if (brcmf_sdio_intr_rstatus(bus)) { | |
5e8149f5 | 3703 | brcmf_err("failed backplane access\n"); |
4531603a FL |
3704 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
3705 | } | |
5b435de0 | 3706 | |
5b435de0 AS |
3707 | /* Disable additional interrupts (is this needed now)? */ |
3708 | if (!bus->intr) | |
5e8149f5 | 3709 | brcmf_err("isr w/o interrupt configured!\n"); |
5b435de0 | 3710 | |
fccfe930 | 3711 | atomic_inc(&bus->dpc_tskcnt); |
f1e68c2e | 3712 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3713 | } |
3714 | ||
cad2b26b | 3715 | static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus) |
5b435de0 | 3716 | { |
8ae74654 | 3717 | #ifdef DEBUG |
cad2b26b | 3718 | struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev); |
8ae74654 | 3719 | #endif /* DEBUG */ |
5b435de0 AS |
3720 | |
3721 | brcmf_dbg(TIMER, "Enter\n"); | |
3722 | ||
5b435de0 | 3723 | /* Poll period: check device if appropriate. */ |
4a3da990 PH |
3724 | if (!bus->sr_enabled && |
3725 | bus->poll && (++bus->polltick >= bus->pollrate)) { | |
5b435de0 AS |
3726 | u32 intstatus = 0; |
3727 | ||
3728 | /* Reset poll tick */ | |
3729 | bus->polltick = 0; | |
3730 | ||
3731 | /* Check device if no interrupts */ | |
80969836 AS |
3732 | if (!bus->intr || |
3733 | (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { | |
5b435de0 | 3734 | |
fccfe930 | 3735 | if (atomic_read(&bus->dpc_tskcnt) == 0) { |
5b435de0 | 3736 | u8 devpend; |
fccfe930 | 3737 | |
38b0b0dd | 3738 | sdio_claim_host(bus->sdiodev->func[1]); |
45db339c FL |
3739 | devpend = brcmf_sdio_regrb(bus->sdiodev, |
3740 | SDIO_CCCR_INTx, | |
3741 | NULL); | |
38b0b0dd | 3742 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3743 | intstatus = |
3744 | devpend & (INTR_STATUS_FUNC1 | | |
3745 | INTR_STATUS_FUNC2); | |
3746 | } | |
3747 | ||
3748 | /* If there is something, make like the ISR and | |
3749 | schedule the DPC */ | |
3750 | if (intstatus) { | |
80969836 | 3751 | bus->sdcnt.pollcnt++; |
1d382273 | 3752 | atomic_set(&bus->ipend, 1); |
5b435de0 | 3753 | |
fccfe930 | 3754 | atomic_inc(&bus->dpc_tskcnt); |
f1e68c2e | 3755 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3756 | } |
3757 | } | |
3758 | ||
3759 | /* Update interrupt tracking */ | |
80969836 | 3760 | bus->sdcnt.lastintrs = bus->sdcnt.intrcount; |
5b435de0 | 3761 | } |
8ae74654 | 3762 | #ifdef DEBUG |
5b435de0 | 3763 | /* Poll for console output periodically */ |
2def5c10 | 3764 | if (bus_if && bus_if->state == BRCMF_BUS_DATA && |
8d169aa0 | 3765 | bus->console_interval != 0) { |
5b435de0 AS |
3766 | bus->console.count += BRCMF_WD_POLL_MS; |
3767 | if (bus->console.count >= bus->console_interval) { | |
3768 | bus->console.count -= bus->console_interval; | |
38b0b0dd | 3769 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 3770 | /* Make sure backplane clock is on */ |
4a3da990 | 3771 | brcmf_sdbrcm_bus_sleep(bus, false, false); |
5b435de0 AS |
3772 | if (brcmf_sdbrcm_readconsole(bus) < 0) |
3773 | /* stop on error */ | |
3774 | bus->console_interval = 0; | |
38b0b0dd | 3775 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3776 | } |
3777 | } | |
8ae74654 | 3778 | #endif /* DEBUG */ |
5b435de0 AS |
3779 | |
3780 | /* On idle timeout clear activity flag and/or turn off clock */ | |
3781 | if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) { | |
3782 | if (++bus->idlecount >= bus->idletime) { | |
3783 | bus->idlecount = 0; | |
3784 | if (bus->activity) { | |
3785 | bus->activity = false; | |
3786 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
3787 | } else { | |
4a3da990 | 3788 | brcmf_dbg(SDIO, "idle\n"); |
38b0b0dd | 3789 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 3790 | brcmf_sdbrcm_bus_sleep(bus, true, false); |
38b0b0dd | 3791 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3792 | } |
3793 | } | |
3794 | } | |
3795 | ||
1d382273 | 3796 | return (atomic_read(&bus->ipend) > 0); |
5b435de0 AS |
3797 | } |
3798 | ||
f1e68c2e FL |
3799 | static void brcmf_sdio_dataworker(struct work_struct *work) |
3800 | { | |
3801 | struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, | |
3802 | datawork); | |
f1e68c2e | 3803 | |
fccfe930 | 3804 | while (atomic_read(&bus->dpc_tskcnt)) { |
f1e68c2e | 3805 | brcmf_sdbrcm_dpc(bus); |
fccfe930 | 3806 | atomic_dec(&bus->dpc_tskcnt); |
f1e68c2e | 3807 | } |
f1e68c2e FL |
3808 | } |
3809 | ||
e92eedf4 | 3810 | static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus) |
5b435de0 AS |
3811 | { |
3812 | brcmf_dbg(TRACE, "Enter\n"); | |
3813 | ||
3814 | kfree(bus->rxbuf); | |
3815 | bus->rxctl = bus->rxbuf = NULL; | |
3816 | bus->rxlen = 0; | |
5b435de0 AS |
3817 | } |
3818 | ||
e92eedf4 | 3819 | static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus) |
5b435de0 AS |
3820 | { |
3821 | brcmf_dbg(TRACE, "Enter\n"); | |
3822 | ||
b01a6b3c | 3823 | if (bus->sdiodev->bus_if->maxctl) { |
5b435de0 | 3824 | bus->rxblen = |
b01a6b3c | 3825 | roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN), |
5b435de0 AS |
3826 | ALIGNMENT) + BRCMF_SDALIGN; |
3827 | bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); | |
3828 | if (!(bus->rxbuf)) | |
354b75bf | 3829 | return false; |
5b435de0 AS |
3830 | } |
3831 | ||
5b435de0 | 3832 | return true; |
5b435de0 AS |
3833 | } |
3834 | ||
5b435de0 | 3835 | static bool |
e92eedf4 | 3836 | brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva) |
5b435de0 AS |
3837 | { |
3838 | u8 clkctl = 0; | |
3839 | int err = 0; | |
3840 | int reg_addr; | |
3841 | u32 reg_val; | |
668761ac | 3842 | u32 drivestrength; |
5b435de0 AS |
3843 | |
3844 | bus->alp_only = true; | |
3845 | ||
38b0b0dd FL |
3846 | sdio_claim_host(bus->sdiodev->func[1]); |
3847 | ||
18aad4f8 | 3848 | pr_debug("F1 signature read @0x18000000=0x%4x\n", |
79ae3957 | 3849 | brcmf_sdio_regrl(bus->sdiodev, SI_ENUM_BASE, NULL)); |
5b435de0 AS |
3850 | |
3851 | /* | |
a97e4fc5 | 3852 | * Force PLL off until brcmf_sdio_chip_attach() |
5b435de0 AS |
3853 | * programs PLL control regs |
3854 | */ | |
3855 | ||
3bba829f FL |
3856 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3857 | BRCMF_INIT_CLKCTL1, &err); | |
5b435de0 | 3858 | if (!err) |
45db339c | 3859 | clkctl = brcmf_sdio_regrb(bus->sdiodev, |
5b435de0 AS |
3860 | SBSDIO_FUNC1_CHIPCLKCSR, &err); |
3861 | ||
3862 | if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { | |
5e8149f5 | 3863 | brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", |
5b435de0 AS |
3864 | err, BRCMF_INIT_CLKCTL1, clkctl); |
3865 | goto fail; | |
3866 | } | |
3867 | ||
a97e4fc5 | 3868 | if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) { |
5e8149f5 | 3869 | brcmf_err("brcmf_sdio_chip_attach failed!\n"); |
5b435de0 AS |
3870 | goto fail; |
3871 | } | |
3872 | ||
4a3da990 PH |
3873 | if (brcmf_sdbrcm_kso_init(bus)) { |
3874 | brcmf_err("error enabling KSO\n"); | |
3875 | goto fail; | |
3876 | } | |
3877 | ||
668761ac HM |
3878 | if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength)) |
3879 | drivestrength = bus->sdiodev->pdata->drive_strength; | |
3880 | else | |
3881 | drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; | |
3882 | brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength); | |
5b435de0 | 3883 | |
454d2a88 | 3884 | /* Get info on the SOCRAM cores... */ |
5b435de0 AS |
3885 | bus->ramsize = bus->ci->ramsize; |
3886 | if (!(bus->ramsize)) { | |
5e8149f5 | 3887 | brcmf_err("failed to find SOCRAM memory!\n"); |
5b435de0 AS |
3888 | goto fail; |
3889 | } | |
3890 | ||
1e9ab4dd PH |
3891 | /* Set card control so an SDIO card reset does a WLAN backplane reset */ |
3892 | reg_val = brcmf_sdio_regrb(bus->sdiodev, | |
3893 | SDIO_CCCR_BRCM_CARDCTRL, &err); | |
3894 | if (err) | |
3895 | goto fail; | |
3896 | ||
3897 | reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; | |
3898 | ||
3899 | brcmf_sdio_regwb(bus->sdiodev, | |
3900 | SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); | |
3901 | if (err) | |
3902 | goto fail; | |
3903 | ||
3904 | /* set PMUControl so a backplane reset does PMU state reload */ | |
3905 | reg_addr = CORE_CC_REG(bus->ci->c_inf[0].base, | |
3906 | pmucontrol); | |
3907 | reg_val = brcmf_sdio_regrl(bus->sdiodev, | |
3908 | reg_addr, | |
3909 | &err); | |
3910 | if (err) | |
3911 | goto fail; | |
3912 | ||
3913 | reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); | |
3914 | ||
3915 | brcmf_sdio_regwl(bus->sdiodev, | |
3916 | reg_addr, | |
3917 | reg_val, | |
3918 | &err); | |
3919 | if (err) | |
3920 | goto fail; | |
3921 | ||
5b435de0 | 3922 | |
38b0b0dd FL |
3923 | sdio_release_host(bus->sdiodev->func[1]); |
3924 | ||
5b435de0 AS |
3925 | brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); |
3926 | ||
3927 | /* Locate an appropriately-aligned portion of hdrbuf */ | |
3928 | bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], | |
3929 | BRCMF_SDALIGN); | |
3930 | ||
3931 | /* Set the poll and/or interrupt flags */ | |
3932 | bus->intr = true; | |
3933 | bus->poll = false; | |
3934 | if (bus->poll) | |
3935 | bus->pollrate = 1; | |
3936 | ||
3937 | return true; | |
3938 | ||
3939 | fail: | |
38b0b0dd | 3940 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3941 | return false; |
3942 | } | |
3943 | ||
e92eedf4 | 3944 | static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus) |
5b435de0 AS |
3945 | { |
3946 | brcmf_dbg(TRACE, "Enter\n"); | |
3947 | ||
38b0b0dd FL |
3948 | sdio_claim_host(bus->sdiodev->func[1]); |
3949 | ||
5b435de0 | 3950 | /* Disable F2 to clear any intermediate frame state on the dongle */ |
3bba829f FL |
3951 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, |
3952 | SDIO_FUNC_ENABLE_1, NULL); | |
5b435de0 | 3953 | |
712ac5b3 | 3954 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
3955 | bus->rxflow = false; |
3956 | ||
3957 | /* Done with backplane-dependent accesses, can drop clock... */ | |
3bba829f | 3958 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); |
5b435de0 | 3959 | |
38b0b0dd FL |
3960 | sdio_release_host(bus->sdiodev->func[1]); |
3961 | ||
5b435de0 AS |
3962 | /* ...and initialize clock/power states */ |
3963 | bus->clkstate = CLK_SDONLY; | |
3964 | bus->idletime = BRCMF_IDLE_INTERVAL; | |
3965 | bus->idleclock = BRCMF_IDLE_ACTIVE; | |
3966 | ||
3967 | /* Query the F2 block size, set roundup accordingly */ | |
3968 | bus->blocksize = bus->sdiodev->func[2]->cur_blksize; | |
3969 | bus->roundup = min(max_roundup, bus->blocksize); | |
3970 | ||
4a3da990 PH |
3971 | /* SR state */ |
3972 | bus->sleeping = false; | |
3973 | bus->sr_enabled = false; | |
3974 | ||
5b435de0 AS |
3975 | return true; |
3976 | } | |
3977 | ||
3978 | static int | |
3979 | brcmf_sdbrcm_watchdog_thread(void *data) | |
3980 | { | |
e92eedf4 | 3981 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3982 | |
3983 | allow_signal(SIGTERM); | |
3984 | /* Run until signal received */ | |
3985 | while (1) { | |
3986 | if (kthread_should_stop()) | |
3987 | break; | |
3988 | if (!wait_for_completion_interruptible(&bus->watchdog_wait)) { | |
cad2b26b | 3989 | brcmf_sdbrcm_bus_watchdog(bus); |
5b435de0 | 3990 | /* Count the tick for reference */ |
80969836 | 3991 | bus->sdcnt.tickcnt++; |
5b435de0 AS |
3992 | } else |
3993 | break; | |
3994 | } | |
3995 | return 0; | |
3996 | } | |
3997 | ||
3998 | static void | |
3999 | brcmf_sdbrcm_watchdog(unsigned long data) | |
4000 | { | |
e92eedf4 | 4001 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
4002 | |
4003 | if (bus->watchdog_tsk) { | |
4004 | complete(&bus->watchdog_wait); | |
4005 | /* Reschedule the watchdog */ | |
4006 | if (bus->wd_timer_valid) | |
4007 | mod_timer(&bus->timer, | |
4008 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
4009 | } | |
4010 | } | |
4011 | ||
e92eedf4 | 4012 | static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus) |
5b435de0 AS |
4013 | { |
4014 | brcmf_dbg(TRACE, "Enter\n"); | |
4015 | ||
4016 | if (bus->ci) { | |
38b0b0dd | 4017 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
4018 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); |
4019 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); | |
38b0b0dd | 4020 | sdio_release_host(bus->sdiodev->func[1]); |
a8a6c045 | 4021 | brcmf_sdio_chip_detach(&bus->ci); |
5b435de0 AS |
4022 | if (bus->vars && bus->varsz) |
4023 | kfree(bus->vars); | |
4024 | bus->vars = NULL; | |
4025 | } | |
4026 | ||
4027 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4028 | } | |
4029 | ||
4030 | /* Detach and free everything */ | |
e92eedf4 | 4031 | static void brcmf_sdbrcm_release(struct brcmf_sdio *bus) |
5b435de0 AS |
4032 | { |
4033 | brcmf_dbg(TRACE, "Enter\n"); | |
4fc0d016 | 4034 | |
5b435de0 AS |
4035 | if (bus) { |
4036 | /* De-register interrupt handler */ | |
ba89bf19 | 4037 | brcmf_sdio_intr_unregister(bus->sdiodev); |
5b435de0 | 4038 | |
f1e68c2e | 4039 | cancel_work_sync(&bus->datawork); |
37ac5780 HM |
4040 | if (bus->brcmf_wq) |
4041 | destroy_workqueue(bus->brcmf_wq); | |
f1e68c2e | 4042 | |
5f947ad9 FL |
4043 | if (bus->sdiodev->bus_if->drvr) { |
4044 | brcmf_detach(bus->sdiodev->dev); | |
5b435de0 | 4045 | brcmf_sdbrcm_release_dongle(bus); |
5b435de0 AS |
4046 | } |
4047 | ||
8da9d2c8 | 4048 | brcmu_pkt_buf_free_skb(bus->txglom_sgpad); |
5b435de0 AS |
4049 | brcmf_sdbrcm_release_malloc(bus); |
4050 | ||
4051 | kfree(bus); | |
4052 | } | |
4053 | ||
4054 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4055 | } | |
4056 | ||
d9cb2596 AS |
4057 | static struct brcmf_bus_ops brcmf_sdio_bus_ops = { |
4058 | .stop = brcmf_sdbrcm_bus_stop, | |
cf458287 | 4059 | .preinit = brcmf_sdbrcm_bus_preinit, |
d9cb2596 AS |
4060 | .init = brcmf_sdbrcm_bus_init, |
4061 | .txdata = brcmf_sdbrcm_bus_txdata, | |
4062 | .txctl = brcmf_sdbrcm_bus_txctl, | |
4063 | .rxctl = brcmf_sdbrcm_bus_rxctl, | |
e2432b67 | 4064 | .gettxq = brcmf_sdbrcm_bus_gettxq, |
d9cb2596 AS |
4065 | }; |
4066 | ||
4175b88b | 4067 | void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev) |
5b435de0 AS |
4068 | { |
4069 | int ret; | |
e92eedf4 | 4070 | struct brcmf_sdio *bus; |
5b435de0 | 4071 | |
5b435de0 AS |
4072 | brcmf_dbg(TRACE, "Enter\n"); |
4073 | ||
4074 | /* We make an assumption about address window mappings: | |
4075 | * regsva == SI_ENUM_BASE*/ | |
4076 | ||
4077 | /* Allocate private bus interface state */ | |
e92eedf4 | 4078 | bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); |
5b435de0 AS |
4079 | if (!bus) |
4080 | goto fail; | |
4081 | ||
4082 | bus->sdiodev = sdiodev; | |
4083 | sdiodev->bus = bus; | |
b83db862 | 4084 | skb_queue_head_init(&bus->glom); |
5b435de0 AS |
4085 | bus->txbound = BRCMF_TXBOUND; |
4086 | bus->rxbound = BRCMF_RXBOUND; | |
4087 | bus->txminmax = BRCMF_TXMINMAX; | |
6bc52319 | 4088 | bus->tx_seq = SDPCM_SEQ_WRAP - 1; |
5b435de0 | 4089 | |
e217d1c8 AS |
4090 | /* platform specific configuration: |
4091 | * alignments must be at least 4 bytes for ADMA | |
4092 | */ | |
4093 | bus->head_align = ALIGNMENT; | |
4094 | bus->sgentry_align = ALIGNMENT; | |
4095 | if (sdiodev->pdata) { | |
4096 | if (sdiodev->pdata->sd_head_align > ALIGNMENT) | |
4097 | bus->head_align = sdiodev->pdata->sd_head_align; | |
4098 | if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT) | |
4099 | bus->sgentry_align = sdiodev->pdata->sd_sgentry_align; | |
4100 | } | |
4101 | ||
37ac5780 HM |
4102 | INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); |
4103 | bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq"); | |
4104 | if (bus->brcmf_wq == NULL) { | |
5e8149f5 | 4105 | brcmf_err("insufficient memory to create txworkqueue\n"); |
37ac5780 HM |
4106 | goto fail; |
4107 | } | |
4108 | ||
5b435de0 AS |
4109 | /* attempt to attach to the dongle */ |
4110 | if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) { | |
5e8149f5 | 4111 | brcmf_err("brcmf_sdbrcm_probe_attach failed\n"); |
5b435de0 AS |
4112 | goto fail; |
4113 | } | |
4114 | ||
dd43a01c | 4115 | spin_lock_init(&bus->rxctl_lock); |
5b435de0 AS |
4116 | spin_lock_init(&bus->txqlock); |
4117 | init_waitqueue_head(&bus->ctrl_wait); | |
4118 | init_waitqueue_head(&bus->dcmd_resp_wait); | |
4119 | ||
4120 | /* Set up the watchdog timer */ | |
4121 | init_timer(&bus->timer); | |
4122 | bus->timer.data = (unsigned long)bus; | |
4123 | bus->timer.function = brcmf_sdbrcm_watchdog; | |
4124 | ||
5b435de0 AS |
4125 | /* Initialize watchdog thread */ |
4126 | init_completion(&bus->watchdog_wait); | |
4127 | bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread, | |
4128 | bus, "brcmf_watchdog"); | |
4129 | if (IS_ERR(bus->watchdog_tsk)) { | |
02f77195 | 4130 | pr_warn("brcmf_watchdog thread failed to start\n"); |
5b435de0 AS |
4131 | bus->watchdog_tsk = NULL; |
4132 | } | |
4133 | /* Initialize DPC thread */ | |
fccfe930 | 4134 | atomic_set(&bus->dpc_tskcnt, 0); |
5b435de0 | 4135 | |
a9ffda88 | 4136 | /* Assign bus interface call back */ |
d9cb2596 AS |
4137 | bus->sdiodev->bus_if->dev = bus->sdiodev->dev; |
4138 | bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops; | |
75d907d3 AS |
4139 | bus->sdiodev->bus_if->chip = bus->ci->chip; |
4140 | bus->sdiodev->bus_if->chiprev = bus->ci->chiprev; | |
d9cb2596 | 4141 | |
706478cb FL |
4142 | /* default sdio bus header length for tx packet */ |
4143 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
4144 | ||
4145 | /* Attach to the common layer, reserve hdr space */ | |
8dee77ba | 4146 | ret = brcmf_attach(bus->sdiodev->dev); |
712ac5b3 | 4147 | if (ret != 0) { |
5e8149f5 | 4148 | brcmf_err("brcmf_attach failed\n"); |
5b435de0 AS |
4149 | goto fail; |
4150 | } | |
4151 | ||
4152 | /* Allocate buffers */ | |
4153 | if (!(brcmf_sdbrcm_probe_malloc(bus))) { | |
5e8149f5 | 4154 | brcmf_err("brcmf_sdbrcm_probe_malloc failed\n"); |
5b435de0 AS |
4155 | goto fail; |
4156 | } | |
4157 | ||
4158 | if (!(brcmf_sdbrcm_probe_init(bus))) { | |
5e8149f5 | 4159 | brcmf_err("brcmf_sdbrcm_probe_init failed\n"); |
5b435de0 AS |
4160 | goto fail; |
4161 | } | |
4162 | ||
80969836 | 4163 | brcmf_sdio_debugfs_create(bus); |
5b435de0 AS |
4164 | brcmf_dbg(INFO, "completed!!\n"); |
4165 | ||
4166 | /* if firmware path present try to download and bring up bus */ | |
ed683c98 | 4167 | ret = brcmf_bus_start(bus->sdiodev->dev); |
5b435de0 | 4168 | if (ret != 0) { |
5e8149f5 | 4169 | brcmf_err("dongle is not responding\n"); |
1799ddf1 | 4170 | goto fail; |
5b435de0 | 4171 | } |
15d45b6f | 4172 | |
5b435de0 AS |
4173 | return bus; |
4174 | ||
4175 | fail: | |
4176 | brcmf_sdbrcm_release(bus); | |
4177 | return NULL; | |
4178 | } | |
4179 | ||
4180 | void brcmf_sdbrcm_disconnect(void *ptr) | |
4181 | { | |
e92eedf4 | 4182 | struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr; |
5b435de0 AS |
4183 | |
4184 | brcmf_dbg(TRACE, "Enter\n"); | |
4185 | ||
4186 | if (bus) | |
4187 | brcmf_sdbrcm_release(bus); | |
4188 | ||
4189 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4190 | } | |
4191 | ||
5b435de0 | 4192 | void |
e92eedf4 | 4193 | brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick) |
5b435de0 | 4194 | { |
5b435de0 | 4195 | /* Totally stop the timer */ |
23677ce3 | 4196 | if (!wdtick && bus->wd_timer_valid) { |
5b435de0 AS |
4197 | del_timer_sync(&bus->timer); |
4198 | bus->wd_timer_valid = false; | |
4199 | bus->save_ms = wdtick; | |
4200 | return; | |
4201 | } | |
4202 | ||
ece960ea | 4203 | /* don't start the wd until fw is loaded */ |
712ac5b3 | 4204 | if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) |
ece960ea FL |
4205 | return; |
4206 | ||
5b435de0 AS |
4207 | if (wdtick) { |
4208 | if (bus->save_ms != BRCMF_WD_POLL_MS) { | |
23677ce3 | 4209 | if (bus->wd_timer_valid) |
5b435de0 AS |
4210 | /* Stop timer and restart at new value */ |
4211 | del_timer_sync(&bus->timer); | |
4212 | ||
4213 | /* Create timer again when watchdog period is | |
4214 | dynamically changed or in the first instance | |
4215 | */ | |
4216 | bus->timer.expires = | |
4217 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000; | |
4218 | add_timer(&bus->timer); | |
4219 | ||
4220 | } else { | |
4221 | /* Re arm the timer, at last watchdog period */ | |
4222 | mod_timer(&bus->timer, | |
4223 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
4224 | } | |
4225 | ||
4226 | bus->wd_timer_valid = true; | |
4227 | bus->save_ms = wdtick; | |
4228 | } | |
4229 | } |