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iwlwifi: pcie: don't disable interrupts for reg_lock
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
8e99ea8d
JB		 1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2007-2015, 2018-2020 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
a42a1844 7#include <linux/pci.h>
e6bb4c9c 8#include <linux/interrupt.h>
87e5666c 9#include <linux/debugfs.h>
cf614297 10#include <linux/sched.h>
6d8f6eeb
EG		 11#include <linux/bitops.h>
12#include <linux/gfp.h>
48eb7b34 13#include <linux/vmalloc.h>
49564a80 14#include <linux/module.h>
f7805b33 15#include <linux/wait.h>
df67a1be 16#include <linux/seq_file.h>
e6bb4c9c 17
82575102 18#include "iwl-drv.h"
c85eb619 19#include "iwl-trans.h"
522376d2
EG		 20#include "iwl-csr.h"
21#include "iwl-prph.h"
cb6bb128 22#include "iwl-scd.h"
7a10e3e4 23#include "iwl-agn-hw.h"
d962f9b1 24#include "fw/error-dump.h"
520f03ea 25#include "fw/dbg.h"
a89c72ff 26#include "fw/api/tx.h"
6468a01a 27#include "internal.h"
06d51e0d 28#include "iwl-fh.h"
6654cd4e 29#include "iwl-context-info-gen3.h"
0439bb62 30
fe45773b
AN		 31/* extended range in FW SRAM */
32#define IWL_FW_MEM_EXTENDED_START 0x40000
33#define IWL_FW_MEM_EXTENDED_END 0x57FFF
34
4290eaad 35void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
a6d24fad 36{
c4d3f2ee
LC		 37#define PCI_DUMP_SIZE 352
38#define PCI_MEM_DUMP_SIZE 64
39#define PCI_PARENT_DUMP_SIZE 524
40#define PREFIX_LEN 32
a6d24fad
RJ		 41 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
42 struct pci_dev *pdev = trans_pcie->pci_dev;
43 u32 i, pos, alloc_size, *ptr, *buf;
44 char *prefix;
45
46 if (trans_pcie->pcie_dbg_dumped_once)
47 return;
48
49 /* Should be a multiple of 4 */
50 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
c4d3f2ee
LC		 51 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
52 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
53
a6d24fad 54 /* Alloc a max size buffer */
c4d3f2ee
LC		 55 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
56 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
57 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
58 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
59
a6d24fad
RJ		 60 buf = kmalloc(alloc_size, GFP_ATOMIC);
61 if (!buf)
62 return;
63 prefix = (char *)buf + alloc_size - PREFIX_LEN;
64
65 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
66
67 /* Print wifi device registers */
68 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
69 IWL_ERR(trans, "iwlwifi device config registers:\n");
70 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
71 if (pci_read_config_dword(pdev, i, ptr))
72 goto err_read;
73 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
74
75 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
c4d3f2ee 76 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 77 *ptr = iwl_read32(trans, i);
78 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
79
80 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
81 if (pos) {
82 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
83 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
84 if (pci_read_config_dword(pdev, pos + i, ptr))
85 goto err_read;
86 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
87 32, 4, buf, i, 0);
88 }
89
90 /* Print parent device registers next */
91 if (!pdev->bus->self)
92 goto out;
93
94 pdev = pdev->bus->self;
95 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
96
97 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
98 pci_name(pdev));
c4d3f2ee 99 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
a6d24fad
RJ		 100 if (pci_read_config_dword(pdev, i, ptr))
101 goto err_read;
102 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
103
104 /* Print root port AER registers */
105 pos = 0;
106 pdev = pcie_find_root_port(pdev);
107 if (pdev)
108 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
109 if (pos) {
110 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
111 pci_name(pdev));
112 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
113 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
114 if (pci_read_config_dword(pdev, pos + i, ptr))
115 goto err_read;
116 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
117 4, buf, i, 0);
118 }
f3402d6d 119 goto out;
a6d24fad
RJ		 120
121err_read:
122 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
123 IWL_ERR(trans, "Read failed at 0x%X\n", i);
124out:
125 trans_pcie->pcie_dbg_dumped_once = 1;
126 kfree(buf);
127}
128
870c2a11
GBA		 129static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
130{
131 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
6dece0e9 132 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
870c2a11
GBA		 133 usleep_range(5000, 6000);
134}
135
c2d20201
EG		 136static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
137{
69f0e505 138 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
c2d20201 139
69f0e505
SM		 140 if (!fw_mon->size)
141 return;
142
143 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
144 fw_mon->physical);
145
146 fw_mon->block = NULL;
147 fw_mon->physical = 0;
148 fw_mon->size = 0;
c2d20201
EG		 149}
150
88964b2e
SS		 151static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
152 u8 max_power, u8 min_power)
c2d20201 153{
69f0e505
SM		 154 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
155 void *block = NULL;
156 dma_addr_t physical = 0;
96c285da 157 u32 size = 0;
c2d20201
EG		 158 u8 power;
159
69f0e505
SM		 160 if (fw_mon->size)
161 return;
162
88964b2e 163 for (power = max_power; power >= min_power; power--) {
c2d20201 164 size = BIT(power);
69f0e505
SM		 165 block = dma_alloc_coherent(trans->dev, size, &physical,
166 GFP_KERNEL | __GFP_NOWARN);
167 if (!block)
c2d20201
EG		 168 continue;
169
c2d20201 170 IWL_INFO(trans,
c5f97542
SM		 171 "Allocated 0x%08x bytes for firmware monitor.\n",
172 size);
c2d20201
EG		 173 break;
174 }
175
69f0e505 176 if (WARN_ON_ONCE(!block))
c2d20201
EG		 177 return;
178
96c285da
EG		 179 if (power != max_power)
180 IWL_ERR(trans,
181 "Sorry - debug buffer is only %luK while you requested %luK\n",
182 (unsigned long)BIT(power - 10),
183 (unsigned long)BIT(max_power - 10));
184
69f0e505
SM		 185 fw_mon->block = block;
186 fw_mon->physical = physical;
187 fw_mon->size = size;
88964b2e
SS		 188}
189
190void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
191{
192 if (!max_power) {
193 /* default max_power is maximum */
194 max_power = 26;
195 } else {
196 max_power += 11;
197 }
198
199 if (WARN(max_power > 26,
200 "External buffer size for monitor is too big %d, check the FW TLV\n",
201 max_power))
202 return;
203
69f0e505 204 if (trans->dbg.fw_mon.size)
88964b2e
SS		 205 return;
206
207 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
c2d20201
EG		 208}
209
a812cba9
AB		 210static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
211{
212 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
213 ((reg & 0x0000ffff) | (2 << 28)));
214 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
215}
216
217static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
218{
219 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
220 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
221 ((reg & 0x0000ffff) | (3 << 28)));
222}
223
ddaf5a5b 224static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 225{
66337b7c 226 if (trans->cfg->apmg_not_supported)
95411d04
AA		 227 return;
228
ddaf5a5b
JB		 229 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
230 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
231 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
232 ~APMG_PS_CTRL_MSK_PWR_SRC);
233 else
234 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
235 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
236 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 237}
238
af634bee
EG		 239/* PCI registers */
240#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 241
eda50cde 242void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 243{
20d3b647 244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 245 u16 lctl;
9180ac50 246 u16 cap;
af634bee 247
af634bee 248 /*
cc894b85
LC		 249 * L0S states have been found to be unstable with our devices
250 * and in newer hardware they are not officially supported at
251 * all, so we must always set the L0S_DISABLED bit.
af634bee 252 */
cc894b85
LC		 253 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
254
7afe3705 255 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
438a0f0a 256 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 257
258 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
259 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
d74a61fc
LC		 260 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
261 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
262 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 263}
264
a6c684ee
EG		 265/*
266 * Start up NIC's basic functionality after it has been reset
7afe3705 267 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 268 * NOTE: This does not load uCode nor start the embedded processor
269 */
7afe3705 270static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee 271{
52b6e168
EG		 272 int ret;
273
a6c684ee
EG		 274 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
275
276 /*
277 * Use "set_bit" below rather than "write", to preserve any hardware
278 * bits already set by default after reset.
279 */
280
281 /* Disable L0S exit timer (platform NMI Work/Around) */
286ca8eb 282 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
e4a9f8ce
EH		 283 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
284 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 285
286 /*
287 * Disable L0s without affecting L1;
288 * don't wait for ICH L0s (ICH bug W/A)
289 */
290 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 291 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 292
293 /* Set FH wait threshold to maximum (HW error during stress W/A) */
294 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
295
296 /*
297 * Enable HAP INTA (interrupt from management bus) to
298 * wake device's PCI Express link L1a -> L0s
299 */
300 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 301 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 302
7afe3705 303 iwl_pcie_apm_config(trans);
a6c684ee
EG		 304
305 /* Configure analog phase-lock-loop before activating to D0A */
286ca8eb 306 if (trans->trans_cfg->base_params->pll_cfg)
77d76931 307 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee 308
7d34a7d7 309 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 310 if (ret)
52b6e168 311 return ret;
a6c684ee 312
2d93aee1
EG		 313 if (trans->cfg->host_interrupt_operation_mode) {
314 /*
315 * This is a bit of an abuse - This is needed for 7260 / 3160
316 * only check host_interrupt_operation_mode even if this is
317 * not related to host_interrupt_operation_mode.
318 *
319 * Enable the oscillator to count wake up time for L1 exit. This
320 * consumes slightly more power (100uA) - but allows to be sure
321 * that we wake up from L1 on time.
322 *
323 * This looks weird: read twice the same register, discard the
324 * value, set a bit, and yet again, read that same register
325 * just to discard the value. But that's the way the hardware
326 * seems to like it.
327 */
328 iwl_read_prph(trans, OSC_CLK);
329 iwl_read_prph(trans, OSC_CLK);
330 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
331 iwl_read_prph(trans, OSC_CLK);
332 iwl_read_prph(trans, OSC_CLK);
333 }
334
a6c684ee
EG		 335 /*
336 * Enable DMA clock and wait for it to stabilize.
337 *
3073d8c0
EH		 338 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
339 * bits do not disable clocks. This preserves any hardware
340 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 341 */
95411d04 342 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 343 iwl_write_prph(trans, APMG_CLK_EN_REG,
344 APMG_CLK_VAL_DMA_CLK_RQT);
345 udelay(20);
346
347 /* Disable L1-Active */
348 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
349 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
350
351 /* Clear the interrupt in APMG if the NIC is in RFKILL */
352 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
353 APMG_RTC_INT_STT_RFKILL);
354 }
889b1696 355
eb7ff77e 356 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee 357
52b6e168 358 return 0;
a6c684ee
EG		 359}
360
a812cba9
AB		 361/*
362 * Enable LP XTAL to avoid HW bug where device may consume much power if
363 * FW is not loaded after device reset. LP XTAL is disabled by default
364 * after device HW reset. Do it only if XTAL is fed by internal source.
365 * Configure device's "persistence" mode to avoid resetting XTAL again when
366 * SHRD_HW_RST occurs in S3.
367 */
368static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
369{
370 int ret;
371 u32 apmg_gp1_reg;
372 u32 apmg_xtal_cfg_reg;
373 u32 dl_cfg_reg;
374
375 /* Force XTAL ON */
376 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
377 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
378
870c2a11 379 iwl_trans_pcie_sw_reset(trans);
a812cba9 380
7d34a7d7 381 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 382 if (WARN_ON(ret)) {
a812cba9
AB		 383 /* Release XTAL ON request */
384 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
385 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
386 return;
387 }
388
389 /*
390 * Clear "disable persistence" to avoid LP XTAL resetting when
391 * SHRD_HW_RST is applied in S3.
392 */
393 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
394 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
395
396 /*
397 * Force APMG XTAL to be active to prevent its disabling by HW
398 * caused by APMG idle state.
399 */
400 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
401 SHR_APMG_XTAL_CFG_REG);
402 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
403 apmg_xtal_cfg_reg |
404 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
405
870c2a11 406 iwl_trans_pcie_sw_reset(trans);
a812cba9
AB		 407
408 /* Enable LP XTAL by indirect access through CSR */
409 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
410 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
411 SHR_APMG_GP1_WF_XTAL_LP_EN |
412 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
413
414 /* Clear delay line clock power up */
415 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
416 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
417 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
418
419 /*
420 * Enable persistence mode to avoid LP XTAL resetting when
421 * SHRD_HW_RST is applied in S3.
422 */
423 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
424 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
425
426 /*
427 * Clear "initialization complete" bit to move adapter from
428 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
429 */
6dece0e9 430 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
a812cba9
AB		 431
432 /* Activates XTAL resources monitor */
433 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
434 CSR_MONITOR_XTAL_RESOURCES);
435
436 /* Release XTAL ON request */
437 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
438 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
439 udelay(10);
440
441 /* Release APMG XTAL */
442 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
443 apmg_xtal_cfg_reg &
444 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
445}
446
e8c8935e 447void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2 448{
e8c8935e 449 int ret;
cc56feb2
EG		 450
451 /* stop device's busmaster DMA activity */
6dece0e9 452 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
cc56feb2 453
6dece0e9
LC		 454 ret = iwl_poll_bit(trans, CSR_RESET,
455 CSR_RESET_REG_FLAG_MASTER_DISABLED,
456 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 457 if (ret < 0)
cc56feb2
EG		 458 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
459
460 IWL_DEBUG_INFO(trans, "stop master\n");
cc56feb2
EG		 461}
462
b7aaeae4 463static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 464{
465 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
466
b7aaeae4
EG		 467 if (op_mode_leave) {
468 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
469 iwl_pcie_apm_init(trans);
470
471 /* inform ME that we are leaving */
286ca8eb 472 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
b7aaeae4
EG		 473 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
474 APMG_PCIDEV_STT_VAL_WAKE_ME);
286ca8eb 475 else if (trans->trans_cfg->device_family >=
79b6c8fe 476 IWL_DEVICE_FAMILY_8000) {
c9fdec9f
EG		 477 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
478 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 479 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
480 CSR_HW_IF_CONFIG_REG_PREPARE |
481 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 482 mdelay(1);
483 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
484 CSR_RESET_LINK_PWR_MGMT_DISABLED);
485 }
b7aaeae4
EG		 486 mdelay(5);
487 }
488
eb7ff77e 489 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 490
491 /* Stop device's DMA activity */
7afe3705 492 iwl_pcie_apm_stop_master(trans);
cc56feb2 493
a812cba9
AB		 494 if (trans->cfg->lp_xtal_workaround) {
495 iwl_pcie_apm_lp_xtal_enable(trans);
496 return;
497 }
498
870c2a11 499 iwl_trans_pcie_sw_reset(trans);
cc56feb2
EG		 500
501 /*
502 * Clear "initialization complete" bit to move adapter from
503 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
504 */
6dece0e9 505 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
cc56feb2
EG		 506}
507
7afe3705 508static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 509{
7b11488f 510 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
52b6e168 511 int ret;
392f8b78
EG		 512
513 /* nic_init */
7b70bd63 514 spin_lock(&trans_pcie->irq_lock);
52b6e168 515 ret = iwl_pcie_apm_init(trans);
7b70bd63 516 spin_unlock(&trans_pcie->irq_lock);
392f8b78 517
52b6e168
EG		 518 if (ret)
519 return ret;
520
95411d04 521 iwl_pcie_set_pwr(trans, false);
392f8b78 522
ecdb975c 523 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 524
525 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 526 iwl_pcie_rx_init(trans);
392f8b78
EG		 527
528 /* Allocate or reset and init all Tx and Command queues */
f02831be 529 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 530 return -ENOMEM;
531
286ca8eb 532 if (trans->trans_cfg->base_params->shadow_reg_enable) {
392f8b78 533 /* enable shadow regs in HW */
20d3b647 534 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 535 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 536 }
537
392f8b78
EG		 538 return 0;
539}
540
541#define HW_READY_TIMEOUT (50)
542
543/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 544static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 545{
546 int ret;
547
1042db2a 548 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 549 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 550
551 /* See if we got it */
1042db2a 552 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 553 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
555 HW_READY_TIMEOUT);
392f8b78 556
6a08f514
EG		 557 if (ret >= 0)
558 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
559
6d8f6eeb 560 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 561 return ret;
562}
563
564/* Note: returns standard 0/-ERROR code */
eda50cde 565int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 566{
567 int ret;
289e5501 568 int t = 0;
501fd989 569 int iter;
392f8b78 570
6d8f6eeb 571 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 572
7afe3705 573 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 574 /* If the card is ready, exit 0 */
392f8b78
EG		 575 if (ret >= 0)
576 return 0;
577
c9fdec9f
EG		 578 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
579 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 580 usleep_range(1000, 2000);
c9fdec9f 581
501fd989
EG		 582 for (iter = 0; iter < 10; iter++) {
583 /* If HW is not ready, prepare the conditions to check again */
584 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
585 CSR_HW_IF_CONFIG_REG_PREPARE);
586
587 do {
588 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 589 if (ret >= 0)
590 return 0;
392f8b78 591
501fd989
EG		 592 usleep_range(200, 1000);
593 t += 200;
594 } while (t < 150000);
595 msleep(25);
596 }
392f8b78 597
7f2ac8fb 598 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 599
392f8b78
EG		 600 return ret;
601}
602
cf614297
EG		 603/*
604 * ucode
605 */
564cdce7
SS		 606static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
607 u32 dst_addr, dma_addr_t phy_addr,
608 u32 byte_cnt)
cf614297 609{
bac842da
EG		 610 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
611 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
612
613 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
614 dst_addr);
615
616 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
617 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
618
619 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
620 (iwl_get_dma_hi_addr(phy_addr)
621 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
622
623 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
624 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
625 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
626 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
627
628 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
629 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
630 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
631 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 632}
633
564cdce7
SS		 634static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
635 u32 dst_addr, dma_addr_t phy_addr,
636 u32 byte_cnt)
637{
638 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
639 unsigned long flags;
640 int ret;
641
642 trans_pcie->ucode_write_complete = false;
643
644 if (!iwl_trans_grab_nic_access(trans, &flags))
645 return -EIO;
646
eda50cde
SS		 647 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
648 byte_cnt);
bac842da 649 iwl_trans_release_nic_access(trans, &flags);
cf614297 650
13df1aab
JB		 651 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
652 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 653 if (!ret) {
83f84d7b 654 IWL_ERR(trans, "Failed to load firmware chunk!\n");
fb12777a 655 iwl_trans_pcie_dump_regs(trans);
cf614297
EG		 656 return -ETIMEDOUT;
657 }
658
659 return 0;
660}
661
7afe3705 662static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 663 const struct fw_desc *section)
cf614297 664{
83f84d7b
JB		 665 u8 *v_addr;
666 dma_addr_t p_addr;
baa21e83 667 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 668 int ret = 0;
669
83f84d7b
JB		 670 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
671 section_num);
672
c571573a
EG		 673 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
674 GFP_KERNEL | __GFP_NOWARN);
675 if (!v_addr) {
676 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
677 chunk_sz = PAGE_SIZE;
678 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
679 &p_addr, GFP_KERNEL);
680 if (!v_addr)
681 return -ENOMEM;
682 }
83f84d7b 683
c571573a 684 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 685 u32 copy_size, dst_addr;
686 bool extended_addr = false;
83f84d7b 687
c571573a 688 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 689 dst_addr = section->offset + offset;
690
691 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
692 dst_addr <= IWL_FW_MEM_EXTENDED_END)
693 extended_addr = true;
694
695 if (extended_addr)
696 iwl_set_bits_prph(trans, LMPM_CHICK,
697 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 698
83f84d7b 699 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 700 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
701 copy_size);
702
703 if (extended_addr)
704 iwl_clear_bits_prph(trans, LMPM_CHICK,
705 LMPM_CHICK_EXTENDED_ADDR_SPACE);
706
83f84d7b
JB		 707 if (ret) {
708 IWL_ERR(trans,
709 "Could not load the [%d] uCode section\n",
710 section_num);
711 break;
6dfa8d01 712 }
83f84d7b
JB		 713 }
714
c571573a 715 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 716 return ret;
717}
718
5dd9c68a
EG		 719static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
720 const struct fw_img *image,
721 int cpu,
722 int *first_ucode_section)
e2d6f4e7
EH		 723{
724 int shift_param;
dcab8ecd
EH		 725 int i, ret = 0, sec_num = 0x1;
726 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 727
728 if (cpu == 1) {
729 shift_param = 0;
034846cf 730 *first_ucode_section = 0;
e2d6f4e7
EH		 731 } else {
732 shift_param = 16;
034846cf 733 (*first_ucode_section)++;
e2d6f4e7
EH		 734 }
735
eef187a7 736 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 737 last_read_idx = i;
738
a6c4fb44
MG		 739 /*
740 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
741 * CPU1 to CPU2.
742 * PAGING_SEPARATOR_SECTION delimiter - separate between
743 * CPU2 non paged to CPU2 paging sec.
744 */
034846cf 745 if (!image->sec[i].data ||
a6c4fb44
MG		 746 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
747 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 748 IWL_DEBUG_FW(trans,
749 "Break since Data not valid or Empty section, sec = %d\n",
750 i);
189fa2fa 751 break;
034846cf
EH		 752 }
753
189fa2fa
EH		 754 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
755 if (ret)
756 return ret;
dcab8ecd 757
d6a2c5c7 758 /* Notify ucode of loaded section number and status */
eda50cde
SS		 759 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
760 val = val | (sec_num << shift_param);
761 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
762
dcab8ecd 763 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 764 }
765
034846cf
EH		 766 *first_ucode_section = last_read_idx;
767
2aabdbdc
EG		 768 iwl_enable_interrupts(trans);
769
286ca8eb 770 if (trans->trans_cfg->use_tfh) {
d6a2c5c7
SS		 771 if (cpu == 1)
772 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
773 0xFFFF);
774 else
775 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
776 0xFFFFFFFF);
777 } else {
778 if (cpu == 1)
779 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
780 0xFFFF);
781 else
782 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
783 0xFFFFFFFF);
784 }
afb88917 785
189fa2fa
EH		 786 return 0;
787}
e2d6f4e7 788
189fa2fa
EH		 789static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
790 const struct fw_img *image,
034846cf
EH		 791 int cpu,
792 int *first_ucode_section)
189fa2fa 793{
189fa2fa 794 int i, ret = 0;
034846cf 795 u32 last_read_idx = 0;
189fa2fa 796
3ce4a038 797 if (cpu == 1)
034846cf 798 *first_ucode_section = 0;
3ce4a038 799 else
034846cf 800 (*first_ucode_section)++;
189fa2fa 801
eef187a7 802 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 803 last_read_idx = i;
804
a6c4fb44
MG		 805 /*
806 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
807 * CPU1 to CPU2.
808 * PAGING_SEPARATOR_SECTION delimiter - separate between
809 * CPU2 non paged to CPU2 paging sec.
810 */
034846cf 811 if (!image->sec[i].data ||
a6c4fb44
MG		 812 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
813 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 814 IWL_DEBUG_FW(trans,
815 "Break since Data not valid or Empty section, sec = %d\n",
816 i);
189fa2fa 817 break;
034846cf
EH		 818 }
819
189fa2fa
EH		 820 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
821 if (ret)
822 return ret;
e2d6f4e7
EH		 823 }
824
034846cf
EH		 825 *first_ucode_section = last_read_idx;
826
e2d6f4e7
EH		 827 return 0;
828}
829
593fae3e
SM		 830static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
831{
832 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
833 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
834 &trans->dbg.fw_mon_cfg[alloc_id];
835 struct iwl_dram_data *frag;
836
837 if (!iwl_trans_dbg_ini_valid(trans))
838 return;
839
840 if (le32_to_cpu(fw_mon_cfg->buf_location) ==
841 IWL_FW_INI_LOCATION_SRAM_PATH) {
842 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
843 /* set sram monitor by enabling bit 7 */
844 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
845 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
846
847 return;
848 }
849
850 if (le32_to_cpu(fw_mon_cfg->buf_location) !=
851 IWL_FW_INI_LOCATION_DRAM_PATH ||
852 !trans->dbg.fw_mon_ini[alloc_id].num_frags)
853 return;
854
855 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
856
857 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
858 alloc_id);
859
860 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
861 frag->physical >> MON_BUFF_SHIFT_VER2);
862 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
863 (frag->physical + frag->size - 256) >>
864 MON_BUFF_SHIFT_VER2);
865}
866
c9be849d 867void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7 868{
91c28b83 869 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
69f0e505 870 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
09e350f7
LK		 871 int i;
872
a1af4c48 873 if (iwl_trans_dbg_ini_valid(trans)) {
593fae3e 874 iwl_pcie_apply_destination_ini(trans);
7a14c23d
SS		 875 return;
876 }
877
09e350f7
LK		 878 IWL_INFO(trans, "Applying debug destination %s\n",
879 get_fw_dbg_mode_string(dest->monitor_mode));
880
881 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 882 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 883 else
884 IWL_WARN(trans, "PCI should have external buffer debug\n");
885
91c28b83 886 for (i = 0; i < trans->dbg.n_dest_reg; i++) {
09e350f7
LK		 887 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
888 u32 val = le32_to_cpu(dest->reg_ops[i].val);
889
890 switch (dest->reg_ops[i].op) {
891 case CSR_ASSIGN:
892 iwl_write32(trans, addr, val);
893 break;
894 case CSR_SETBIT:
895 iwl_set_bit(trans, addr, BIT(val));
896 break;
897 case CSR_CLEARBIT:
898 iwl_clear_bit(trans, addr, BIT(val));
899 break;
900 case PRPH_ASSIGN:
901 iwl_write_prph(trans, addr, val);
902 break;
903 case PRPH_SETBIT:
904 iwl_set_bits_prph(trans, addr, BIT(val));
905 break;
906 case PRPH_CLEARBIT:
907 iwl_clear_bits_prph(trans, addr, BIT(val));
908 break;
869f3b15
HD		 909 case PRPH_BLOCKBIT:
910 if (iwl_read_prph(trans, addr) & BIT(val)) {
911 IWL_ERR(trans,
912 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
913 val, addr);
914 goto monitor;
915 }
916 break;
09e350f7
LK		 917 default:
918 IWL_ERR(trans, "FW debug - unknown OP %d\n",
919 dest->reg_ops[i].op);
920 break;
921 }
922 }
923
869f3b15 924monitor:
69f0e505 925 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
09e350f7 926 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
69f0e505 927 fw_mon->physical >> dest->base_shift);
286ca8eb 928 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
62d7476d 929 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 930 (fw_mon->physical + fw_mon->size -
931 256) >> dest->end_shift);
62d7476d
EG		 932 else
933 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
69f0e505
SM		 934 (fw_mon->physical + fw_mon->size) >>
935 dest->end_shift);
09e350f7
LK		 936 }
937}
938
7afe3705 939static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 940 const struct fw_img *image)
cf614297 941{
189fa2fa 942 int ret = 0;
034846cf 943 int first_ucode_section;
cf614297 944
dcab8ecd 945 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 946 image->is_dual_cpus ? "Dual" : "Single");
947
dcab8ecd
EH		 948 /* load to FW the binary non secured sections of CPU1 */
949 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
950 if (ret)
951 return ret;
e2d6f4e7
EH		 952
953 if (image->is_dual_cpus) {
189fa2fa
EH		 954 /* set CPU2 header address */
955 iwl_write_prph(trans,
956 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
957 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 958
189fa2fa 959 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 960 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
961 &first_ucode_section);
189fa2fa
EH		 962 if (ret)
963 return ret;
e2d6f4e7 964 }
cf614297 965
9efab1ad 966 if (iwl_pcie_dbg_on(trans))
09e350f7 967 iwl_pcie_apply_destination(trans);
c2d20201 968
2aabdbdc
EG		 969 iwl_enable_interrupts(trans);
970
e12ba844 971 /* release CPU reset */
5dd9c68a 972 iwl_write32(trans, CSR_RESET, 0);
e12ba844 973
dcab8ecd
EH		 974 return 0;
975}
189fa2fa 976
5dd9c68a
EG		 977static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
978 const struct fw_img *image)
dcab8ecd
EH		 979{
980 int ret = 0;
981 int first_ucode_section;
dcab8ecd
EH		 982
983 IWL_DEBUG_FW(trans, "working with %s CPU\n",
984 image->is_dual_cpus ? "Dual" : "Single");
985
7a14c23d 986 if (iwl_pcie_dbg_on(trans))
a2227ce2
EG		 987 iwl_pcie_apply_destination(trans);
988
82ea7966
SS		 989 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
990 iwl_read_prph(trans, WFPM_GP2));
991
992 /*
993 * Set default value. On resume reading the values that were
994 * zeored can provide debug data on the resume flow.
995 * This is for debugging only and has no functional impact.
996 */
997 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
998
dcab8ecd
EH		 999 /* configure the ucode to be ready to get the secured image */
1000 /* release CPU reset */
1001 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1002
1003 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1004 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1005 &first_ucode_section);
dcab8ecd
EH		 1006 if (ret)
1007 return ret;
1008
1009 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1010 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1011 &first_ucode_section);
cf614297
EG		 1012}
1013
9ad8fd0b 1014bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
727c02df 1015{
326477e4 1016 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727c02df 1017 bool hw_rfkill = iwl_is_rfkill_set(trans);
326477e4
JB		 1018 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1019 bool report;
727c02df 1020
326477e4
JB		 1021 if (hw_rfkill) {
1022 set_bit(STATUS_RFKILL_HW, &trans->status);
1023 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1024 } else {
1025 clear_bit(STATUS_RFKILL_HW, &trans->status);
1026 if (trans_pcie->opmode_down)
1027 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1028 }
1029
1030 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
727c02df 1031
326477e4
JB		 1032 if (prev != report)
1033 iwl_trans_pcie_rf_kill(trans, report);
727c02df
SS		 1034
1035 return hw_rfkill;
1036}
1037
7ca00409
HD		 1038struct iwl_causes_list {
1039 u32 cause_num;
1040 u32 mask_reg;
1041 u8 addr;
1042};
1043
1044static struct iwl_causes_list causes_list[] = {
1045 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1046 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1047 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1048 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1049 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1050 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
906d4eb8 1051 {MSIX_HW_INT_CAUSES_REG_RESET_DONE, CSR_MSIX_HW_INT_MASK_AD, 0x12},
7ca00409
HD		 1052 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1053 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1054 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1055 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1056 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1057 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1058 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1059 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1060};
1061
1062static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1063{
1064 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1065 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
3681021f
JB		 1066 int i, arr_size = ARRAY_SIZE(causes_list);
1067 struct iwl_causes_list *causes = causes_list;
7ca00409
HD		 1068
1069 /*
1070 * Access all non RX causes and map them to the default irq.
1071 * In case we are missing at least one interrupt vector,
1072 * the first interrupt vector will serve non-RX and FBQ causes.
1073 */
9b58419e 1074 for (i = 0; i < arr_size; i++) {
9b58419e
GBA		 1075 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1076 iwl_clear_bit(trans, causes[i].mask_reg,
1077 causes[i].cause_num);
7ca00409
HD		 1078 }
1079}
1080
1081static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1082{
1083 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1084 u32 offset =
1085 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1086 u32 val, idx;
1087
1088 /*
1089 * The first RX queue - fallback queue, which is designated for
1090 * management frame, command responses etc, is always mapped to the
1091 * first interrupt vector. The other RX queues are mapped to
1092 * the other (N - 2) interrupt vectors.
1093 */
1094 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1095 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1096 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1097 MSIX_FH_INT_CAUSES_Q(idx - offset));
1098 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1099 }
1100 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1101
1102 val = MSIX_FH_INT_CAUSES_Q(0);
1103 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1104 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1105 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1106
1107 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1108 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1109}
1110
77c09bc8 1111void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1112{
1113 struct iwl_trans *trans = trans_pcie->trans;
1114
1115 if (!trans_pcie->msix_enabled) {
286ca8eb 1116 if (trans->trans_cfg->mq_rx_supported &&
d7270d61 1117 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c
ST		 1118 iwl_write_umac_prph(trans, UREG_CHICK,
1119 UREG_CHICK_MSI_ENABLE);
7ca00409
HD		 1120 return;
1121 }
d7270d61
HD		 1122 /*
1123 * The IVAR table needs to be configured again after reset,
1124 * but if the device is disabled, we can't write to
1125 * prph.
1126 */
1127 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
ea695b7c 1128 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1129
1130 /*
1131 * Each cause from the causes list above and the RX causes is
1132 * represented as a byte in the IVAR table. The first nibble
1133 * represents the bound interrupt vector of the cause, the second
1134 * represents no auto clear for this cause. This will be set if its
1135 * interrupt vector is bound to serve other causes.
1136 */
1137 iwl_pcie_map_rx_causes(trans);
1138
1139 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1140}
1141
1142static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1143{
1144 struct iwl_trans *trans = trans_pcie->trans;
1145
1146 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1147
83730058
HD		 1148 if (!trans_pcie->msix_enabled)
1149 return;
1150
1151 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1152 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1153 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1154 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1155}
1156
bab3cb92 1157static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 1158{
43e58856 1159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f 1160
fa9f3281
EG		 1161 lockdep_assert_held(&trans_pcie->mutex);
1162
1163 if (trans_pcie->is_down)
1164 return;
1165
1166 trans_pcie->is_down = true;
1167
43e58856 1168 /* tell the device to stop sending interrupts */
ae2c30bf 1169 iwl_disable_interrupts(trans);
ae2c30bf 1170
ab6cf8e8 1171 /* device going down, Stop using ICT table */
990aa6d7 1172 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1173
1174 /*
1175 * If a HW restart happens during firmware loading,
1176 * then the firmware loading might call this function
1177 * and later it might be called again due to the
1178 * restart. So don't process again if the device is
1179 * already dead.
1180 */
31b8b343 1181 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1182 IWL_DEBUG_INFO(trans,
1183 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1184 iwl_pcie_tx_stop(trans);
9805c446 1185 iwl_pcie_rx_stop(trans);
6379103e 1186
ab6cf8e8 1187 /* Power-down device's busmaster DMA clocks */
95411d04 1188 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1189 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1190 APMG_CLK_VAL_DMA_CLK_RQT);
1191 udelay(5);
1192 }
ab6cf8e8
EG		 1193 }
1194
1195 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1196 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 1197 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1198
1199 /* Stop the device, and put it in low power state */
b7aaeae4 1200 iwl_pcie_apm_stop(trans, false);
43e58856 1201
870c2a11 1202 iwl_trans_pcie_sw_reset(trans);
03d6c3b0 1203
f4a1f04a
GBA		 1204 /*
1205 * Upon stop, the IVAR table gets erased, so msi-x won't
1206 * work. This causes a bug in RF-KILL flows, since the interrupt
1207 * that enables radio won't fire on the correct irq, and the
1208 * driver won't be able to handle the interrupt.
1209 * Configure the IVAR table again after reset.
1210 */
1211 iwl_pcie_conf_msix_hw(trans_pcie);
1212
03d6c3b0
EG		 1213 /*
1214 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1215 * This is a bug in certain verions of the hardware.
1216 * Certain devices also keep sending HW RF kill interrupt all
1217 * the time, unless the interrupt is ACKed even if the interrupt
1218 * should be masked. Re-ACK all the interrupts here.
43e58856 1219 */
43e58856 1220 iwl_disable_interrupts(trans);
43e58856 1221
74fda971 1222 /* clear all status bits */
eb7ff77e
AN		 1223 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1224 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e 1225 clear_bit(STATUS_TPOWER_PMI, &trans->status);
a4082843
AN		 1226
1227 /*
1228 * Even if we stop the HW, we still want the RF kill
1229 * interrupt
1230 */
1231 iwl_enable_rfkill_int(trans);
1232
a6bd005f 1233 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1234 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1235}
1236
eda50cde 1237void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1238{
1239 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1240
1241 if (trans_pcie->msix_enabled) {
1242 int i;
1243
496d83ca 1244 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1245 synchronize_irq(trans_pcie->msix_entries[i].vector);
1246 } else {
1247 synchronize_irq(trans_pcie->pci_dev->irq);
1248 }
1249}
1250
a6bd005f
EG		 1251static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1252 const struct fw_img *fw, bool run_in_rfkill)
1253{
1254 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1255 bool hw_rfkill;
1256 int ret;
1257
1258 /* This may fail if AMT took ownership of the device */
1259 if (iwl_pcie_prepare_card_hw(trans)) {
1260 IWL_WARN(trans, "Exit HW not ready\n");
1261 ret = -EIO;
1262 goto out;
1263 }
1264
1265 iwl_enable_rfkill_int(trans);
1266
1267 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1268
1269 /*
1270 * We enabled the RF-Kill interrupt and the handler may very
1271 * well be running. Disable the interrupts to make sure no other
1272 * interrupt can be fired.
1273 */
1274 iwl_disable_interrupts(trans);
1275
1276 /* Make sure it finished running */
2e5d4a8f 1277 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1278
1279 mutex_lock(&trans_pcie->mutex);
1280
1281 /* If platform's RF_KILL switch is NOT set to KILL */
9ad8fd0b 1282 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1283 if (hw_rfkill && !run_in_rfkill) {
1284 ret = -ERFKILL;
1285 goto out;
1286 }
1287
1288 /* Someone called stop_device, don't try to start_fw */
1289 if (trans_pcie->is_down) {
1290 IWL_WARN(trans,
1291 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1292 ret = -EIO;
a6bd005f
EG		 1293 goto out;
1294 }
1295
1296 /* make sure rfkill handshake bits are cleared */
1297 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1298 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1299 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1300
1301 /* clear (again), then enable host interrupts */
1302 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1303
1304 ret = iwl_pcie_nic_init(trans);
1305 if (ret) {
1306 IWL_ERR(trans, "Unable to init nic\n");
1307 goto out;
1308 }
1309
1310 /*
1311 * Now, we load the firmware and don't want to be interrupted, even
1312 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1313 * FH_TX interrupt which is needed to load the firmware). If the
1314 * RF-Kill switch is toggled, we will find out after having loaded
1315 * the firmware and return the proper value to the caller.
1316 */
1317 iwl_enable_fw_load_int(trans);
1318
1319 /* really make sure rfkill handshake bits are cleared */
1320 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1321 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1322
1323 /* Load the given image to the HW */
286ca8eb 1324 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
a6bd005f
EG		 1325 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1326 else
1327 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1328
1329 /* re-check RF-Kill state since we may have missed the interrupt */
9ad8fd0b 1330 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
a6bd005f
EG		 1331 if (hw_rfkill && !run_in_rfkill)
1332 ret = -ERFKILL;
1333
1334out:
1335 mutex_unlock(&trans_pcie->mutex);
1336 return ret;
1337}
1338
1339static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1340{
1341 iwl_pcie_reset_ict(trans);
1342 iwl_pcie_tx_start(trans, scd_addr);
1343}
1344
326477e4
JB		 1345void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1346 bool was_in_rfkill)
1347{
1348 bool hw_rfkill;
1349
1350 /*
1351 * Check again since the RF kill state may have changed while
1352 * all the interrupts were disabled, in this case we couldn't
1353 * receive the RF kill interrupt and update the state in the
1354 * op_mode.
1355 * Don't call the op_mode if the rkfill state hasn't changed.
1356 * This allows the op_mode to call stop_device from the rfkill
1357 * notification without endless recursion. Under very rare
1358 * circumstances, we might have a small recursion if the rfkill
1359 * state changed exactly now while we were called from stop_device.
1360 * This is very unlikely but can happen and is supported.
1361 */
1362 hw_rfkill = iwl_is_rfkill_set(trans);
1363 if (hw_rfkill) {
1364 set_bit(STATUS_RFKILL_HW, &trans->status);
1365 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1366 } else {
1367 clear_bit(STATUS_RFKILL_HW, &trans->status);
1368 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1369 }
1370 if (hw_rfkill != was_in_rfkill)
1371 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1372}
1373
bab3cb92 1374static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
fa9f3281
EG		 1375{
1376 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326477e4 1377 bool was_in_rfkill;
fa9f3281
EG		 1378
1379 mutex_lock(&trans_pcie->mutex);
326477e4
JB		 1380 trans_pcie->opmode_down = true;
1381 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
bab3cb92 1382 _iwl_trans_pcie_stop_device(trans);
326477e4 1383 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
fa9f3281
EG		 1384 mutex_unlock(&trans_pcie->mutex);
1385}
1386
14cfca71
JB		 1387void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1388{
fa9f3281
EG		 1389 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1390 IWL_TRANS_GET_PCIE_TRANS(trans);
1391
1392 lockdep_assert_held(&trans_pcie->mutex);
1393
326477e4
JB		 1394 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1395 state ? "disabled" : "enabled");
77c09bc8 1396 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
286ca8eb 1397 if (trans->trans_cfg->gen2)
bab3cb92 1398 _iwl_trans_pcie_gen2_stop_device(trans);
77c09bc8 1399 else
bab3cb92 1400 _iwl_trans_pcie_stop_device(trans);
77c09bc8 1401 }
ab6cf8e8
EG		 1402}
1403
e5f3f215
HD		 1404void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1405 bool test, bool reset)
2dd4f9f7 1406{
2dd4f9f7 1407 iwl_disable_interrupts(trans);
debff618
JB		 1408
1409 /*
1410 * in testing mode, the host stays awake and the
1411 * hardware won't be reset (not even partially)
1412 */
1413 if (test)
1414 return;
1415
ddaf5a5b
JB		 1416 iwl_pcie_disable_ict(trans);
1417
2e5d4a8f 1418 iwl_pcie_synchronize_irqs(trans);
33b56af1 1419
2dd4f9f7 1420 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9
LC		 1421 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1422 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
ddaf5a5b 1423
23ae6128 1424 if (reset) {
6dfb36c8
EP		 1425 /*
1426 * reset TX queues -- some of their registers reset during S3
1427 * so if we don't reset everything here the D3 image would try
1428 * to execute some invalid memory upon resume
1429 */
1430 iwl_trans_pcie_tx_reset(trans);
1431 }
ddaf5a5b
JB		 1432
1433 iwl_pcie_set_pwr(trans, true);
1434}
1435
e5f3f215
HD		 1436static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1437 bool reset)
1438{
1439 int ret;
1440 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1441
771db3a1 1442 if (!reset)
e5f3f215
HD		 1443 /* Enable persistence mode to avoid reset */
1444 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1445 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
e5f3f215
HD		 1446
1447 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1448 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1449 UREG_DOORBELL_TO_ISR6_SUSPEND);
1450
1451 ret = wait_event_timeout(trans_pcie->sx_waitq,
1452 trans_pcie->sx_complete, 2 * HZ);
1453 /*
1454 * Invalidate it toward resume.
1455 */
1456 trans_pcie->sx_complete = false;
1457
1458 if (!ret) {
1459 IWL_ERR(trans, "Timeout entering D3\n");
1460 return -ETIMEDOUT;
1461 }
1462 }
1463 iwl_pcie_d3_complete_suspend(trans, test, reset);
1464
1465 return 0;
1466}
1467
ddaf5a5b 1468static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1469 enum iwl_d3_status *status,
23ae6128 1470 bool test, bool reset)
ddaf5a5b 1471{
d7270d61 1472 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1473 u32 val;
1474 int ret;
1475
debff618
JB		 1476 if (test) {
1477 iwl_enable_interrupts(trans);
1478 *status = IWL_D3_STATUS_ALIVE;
e5f3f215 1479 goto out;
debff618
JB		 1480 }
1481
a8cbb46f 1482 iwl_set_bit(trans, CSR_GP_CNTRL,
6dece0e9 1483 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b 1484
7d34a7d7 1485 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
c96b5eec 1486 if (ret)
ddaf5a5b 1487 return ret;
ddaf5a5b 1488
f98ad635
EG		 1489 /*
1490 * Reconfigure IVAR table in case of MSIX or reset ict table in
1491 * MSI mode since HW reset erased it.
1492 * Also enables interrupts - none will happen as
1493 * the device doesn't know we're waking it up, only when
1494 * the opmode actually tells it after this call.
1495 */
1496 iwl_pcie_conf_msix_hw(trans_pcie);
1497 if (!trans_pcie->msix_enabled)
1498 iwl_pcie_reset_ict(trans);
1499 iwl_enable_interrupts(trans);
1500
a3ead656
EG		 1501 iwl_pcie_set_pwr(trans, false);
1502
23ae6128 1503 if (!reset) {
6dfb36c8 1504 iwl_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 1505 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
6dfb36c8
EP		 1506 } else {
1507 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1508
6dfb36c8
EP		 1509 ret = iwl_pcie_rx_init(trans);
1510 if (ret) {
1511 IWL_ERR(trans,
1512 "Failed to resume the device (RX reset)\n");
1513 return ret;
1514 }
ddaf5a5b
JB		 1515 }
1516
82ea7966 1517 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
ea695b7c 1518 iwl_read_umac_prph(trans, WFPM_GP2));
82ea7966 1519
a3ead656
EG		 1520 val = iwl_read32(trans, CSR_RESET);
1521 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1522 *status = IWL_D3_STATUS_RESET;
1523 else
1524 *status = IWL_D3_STATUS_ALIVE;
1525
e5f3f215
HD		 1526out:
1527 if (*status == IWL_D3_STATUS_ALIVE &&
1528 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1529 trans_pcie->sx_complete = false;
1530 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1531 UREG_DOORBELL_TO_ISR6_RESUME);
1532
1533 ret = wait_event_timeout(trans_pcie->sx_waitq,
1534 trans_pcie->sx_complete, 2 * HZ);
1535 /*
1536 * Invalidate it toward next suspend.
1537 */
1538 trans_pcie->sx_complete = false;
1539
1540 if (!ret) {
1541 IWL_ERR(trans, "Timeout exiting D3\n");
1542 return -ETIMEDOUT;
1543 }
1544 }
ddaf5a5b 1545 return 0;
2dd4f9f7
JB		 1546}
1547
0c18714a
LC		 1548static void
1549iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1550 struct iwl_trans *trans,
1551 const struct iwl_cfg_trans_params *cfg_trans)
2e5d4a8f
HD		 1552{
1553 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ab1068d6 1554 int max_irqs, num_irqs, i, ret;
2e5d4a8f 1555 u16 pci_cmd;
0cd38f4d 1556 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
2e5d4a8f 1557
0c18714a 1558 if (!cfg_trans->mq_rx_supported)
06f4b081
SS		 1559 goto enable_msi;
1560
0cd38f4d
MG		 1561 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
1562 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1563
1564 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
06f4b081
SS		 1565 for (i = 0; i < max_irqs; i++)
1566 trans_pcie->msix_entries[i].entry = i;
496d83ca 1567
06f4b081
SS		 1568 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1569 MSIX_MIN_INTERRUPT_VECTORS,
1570 max_irqs);
1571 if (num_irqs < 0) {
2e5d4a8f 1572 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1573 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1574 num_irqs);
1575 goto enable_msi;
1576 }
1577 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1578
06f4b081
SS		 1579 IWL_DEBUG_INFO(trans,
1580 "MSI-X enabled. %d interrupt vectors were allocated\n",
1581 num_irqs);
1582
1583 /*
1584 * In case the OS provides fewer interrupts than requested, different
1585 * causes will share the same interrupt vector as follows:
1586 * One interrupt less: non rx causes shared with FBQ.
1587 * Two interrupts less: non rx causes shared with FBQ and RSS.
1588 * More than two interrupts: we will use fewer RSS queues.
1589 */
ab1068d6 1590 if (num_irqs <= max_irqs - 2) {
06f4b081
SS		 1591 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1592 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1593 IWL_SHARED_IRQ_FIRST_RSS;
ab1068d6 1594 } else if (num_irqs == max_irqs - 1) {
06f4b081
SS		 1595 trans_pcie->trans->num_rx_queues = num_irqs;
1596 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1597 } else {
1598 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f 1599 }
ab1068d6 1600 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
2e5d4a8f 1601
06f4b081
SS		 1602 trans_pcie->alloc_vecs = num_irqs;
1603 trans_pcie->msix_enabled = true;
1604 return;
1605
1606enable_msi:
1607 ret = pci_enable_msi(pdev);
1608 if (ret) {
1609 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1610 /* enable rfkill interrupt: hw bug w/a */
1611 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1612 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1613 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1614 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1615 }
1616 }
1617}
1618
7c8d91eb
HD		 1619static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1620{
1621 int iter_rx_q, i, ret, cpu, offset;
1622 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1623
1624 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1625 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1626 offset = 1 + i;
1627 for (; i < iter_rx_q ; i++) {
1628 /*
1629 * Get the cpu prior to the place to search
1630 * (i.e. return will be > i - 1).
1631 */
1632 cpu = cpumask_next(i - offset, cpu_online_mask);
1633 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1634 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1635 &trans_pcie->affinity_mask[i]);
1636 if (ret)
1637 IWL_ERR(trans_pcie->trans,
1638 "Failed to set affinity mask for IRQ %d\n",
1639 i);
1640 }
1641}
1642
2e5d4a8f
HD		 1643static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1644 struct iwl_trans_pcie *trans_pcie)
1645{
496d83ca 1646 int i;
2e5d4a8f 1647
496d83ca 1648 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1649 int ret;
5a41a86c 1650 struct msix_entry *msix_entry;
64fa3aff
SD		 1651 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1652
1653 if (!qname)
1654 return -ENOMEM;
5a41a86c
SD		 1655
1656 msix_entry = &trans_pcie->msix_entries[i];
1657 ret = devm_request_threaded_irq(&pdev->dev,
1658 msix_entry->vector,
1659 iwl_pcie_msix_isr,
1660 (i == trans_pcie->def_irq) ?
1661 iwl_pcie_irq_msix_handler :
1662 iwl_pcie_irq_rx_msix_handler,
1663 IRQF_SHARED,
64fa3aff 1664 qname,
5a41a86c 1665 msix_entry);
2e5d4a8f 1666 if (ret) {
2e5d4a8f
HD		 1667 IWL_ERR(trans_pcie->trans,
1668 "Error allocating IRQ %d\n", i);
5a41a86c 1669
2e5d4a8f
HD		 1670 return ret;
1671 }
1672 }
7c8d91eb 1673 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1674
1675 return 0;
1676}
1677
44f61b5c 1678static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
e6bb4c9c 1679{
44f61b5c 1680 u32 hpm, wprot;
fa9f3281 1681
286ca8eb 1682 switch (trans->trans_cfg->device_family) {
44f61b5c
SM		 1683 case IWL_DEVICE_FAMILY_9000:
1684 wprot = PREG_PRPH_WPROT_9000;
1685 break;
1686 case IWL_DEVICE_FAMILY_22000:
1687 wprot = PREG_PRPH_WPROT_22000;
1688 break;
1689 default:
1690 return 0;
ebb7678d 1691 }
a6c684ee 1692
ea695b7c 1693 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
8954e1eb 1694 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
44f61b5c 1695 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
ea695b7c 1696
44f61b5c 1697 if (wprot_val & PREG_WFPM_ACCESS) {
8954e1eb
SM		 1698 IWL_ERR(trans,
1699 "Error, can not clear persistence bit\n");
1700 return -EPERM;
1701 }
ea695b7c
ST		 1702 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1703 hpm & ~PERSISTENCE_BIT);
8954e1eb
SM		 1704 }
1705
44f61b5c
SM		 1706 return 0;
1707}
1708
0df36b90
LC		 1709static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1710{
1711 int ret;
1712
1713 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1714 if (ret < 0)
1715 return ret;
1716
1717 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1718 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1719 udelay(20);
1720 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1721 HPM_HIPM_GEN_CFG_CR_PG_EN |
1722 HPM_HIPM_GEN_CFG_CR_SLP_EN);
1723 udelay(20);
1724 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1725 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1726
1727 iwl_trans_pcie_sw_reset(trans);
1728
1729 return 0;
1730}
1731
bab3cb92 1732static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
44f61b5c
SM		 1733{
1734 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1735 int err;
1736
1737 lockdep_assert_held(&trans_pcie->mutex);
1738
1739 err = iwl_pcie_prepare_card_hw(trans);
1740 if (err) {
1741 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1742 return err;
1743 }
1744
1745 err = iwl_trans_pcie_clear_persistence_bit(trans);
1746 if (err)
1747 return err;
1748
870c2a11 1749 iwl_trans_pcie_sw_reset(trans);
2997494f 1750
0df36b90 1751 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
7897dfa2 1752 trans->trans_cfg->integrated) {
0df36b90
LC		 1753 err = iwl_pcie_gen2_force_power_gating(trans);
1754 if (err)
1755 return err;
1756 }
1757
52b6e168
EG		 1758 err = iwl_pcie_apm_init(trans);
1759 if (err)
1760 return err;
a6c684ee 1761
2e5d4a8f 1762 iwl_pcie_init_msix(trans_pcie);
83730058 1763
226c02ca
EG		 1764 /* From now on, the op_mode will be kept updated about RF kill state */
1765 iwl_enable_rfkill_int(trans);
1766
326477e4
JB		 1767 trans_pcie->opmode_down = false;
1768
fa9f3281
EG		 1769 /* Set is_down to false here so that...*/
1770 trans_pcie->is_down = false;
1771
727c02df 1772 /* ...rfkill can call stop_device and set it false if needed */
9ad8fd0b 1773 iwl_pcie_check_hw_rf_kill(trans);
d48e2074 1774
a8b691e6 1775 return 0;
e6bb4c9c
EG		 1776}
1777
bab3cb92 1778static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
fa9f3281
EG		 1779{
1780 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1781 int ret;
1782
1783 mutex_lock(&trans_pcie->mutex);
bab3cb92 1784 ret = _iwl_trans_pcie_start_hw(trans);
fa9f3281
EG		 1785 mutex_unlock(&trans_pcie->mutex);
1786
1787 return ret;
1788}
1789
a4082843 1790static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1791{
20d3b647 1792 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1793
fa9f3281
EG		 1794 mutex_lock(&trans_pcie->mutex);
1795
a4082843 1796 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1797 iwl_disable_interrupts(trans);
ee7d737c 1798
b7aaeae4 1799 iwl_pcie_apm_stop(trans, true);
cc56feb2 1800
218733cf 1801 iwl_disable_interrupts(trans);
1df06bdc 1802
8d96bb61 1803 iwl_pcie_disable_ict(trans);
33b56af1 1804
fa9f3281 1805 mutex_unlock(&trans_pcie->mutex);
33b56af1 1806
2e5d4a8f 1807 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1808}
1809
03905495
EG		 1810static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1811{
05f5b97e 1812 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1813}
1814
1815static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1816{
05f5b97e 1817 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1818}
1819
1820static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1821{
05f5b97e 1822 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1823}
1824
84fb372c
SS		 1825static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1826{
3681021f 1827 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
84fb372c
SS		 1828 return 0x00FFFFFF;
1829 else
1830 return 0x000FFFFF;
1831}
1832
6a06b6c1
EG		 1833static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1834{
84fb372c
SS		 1835 u32 mask = iwl_trans_pcie_prph_msk(trans);
1836
f9477c17 1837 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
84fb372c 1838 ((reg & mask) | (3 << 24)));
6a06b6c1
EG		 1839 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1840}
1841
1842static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1843 u32 val)
1844{
84fb372c
SS		 1845 u32 mask = iwl_trans_pcie_prph_msk(trans);
1846
6a06b6c1 1847 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
84fb372c 1848 ((addr & mask) | (3 << 24)));
6a06b6c1
EG		 1849 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1850}
1851
c6f600fc 1852static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1853 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1854{
1855 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1856
4f4822b7
MG		 1857 trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
1858 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
1859 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
22852fad
MG		 1860 trans->txqs.page_offs = trans_cfg->cb_data_offs;
1861 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1862
d663ee73
JB		 1863 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1864 trans_pcie->n_no_reclaim_cmds = 0;
1865 else
1866 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1867 if (trans_pcie->n_no_reclaim_cmds)
1868 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1869 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1870
6c4fbcbc
EG		 1871 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1872 trans_pcie->rx_page_order =
1873 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
80084e35
JB		 1874 trans_pcie->rx_buf_bytes =
1875 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
cfdc20ef
JB		 1876 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1877 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1878 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
7c5ba4a8 1879
8e3b79f8 1880 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1881 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39 1882
39bdb17e
SD		 1883 trans->command_groups = trans_cfg->command_groups;
1884 trans->command_groups_size = trans_cfg->command_groups_size;
1885
f14d6b39
JB		 1886 /* Initialize NAPI here - it should be before registering to mac80211
1887 * in the opmode but after the HW struct is allocated.
1888 * As this function may be called again in some corner cases don't
1889 * do anything if NAPI was already initialized.
1890 */
bce97731 1891 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1892 init_dummy_netdev(&trans_pcie->napi_dev);
906d4eb8
JB		 1893
1894 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
c6f600fc
MV		 1895}
1896
d1ff5253 1897void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1898{
20d3b647 1899 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1900 int i;
a42a1844 1901
2e5d4a8f 1902 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1903
286ca8eb 1904 if (trans->trans_cfg->gen2)
0cd1ad2d 1905 iwl_txq_gen2_tx_free(trans);
13a3a390
SS		 1906 else
1907 iwl_pcie_tx_free(trans);
9805c446 1908 iwl_pcie_rx_free(trans);
6379103e 1909
10a54d81
LC		 1910 if (trans_pcie->rba.alloc_wq) {
1911 destroy_workqueue(trans_pcie->rba.alloc_wq);
1912 trans_pcie->rba.alloc_wq = NULL;
1913 }
1914
2e5d4a8f 1915 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1916 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1917 irq_set_affinity_hint(
1918 trans_pcie->msix_entries[i].vector,
1919 NULL);
7c8d91eb 1920 }
2e5d4a8f 1921
2e5d4a8f
HD		 1922 trans_pcie->msix_enabled = false;
1923 } else {
2e5d4a8f 1924 iwl_pcie_free_ict(trans);
2e5d4a8f 1925 }
a42a1844 1926
c2d20201
EG		 1927 iwl_pcie_free_fw_monitor(trans);
1928
69725928
LC		 1929 if (trans_pcie->pnvm_dram.size)
1930 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
1931 trans_pcie->pnvm_dram.block,
1932 trans_pcie->pnvm_dram.physical);
1933
a2a57a35 1934 mutex_destroy(&trans_pcie->mutex);
7b501d10 1935 iwl_trans_free(trans);
34c1b7ba
EG		 1936}
1937
47107e84
DF		 1938static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1939{
47107e84 1940 if (state)
eb7ff77e 1941 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1942 else
eb7ff77e 1943 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1944}
1945
49564a80
LC		 1946struct iwl_trans_pcie_removal {
1947 struct pci_dev *pdev;
1948 struct work_struct work;
1949};
1950
1951static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
1952{
1953 struct iwl_trans_pcie_removal *removal =
1954 container_of(wk, struct iwl_trans_pcie_removal, work);
1955 struct pci_dev *pdev = removal->pdev;
aba1e632 1956 static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
49564a80
LC		 1957
1958 dev_err(&pdev->dev, "Device gone - attempting removal\n");
1959 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
1960 pci_lock_rescan_remove();
1961 pci_dev_put(pdev);
1962 pci_stop_and_remove_bus_device(pdev);
1963 pci_unlock_rescan_remove();
1964
1965 kfree(removal);
1966 module_put(THIS_MODULE);
1967}
1968
23ba9340
EG		 1969static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1970 unsigned long *flags)
7a65d170
EG		 1971{
1972 int ret;
cfb4e624
JB		 1973 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1974
d97c29ee 1975 spin_lock_bh(&trans_pcie->reg_lock);
7a65d170 1976
fc8a350d 1977 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1978 goto out;
1979
7a65d170 1980 /* this bit wakes up the NIC */
e139dc4a 1981 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
6dece0e9 1982 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
286ca8eb 1983 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
01e58a28 1984 udelay(2);
7a65d170
EG		 1985
1986 /*
1987 * These bits say the device is running, and should keep running for
1988 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1989 * but they do not indicate that embedded SRAM is restored yet;
fb70d49f
LC		 1990 * HW with volatile SRAM must save/restore contents to/from
1991 * host DRAM when sleeping/waking for power-saving.
7a65d170
EG		 1992 * Each direction takes approximately 1/4 millisecond; with this
1993 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1994 * series of register accesses are expected (e.g. reading Event Log),
1995 * to keep device from sleeping.
1996 *
1997 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1998 * SRAM is okay/restored. We don't check that here because this call
fb70d49f
LC		 1999 * is just for hardware register access; but GP1 MAC_SLEEP
2000 * check is a good idea before accessing the SRAM of HW with
2001 * volatile SRAM (e.g. reading Event Log).
7a65d170
EG		 2002 *
2003 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2004 * and do not save/restore SRAM when power cycling.
2005 */
2006 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
6dece0e9
LC		 2007 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
2008 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
7a65d170
EG		 2009 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2010 if (unlikely(ret < 0)) {
49564a80
LC		 2011 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2012
23ba9340
EG		 2013 WARN_ONCE(1,
2014 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
49564a80
LC		 2015 cntrl);
2016
2017 iwl_trans_pcie_dump_regs(trans);
2018
2019 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2020 struct iwl_trans_pcie_removal *removal;
2021
f60c9e59 2022 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
49564a80
LC		 2023 goto err;
2024
2025 IWL_ERR(trans, "Device gone - scheduling removal!\n");
2026
2027 /*
2028 * get a module reference to avoid doing this
2029 * while unloading anyway and to avoid
2030 * scheduling a work with code that's being
2031 * removed.
2032 */
2033 if (!try_module_get(THIS_MODULE)) {
2034 IWL_ERR(trans,
2035 "Module is being unloaded - abort\n");
2036 goto err;
2037 }
2038
2039 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2040 if (!removal) {
2041 module_put(THIS_MODULE);
2042 goto err;
2043 }
2044 /*
2045 * we don't need to clear this flag, because
2046 * the trans will be freed and reallocated.
2047 */
f60c9e59 2048 set_bit(STATUS_TRANS_DEAD, &trans->status);
49564a80
LC		 2049
2050 removal->pdev = to_pci_dev(trans->dev);
2051 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2052 pci_dev_get(removal->pdev);
2053 schedule_work(&removal->work);
2054 } else {
2055 iwl_write32(trans, CSR_RESET,
2056 CSR_RESET_REG_FLAG_FORCE_NMI);
2057 }
2058
2059err:
d97c29ee 2060 spin_unlock_bh(&trans_pcie->reg_lock);
23ba9340 2061 return false;
7a65d170
EG		 2062 }
2063
b9439491 2064out:
e56b04ef
LE		 2065 /*
2066 * Fool sparse by faking we release the lock - sparse will
2067 * track nic_access anyway.
2068 */
cfb4e624 2069 __release(&trans_pcie->reg_lock);
7a65d170
EG		 2070 return true;
2071}
2072
e56b04ef
LE		 2073static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2074 unsigned long *flags)
7a65d170 2075{
cfb4e624 2076 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 2077
cfb4e624 2078 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 2079
2080 /*
2081 * Fool sparse by faking we acquiring the lock - sparse will
2082 * track nic_access anyway.
2083 */
cfb4e624 2084 __acquire(&trans_pcie->reg_lock);
e56b04ef 2085
fc8a350d 2086 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 2087 goto out;
2088
e139dc4a 2089 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
6dece0e9 2090 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 2091 /*
2092 * Above we read the CSR_GP_CNTRL register, which will flush
2093 * any previous writes, but we need the write that clears the
2094 * MAC_ACCESS_REQ bit to be performed before any other writes
2095 * scheduled on different CPUs (after we drop reg_lock).
2096 */
b9439491 2097out:
d97c29ee 2098 spin_unlock_bh(&trans_pcie->reg_lock);
7a65d170
EG		 2099}
2100
4fd442db
EG		 2101static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2102 void *buf, int dwords)
2103{
2104 unsigned long flags;
04516706 2105 int offs = 0;
4fd442db
EG		 2106 u32 *vals = buf;
2107
04516706
JB		 2108 while (offs < dwords) {
2109 /* limit the time we spin here under lock to 1/2s */
67013174 2110 unsigned long end = jiffies + HZ / 2;
3d372c4e 2111 bool resched = false;
04516706
JB		 2112
2113 if (iwl_trans_grab_nic_access(trans, &flags)) {
2114 iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2115 addr + 4 * offs);
2116
2117 while (offs < dwords) {
2118 vals[offs] = iwl_read32(trans,
2119 HBUS_TARG_MEM_RDAT);
2120 offs++;
2121
3d372c4e
JB		 2122 if (time_after(jiffies, end)) {
2123 resched = true;
04516706 2124 break;
3d372c4e 2125 }
04516706
JB		 2126 }
2127 iwl_trans_release_nic_access(trans, &flags);
3d372c4e
JB		 2128
2129 if (resched)
2130 cond_resched();
04516706
JB		 2131 } else {
2132 return -EBUSY;
2133 }
4fd442db 2134 }
04516706
JB		 2135
2136 return 0;
4fd442db
EG		 2137}
2138
2139static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 2140 const void *buf, int dwords)
4fd442db
EG		 2141{
2142 unsigned long flags;
2143 int offs, ret = 0;
bf0fd5da 2144 const u32 *vals = buf;
4fd442db 2145
23ba9340 2146 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 2147 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2148 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 2149 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2150 vals ? vals[offs] : 0);
e56b04ef 2151 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 2152 } else {
2153 ret = -EBUSY;
2154 }
4fd442db
EG		 2155 return ret;
2156}
7a65d170 2157
7f1fe1d4
LC		 2158static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2159 u32 *val)
2160{
2161 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2162 ofs, val);
2163}
2164
0cd58eaa
EG		 2165static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2166{
0cd58eaa
EG		 2167 int i;
2168
286ca8eb 2169 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
4f4822b7 2170 struct iwl_txq *txq = trans->txqs.txq[i];
0cd58eaa 2171
4f4822b7 2172 if (i == trans->txqs.cmd.q_id)
0cd58eaa
EG		 2173 continue;
2174
2175 spin_lock_bh(&txq->lock);
2176
2177 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2178 txq->block--;
2179 if (!txq->block) {
2180 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2181 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2182 }
2183 } else if (block) {
2184 txq->block++;
2185 }
2186
2187 spin_unlock_bh(&txq->lock);
2188 }
2189}
2190
5f178cd2
EG		 2191#define IWL_FLUSH_WAIT_MS 2000
2192
92536c96
SS		 2193static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2194 struct iwl_trans_rxq_dma_data *data)
2195{
2196 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2197
2198 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2199 return -EINVAL;
2200
2201 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2202 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2203 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2204 data->fr_bd_wid = 0;
2205
2206 return 0;
2207}
2208
d6d517b7 2209static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
5f178cd2 2210{
990aa6d7 2211 struct iwl_txq *txq;
5f178cd2 2212 unsigned long now = jiffies;
2ae48edc 2213 bool overflow_tx;
d6d517b7
SS		 2214 u8 wr_ptr;
2215
2b3fae66 2216 /* Make sure the NIC is still alive in the bus */
f60c9e59
EG		 2217 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2218 return -ENODEV;
2b3fae66 2219
4f4822b7 2220 if (!test_bit(txq_idx, trans->txqs.queue_used))
d6d517b7
SS		 2221 return -EINVAL;
2222
2223 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
4f4822b7 2224 txq = trans->txqs.txq[txq_idx];
2ae48edc
SS		 2225
2226 spin_lock_bh(&txq->lock);
2227 overflow_tx = txq->overflow_tx ||
2228 !skb_queue_empty(&txq->overflow_q);
2229 spin_unlock_bh(&txq->lock);
2230
6aa7de05 2231 wr_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2232
2ae48edc
SS		 2233 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2234 overflow_tx) &&
d6d517b7
SS		 2235 !time_after(jiffies,
2236 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
6aa7de05 2237 u8 write_ptr = READ_ONCE(txq->write_ptr);
d6d517b7 2238
2ae48edc
SS		 2239 /*
2240 * If write pointer moved during the wait, warn only
2241 * if the TX came from op mode. In case TX came from
2242 * trans layer (overflow TX) don't warn.
2243 */
2244 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
d6d517b7
SS		 2245 "WR pointer moved while flushing %d -> %d\n",
2246 wr_ptr, write_ptr))
2247 return -ETIMEDOUT;
2ae48edc
SS		 2248 wr_ptr = write_ptr;
2249
d6d517b7 2250 usleep_range(1000, 2000);
2ae48edc
SS		 2251
2252 spin_lock_bh(&txq->lock);
2253 overflow_tx = txq->overflow_tx ||
2254 !skb_queue_empty(&txq->overflow_q);
2255 spin_unlock_bh(&txq->lock);
d6d517b7
SS		 2256 }
2257
2258 if (txq->read_ptr != txq->write_ptr) {
2259 IWL_ERR(trans,
2260 "fail to flush all tx fifo queues Q %d\n", txq_idx);
0cd1ad2d 2261 iwl_txq_log_scd_error(trans, txq);
d6d517b7
SS		 2262 return -ETIMEDOUT;
2263 }
2264
2265 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2266
2267 return 0;
2268}
2269
2270static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2271{
d6d517b7 2272 int cnt;
5f178cd2
EG		 2273 int ret = 0;
2274
2275 /* waiting for all the tx frames complete might take a while */
79b6c8fe 2276 for (cnt = 0;
286ca8eb 2277 cnt < trans->trans_cfg->base_params->num_of_queues;
79b6c8fe 2278 cnt++) {
fa1a91fd 2279
4f4822b7 2280 if (cnt == trans->txqs.cmd.q_id)
5f178cd2 2281 continue;
4f4822b7 2282 if (!test_bit(cnt, trans->txqs.queue_used))
3cafdbe6
EG		 2283 continue;
2284 if (!(BIT(cnt) & txq_bm))
2285 continue;
748fa67c 2286
d6d517b7
SS		 2287 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2288 if (ret)
5f178cd2 2289 break;
5f178cd2 2290 }
1c3fea82 2291
5f178cd2
EG		 2292 return ret;
2293}
2294
e139dc4a
LE		 2295static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2296 u32 mask, u32 value)
2297{
e56b04ef 2298 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a 2299
d97c29ee 2300 spin_lock_bh(&trans_pcie->reg_lock);
e139dc4a 2301 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
d97c29ee 2302 spin_unlock_bh(&trans_pcie->reg_lock);
e139dc4a
LE		 2303}
2304
ff620849
EG		 2305static const char *get_csr_string(int cmd)
2306{
d9fb6465 2307#define IWL_CMD(x) case x: return #x
ff620849
EG		 2308 switch (cmd) {
2309 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2310 IWL_CMD(CSR_INT_COALESCING);
2311 IWL_CMD(CSR_INT);
2312 IWL_CMD(CSR_INT_MASK);
2313 IWL_CMD(CSR_FH_INT_STATUS);
2314 IWL_CMD(CSR_GPIO_IN);
2315 IWL_CMD(CSR_RESET);
2316 IWL_CMD(CSR_GP_CNTRL);
2317 IWL_CMD(CSR_HW_REV);
2318 IWL_CMD(CSR_EEPROM_REG);
2319 IWL_CMD(CSR_EEPROM_GP);
2320 IWL_CMD(CSR_OTP_GP_REG);
2321 IWL_CMD(CSR_GIO_REG);
2322 IWL_CMD(CSR_GP_UCODE_REG);
2323 IWL_CMD(CSR_GP_DRIVER_REG);
2324 IWL_CMD(CSR_UCODE_DRV_GP1);
2325 IWL_CMD(CSR_UCODE_DRV_GP2);
2326 IWL_CMD(CSR_LED_REG);
2327 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2328 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2329 IWL_CMD(CSR_ANA_PLL_CFG);
2330 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2331 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2332 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2333 default:
2334 return "UNKNOWN";
2335 }
d9fb6465 2336#undef IWL_CMD
ff620849
EG		 2337}
2338
990aa6d7 2339void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2340{
2341 int i;
2342 static const u32 csr_tbl[] = {
2343 CSR_HW_IF_CONFIG_REG,
2344 CSR_INT_COALESCING,
2345 CSR_INT,
2346 CSR_INT_MASK,
2347 CSR_FH_INT_STATUS,
2348 CSR_GPIO_IN,
2349 CSR_RESET,
2350 CSR_GP_CNTRL,
2351 CSR_HW_REV,
2352 CSR_EEPROM_REG,
2353 CSR_EEPROM_GP,
2354 CSR_OTP_GP_REG,
2355 CSR_GIO_REG,
2356 CSR_GP_UCODE_REG,
2357 CSR_GP_DRIVER_REG,
2358 CSR_UCODE_DRV_GP1,
2359 CSR_UCODE_DRV_GP2,
2360 CSR_LED_REG,
2361 CSR_DRAM_INT_TBL_REG,
2362 CSR_GIO_CHICKEN_BITS,
2363 CSR_ANA_PLL_CFG,
a812cba9 2364 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2365 CSR_HW_REV_WA_REG,
2366 CSR_DBG_HPET_MEM_REG
2367 };
2368 IWL_ERR(trans, "CSR values:\n");
2369 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2370 "CSR_INT_PERIODIC_REG)\n");
2371 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2372 IWL_ERR(trans, " %25s: 0X%08x\n",
2373 get_csr_string(csr_tbl[i]),
1042db2a 2374 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2375 }
2376}
2377
87e5666c
EG		 2378#ifdef CONFIG_IWLWIFI_DEBUGFS
2379/* create and remove of files */
2380#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
cf5d5663
GKH		 2381 debugfs_create_file(#name, mode, parent, trans, \
2382 &iwl_dbgfs_##name##_ops); \
87e5666c
EG		 2383} while (0)
2384
2385/* file operation */
87e5666c 2386#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2387static const struct file_operations iwl_dbgfs_##name##_ops = { \
2388 .read = iwl_dbgfs_##name##_read, \
234e3405 2389 .open = simple_open, \
87e5666c
EG		 2390 .llseek = generic_file_llseek, \
2391};
2392
16db88ba 2393#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2394static const struct file_operations iwl_dbgfs_##name##_ops = { \
2395 .write = iwl_dbgfs_##name##_write, \
234e3405 2396 .open = simple_open, \
16db88ba
EG		 2397 .llseek = generic_file_llseek, \
2398};
2399
87e5666c 2400#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2401static const struct file_operations iwl_dbgfs_##name##_ops = { \
2402 .write = iwl_dbgfs_##name##_write, \
2403 .read = iwl_dbgfs_##name##_read, \
234e3405 2404 .open = simple_open, \
87e5666c
EG		 2405 .llseek = generic_file_llseek, \
2406};
2407
df67a1be
JB		 2408struct iwl_dbgfs_tx_queue_priv {
2409 struct iwl_trans *trans;
2410};
2411
2412struct iwl_dbgfs_tx_queue_state {
2413 loff_t pos;
2414};
2415
2416static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
8ad71bef 2417{
df67a1be
JB		 2418 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2419 struct iwl_dbgfs_tx_queue_state *state;
2420
2421 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2422 return NULL;
2423
2424 state = kmalloc(sizeof(*state), GFP_KERNEL);
2425 if (!state)
2426 return NULL;
2427 state->pos = *pos;
2428 return state;
2429}
2430
2431static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2432 void *v, loff_t *pos)
2433{
2434 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2435 struct iwl_dbgfs_tx_queue_state *state = v;
2436
2437 *pos = ++state->pos;
2438
2439 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2440 return NULL;
2441
2442 return state;
2443}
2444
2445static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2446{
2447 kfree(v);
2448}
2449
2450static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2451{
2452 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2453 struct iwl_dbgfs_tx_queue_state *state = v;
2454 struct iwl_trans *trans = priv->trans;
4f4822b7 2455 struct iwl_txq *txq = trans->txqs.txq[state->pos];
df67a1be
JB		 2456
2457 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2458 (unsigned int)state->pos,
4f4822b7
MG		 2459 !!test_bit(state->pos, trans->txqs.queue_used),
2460 !!test_bit(state->pos, trans->txqs.queue_stopped));
df67a1be
JB		 2461 if (txq)
2462 seq_printf(seq,
95a9e44f 2463 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
df67a1be 2464 txq->read_ptr, txq->write_ptr,
95a9e44f
JB		 2465 txq->need_update, txq->frozen,
2466 txq->n_window, txq->ampdu);
df67a1be
JB		 2467 else
2468 seq_puts(seq, "(unallocated)");
1745e440 2469
4f4822b7 2470 if (state->pos == trans->txqs.cmd.q_id)
df67a1be
JB		 2471 seq_puts(seq, " (HCMD)");
2472 seq_puts(seq, "\n");
87e5666c 2473
df67a1be
JB		 2474 return 0;
2475}
f9e75447 2476
df67a1be
JB		 2477static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2478 .start = iwl_dbgfs_tx_queue_seq_start,
2479 .next = iwl_dbgfs_tx_queue_seq_next,
2480 .stop = iwl_dbgfs_tx_queue_seq_stop,
2481 .show = iwl_dbgfs_tx_queue_seq_show,
2482};
2483
2484static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2485{
2486 struct iwl_dbgfs_tx_queue_priv *priv;
2487
2488 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2489 sizeof(*priv));
2490
2491 if (!priv)
87e5666c
EG		 2492 return -ENOMEM;
2493
df67a1be
JB		 2494 priv->trans = inode->i_private;
2495 return 0;
87e5666c
EG		 2496}
2497
2498static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2499 char __user *user_buf,
2500 size_t count, loff_t *ppos)
2501{
5a878bf6 2502 struct iwl_trans *trans = file->private_data;
20d3b647 2503 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2504 char *buf;
2505 int pos = 0, i, ret;
eb3dc36e 2506 size_t bufsz;
78485054
SS		 2507
2508 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2509
2510 if (!trans_pcie->rxq)
2511 return -EAGAIN;
2512
2513 buf = kzalloc(bufsz, GFP_KERNEL);
2514 if (!buf)
2515 return -ENOMEM;
2516
2517 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2518 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2519
2520 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2521 i);
2522 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2523 rxq->read);
2524 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2525 rxq->write);
2526 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2527 rxq->write_actual);
2528 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2529 rxq->need_update);
2530 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2531 rxq->free_count);
2532 if (rxq->rb_stts) {
0307c839
GBA		 2533 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2534 rxq));
78485054
SS		 2535 pos += scnprintf(buf + pos, bufsz - pos,
2536 "\tclosed_rb_num: %u\n",
0307c839 2537 r & 0x0FFF);
78485054
SS		 2538 } else {
2539 pos += scnprintf(buf + pos, bufsz - pos,
2540 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2541 }
87e5666c 2542 }
78485054
SS		 2543 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2544 kfree(buf);
2545
2546 return ret;
87e5666c
EG		 2547}
2548
1f7b6172
EG		 2549static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2550 char __user *user_buf,
20d3b647
JB		 2551 size_t count, loff_t *ppos)
2552{
1f7b6172 2553 struct iwl_trans *trans = file->private_data;
20d3b647 2554 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2555 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2556
2557 int pos = 0;
2558 char *buf;
2559 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2560 ssize_t ret;
2561
2562 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2563 if (!buf)
1f7b6172 2564 return -ENOMEM;
1f7b6172
EG		 2565
2566 pos += scnprintf(buf + pos, bufsz - pos,
2567 "Interrupt Statistics Report:\n");
2568
2569 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2570 isr_stats->hw);
2571 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2572 isr_stats->sw);
2573 if (isr_stats->sw || isr_stats->hw) {
2574 pos += scnprintf(buf + pos, bufsz - pos,
2575 "\tLast Restarting Code: 0x%X\n",
2576 isr_stats->err_code);
2577 }
2578#ifdef CONFIG_IWLWIFI_DEBUG
2579 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2580 isr_stats->sch);
2581 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2582 isr_stats->alive);
2583#endif
2584 pos += scnprintf(buf + pos, bufsz - pos,
2585 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2586
2587 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2588 isr_stats->ctkill);
2589
2590 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2591 isr_stats->wakeup);
2592
2593 pos += scnprintf(buf + pos, bufsz - pos,
2594 "Rx command responses:\t\t %u\n", isr_stats->rx);
2595
2596 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2597 isr_stats->tx);
2598
2599 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2600 isr_stats->unhandled);
2601
2602 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2603 kfree(buf);
2604 return ret;
2605}
2606
2607static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2608 const char __user *user_buf,
2609 size_t count, loff_t *ppos)
2610{
2611 struct iwl_trans *trans = file->private_data;
20d3b647 2612 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172 2613 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1f7b6172 2614 u32 reset_flag;
078f1131 2615 int ret;
1f7b6172 2616
078f1131
JB		 2617 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2618 if (ret)
2619 return ret;
1f7b6172
EG		 2620 if (reset_flag == 0)
2621 memset(isr_stats, 0, sizeof(*isr_stats));
2622
2623 return count;
2624}
2625
16db88ba 2626static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2627 const char __user *user_buf,
2628 size_t count, loff_t *ppos)
16db88ba
EG		 2629{
2630 struct iwl_trans *trans = file->private_data;
16db88ba 2631
990aa6d7 2632 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2633
2634 return count;
2635}
2636
16db88ba 2637static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2638 char __user *user_buf,
2639 size_t count, loff_t *ppos)
16db88ba
EG		 2640{
2641 struct iwl_trans *trans = file->private_data;
94543a8d 2642 char *buf = NULL;
56c2477f 2643 ssize_t ret;
16db88ba 2644
56c2477f
JB		 2645 ret = iwl_dump_fh(trans, &buf);
2646 if (ret < 0)
2647 return ret;
2648 if (!buf)
2649 return -EINVAL;
2650 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2651 kfree(buf);
16db88ba
EG		 2652 return ret;
2653}
2654
fa4de7f7
JB		 2655static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2656 char __user *user_buf,
2657 size_t count, loff_t *ppos)
2658{
2659 struct iwl_trans *trans = file->private_data;
2660 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2661 char buf[100];
2662 int pos;
2663
2664 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2665 trans_pcie->debug_rfkill,
2666 !(iwl_read32(trans, CSR_GP_CNTRL) &
2667 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2668
2669 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2670}
2671
2672static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2673 const char __user *user_buf,
2674 size_t count, loff_t *ppos)
2675{
2676 struct iwl_trans *trans = file->private_data;
2677 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c5bf4fa1 2678 bool new_value;
fa4de7f7
JB		 2679 int ret;
2680
c5bf4fa1 2681 ret = kstrtobool_from_user(user_buf, count, &new_value);
fa4de7f7
JB		 2682 if (ret)
2683 return ret;
c5bf4fa1 2684 if (new_value == trans_pcie->debug_rfkill)
fa4de7f7
JB		 2685 return count;
2686 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
c5bf4fa1
JB		 2687 trans_pcie->debug_rfkill, new_value);
2688 trans_pcie->debug_rfkill = new_value;
fa4de7f7
JB		 2689 iwl_pcie_handle_rfkill_irq(trans);
2690
2691 return count;
2692}
2693
f7805b33
LC		 2694static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2695 struct file *file)
2696{
2697 struct iwl_trans *trans = inode->i_private;
2698 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2699
91c28b83
SM		 2700 if (!trans->dbg.dest_tlv ||
2701 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
f7805b33
LC		 2702 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2703 return -ENOENT;
2704 }
2705
2706 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2707 return -EBUSY;
2708
2709 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2710 return simple_open(inode, file);
2711}
2712
2713static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2714 struct file *file)
2715{
2716 struct iwl_trans_pcie *trans_pcie =
2717 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2718
2719 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2720 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2721 return 0;
2722}
2723
2724static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2725 void *buf, ssize_t *size,
2726 ssize_t *bytes_copied)
2727{
2728 int buf_size_left = count - *bytes_copied;
2729
2730 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2731 if (*size > buf_size_left)
2732 *size = buf_size_left;
2733
2734 *size -= copy_to_user(user_buf, buf, *size);
2735 *bytes_copied += *size;
2736
2737 if (buf_size_left == *size)
2738 return true;
2739 return false;
2740}
2741
2742static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2743 char __user *user_buf,
2744 size_t count, loff_t *ppos)
2745{
2746 struct iwl_trans *trans = file->private_data;
2747 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
69f0e505 2748 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
f7805b33
LC		 2749 struct cont_rec *data = &trans_pcie->fw_mon_data;
2750 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2751 ssize_t size, bytes_copied = 0;
2752 bool b_full;
2753
91c28b83 2754 if (trans->dbg.dest_tlv) {
f7805b33 2755 write_ptr_addr =
91c28b83
SM		 2756 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2757 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
f7805b33
LC		 2758 } else {
2759 write_ptr_addr = MON_BUFF_WRPTR;
2760 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2761 }
2762
91c28b83 2763 if (unlikely(!trans->dbg.rec_on))
f7805b33
LC		 2764 return 0;
2765
2766 mutex_lock(&data->mutex);
2767 if (data->state ==
2768 IWL_FW_MON_DBGFS_STATE_DISABLED) {
2769 mutex_unlock(&data->mutex);
2770 return 0;
2771 }
2772
2773 /* write_ptr position in bytes rather then DW */
2774 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2775 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2776
2777 if (data->prev_wrap_cnt == wrap_cnt) {
2778 size = write_ptr - data->prev_wr_ptr;
2779 curr_buf = cpu_addr + data->prev_wr_ptr;
2780 b_full = iwl_write_to_user_buf(user_buf, count,
2781 curr_buf, &size,
2782 &bytes_copied);
2783 data->prev_wr_ptr += size;
2784
2785 } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2786 write_ptr < data->prev_wr_ptr) {
69f0e505 2787 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
f7805b33
LC		 2788 curr_buf = cpu_addr + data->prev_wr_ptr;
2789 b_full = iwl_write_to_user_buf(user_buf, count,
2790 curr_buf, &size,
2791 &bytes_copied);
2792 data->prev_wr_ptr += size;
2793
2794 if (!b_full) {
2795 size = write_ptr;
2796 b_full = iwl_write_to_user_buf(user_buf, count,
2797 cpu_addr, &size,
2798 &bytes_copied);
2799 data->prev_wr_ptr = size;
2800 data->prev_wrap_cnt++;
2801 }
2802 } else {
2803 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2804 write_ptr > data->prev_wr_ptr)
2805 IWL_WARN(trans,
2806 "write pointer passed previous write pointer, start copying from the beginning\n");
2807 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2808 data->prev_wr_ptr == 0))
2809 IWL_WARN(trans,
2810 "monitor data is out of sync, start copying from the beginning\n");
2811
2812 size = write_ptr;
2813 b_full = iwl_write_to_user_buf(user_buf, count,
2814 cpu_addr, &size,
2815 &bytes_copied);
2816 data->prev_wr_ptr = size;
2817 data->prev_wrap_cnt = wrap_cnt;
2818 }
2819
2820 mutex_unlock(&data->mutex);
2821
2822 return bytes_copied;
2823}
2824
1f7b6172 2825DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2826DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c 2827DEBUGFS_READ_FILE_OPS(rx_queue);
16db88ba 2828DEBUGFS_WRITE_FILE_OPS(csr);
fa4de7f7 2829DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
df67a1be
JB		 2830static const struct file_operations iwl_dbgfs_tx_queue_ops = {
2831 .owner = THIS_MODULE,
2832 .open = iwl_dbgfs_tx_queue_open,
2833 .read = seq_read,
2834 .llseek = seq_lseek,
2835 .release = seq_release_private,
2836};
87e5666c 2837
f7805b33
LC		 2838static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2839 .read = iwl_dbgfs_monitor_data_read,
2840 .open = iwl_dbgfs_monitor_data_open,
2841 .release = iwl_dbgfs_monitor_data_release,
2842};
2843
f8a1edb7 2844/* Create the debugfs files and directories */
cf5d5663 2845void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2846{
f8a1edb7
JB		 2847 struct dentry *dir = trans->dbgfs_dir;
2848
2ef00c53
JP		 2849 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2850 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2851 DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2852 DEBUGFS_ADD_FILE(csr, dir, 0200);
2853 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2854 DEBUGFS_ADD_FILE(rfkill, dir, 0600);
f7805b33 2855 DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
87e5666c 2856}
f7805b33
LC		 2857
2858static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2859{
2860 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2861 struct cont_rec *data = &trans_pcie->fw_mon_data;
2862
2863 mutex_lock(&data->mutex);
2864 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2865 mutex_unlock(&data->mutex);
2866}
aadede6e 2867#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2868
6983ba69 2869static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007
JB		 2870{
2871 u32 cmdlen = 0;
2872 int i;
2873
885375d0 2874 for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
0179bfff 2875 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2876
2877 return cmdlen;
2878}
2879
bd7fc617
EG		 2880static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2881 struct iwl_fw_error_dump_data **data,
2882 int allocated_rb_nums)
2883{
2884 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
80084e35 2885 int max_len = trans_pcie->rx_buf_bytes;
78485054
SS		 2886 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2887 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2888 u32 i, r, j, rb_len = 0;
2889
2890 spin_lock(&rxq->lock);
2891
0307c839 2892 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
bd7fc617
EG		 2893
2894 for (i = rxq->read, j = 0;
2895 i != r && j < allocated_rb_nums;
2896 i = (i + 1) & RX_QUEUE_MASK, j++) {
2897 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2898 struct iwl_fw_error_dump_rb *rb;
2899
2900 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2901 DMA_FROM_DEVICE);
2902
2903 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2904
2905 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2906 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2907 rb = (void *)(*data)->data;
2908 rb->index = cpu_to_le32(i);
2909 memcpy(rb->data, page_address(rxb->page), max_len);
2910 /* remap the page for the free benefit */
cfdc20ef
JB		 2911 rxb->page_dma = dma_map_page(trans->dev, rxb->page,
2912 rxb->offset, max_len,
2913 DMA_FROM_DEVICE);
bd7fc617
EG		 2914
2915 *data = iwl_fw_error_next_data(*data);
2916 }
2917
2918 spin_unlock(&rxq->lock);
2919
2920 return rb_len;
2921}
473ad712
EG		 2922#define IWL_CSR_TO_DUMP (0x250)
2923
2924static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2925 struct iwl_fw_error_dump_data **data)
2926{
2927 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2928 __le32 *val;
2929 int i;
2930
2931 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2932 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2933 val = (void *)(*data)->data;
2934
2935 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2936 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2937
2938 *data = iwl_fw_error_next_data(*data);
2939
2940 return csr_len;
2941}
2942
06d51e0d
LK		 2943static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2944 struct iwl_fw_error_dump_data **data)
2945{
2946 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2947 unsigned long flags;
2948 __le32 *val;
2949 int i;
2950
23ba9340 2951 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2952 return 0;
2953
2954 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2955 (*data)->len = cpu_to_le32(fh_regs_len);
2956 val = (void *)(*data)->data;
2957
286ca8eb 2958 if (!trans->trans_cfg->gen2)
723b45e2
LK		 2959 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2960 i += sizeof(u32))
2961 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2962 else
ea695b7c
ST		 2963 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
2964 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
723b45e2
LK		 2965 i += sizeof(u32))
2966 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2967 i));
06d51e0d
LK		 2968
2969 iwl_trans_release_nic_access(trans, &flags);
2970
2971 *data = iwl_fw_error_next_data(*data);
2972
2973 return sizeof(**data) + fh_regs_len;
2974}
2975
cc79ef66
LK		 2976static u32
2977iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2978 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2979 u32 monitor_len)
2980{
2981 u32 buf_size_in_dwords = (monitor_len >> 2);
2982 u32 *buffer = (u32 *)fw_mon_data->data;
2983 unsigned long flags;
2984 u32 i;
2985
23ba9340 2986 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2987 return 0;
2988
ea695b7c 2989 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2990 for (i = 0; i < buf_size_in_dwords; i++)
ea695b7c
ST		 2991 buffer[i] = iwl_read_umac_prph_no_grab(trans,
2992 MON_DMARB_RD_DATA_ADDR);
2993 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2994
2995 iwl_trans_release_nic_access(trans, &flags);
2996
2997 return monitor_len;
2998}
2999
7a14c23d
SS		 3000static void
3001iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3002 struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3003{
c88580e1 3004 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
7a14c23d 3005
286ca8eb 3006 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3007 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3008 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3009 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3010 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
91c28b83
SM		 3011 } else if (trans->dbg.dest_tlv) {
3012 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3013 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3014 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
7a14c23d
SS		 3015 } else {
3016 base = MON_BUFF_BASE_ADDR;
3017 write_ptr = MON_BUFF_WRPTR;
3018 wrap_cnt = MON_BUFF_CYCLE_CNT;
3019 }
c88580e1
SM		 3020
3021 write_ptr_val = iwl_read_prph(trans, write_ptr);
7a14c23d
SS		 3022 fw_mon_data->fw_mon_cycle_cnt =
3023 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3024 fw_mon_data->fw_mon_base_ptr =
3025 cpu_to_le32(iwl_read_prph(trans, base));
286ca8eb 3026 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
c88580e1
SM		 3027 fw_mon_data->fw_mon_base_high_ptr =
3028 cpu_to_le32(iwl_read_prph(trans, base_high));
3029 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
cc598782
RS		 3030 /* convert wrtPtr to DWs, to align with all HWs */
3031 write_ptr_val >>= 2;
c88580e1
SM		 3032 }
3033 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
7a14c23d
SS		 3034}
3035
36fb9017
OG		 3036static u32
3037iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3038 struct iwl_fw_error_dump_data **data,
3039 u32 monitor_len)
3040{
69f0e505 3041 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
36fb9017
OG		 3042 u32 len = 0;
3043
91c28b83 3044 if (trans->dbg.dest_tlv ||
69f0e505 3045 (fw_mon->size &&
286ca8eb
LC		 3046 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3047 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
36fb9017 3048 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
36fb9017
OG		 3049
3050 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3051 fw_mon_data = (void *)(*data)->data;
7a14c23d
SS		 3052
3053 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
36fb9017
OG		 3054
3055 len += sizeof(**data) + sizeof(*fw_mon_data);
69f0e505
SM		 3056 if (fw_mon->size) {
3057 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3058 monitor_len = fw_mon->size;
91c28b83 3059 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
7a14c23d 3060 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
36fb9017
OG		 3061 /*
3062 * Update pointers to reflect actual values after
3063 * shifting
3064 */
91c28b83 3065 if (trans->dbg.dest_tlv->version) {
fd527eb5
GBA		 3066 base = (iwl_read_prph(trans, base) &
3067 IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3068 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3069 base *= IWL_M2S_UNIT_SIZE;
3070 base += trans->cfg->smem_offset;
3071 } else {
3072 base = iwl_read_prph(trans, base) <<
91c28b83 3073 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3074 }
3075
36fb9017
OG		 3076 iwl_trans_read_mem(trans, base, fw_mon_data->data,
3077 monitor_len / sizeof(u32));
91c28b83 3078 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
36fb9017
OG		 3079 monitor_len =
3080 iwl_trans_pci_dump_marbh_monitor(trans,
3081 fw_mon_data,
3082 monitor_len);
3083 } else {
3084 /* Didn't match anything - output no monitor data */
3085 monitor_len = 0;
3086 }
3087
3088 len += monitor_len;
3089 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3090 }
3091
3092 return len;
3093}
3094
93079fd5 3095static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
4d075007 3096{
69f0e505 3097 if (trans->dbg.fw_mon.size) {
da752717
SM		 3098 *len += sizeof(struct iwl_fw_error_dump_data) +
3099 sizeof(struct iwl_fw_error_dump_fw_mon) +
69f0e505
SM		 3100 trans->dbg.fw_mon.size;
3101 return trans->dbg.fw_mon.size;
91c28b83 3102 } else if (trans->dbg.dest_tlv) {
da752717 3103 u32 base, end, cfg_reg, monitor_len;
99684ae3 3104
91c28b83
SM		 3105 if (trans->dbg.dest_tlv->version == 1) {
3106 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
fd527eb5
GBA		 3107 cfg_reg = iwl_read_prph(trans, cfg_reg);
3108 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
91c28b83 3109 trans->dbg.dest_tlv->base_shift;
fd527eb5
GBA		 3110 base *= IWL_M2S_UNIT_SIZE;
3111 base += trans->cfg->smem_offset;
99684ae3 3112
fd527eb5
GBA		 3113 monitor_len =
3114 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
91c28b83 3115 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3116 monitor_len *= IWL_M2S_UNIT_SIZE;
3117 } else {
91c28b83
SM		 3118 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3119 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
99684ae3 3120
fd527eb5 3121 base = iwl_read_prph(trans, base) <<
91c28b83 3122 trans->dbg.dest_tlv->base_shift;
fd527eb5 3123 end = iwl_read_prph(trans, end) <<
91c28b83 3124 trans->dbg.dest_tlv->end_shift;
fd527eb5
GBA		 3125
3126 /* Make "end" point to the actual end */
286ca8eb 3127 if (trans->trans_cfg->device_family >=
fd527eb5 3128 IWL_DEVICE_FAMILY_8000 ||
91c28b83
SM		 3129 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3130 end += (1 << trans->dbg.dest_tlv->end_shift);
fd527eb5
GBA		 3131 monitor_len = end - base;
3132 }
da752717
SM		 3133 *len += sizeof(struct iwl_fw_error_dump_data) +
3134 sizeof(struct iwl_fw_error_dump_fw_mon) +
3135 monitor_len;
3136 return monitor_len;
99684ae3 3137 }
da752717
SM		 3138 return 0;
3139}
3140
3141static struct iwl_trans_dump_data
3142*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
79f033f6 3143 u32 dump_mask)
da752717
SM		 3144{
3145 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3146 struct iwl_fw_error_dump_data *data;
4f4822b7 3147 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
da752717
SM		 3148 struct iwl_fw_error_dump_txcmd *txcmd;
3149 struct iwl_trans_dump_data *dump_data;
fefbf853 3150 u32 len, num_rbs = 0, monitor_len = 0;
da752717
SM		 3151 int i, ptr;
3152 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
286ca8eb 3153 !trans->trans_cfg->mq_rx_supported &&
79f033f6
SS		 3154 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3155
3156 if (!dump_mask)
3157 return NULL;
da752717
SM		 3158
3159 /* transport dump header */
3160 len = sizeof(*dump_data);
3161
3162 /* host commands */
e4eee943 3163 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
8672aad3
SM		 3164 len += sizeof(*data) +
3165 cmdq->n_window * (sizeof(*txcmd) +
3166 TFD_MAX_PAYLOAD_SIZE);
da752717
SM		 3167
3168 /* FW monitor */
fefbf853
SM		 3169 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3170 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
36fb9017
OG		 3171
3172 /* CSR registers */
79f033f6 3173 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3174 len += sizeof(*data) + IWL_CSR_TO_DUMP;
36fb9017 3175
36fb9017 3176 /* FH registers */
79f033f6 3177 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
286ca8eb 3178 if (trans->trans_cfg->gen2)
520f03ea 3179 len += sizeof(*data) +
ea695b7c
ST		 3180 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3181 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
520f03ea
SM		 3182 else
3183 len += sizeof(*data) +
3184 (FH_MEM_UPPER_BOUND -
3185 FH_MEM_LOWER_BOUND);
3186 }
36fb9017
OG		 3187
3188 if (dump_rbs) {
78485054
SS		 3189 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3190 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 3191 /* RBs */
0307c839
GBA		 3192 num_rbs =
3193 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3194 & 0x0FFF;
78485054 3195 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 3196 len += num_rbs * (sizeof(*data) +
3197 sizeof(struct iwl_fw_error_dump_rb) +
3198 (PAGE_SIZE << trans_pcie->rx_page_order));
3199 }
3200
5538409b 3201 /* Paged memory for gen2 HW */
286ca8eb 3202 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
505a00c0 3203 for (i = 0; i < trans->init_dram.paging_cnt; i++)
5538409b
LK		 3204 len += sizeof(*data) +
3205 sizeof(struct iwl_fw_error_dump_paging) +
505a00c0 3206 trans->init_dram.paging[i].size;
5538409b 3207
48eb7b34
EG		 3208 dump_data = vzalloc(len);
3209 if (!dump_data)
3210 return NULL;
4d075007
JB		 3211
3212 len = 0;
48eb7b34 3213 data = (void *)dump_data->data;
520f03ea 3214
e4eee943 3215 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
885375d0 3216 u16 tfd_size = trans->txqs.tfd.size;
520f03ea
SM		 3217
3218 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3219 txcmd = (void *)data->data;
3220 spin_lock_bh(&cmdq->lock);
3221 ptr = cmdq->write_ptr;
3222 for (i = 0; i < cmdq->n_window; i++) {
0cd1ad2d 3223 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
08326a97 3224 u8 tfdidx;
520f03ea
SM		 3225 u32 caplen, cmdlen;
3226
08326a97
JB		 3227 if (trans->trans_cfg->use_tfh)
3228 tfdidx = idx;
3229 else
3230 tfdidx = ptr;
3231
520f03ea 3232 cmdlen = iwl_trans_pcie_get_cmdlen(trans,
08326a97
JB		 3233 (u8 *)cmdq->tfds +
3234 tfd_size * tfdidx);
520f03ea
SM		 3235 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3236
3237 if (cmdlen) {
3238 len += sizeof(*txcmd) + caplen;
3239 txcmd->cmdlen = cpu_to_le32(cmdlen);
3240 txcmd->caplen = cpu_to_le32(caplen);
3241 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3242 caplen);
3243 txcmd = (void *)((u8 *)txcmd->data + caplen);
3244 }
3245
0cd1ad2d 3246 ptr = iwl_txq_dec_wrap(trans, ptr);
4d075007 3247 }
520f03ea 3248 spin_unlock_bh(&cmdq->lock);
4d075007 3249
520f03ea
SM		 3250 data->len = cpu_to_le32(len);
3251 len += sizeof(*data);
3252 data = iwl_fw_error_next_data(data);
4d075007 3253 }
67c65f2c 3254
79f033f6 3255 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
520f03ea 3256 len += iwl_trans_pcie_dump_csr(trans, &data);
79f033f6 3257 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
520f03ea 3258 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 3259 if (dump_rbs)
3260 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 3261
5538409b 3262 /* Paged memory for gen2 HW */
286ca8eb 3263 if (trans->trans_cfg->gen2 &&
79b6c8fe 3264 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
505a00c0 3265 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
5538409b 3266 struct iwl_fw_error_dump_paging *paging;
505a00c0 3267 u32 page_len = trans->init_dram.paging[i].size;
5538409b
LK		 3268
3269 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3270 data->len = cpu_to_le32(sizeof(*paging) + page_len);
3271 paging = (void *)data->data;
3272 paging->index = cpu_to_le32(i);
5538409b 3273 memcpy(paging->data,
505a00c0 3274 trans->init_dram.paging[i].block, page_len);
5538409b
LK		 3275 data = iwl_fw_error_next_data(data);
3276
3277 len += sizeof(*data) + sizeof(*paging) + page_len;
3278 }
3279 }
79f033f6 3280 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
520f03ea 3281 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 3282
48eb7b34
EG		 3283 dump_data->len = len;
3284
3285 return dump_data;
4d075007 3286}
87e5666c 3287
4cbb8e50
LC		 3288#ifdef CONFIG_PM_SLEEP
3289static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3290{
4cbb8e50
LC		 3291 return 0;
3292}
3293
3294static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3295{
4cbb8e50
LC		 3296}
3297#endif /* CONFIG_PM_SLEEP */
3298
623e7766
SS		 3299#define IWL_TRANS_COMMON_OPS \
3300 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3301 .write8 = iwl_trans_pcie_write8, \
3302 .write32 = iwl_trans_pcie_write32, \
3303 .read32 = iwl_trans_pcie_read32, \
3304 .read_prph = iwl_trans_pcie_read_prph, \
3305 .write_prph = iwl_trans_pcie_write_prph, \
3306 .read_mem = iwl_trans_pcie_read_mem, \
3307 .write_mem = iwl_trans_pcie_write_mem, \
7f1fe1d4 3308 .read_config32 = iwl_trans_pcie_read_config32, \
623e7766
SS		 3309 .configure = iwl_trans_pcie_configure, \
3310 .set_pmi = iwl_trans_pcie_set_pmi, \
870c2a11 3311 .sw_reset = iwl_trans_pcie_sw_reset, \
623e7766
SS		 3312 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3313 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3314 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
623e7766 3315 .dump_data = iwl_trans_pcie_dump_data, \
623e7766 3316 .d3_suspend = iwl_trans_pcie_d3_suspend, \
d1967ce6
SM		 3317 .d3_resume = iwl_trans_pcie_d3_resume, \
3318 .sync_nmi = iwl_trans_pcie_sync_nmi
623e7766
SS		 3319
3320#ifdef CONFIG_PM_SLEEP
3321#define IWL_TRANS_PM_OPS \
3322 .suspend = iwl_trans_pcie_suspend, \
3323 .resume = iwl_trans_pcie_resume,
3324#else
3325#define IWL_TRANS_PM_OPS
3326#endif /* CONFIG_PM_SLEEP */
3327
d1ff5253 3328static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 3329 IWL_TRANS_COMMON_OPS,
3330 IWL_TRANS_PM_OPS
57a1dc89 3331 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 3332 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 3333 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 3334 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 3335
623e7766 3336 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 3337
623e7766 3338 .tx = iwl_trans_pcie_tx,
a4450980 3339 .reclaim = iwl_txq_reclaim,
623e7766
SS		 3340
3341 .txq_disable = iwl_trans_pcie_txq_disable,
3342 .txq_enable = iwl_trans_pcie_txq_enable,
3343
3344 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3345
d6d517b7
SS		 3346 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3347
a4450980 3348 .freeze_txq_timer = iwl_trans_txq_freeze_timer,
623e7766 3349 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
f7805b33
LC		 3350#ifdef CONFIG_IWLWIFI_DEBUGFS
3351 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3352#endif
623e7766
SS		 3353};
3354
3355static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3356 IWL_TRANS_COMMON_OPS,
3357 IWL_TRANS_PM_OPS
3358 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 3359 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3360 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 3361 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 3362
ca60da2e 3363 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 3364
0cd1ad2d 3365 .tx = iwl_txq_gen2_tx,
a4450980 3366 .reclaim = iwl_txq_reclaim,
34c1b7ba 3367
a4450980 3368 .set_q_ptrs = iwl_txq_set_q_ptrs,
ba7136f3 3369
0cd1ad2d
MG		 3370 .txq_alloc = iwl_txq_dyn_alloc,
3371 .txq_free = iwl_txq_dyn_free,
d6d517b7 3372 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
92536c96 3373 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
6654cd4e 3374 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
f7805b33
LC		 3375#ifdef CONFIG_IWLWIFI_DEBUGFS
3376 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3377#endif
e6bb4c9c 3378};
a42a1844 3379
87ce05a2 3380struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
7e8258c0
LC		 3381 const struct pci_device_id *ent,
3382 const struct iwl_cfg_trans_params *cfg_trans)
a42a1844 3383{
a42a1844
EG		 3384 struct iwl_trans_pcie *trans_pcie;
3385 struct iwl_trans *trans;
fda1bd0d 3386 int ret, addr_size;
a89c72ff
JB		 3387 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3388
fda1bd0d 3389 if (!cfg_trans->gen2)
a89c72ff 3390 ops = &trans_ops_pcie;
a42a1844 3391
5a41a86c
SD		 3392 ret = pcim_enable_device(pdev);
3393 if (ret)
3394 return ERR_PTR(ret);
3395
a89c72ff 3396 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
fda1bd0d 3397 cfg_trans);
7b501d10
JB		 3398 if (!trans)
3399 return ERR_PTR(-ENOMEM);
a42a1844
EG		 3400
3401 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3402
a42a1844 3403 trans_pcie->trans = trans;
326477e4 3404 trans_pcie->opmode_down = true;
7b11488f 3405 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 3406 spin_lock_init(&trans_pcie->reg_lock);
cfdc20ef 3407 spin_lock_init(&trans_pcie->alloc_page_lock);
fa9f3281 3408 mutex_init(&trans_pcie->mutex);
13df1aab 3409 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
906d4eb8 3410 init_waitqueue_head(&trans_pcie->fw_reset_waitq);
8188a18e
JB		 3411
3412 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3413 WQ_HIGHPRI | WQ_UNBOUND, 1);
3414 if (!trans_pcie->rba.alloc_wq) {
3415 ret = -ENOMEM;
3416 goto out_free_trans;
3417 }
3418 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3419
c5bf4fa1 3420 trans_pcie->debug_rfkill = -1;
d819c6cf 3421
7e8258c0 3422 if (!cfg_trans->base_params->pcie_l1_allowed) {
f2532b04
EG		 3423 /*
3424 * W/A - seems to solve weird behavior. We need to remove this
3425 * if we don't want to stay in L1 all the time. This wastes a
3426 * lot of power.
3427 */
3428 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3429 PCIE_LINK_STATE_L1 |
3430 PCIE_LINK_STATE_CLKPM);
3431 }
a42a1844 3432
9416560e
GBA		 3433 trans_pcie->def_rx_queue = 0;
3434
a42a1844
EG		 3435 pci_set_master(pdev);
3436
885375d0 3437 addr_size = trans->txqs.tfd.addr_size;
96a6497b 3438 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 3439 if (!ret)
96a6497b
SS		 3440 ret = pci_set_consistent_dma_mask(pdev,
3441 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 3442 if (ret) {
3443 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3444 if (!ret)
3445 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 3446 DMA_BIT_MASK(32));
a42a1844 3447 /* both attempts failed: */
af3f2f74 3448 if (ret) {
6a4b09f8 3449 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 3450 goto out_no_pci;
a42a1844
EG		 3451 }
3452 }
3453
5a41a86c 3454 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 3455 if (ret) {
5a41a86c
SD		 3456 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3457 goto out_no_pci;
a42a1844
EG		 3458 }
3459
5a41a86c 3460 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3461 if (!trans_pcie->hw_base) {
5a41a86c 3462 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3463 ret = -ENODEV;
5a41a86c 3464 goto out_no_pci;
a42a1844
EG		 3465 }
3466
a42a1844
EG		 3467 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3468 * PCI Tx retries from interfering with C3 CPU state */
3469 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3470
83f7a85f
EG		 3471 trans_pcie->pci_dev = pdev;
3472 iwl_disable_interrupts(trans);
3473
08079a49 3474 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
9a098a89
RJ		 3475 if (trans->hw_rev == 0xffffffff) {
3476 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3477 ret = -EIO;
3478 goto out_no_pci;
3479 }
3480
b513ee7f
LK		 3481 /*
3482 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3483 * changed, and now the revision step also includes bit 0-1 (no more
3484 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3485 * in the old format.
3486 */
4adfaf9b 3487 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000)
b513ee7f 3488 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3489 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3490
99be6166
LC		 3491 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3492
7e8258c0 3493 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
99673ee5 3494 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3495 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3496 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3497
69a10b29 3498 /* Initialize the wait queue for commands */
f946b529 3499 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3500
e5f3f215
HD		 3501 init_waitqueue_head(&trans_pcie->sx_waitq);
3502
c239feec 3503
2e5d4a8f 3504 if (trans_pcie->msix_enabled) {
2388bd7b
DC		 3505 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3506 if (ret)
5a41a86c 3507 goto out_no_pci;
2e5d4a8f
HD		 3508 } else {
3509 ret = iwl_pcie_alloc_ict(trans);
3510 if (ret)
5a41a86c 3511 goto out_no_pci;
a8b691e6 3512
5a41a86c
SD		 3513 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3514 iwl_pcie_isr,
3515 iwl_pcie_irq_handler,
3516 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3517 if (ret) {
3518 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3519 goto out_free_ict;
3520 }
2e5d4a8f 3521 }
83f7a85f 3522
f7805b33
LC		 3523#ifdef CONFIG_IWLWIFI_DEBUGFS
3524 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3525 mutex_init(&trans_pcie->fw_mon_data.mutex);
3526#endif
3527
a9248de4
SM		 3528 iwl_dbg_tlv_init(trans);
3529
a42a1844
EG		 3530 return trans;
3531
a8b691e6
JB		 3532out_free_ict:
3533 iwl_pcie_free_ict(trans);
a42a1844 3534out_no_pci:
8188a18e
JB		 3535 destroy_workqueue(trans_pcie->rba.alloc_wq);
3536out_free_trans:
7b501d10 3537 iwl_trans_free(trans);
af3f2f74 3538 return ERR_PTR(ret);
a42a1844 3539}
b8a7547d 3540
d1967ce6 3541void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
b8a7547d 3542{
1c6bca6d 3543 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
b8a7547d 3544 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
e4eee943 3545 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
1c6bca6d
SM		 3546 u32 inta_addr, sw_err_bit;
3547
3548 if (trans_pcie->msix_enabled) {
3549 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3550 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3551 } else {
3552 inta_addr = CSR_INT;
3553 sw_err_bit = CSR_INT_BIT_SW_ERR;
3554 }
b8a7547d 3555
e4eee943
SM		 3556 /* if the interrupts were already disabled, there is no point in
3557 * calling iwl_disable_interrupts
3558 */
3559 if (interrupts_enabled)
3560 iwl_disable_interrupts(trans);
3561
b8a7547d
SM		 3562 iwl_force_nmi(trans);
3563 while (time_after(timeout, jiffies)) {
1c6bca6d 3564 u32 inta_hw = iwl_read32(trans, inta_addr);
b8a7547d
SM		 3565
3566 /* Error detected by uCode */
1c6bca6d 3567 if (inta_hw & sw_err_bit) {
b8a7547d 3568 /* Clear causes register */
1c6bca6d 3569 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
b8a7547d
SM		 3570 break;
3571 }
3572
3573 mdelay(1);
3574 }
e4eee943
SM		 3575
3576 /* enable interrupts only if there were already enabled before this
3577 * function to avoid a case were the driver enable interrupts before
3578 * proper configurations were made
3579 */
3580 if (interrupts_enabled)
3581 iwl_enable_interrupts(trans);
3582
b8a7547d
SM		 3583 iwl_trans_fw_error(trans);
3584}
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