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95ea3627 | 1 | /* |
9c9a0d14 | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
a05b8c58 | 16 | along with this program; if not, see <http://www.gnu.org/licenses/>. |
95ea3627 ID |
17 | */ |
18 | ||
19 | /* | |
20 | Module: rt2400pci | |
21 | Abstract: rt2400pci device specific routines. | |
22 | Supported chipsets: RT2460. | |
23 | */ | |
24 | ||
95ea3627 ID |
25 | #include <linux/delay.h> |
26 | #include <linux/etherdevice.h> | |
95ea3627 ID |
27 | #include <linux/kernel.h> |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/eeprom_93cx6.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
95ea3627 ID |
32 | |
33 | #include "rt2x00.h" | |
69a2bac8 | 34 | #include "rt2x00mmio.h" |
95ea3627 ID |
35 | #include "rt2x00pci.h" |
36 | #include "rt2400pci.h" | |
37 | ||
38 | /* | |
39 | * Register access. | |
40 | * All access to the CSR registers will go through the methods | |
172c5911 | 41 | * rt2x00mmio_register_read and rt2x00mmio_register_write. |
95ea3627 ID |
42 | * BBP and RF register require indirect register access, |
43 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
44 | * These indirect registers work with busy bits, | |
45 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
46 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
f5a9987d | 47 | * between each attempt. When the busy bit is still set at that time, |
95ea3627 ID |
48 | * the access attempt is considered to have failed, |
49 | * and we will print an error. | |
50 | */ | |
c9c3b1a5 | 51 | #define WAIT_FOR_BBP(__dev, __reg) \ |
172c5911 | 52 | rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg)) |
c9c3b1a5 | 53 | #define WAIT_FOR_RF(__dev, __reg) \ |
172c5911 | 54 | rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg)) |
95ea3627 | 55 | |
0e14f6d3 | 56 | static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
57 | const unsigned int word, const u8 value) |
58 | { | |
59 | u32 reg; | |
60 | ||
8ff48a8b ID |
61 | mutex_lock(&rt2x00dev->csr_mutex); |
62 | ||
95ea3627 | 63 | /* |
c9c3b1a5 ID |
64 | * Wait until the BBP becomes available, afterwards we |
65 | * can safely write the new data into the register. | |
95ea3627 | 66 | */ |
c9c3b1a5 ID |
67 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
68 | reg = 0; | |
69 | rt2x00_set_field32(®, BBPCSR_VALUE, value); | |
70 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); | |
71 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); | |
72 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); | |
73 | ||
172c5911 | 74 | rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); |
c9c3b1a5 | 75 | } |
8ff48a8b | 76 | |
8ff48a8b | 77 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
78 | } |
79 | ||
0e14f6d3 | 80 | static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
81 | const unsigned int word, u8 *value) |
82 | { | |
83 | u32 reg; | |
84 | ||
8ff48a8b ID |
85 | mutex_lock(&rt2x00dev->csr_mutex); |
86 | ||
95ea3627 | 87 | /* |
c9c3b1a5 ID |
88 | * Wait until the BBP becomes available, afterwards we |
89 | * can safely write the read request into the register. | |
90 | * After the data has been written, we wait until hardware | |
91 | * returns the correct value, if at any time the register | |
92 | * doesn't become available in time, reg will be 0xffffffff | |
93 | * which means we return 0xff to the caller. | |
95ea3627 | 94 | */ |
c9c3b1a5 ID |
95 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
96 | reg = 0; | |
97 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); | |
98 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); | |
99 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); | |
95ea3627 | 100 | |
172c5911 | 101 | rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); |
95ea3627 | 102 | |
c9c3b1a5 ID |
103 | WAIT_FOR_BBP(rt2x00dev, ®); |
104 | } | |
95ea3627 ID |
105 | |
106 | *value = rt2x00_get_field32(reg, BBPCSR_VALUE); | |
8ff48a8b ID |
107 | |
108 | mutex_unlock(&rt2x00dev->csr_mutex); | |
95ea3627 ID |
109 | } |
110 | ||
0e14f6d3 | 111 | static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
112 | const unsigned int word, const u32 value) |
113 | { | |
114 | u32 reg; | |
95ea3627 | 115 | |
8ff48a8b ID |
116 | mutex_lock(&rt2x00dev->csr_mutex); |
117 | ||
c9c3b1a5 ID |
118 | /* |
119 | * Wait until the RF becomes available, afterwards we | |
120 | * can safely write the new data into the register. | |
121 | */ | |
122 | if (WAIT_FOR_RF(rt2x00dev, ®)) { | |
123 | reg = 0; | |
124 | rt2x00_set_field32(®, RFCSR_VALUE, value); | |
125 | rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); | |
126 | rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); | |
127 | rt2x00_set_field32(®, RFCSR_BUSY, 1); | |
128 | ||
172c5911 | 129 | rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); |
c9c3b1a5 | 130 | rt2x00_rf_write(rt2x00dev, word, value); |
95ea3627 ID |
131 | } |
132 | ||
8ff48a8b | 133 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
134 | } |
135 | ||
136 | static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom) | |
137 | { | |
138 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
139 | u32 reg; | |
140 | ||
172c5911 | 141 | rt2x00mmio_register_read(rt2x00dev, CSR21, ®); |
95ea3627 ID |
142 | |
143 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); | |
144 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); | |
145 | eeprom->reg_data_clock = | |
146 | !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); | |
147 | eeprom->reg_chip_select = | |
148 | !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); | |
149 | } | |
150 | ||
151 | static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom) | |
152 | { | |
153 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
154 | u32 reg = 0; | |
155 | ||
156 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); | |
157 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); | |
158 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, | |
159 | !!eeprom->reg_data_clock); | |
160 | rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, | |
161 | !!eeprom->reg_chip_select); | |
162 | ||
172c5911 | 163 | rt2x00mmio_register_write(rt2x00dev, CSR21, reg); |
95ea3627 ID |
164 | } |
165 | ||
166 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
95ea3627 ID |
167 | static const struct rt2x00debug rt2400pci_rt2x00debug = { |
168 | .owner = THIS_MODULE, | |
169 | .csr = { | |
172c5911 GJ |
170 | .read = rt2x00mmio_register_read, |
171 | .write = rt2x00mmio_register_write, | |
743b97ca ID |
172 | .flags = RT2X00DEBUGFS_OFFSET, |
173 | .word_base = CSR_REG_BASE, | |
95ea3627 ID |
174 | .word_size = sizeof(u32), |
175 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
176 | }, | |
177 | .eeprom = { | |
178 | .read = rt2x00_eeprom_read, | |
179 | .write = rt2x00_eeprom_write, | |
743b97ca | 180 | .word_base = EEPROM_BASE, |
95ea3627 ID |
181 | .word_size = sizeof(u16), |
182 | .word_count = EEPROM_SIZE / sizeof(u16), | |
183 | }, | |
184 | .bbp = { | |
185 | .read = rt2400pci_bbp_read, | |
186 | .write = rt2400pci_bbp_write, | |
743b97ca | 187 | .word_base = BBP_BASE, |
95ea3627 ID |
188 | .word_size = sizeof(u8), |
189 | .word_count = BBP_SIZE / sizeof(u8), | |
190 | }, | |
191 | .rf = { | |
192 | .read = rt2x00_rf_read, | |
193 | .write = rt2400pci_rf_write, | |
743b97ca | 194 | .word_base = RF_BASE, |
95ea3627 ID |
195 | .word_size = sizeof(u32), |
196 | .word_count = RF_SIZE / sizeof(u32), | |
197 | }, | |
198 | }; | |
199 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
200 | ||
95ea3627 ID |
201 | static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
202 | { | |
203 | u32 reg; | |
204 | ||
172c5911 | 205 | rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); |
99bdf51a | 206 | return rt2x00_get_field32(reg, GPIOCSR_VAL0); |
95ea3627 | 207 | } |
95ea3627 | 208 | |
771fd565 | 209 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a2e1d52a | 210 | static void rt2400pci_brightness_set(struct led_classdev *led_cdev, |
a9450b70 ID |
211 | enum led_brightness brightness) |
212 | { | |
213 | struct rt2x00_led *led = | |
214 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
215 | unsigned int enabled = brightness != LED_OFF; | |
a9450b70 ID |
216 | u32 reg; |
217 | ||
172c5911 | 218 | rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); |
a9450b70 | 219 | |
a2e1d52a | 220 | if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) |
a9450b70 | 221 | rt2x00_set_field32(®, LEDCSR_LINK, enabled); |
a2e1d52a ID |
222 | else if (led->type == LED_TYPE_ACTIVITY) |
223 | rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); | |
a9450b70 | 224 | |
172c5911 | 225 | rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); |
a9450b70 | 226 | } |
a2e1d52a ID |
227 | |
228 | static int rt2400pci_blink_set(struct led_classdev *led_cdev, | |
229 | unsigned long *delay_on, | |
230 | unsigned long *delay_off) | |
231 | { | |
232 | struct rt2x00_led *led = | |
233 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
234 | u32 reg; | |
235 | ||
172c5911 | 236 | rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); |
a2e1d52a ID |
237 | rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); |
238 | rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); | |
172c5911 | 239 | rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); |
a2e1d52a ID |
240 | |
241 | return 0; | |
242 | } | |
475433be ID |
243 | |
244 | static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev, | |
245 | struct rt2x00_led *led, | |
246 | enum led_type type) | |
247 | { | |
248 | led->rt2x00dev = rt2x00dev; | |
249 | led->type = type; | |
250 | led->led_dev.brightness_set = rt2400pci_brightness_set; | |
251 | led->led_dev.blink_set = rt2400pci_blink_set; | |
252 | led->flags = LED_INITIALIZED; | |
253 | } | |
771fd565 | 254 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
a9450b70 | 255 | |
95ea3627 ID |
256 | /* |
257 | * Configuration handlers. | |
258 | */ | |
3a643d24 ID |
259 | static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev, |
260 | const unsigned int filter_flags) | |
261 | { | |
262 | u32 reg; | |
263 | ||
264 | /* | |
265 | * Start configuration steps. | |
266 | * Note that the version error will always be dropped | |
267 | * since there is no filter for it at this time. | |
268 | */ | |
172c5911 | 269 | rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); |
3a643d24 ID |
270 | rt2x00_set_field32(®, RXCSR0_DROP_CRC, |
271 | !(filter_flags & FIF_FCSFAIL)); | |
272 | rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, | |
273 | !(filter_flags & FIF_PLCPFAIL)); | |
274 | rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, | |
275 | !(filter_flags & FIF_CONTROL)); | |
df140465 | 276 | rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, 1); |
3a643d24 | 277 | rt2x00_set_field32(®, RXCSR0_DROP_TODS, |
e0b005fa | 278 | !rt2x00dev->intf_ap_count); |
3a643d24 | 279 | rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); |
172c5911 | 280 | rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); |
3a643d24 ID |
281 | } |
282 | ||
6bb40dd1 ID |
283 | static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev, |
284 | struct rt2x00_intf *intf, | |
285 | struct rt2x00intf_conf *conf, | |
286 | const unsigned int flags) | |
95ea3627 | 287 | { |
6bb40dd1 ID |
288 | unsigned int bcn_preload; |
289 | u32 reg; | |
95ea3627 | 290 | |
6bb40dd1 | 291 | if (flags & CONFIG_UPDATE_TYPE) { |
6bb40dd1 ID |
292 | /* |
293 | * Enable beacon config | |
294 | */ | |
bad13639 | 295 | bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20); |
172c5911 | 296 | rt2x00mmio_register_read(rt2x00dev, BCNCSR1, ®); |
6bb40dd1 | 297 | rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); |
172c5911 | 298 | rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); |
95ea3627 | 299 | |
6bb40dd1 ID |
300 | /* |
301 | * Enable synchronisation. | |
302 | */ | |
172c5911 | 303 | rt2x00mmio_register_read(rt2x00dev, CSR14, ®); |
6bb40dd1 | 304 | rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); |
172c5911 | 305 | rt2x00mmio_register_write(rt2x00dev, CSR14, reg); |
6bb40dd1 | 306 | } |
95ea3627 | 307 | |
6bb40dd1 | 308 | if (flags & CONFIG_UPDATE_MAC) |
172c5911 GJ |
309 | rt2x00mmio_register_multiwrite(rt2x00dev, CSR3, |
310 | conf->mac, sizeof(conf->mac)); | |
95ea3627 | 311 | |
6bb40dd1 | 312 | if (flags & CONFIG_UPDATE_BSSID) |
172c5911 GJ |
313 | rt2x00mmio_register_multiwrite(rt2x00dev, CSR5, |
314 | conf->bssid, | |
315 | sizeof(conf->bssid)); | |
95ea3627 ID |
316 | } |
317 | ||
3a643d24 | 318 | static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, |
02044643 HS |
319 | struct rt2x00lib_erp *erp, |
320 | u32 changed) | |
95ea3627 | 321 | { |
5c58ee51 | 322 | int preamble_mask; |
95ea3627 | 323 | u32 reg; |
95ea3627 | 324 | |
5c58ee51 ID |
325 | /* |
326 | * When short preamble is enabled, we should set bit 0x08 | |
327 | */ | |
02044643 HS |
328 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
329 | preamble_mask = erp->short_preamble << 3; | |
330 | ||
172c5911 | 331 | rt2x00mmio_register_read(rt2x00dev, TXCSR1, ®); |
02044643 HS |
332 | rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff); |
333 | rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a); | |
334 | rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); | |
335 | rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); | |
172c5911 | 336 | rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); |
02044643 | 337 | |
172c5911 | 338 | rt2x00mmio_register_read(rt2x00dev, ARCSR2, ®); |
02044643 HS |
339 | rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); |
340 | rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); | |
341 | rt2x00_set_field32(®, ARCSR2_LENGTH, | |
342 | GET_DURATION(ACK_SIZE, 10)); | |
172c5911 | 343 | rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); |
02044643 | 344 | |
172c5911 | 345 | rt2x00mmio_register_read(rt2x00dev, ARCSR3, ®); |
02044643 HS |
346 | rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); |
347 | rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); | |
348 | rt2x00_set_field32(®, ARCSR2_LENGTH, | |
349 | GET_DURATION(ACK_SIZE, 20)); | |
172c5911 | 350 | rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); |
02044643 | 351 | |
172c5911 | 352 | rt2x00mmio_register_read(rt2x00dev, ARCSR4, ®); |
02044643 HS |
353 | rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); |
354 | rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); | |
355 | rt2x00_set_field32(®, ARCSR2_LENGTH, | |
356 | GET_DURATION(ACK_SIZE, 55)); | |
172c5911 | 357 | rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); |
02044643 | 358 | |
172c5911 | 359 | rt2x00mmio_register_read(rt2x00dev, ARCSR5, ®); |
02044643 HS |
360 | rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); |
361 | rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); | |
362 | rt2x00_set_field32(®, ARCSR2_LENGTH, | |
363 | GET_DURATION(ACK_SIZE, 110)); | |
172c5911 | 364 | rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); |
02044643 HS |
365 | } |
366 | ||
367 | if (changed & BSS_CHANGED_BASIC_RATES) | |
172c5911 | 368 | rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates); |
02044643 HS |
369 | |
370 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
172c5911 | 371 | rt2x00mmio_register_read(rt2x00dev, CSR11, ®); |
02044643 | 372 | rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); |
172c5911 | 373 | rt2x00mmio_register_write(rt2x00dev, CSR11, reg); |
02044643 | 374 | |
172c5911 | 375 | rt2x00mmio_register_read(rt2x00dev, CSR18, ®); |
02044643 HS |
376 | rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); |
377 | rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); | |
172c5911 | 378 | rt2x00mmio_register_write(rt2x00dev, CSR18, reg); |
02044643 | 379 | |
172c5911 | 380 | rt2x00mmio_register_read(rt2x00dev, CSR19, ®); |
02044643 HS |
381 | rt2x00_set_field32(®, CSR19_DIFS, erp->difs); |
382 | rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); | |
172c5911 | 383 | rt2x00mmio_register_write(rt2x00dev, CSR19, reg); |
02044643 HS |
384 | } |
385 | ||
386 | if (changed & BSS_CHANGED_BEACON_INT) { | |
172c5911 | 387 | rt2x00mmio_register_read(rt2x00dev, CSR12, ®); |
02044643 HS |
388 | rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, |
389 | erp->beacon_int * 16); | |
390 | rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, | |
391 | erp->beacon_int * 16); | |
172c5911 | 392 | rt2x00mmio_register_write(rt2x00dev, CSR12, reg); |
02044643 | 393 | } |
95ea3627 ID |
394 | } |
395 | ||
e4ea1c40 ID |
396 | static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev, |
397 | struct antenna_setup *ant) | |
95ea3627 | 398 | { |
e4ea1c40 ID |
399 | u8 r1; |
400 | u8 r4; | |
401 | ||
402 | /* | |
403 | * We should never come here because rt2x00lib is supposed | |
404 | * to catch this and send us the correct antenna explicitely. | |
405 | */ | |
406 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || | |
407 | ant->tx == ANTENNA_SW_DIVERSITY); | |
408 | ||
409 | rt2400pci_bbp_read(rt2x00dev, 4, &r4); | |
410 | rt2400pci_bbp_read(rt2x00dev, 1, &r1); | |
411 | ||
412 | /* | |
413 | * Configure the TX antenna. | |
414 | */ | |
415 | switch (ant->tx) { | |
416 | case ANTENNA_HW_DIVERSITY: | |
417 | rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1); | |
418 | break; | |
419 | case ANTENNA_A: | |
420 | rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0); | |
421 | break; | |
422 | case ANTENNA_B: | |
423 | default: | |
424 | rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2); | |
425 | break; | |
426 | } | |
427 | ||
428 | /* | |
429 | * Configure the RX antenna. | |
430 | */ | |
431 | switch (ant->rx) { | |
432 | case ANTENNA_HW_DIVERSITY: | |
433 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1); | |
434 | break; | |
435 | case ANTENNA_A: | |
436 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0); | |
437 | break; | |
438 | case ANTENNA_B: | |
439 | default: | |
440 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2); | |
441 | break; | |
442 | } | |
443 | ||
444 | rt2400pci_bbp_write(rt2x00dev, 4, r4); | |
445 | rt2400pci_bbp_write(rt2x00dev, 1, r1); | |
95ea3627 ID |
446 | } |
447 | ||
448 | static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev, | |
5c58ee51 | 449 | struct rf_channel *rf) |
95ea3627 | 450 | { |
95ea3627 ID |
451 | /* |
452 | * Switch on tuning bits. | |
453 | */ | |
5c58ee51 ID |
454 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); |
455 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); | |
95ea3627 | 456 | |
5c58ee51 ID |
457 | rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); |
458 | rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); | |
459 | rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); | |
95ea3627 ID |
460 | |
461 | /* | |
462 | * RF2420 chipset don't need any additional actions. | |
463 | */ | |
5122d898 | 464 | if (rt2x00_rf(rt2x00dev, RF2420)) |
95ea3627 ID |
465 | return; |
466 | ||
467 | /* | |
468 | * For the RT2421 chipsets we need to write an invalid | |
469 | * reference clock rate to activate auto_tune. | |
470 | * After that we set the value back to the correct channel. | |
471 | */ | |
5c58ee51 | 472 | rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); |
95ea3627 | 473 | rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32); |
5c58ee51 | 474 | rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); |
95ea3627 ID |
475 | |
476 | msleep(1); | |
477 | ||
5c58ee51 ID |
478 | rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); |
479 | rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); | |
480 | rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); | |
95ea3627 ID |
481 | |
482 | msleep(1); | |
483 | ||
484 | /* | |
485 | * Switch off tuning bits. | |
486 | */ | |
5c58ee51 ID |
487 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); |
488 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); | |
95ea3627 | 489 | |
5c58ee51 ID |
490 | rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); |
491 | rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); | |
95ea3627 ID |
492 | |
493 | /* | |
494 | * Clear false CRC during channel switch. | |
495 | */ | |
172c5911 | 496 | rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1); |
95ea3627 ID |
497 | } |
498 | ||
499 | static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower) | |
500 | { | |
501 | rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower)); | |
502 | } | |
503 | ||
e4ea1c40 ID |
504 | static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
505 | struct rt2x00lib_conf *libconf) | |
95ea3627 | 506 | { |
e4ea1c40 | 507 | u32 reg; |
95ea3627 | 508 | |
172c5911 | 509 | rt2x00mmio_register_read(rt2x00dev, CSR11, ®); |
e4ea1c40 ID |
510 | rt2x00_set_field32(®, CSR11_LONG_RETRY, |
511 | libconf->conf->long_frame_max_tx_count); | |
512 | rt2x00_set_field32(®, CSR11_SHORT_RETRY, | |
513 | libconf->conf->short_frame_max_tx_count); | |
172c5911 | 514 | rt2x00mmio_register_write(rt2x00dev, CSR11, reg); |
95ea3627 ID |
515 | } |
516 | ||
7d7f19cc ID |
517 | static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev, |
518 | struct rt2x00lib_conf *libconf) | |
519 | { | |
520 | enum dev_state state = | |
521 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
522 | STATE_SLEEP : STATE_AWAKE; | |
523 | u32 reg; | |
524 | ||
525 | if (state == STATE_SLEEP) { | |
172c5911 | 526 | rt2x00mmio_register_read(rt2x00dev, CSR20, ®); |
7d7f19cc | 527 | rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, |
6b347bff | 528 | (rt2x00dev->beacon_int - 20) * 16); |
7d7f19cc ID |
529 | rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, |
530 | libconf->conf->listen_interval - 1); | |
531 | ||
532 | /* We must first disable autowake before it can be enabled */ | |
533 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); | |
172c5911 | 534 | rt2x00mmio_register_write(rt2x00dev, CSR20, reg); |
7d7f19cc ID |
535 | |
536 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); | |
172c5911 | 537 | rt2x00mmio_register_write(rt2x00dev, CSR20, reg); |
5731858d | 538 | } else { |
172c5911 | 539 | rt2x00mmio_register_read(rt2x00dev, CSR20, ®); |
5731858d | 540 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); |
172c5911 | 541 | rt2x00mmio_register_write(rt2x00dev, CSR20, reg); |
7d7f19cc ID |
542 | } |
543 | ||
544 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
545 | } | |
546 | ||
95ea3627 | 547 | static void rt2400pci_config(struct rt2x00_dev *rt2x00dev, |
6bb40dd1 ID |
548 | struct rt2x00lib_conf *libconf, |
549 | const unsigned int flags) | |
95ea3627 | 550 | { |
e4ea1c40 | 551 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
5c58ee51 | 552 | rt2400pci_config_channel(rt2x00dev, &libconf->rf); |
e4ea1c40 | 553 | if (flags & IEEE80211_CONF_CHANGE_POWER) |
5c58ee51 ID |
554 | rt2400pci_config_txpower(rt2x00dev, |
555 | libconf->conf->power_level); | |
e4ea1c40 ID |
556 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
557 | rt2400pci_config_retry_limit(rt2x00dev, libconf); | |
7d7f19cc ID |
558 | if (flags & IEEE80211_CONF_CHANGE_PS) |
559 | rt2400pci_config_ps(rt2x00dev, libconf); | |
95ea3627 ID |
560 | } |
561 | ||
562 | static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, | |
181d6902 | 563 | const int cw_min, const int cw_max) |
95ea3627 ID |
564 | { |
565 | u32 reg; | |
566 | ||
172c5911 | 567 | rt2x00mmio_register_read(rt2x00dev, CSR11, ®); |
181d6902 ID |
568 | rt2x00_set_field32(®, CSR11_CWMIN, cw_min); |
569 | rt2x00_set_field32(®, CSR11_CWMAX, cw_max); | |
172c5911 | 570 | rt2x00mmio_register_write(rt2x00dev, CSR11, reg); |
95ea3627 ID |
571 | } |
572 | ||
95ea3627 ID |
573 | /* |
574 | * Link tuning | |
575 | */ | |
ebcf26da ID |
576 | static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev, |
577 | struct link_qual *qual) | |
95ea3627 ID |
578 | { |
579 | u32 reg; | |
580 | u8 bbp; | |
581 | ||
582 | /* | |
583 | * Update FCS error count from register. | |
584 | */ | |
172c5911 | 585 | rt2x00mmio_register_read(rt2x00dev, CNT0, ®); |
ebcf26da | 586 | qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); |
95ea3627 ID |
587 | |
588 | /* | |
589 | * Update False CCA count from register. | |
590 | */ | |
591 | rt2400pci_bbp_read(rt2x00dev, 39, &bbp); | |
ebcf26da | 592 | qual->false_cca = bbp; |
95ea3627 ID |
593 | } |
594 | ||
5352ff65 ID |
595 | static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev, |
596 | struct link_qual *qual, u8 vgc_level) | |
eb20b4e8 | 597 | { |
223dcc26 ID |
598 | if (qual->vgc_level_reg != vgc_level) { |
599 | rt2400pci_bbp_write(rt2x00dev, 13, vgc_level); | |
600 | qual->vgc_level = vgc_level; | |
601 | qual->vgc_level_reg = vgc_level; | |
602 | } | |
eb20b4e8 ID |
603 | } |
604 | ||
5352ff65 ID |
605 | static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev, |
606 | struct link_qual *qual) | |
95ea3627 | 607 | { |
5352ff65 | 608 | rt2400pci_set_vgc(rt2x00dev, qual, 0x08); |
95ea3627 ID |
609 | } |
610 | ||
5352ff65 ID |
611 | static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev, |
612 | struct link_qual *qual, const u32 count) | |
95ea3627 | 613 | { |
95ea3627 ID |
614 | /* |
615 | * The link tuner should not run longer then 60 seconds, | |
616 | * and should run once every 2 seconds. | |
617 | */ | |
5352ff65 | 618 | if (count > 60 || !(count & 1)) |
95ea3627 ID |
619 | return; |
620 | ||
621 | /* | |
622 | * Base r13 link tuning on the false cca count. | |
623 | */ | |
5352ff65 ID |
624 | if ((qual->false_cca > 512) && (qual->vgc_level < 0x20)) |
625 | rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); | |
626 | else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08)) | |
627 | rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); | |
95ea3627 ID |
628 | } |
629 | ||
5450b7e2 ID |
630 | /* |
631 | * Queue handlers. | |
632 | */ | |
633 | static void rt2400pci_start_queue(struct data_queue *queue) | |
634 | { | |
635 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
636 | u32 reg; | |
637 | ||
638 | switch (queue->qid) { | |
639 | case QID_RX: | |
172c5911 | 640 | rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); |
5450b7e2 | 641 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); |
172c5911 | 642 | rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); |
5450b7e2 ID |
643 | break; |
644 | case QID_BEACON: | |
172c5911 | 645 | rt2x00mmio_register_read(rt2x00dev, CSR14, ®); |
5450b7e2 ID |
646 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); |
647 | rt2x00_set_field32(®, CSR14_TBCN, 1); | |
648 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); | |
172c5911 | 649 | rt2x00mmio_register_write(rt2x00dev, CSR14, reg); |
5450b7e2 ID |
650 | break; |
651 | default: | |
652 | break; | |
653 | } | |
654 | } | |
655 | ||
656 | static void rt2400pci_kick_queue(struct data_queue *queue) | |
657 | { | |
658 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
659 | u32 reg; | |
660 | ||
661 | switch (queue->qid) { | |
f615e9a3 | 662 | case QID_AC_VO: |
172c5911 | 663 | rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); |
5450b7e2 | 664 | rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); |
172c5911 | 665 | rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); |
5450b7e2 | 666 | break; |
f615e9a3 | 667 | case QID_AC_VI: |
172c5911 | 668 | rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); |
5450b7e2 | 669 | rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); |
172c5911 | 670 | rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); |
5450b7e2 ID |
671 | break; |
672 | case QID_ATIM: | |
172c5911 | 673 | rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); |
5450b7e2 | 674 | rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); |
172c5911 | 675 | rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); |
5450b7e2 ID |
676 | break; |
677 | default: | |
678 | break; | |
679 | } | |
680 | } | |
681 | ||
682 | static void rt2400pci_stop_queue(struct data_queue *queue) | |
683 | { | |
684 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
685 | u32 reg; | |
686 | ||
687 | switch (queue->qid) { | |
f615e9a3 ID |
688 | case QID_AC_VO: |
689 | case QID_AC_VI: | |
5450b7e2 | 690 | case QID_ATIM: |
172c5911 | 691 | rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); |
5450b7e2 | 692 | rt2x00_set_field32(®, TXCSR0_ABORT, 1); |
172c5911 | 693 | rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); |
5450b7e2 ID |
694 | break; |
695 | case QID_RX: | |
172c5911 | 696 | rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); |
5450b7e2 | 697 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); |
172c5911 | 698 | rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); |
5450b7e2 ID |
699 | break; |
700 | case QID_BEACON: | |
172c5911 | 701 | rt2x00mmio_register_read(rt2x00dev, CSR14, ®); |
5450b7e2 ID |
702 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); |
703 | rt2x00_set_field32(®, CSR14_TBCN, 0); | |
704 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | |
172c5911 | 705 | rt2x00mmio_register_write(rt2x00dev, CSR14, reg); |
bcf3cfd0 HS |
706 | |
707 | /* | |
708 | * Wait for possibly running tbtt tasklets. | |
709 | */ | |
abc11994 | 710 | tasklet_kill(&rt2x00dev->tbtt_tasklet); |
5450b7e2 ID |
711 | break; |
712 | default: | |
713 | break; | |
714 | } | |
715 | } | |
716 | ||
95ea3627 ID |
717 | /* |
718 | * Initialization functions. | |
719 | */ | |
798b7adb | 720 | static bool rt2400pci_get_entry_state(struct queue_entry *entry) |
95ea3627 | 721 | { |
172c5911 | 722 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
95ea3627 ID |
723 | u32 word; |
724 | ||
798b7adb ID |
725 | if (entry->queue->qid == QID_RX) { |
726 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 | 727 | |
798b7adb ID |
728 | return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); |
729 | } else { | |
730 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 | 731 | |
798b7adb ID |
732 | return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
733 | rt2x00_get_field32(word, TXD_W0_VALID)); | |
734 | } | |
95ea3627 ID |
735 | } |
736 | ||
798b7adb | 737 | static void rt2400pci_clear_entry(struct queue_entry *entry) |
95ea3627 | 738 | { |
172c5911 | 739 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
798b7adb | 740 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
95ea3627 ID |
741 | u32 word; |
742 | ||
798b7adb ID |
743 | if (entry->queue->qid == QID_RX) { |
744 | rt2x00_desc_read(entry_priv->desc, 2, &word); | |
745 | rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len); | |
746 | rt2x00_desc_write(entry_priv->desc, 2, word); | |
747 | ||
748 | rt2x00_desc_read(entry_priv->desc, 1, &word); | |
749 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); | |
750 | rt2x00_desc_write(entry_priv->desc, 1, word); | |
751 | ||
752 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
753 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); | |
754 | rt2x00_desc_write(entry_priv->desc, 0, word); | |
755 | } else { | |
756 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
757 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); | |
758 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); | |
759 | rt2x00_desc_write(entry_priv->desc, 0, word); | |
760 | } | |
95ea3627 ID |
761 | } |
762 | ||
181d6902 | 763 | static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) |
95ea3627 | 764 | { |
172c5911 | 765 | struct queue_entry_priv_mmio *entry_priv; |
95ea3627 ID |
766 | u32 reg; |
767 | ||
95ea3627 ID |
768 | /* |
769 | * Initialize registers. | |
770 | */ | |
172c5911 | 771 | rt2x00mmio_register_read(rt2x00dev, TXCSR2, ®); |
181d6902 ID |
772 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); |
773 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); | |
e74df4a7 | 774 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); |
181d6902 | 775 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); |
172c5911 | 776 | rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); |
95ea3627 | 777 | |
b8be63ff | 778 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
172c5911 | 779 | rt2x00mmio_register_read(rt2x00dev, TXCSR3, ®); |
30b3a23c | 780 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, |
b8be63ff | 781 | entry_priv->desc_dma); |
172c5911 | 782 | rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); |
95ea3627 | 783 | |
b8be63ff | 784 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
172c5911 | 785 | rt2x00mmio_register_read(rt2x00dev, TXCSR5, ®); |
30b3a23c | 786 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, |
b8be63ff | 787 | entry_priv->desc_dma); |
172c5911 | 788 | rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); |
95ea3627 | 789 | |
e74df4a7 | 790 | entry_priv = rt2x00dev->atim->entries[0].priv_data; |
172c5911 | 791 | rt2x00mmio_register_read(rt2x00dev, TXCSR4, ®); |
30b3a23c | 792 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, |
b8be63ff | 793 | entry_priv->desc_dma); |
172c5911 | 794 | rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); |
95ea3627 | 795 | |
e74df4a7 | 796 | entry_priv = rt2x00dev->bcn->entries[0].priv_data; |
172c5911 | 797 | rt2x00mmio_register_read(rt2x00dev, TXCSR6, ®); |
30b3a23c | 798 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, |
b8be63ff | 799 | entry_priv->desc_dma); |
172c5911 | 800 | rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); |
95ea3627 | 801 | |
172c5911 | 802 | rt2x00mmio_register_read(rt2x00dev, RXCSR1, ®); |
95ea3627 | 803 | rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); |
181d6902 | 804 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); |
172c5911 | 805 | rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); |
95ea3627 | 806 | |
b8be63ff | 807 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
172c5911 | 808 | rt2x00mmio_register_read(rt2x00dev, RXCSR2, ®); |
b8be63ff ID |
809 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, |
810 | entry_priv->desc_dma); | |
172c5911 | 811 | rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); |
95ea3627 ID |
812 | |
813 | return 0; | |
814 | } | |
815 | ||
816 | static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) | |
817 | { | |
818 | u32 reg; | |
819 | ||
172c5911 GJ |
820 | rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002); |
821 | rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002); | |
822 | rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20); | |
823 | rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002); | |
95ea3627 | 824 | |
172c5911 | 825 | rt2x00mmio_register_read(rt2x00dev, TIMECSR, ®); |
95ea3627 ID |
826 | rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); |
827 | rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); | |
828 | rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); | |
172c5911 | 829 | rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); |
95ea3627 | 830 | |
172c5911 | 831 | rt2x00mmio_register_read(rt2x00dev, CSR9, ®); |
95ea3627 ID |
832 | rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, |
833 | (rt2x00dev->rx->data_size / 128)); | |
172c5911 | 834 | rt2x00mmio_register_write(rt2x00dev, CSR9, reg); |
95ea3627 | 835 | |
172c5911 | 836 | rt2x00mmio_register_read(rt2x00dev, CSR14, ®); |
1f909162 ID |
837 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); |
838 | rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); | |
839 | rt2x00_set_field32(®, CSR14_TBCN, 0); | |
840 | rt2x00_set_field32(®, CSR14_TCFP, 0); | |
841 | rt2x00_set_field32(®, CSR14_TATIMW, 0); | |
842 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | |
843 | rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); | |
844 | rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); | |
172c5911 | 845 | rt2x00mmio_register_write(rt2x00dev, CSR14, reg); |
1f909162 | 846 | |
172c5911 | 847 | rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000); |
95ea3627 | 848 | |
172c5911 | 849 | rt2x00mmio_register_read(rt2x00dev, ARCSR0, ®); |
95ea3627 ID |
850 | rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133); |
851 | rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134); | |
852 | rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136); | |
853 | rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135); | |
172c5911 | 854 | rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg); |
95ea3627 | 855 | |
172c5911 | 856 | rt2x00mmio_register_read(rt2x00dev, RXCSR3, ®); |
95ea3627 ID |
857 | rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/ |
858 | rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); | |
859 | rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */ | |
860 | rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); | |
861 | rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */ | |
862 | rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); | |
172c5911 | 863 | rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); |
95ea3627 | 864 | |
172c5911 | 865 | rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); |
95ea3627 ID |
866 | |
867 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
868 | return -EBUSY; | |
869 | ||
172c5911 GJ |
870 | rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223); |
871 | rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518); | |
95ea3627 | 872 | |
172c5911 | 873 | rt2x00mmio_register_read(rt2x00dev, MACCSR2, ®); |
95ea3627 | 874 | rt2x00_set_field32(®, MACCSR2_DELAY, 64); |
172c5911 | 875 | rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); |
95ea3627 | 876 | |
172c5911 | 877 | rt2x00mmio_register_read(rt2x00dev, RALINKCSR, ®); |
95ea3627 ID |
878 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); |
879 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154); | |
880 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); | |
881 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154); | |
172c5911 | 882 | rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); |
95ea3627 | 883 | |
172c5911 | 884 | rt2x00mmio_register_read(rt2x00dev, CSR1, ®); |
95ea3627 ID |
885 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); |
886 | rt2x00_set_field32(®, CSR1_BBP_RESET, 0); | |
887 | rt2x00_set_field32(®, CSR1_HOST_READY, 0); | |
172c5911 | 888 | rt2x00mmio_register_write(rt2x00dev, CSR1, reg); |
95ea3627 | 889 | |
172c5911 | 890 | rt2x00mmio_register_read(rt2x00dev, CSR1, ®); |
95ea3627 ID |
891 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); |
892 | rt2x00_set_field32(®, CSR1_HOST_READY, 1); | |
172c5911 | 893 | rt2x00mmio_register_write(rt2x00dev, CSR1, reg); |
95ea3627 ID |
894 | |
895 | /* | |
896 | * We must clear the FCS and FIFO error count. | |
897 | * These registers are cleared on read, | |
898 | * so we may pass a useless variable to store the value. | |
899 | */ | |
172c5911 GJ |
900 | rt2x00mmio_register_read(rt2x00dev, CNT0, ®); |
901 | rt2x00mmio_register_read(rt2x00dev, CNT4, ®); | |
95ea3627 ID |
902 | |
903 | return 0; | |
904 | } | |
905 | ||
2b08da3f | 906 | static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
907 | { |
908 | unsigned int i; | |
95ea3627 ID |
909 | u8 value; |
910 | ||
911 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
912 | rt2400pci_bbp_read(rt2x00dev, 0, &value); | |
913 | if ((value != 0xff) && (value != 0x00)) | |
2b08da3f | 914 | return 0; |
95ea3627 ID |
915 | udelay(REGISTER_BUSY_DELAY); |
916 | } | |
917 | ||
ec9c4989 | 918 | rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); |
95ea3627 | 919 | return -EACCES; |
2b08da3f ID |
920 | } |
921 | ||
922 | static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev) | |
923 | { | |
924 | unsigned int i; | |
925 | u16 eeprom; | |
926 | u8 reg_id; | |
927 | u8 value; | |
928 | ||
929 | if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev))) | |
930 | return -EACCES; | |
95ea3627 | 931 | |
95ea3627 ID |
932 | rt2400pci_bbp_write(rt2x00dev, 1, 0x00); |
933 | rt2400pci_bbp_write(rt2x00dev, 3, 0x27); | |
934 | rt2400pci_bbp_write(rt2x00dev, 4, 0x08); | |
935 | rt2400pci_bbp_write(rt2x00dev, 10, 0x0f); | |
936 | rt2400pci_bbp_write(rt2x00dev, 15, 0x72); | |
937 | rt2400pci_bbp_write(rt2x00dev, 16, 0x74); | |
938 | rt2400pci_bbp_write(rt2x00dev, 17, 0x20); | |
939 | rt2400pci_bbp_write(rt2x00dev, 18, 0x72); | |
940 | rt2400pci_bbp_write(rt2x00dev, 19, 0x0b); | |
941 | rt2400pci_bbp_write(rt2x00dev, 20, 0x00); | |
942 | rt2400pci_bbp_write(rt2x00dev, 28, 0x11); | |
943 | rt2400pci_bbp_write(rt2x00dev, 29, 0x04); | |
944 | rt2400pci_bbp_write(rt2x00dev, 30, 0x21); | |
945 | rt2400pci_bbp_write(rt2x00dev, 31, 0x00); | |
946 | ||
95ea3627 ID |
947 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
948 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
949 | ||
950 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
951 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
952 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
95ea3627 ID |
953 | rt2400pci_bbp_write(rt2x00dev, reg_id, value); |
954 | } | |
955 | } | |
95ea3627 ID |
956 | |
957 | return 0; | |
958 | } | |
959 | ||
960 | /* | |
961 | * Device state switch handlers. | |
962 | */ | |
95ea3627 ID |
963 | static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
964 | enum dev_state state) | |
965 | { | |
b550911a | 966 | int mask = (state == STATE_RADIO_IRQ_OFF); |
95ea3627 | 967 | u32 reg; |
bcf3cfd0 | 968 | unsigned long flags; |
95ea3627 ID |
969 | |
970 | /* | |
971 | * When interrupts are being enabled, the interrupt registers | |
972 | * should clear the register to assure a clean state. | |
973 | */ | |
974 | if (state == STATE_RADIO_IRQ_ON) { | |
172c5911 GJ |
975 | rt2x00mmio_register_read(rt2x00dev, CSR7, ®); |
976 | rt2x00mmio_register_write(rt2x00dev, CSR7, reg); | |
95ea3627 ID |
977 | } |
978 | ||
979 | /* | |
980 | * Only toggle the interrupts bits we are going to use. | |
981 | * Non-checked interrupt bits are disabled by default. | |
982 | */ | |
bcf3cfd0 HS |
983 | spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); |
984 | ||
172c5911 | 985 | rt2x00mmio_register_read(rt2x00dev, CSR8, ®); |
95ea3627 ID |
986 | rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); |
987 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); | |
988 | rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); | |
989 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); | |
990 | rt2x00_set_field32(®, CSR8_RXDONE, mask); | |
172c5911 | 991 | rt2x00mmio_register_write(rt2x00dev, CSR8, reg); |
bcf3cfd0 HS |
992 | |
993 | spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); | |
994 | ||
995 | if (state == STATE_RADIO_IRQ_OFF) { | |
996 | /* | |
997 | * Ensure that all tasklets are finished before | |
998 | * disabling the interrupts. | |
999 | */ | |
abc11994 HS |
1000 | tasklet_kill(&rt2x00dev->txstatus_tasklet); |
1001 | tasklet_kill(&rt2x00dev->rxdone_tasklet); | |
1002 | tasklet_kill(&rt2x00dev->tbtt_tasklet); | |
bcf3cfd0 | 1003 | } |
95ea3627 ID |
1004 | } |
1005 | ||
1006 | static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev) | |
1007 | { | |
1008 | /* | |
1009 | * Initialize all registers. | |
1010 | */ | |
2b08da3f ID |
1011 | if (unlikely(rt2400pci_init_queues(rt2x00dev) || |
1012 | rt2400pci_init_registers(rt2x00dev) || | |
1013 | rt2400pci_init_bbp(rt2x00dev))) | |
95ea3627 | 1014 | return -EIO; |
95ea3627 | 1015 | |
95ea3627 ID |
1016 | return 0; |
1017 | } | |
1018 | ||
1019 | static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1020 | { | |
95ea3627 | 1021 | /* |
a2c9b652 | 1022 | * Disable power |
95ea3627 | 1023 | */ |
172c5911 | 1024 | rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0); |
95ea3627 ID |
1025 | } |
1026 | ||
1027 | static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, | |
1028 | enum dev_state state) | |
1029 | { | |
9655a6ec | 1030 | u32 reg, reg2; |
95ea3627 ID |
1031 | unsigned int i; |
1032 | char put_to_sleep; | |
1033 | char bbp_state; | |
1034 | char rf_state; | |
1035 | ||
1036 | put_to_sleep = (state != STATE_AWAKE); | |
1037 | ||
172c5911 | 1038 | rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®); |
95ea3627 ID |
1039 | rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); |
1040 | rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); | |
1041 | rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); | |
1042 | rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); | |
172c5911 | 1043 | rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); |
95ea3627 ID |
1044 | |
1045 | /* | |
1046 | * Device is not guaranteed to be in the requested state yet. | |
1047 | * We must wait until the register indicates that the | |
1048 | * device has entered the correct state. | |
1049 | */ | |
1050 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
172c5911 | 1051 | rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®2); |
9655a6ec GW |
1052 | bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE); |
1053 | rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE); | |
95ea3627 ID |
1054 | if (bbp_state == state && rf_state == state) |
1055 | return 0; | |
172c5911 | 1056 | rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); |
95ea3627 ID |
1057 | msleep(10); |
1058 | } | |
1059 | ||
95ea3627 ID |
1060 | return -EBUSY; |
1061 | } | |
1062 | ||
1063 | static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1064 | enum dev_state state) | |
1065 | { | |
1066 | int retval = 0; | |
1067 | ||
1068 | switch (state) { | |
1069 | case STATE_RADIO_ON: | |
1070 | retval = rt2400pci_enable_radio(rt2x00dev); | |
1071 | break; | |
1072 | case STATE_RADIO_OFF: | |
1073 | rt2400pci_disable_radio(rt2x00dev); | |
1074 | break; | |
2b08da3f ID |
1075 | case STATE_RADIO_IRQ_ON: |
1076 | case STATE_RADIO_IRQ_OFF: | |
1077 | rt2400pci_toggle_irq(rt2x00dev, state); | |
95ea3627 ID |
1078 | break; |
1079 | case STATE_DEEP_SLEEP: | |
1080 | case STATE_SLEEP: | |
1081 | case STATE_STANDBY: | |
1082 | case STATE_AWAKE: | |
1083 | retval = rt2400pci_set_state(rt2x00dev, state); | |
1084 | break; | |
1085 | default: | |
1086 | retval = -ENOTSUPP; | |
1087 | break; | |
1088 | } | |
1089 | ||
2b08da3f | 1090 | if (unlikely(retval)) |
ec9c4989 JP |
1091 | rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", |
1092 | state, retval); | |
2b08da3f | 1093 | |
95ea3627 ID |
1094 | return retval; |
1095 | } | |
1096 | ||
1097 | /* | |
1098 | * TX descriptor initialization | |
1099 | */ | |
93331458 | 1100 | static void rt2400pci_write_tx_desc(struct queue_entry *entry, |
61486e0f | 1101 | struct txentry_desc *txdesc) |
95ea3627 | 1102 | { |
93331458 | 1103 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
172c5911 | 1104 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
85b7a8b3 | 1105 | __le32 *txd = entry_priv->desc; |
95ea3627 | 1106 | u32 word; |
95ea3627 ID |
1107 | |
1108 | /* | |
1109 | * Start writing the descriptor words. | |
1110 | */ | |
85b7a8b3 | 1111 | rt2x00_desc_read(txd, 1, &word); |
c4da0048 | 1112 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); |
85b7a8b3 | 1113 | rt2x00_desc_write(txd, 1, word); |
4de36fe5 | 1114 | |
95ea3627 | 1115 | rt2x00_desc_read(txd, 2, &word); |
df624ca5 GW |
1116 | rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length); |
1117 | rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length); | |
95ea3627 ID |
1118 | rt2x00_desc_write(txd, 2, word); |
1119 | ||
1120 | rt2x00_desc_read(txd, 3, &word); | |
26a1d07f | 1121 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); |
49da2605 ID |
1122 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); |
1123 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); | |
26a1d07f | 1124 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); |
49da2605 ID |
1125 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6); |
1126 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); | |
95ea3627 ID |
1127 | rt2x00_desc_write(txd, 3, word); |
1128 | ||
1129 | rt2x00_desc_read(txd, 4, &word); | |
26a1d07f HS |
1130 | rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, |
1131 | txdesc->u.plcp.length_low); | |
49da2605 ID |
1132 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); |
1133 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1); | |
26a1d07f HS |
1134 | rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, |
1135 | txdesc->u.plcp.length_high); | |
49da2605 ID |
1136 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7); |
1137 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); | |
95ea3627 ID |
1138 | rt2x00_desc_write(txd, 4, word); |
1139 | ||
e01f1ec3 GW |
1140 | /* |
1141 | * Writing TXD word 0 must the last to prevent a race condition with | |
1142 | * the device, whereby the device may take hold of the TXD before we | |
1143 | * finished updating it. | |
1144 | */ | |
95ea3627 ID |
1145 | rt2x00_desc_read(txd, 0, &word); |
1146 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); | |
1147 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | |
1148 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
181d6902 | 1149 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
95ea3627 | 1150 | rt2x00_set_field32(&word, TXD_W0_ACK, |
181d6902 | 1151 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
95ea3627 | 1152 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
181d6902 | 1153 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
95ea3627 | 1154 | rt2x00_set_field32(&word, TXD_W0_RTS, |
181d6902 | 1155 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); |
2517794b | 1156 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); |
95ea3627 | 1157 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
aade5102 | 1158 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
95ea3627 | 1159 | rt2x00_desc_write(txd, 0, word); |
85b7a8b3 GW |
1160 | |
1161 | /* | |
1162 | * Register descriptor details in skb frame descriptor. | |
1163 | */ | |
1164 | skbdesc->desc = txd; | |
1165 | skbdesc->desc_len = TXD_DESC_SIZE; | |
95ea3627 ID |
1166 | } |
1167 | ||
1168 | /* | |
1169 | * TX data initialization | |
1170 | */ | |
f224f4ef GW |
1171 | static void rt2400pci_write_beacon(struct queue_entry *entry, |
1172 | struct txentry_desc *txdesc) | |
bd88a781 ID |
1173 | { |
1174 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
bd88a781 ID |
1175 | u32 reg; |
1176 | ||
1177 | /* | |
1178 | * Disable beaconing while we are reloading the beacon data, | |
1179 | * otherwise we might be sending out invalid data. | |
1180 | */ | |
172c5911 | 1181 | rt2x00mmio_register_read(rt2x00dev, CSR14, ®); |
bd88a781 | 1182 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); |
172c5911 | 1183 | rt2x00mmio_register_write(rt2x00dev, CSR14, reg); |
bd88a781 | 1184 | |
4ea545d4 | 1185 | if (rt2x00queue_map_txskb(entry)) { |
ec9c4989 | 1186 | rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n"); |
4ea545d4 SG |
1187 | goto out; |
1188 | } | |
1189 | /* | |
1190 | * Enable beaconing again. | |
1191 | */ | |
1192 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); | |
5c3b685c GW |
1193 | /* |
1194 | * Write the TX descriptor for the beacon. | |
1195 | */ | |
93331458 | 1196 | rt2400pci_write_tx_desc(entry, txdesc); |
5c3b685c GW |
1197 | |
1198 | /* | |
1199 | * Dump beacon to userspace through debugfs. | |
1200 | */ | |
1201 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); | |
4ea545d4 | 1202 | out: |
d61cb266 GW |
1203 | /* |
1204 | * Enable beaconing again. | |
1205 | */ | |
d61cb266 | 1206 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); |
172c5911 | 1207 | rt2x00mmio_register_write(rt2x00dev, CSR14, reg); |
bd88a781 ID |
1208 | } |
1209 | ||
95ea3627 ID |
1210 | /* |
1211 | * RX control handlers | |
1212 | */ | |
181d6902 ID |
1213 | static void rt2400pci_fill_rxdone(struct queue_entry *entry, |
1214 | struct rxdone_entry_desc *rxdesc) | |
95ea3627 | 1215 | { |
ae73e58e | 1216 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
172c5911 | 1217 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
95ea3627 ID |
1218 | u32 word0; |
1219 | u32 word2; | |
89993890 | 1220 | u32 word3; |
ae73e58e ID |
1221 | u32 word4; |
1222 | u64 tsf; | |
1223 | u32 rx_low; | |
1224 | u32 rx_high; | |
95ea3627 | 1225 | |
b8be63ff ID |
1226 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
1227 | rt2x00_desc_read(entry_priv->desc, 2, &word2); | |
1228 | rt2x00_desc_read(entry_priv->desc, 3, &word3); | |
ae73e58e | 1229 | rt2x00_desc_read(entry_priv->desc, 4, &word4); |
95ea3627 | 1230 | |
4150c572 | 1231 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
181d6902 | 1232 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
4150c572 | 1233 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) |
181d6902 | 1234 | rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; |
95ea3627 | 1235 | |
ae73e58e ID |
1236 | /* |
1237 | * We only get the lower 32bits from the timestamp, | |
1238 | * to get the full 64bits we must complement it with | |
1239 | * the timestamp from get_tsf(). | |
1240 | * Note that when a wraparound of the lower 32bits | |
1241 | * has occurred between the frame arrival and the get_tsf() | |
1242 | * call, we must decrease the higher 32bits with 1 to get | |
1243 | * to correct value. | |
1244 | */ | |
37a41b4a | 1245 | tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL); |
ae73e58e ID |
1246 | rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME); |
1247 | rx_high = upper_32_bits(tsf); | |
1248 | ||
1249 | if ((u32)tsf <= rx_low) | |
1250 | rx_high--; | |
1251 | ||
95ea3627 ID |
1252 | /* |
1253 | * Obtain the status about this packet. | |
8ed09854 ID |
1254 | * The signal is the PLCP value, and needs to be stripped |
1255 | * of the preamble bit (0x08). | |
95ea3627 | 1256 | */ |
ae73e58e | 1257 | rxdesc->timestamp = ((u64)rx_high << 32) | rx_low; |
8ed09854 | 1258 | rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08; |
2bf127a5 | 1259 | rxdesc->rssi = rt2x00_get_field32(word3, RXD_W3_RSSI) - |
181d6902 | 1260 | entry->queue->rt2x00dev->rssi_offset; |
181d6902 | 1261 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
19d30e02 | 1262 | |
dec13b6b | 1263 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; |
19d30e02 ID |
1264 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
1265 | rxdesc->dev_flags |= RXDONE_MY_BSS; | |
95ea3627 ID |
1266 | } |
1267 | ||
1268 | /* | |
1269 | * Interrupt functions. | |
1270 | */ | |
181d6902 | 1271 | static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, |
e58c6aca | 1272 | const enum data_queue_qid queue_idx) |
95ea3627 | 1273 | { |
61c6e489 | 1274 | struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
172c5911 | 1275 | struct queue_entry_priv_mmio *entry_priv; |
181d6902 ID |
1276 | struct queue_entry *entry; |
1277 | struct txdone_entry_desc txdesc; | |
95ea3627 | 1278 | u32 word; |
95ea3627 | 1279 | |
181d6902 ID |
1280 | while (!rt2x00queue_empty(queue)) { |
1281 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); | |
b8be63ff ID |
1282 | entry_priv = entry->priv_data; |
1283 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 ID |
1284 | |
1285 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || | |
1286 | !rt2x00_get_field32(word, TXD_W0_VALID)) | |
1287 | break; | |
1288 | ||
1289 | /* | |
1290 | * Obtain the status about this packet. | |
1291 | */ | |
fb55f4d1 ID |
1292 | txdesc.flags = 0; |
1293 | switch (rt2x00_get_field32(word, TXD_W0_RESULT)) { | |
1294 | case 0: /* Success */ | |
1295 | case 1: /* Success with retry */ | |
1296 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | |
1297 | break; | |
1298 | case 2: /* Failure, excessive retries */ | |
1299 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); | |
1300 | /* Don't break, this is a failed frame! */ | |
1301 | default: /* Failure */ | |
1302 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | |
1303 | } | |
181d6902 | 1304 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); |
95ea3627 | 1305 | |
e513a0b6 | 1306 | rt2x00lib_txdone(entry, &txdesc); |
95ea3627 | 1307 | } |
95ea3627 ID |
1308 | } |
1309 | ||
7a5a681a HS |
1310 | static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, |
1311 | struct rt2x00_field32 irq_field) | |
95ea3627 | 1312 | { |
bcf3cfd0 | 1313 | u32 reg; |
95ea3627 ID |
1314 | |
1315 | /* | |
bcf3cfd0 HS |
1316 | * Enable a single interrupt. The interrupt mask register |
1317 | * access needs locking. | |
95ea3627 | 1318 | */ |
0aa13b2e | 1319 | spin_lock_irq(&rt2x00dev->irqmask_lock); |
95ea3627 | 1320 | |
172c5911 | 1321 | rt2x00mmio_register_read(rt2x00dev, CSR8, ®); |
bcf3cfd0 | 1322 | rt2x00_set_field32(®, irq_field, 0); |
172c5911 | 1323 | rt2x00mmio_register_write(rt2x00dev, CSR8, reg); |
95ea3627 | 1324 | |
0aa13b2e | 1325 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
bcf3cfd0 | 1326 | } |
95ea3627 | 1327 | |
bcf3cfd0 HS |
1328 | static void rt2400pci_txstatus_tasklet(unsigned long data) |
1329 | { | |
1330 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
1331 | u32 reg; | |
95ea3627 ID |
1332 | |
1333 | /* | |
bcf3cfd0 | 1334 | * Handle all tx queues. |
95ea3627 | 1335 | */ |
bcf3cfd0 HS |
1336 | rt2400pci_txdone(rt2x00dev, QID_ATIM); |
1337 | rt2400pci_txdone(rt2x00dev, QID_AC_VO); | |
1338 | rt2400pci_txdone(rt2x00dev, QID_AC_VI); | |
95ea3627 ID |
1339 | |
1340 | /* | |
bcf3cfd0 | 1341 | * Enable all TXDONE interrupts again. |
95ea3627 | 1342 | */ |
abc11994 HS |
1343 | if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) { |
1344 | spin_lock_irq(&rt2x00dev->irqmask_lock); | |
95ea3627 | 1345 | |
172c5911 | 1346 | rt2x00mmio_register_read(rt2x00dev, CSR8, ®); |
abc11994 HS |
1347 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); |
1348 | rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); | |
1349 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); | |
172c5911 | 1350 | rt2x00mmio_register_write(rt2x00dev, CSR8, reg); |
bcf3cfd0 | 1351 | |
abc11994 HS |
1352 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
1353 | } | |
bcf3cfd0 HS |
1354 | } |
1355 | ||
1356 | static void rt2400pci_tbtt_tasklet(unsigned long data) | |
1357 | { | |
1358 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
1359 | rt2x00lib_beacondone(rt2x00dev); | |
abc11994 HS |
1360 | if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
1361 | rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE); | |
bcf3cfd0 HS |
1362 | } |
1363 | ||
1364 | static void rt2400pci_rxdone_tasklet(unsigned long data) | |
1365 | { | |
1366 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
172c5911 | 1367 | if (rt2x00mmio_rxdone(rt2x00dev)) |
16638937 | 1368 | tasklet_schedule(&rt2x00dev->rxdone_tasklet); |
abc11994 | 1369 | else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
16638937 | 1370 | rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); |
95ea3627 ID |
1371 | } |
1372 | ||
78e256c9 HS |
1373 | static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) |
1374 | { | |
1375 | struct rt2x00_dev *rt2x00dev = dev_instance; | |
bcf3cfd0 | 1376 | u32 reg, mask; |
78e256c9 HS |
1377 | |
1378 | /* | |
1379 | * Get the interrupt sources & saved to local variable. | |
1380 | * Write register value back to clear pending interrupts. | |
1381 | */ | |
172c5911 GJ |
1382 | rt2x00mmio_register_read(rt2x00dev, CSR7, ®); |
1383 | rt2x00mmio_register_write(rt2x00dev, CSR7, reg); | |
78e256c9 HS |
1384 | |
1385 | if (!reg) | |
1386 | return IRQ_NONE; | |
1387 | ||
1388 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) | |
1389 | return IRQ_HANDLED; | |
1390 | ||
bcf3cfd0 HS |
1391 | mask = reg; |
1392 | ||
1393 | /* | |
1394 | * Schedule tasklets for interrupt handling. | |
1395 | */ | |
1396 | if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) | |
1397 | tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); | |
1398 | ||
1399 | if (rt2x00_get_field32(reg, CSR7_RXDONE)) | |
1400 | tasklet_schedule(&rt2x00dev->rxdone_tasklet); | |
1401 | ||
1402 | if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || | |
1403 | rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || | |
1404 | rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { | |
1405 | tasklet_schedule(&rt2x00dev->txstatus_tasklet); | |
1406 | /* | |
1407 | * Mask out all txdone interrupts. | |
1408 | */ | |
1409 | rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); | |
1410 | rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); | |
1411 | rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); | |
1412 | } | |
78e256c9 | 1413 | |
bcf3cfd0 HS |
1414 | /* |
1415 | * Disable all interrupts for which a tasklet was scheduled right now, | |
1416 | * the tasklet will reenable the appropriate interrupts. | |
1417 | */ | |
0aa13b2e | 1418 | spin_lock(&rt2x00dev->irqmask_lock); |
78e256c9 | 1419 | |
172c5911 | 1420 | rt2x00mmio_register_read(rt2x00dev, CSR8, ®); |
bcf3cfd0 | 1421 | reg |= mask; |
172c5911 | 1422 | rt2x00mmio_register_write(rt2x00dev, CSR8, reg); |
bcf3cfd0 | 1423 | |
0aa13b2e | 1424 | spin_unlock(&rt2x00dev->irqmask_lock); |
bcf3cfd0 HS |
1425 | |
1426 | ||
1427 | ||
1428 | return IRQ_HANDLED; | |
78e256c9 HS |
1429 | } |
1430 | ||
95ea3627 ID |
1431 | /* |
1432 | * Device probe functions. | |
1433 | */ | |
1434 | static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
1435 | { | |
1436 | struct eeprom_93cx6 eeprom; | |
1437 | u32 reg; | |
1438 | u16 word; | |
1439 | u8 *mac; | |
1440 | ||
172c5911 | 1441 | rt2x00mmio_register_read(rt2x00dev, CSR21, ®); |
95ea3627 ID |
1442 | |
1443 | eeprom.data = rt2x00dev; | |
1444 | eeprom.register_read = rt2400pci_eepromregister_read; | |
1445 | eeprom.register_write = rt2400pci_eepromregister_write; | |
1446 | eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? | |
1447 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; | |
1448 | eeprom.reg_data_in = 0; | |
1449 | eeprom.reg_data_out = 0; | |
1450 | eeprom.reg_data_clock = 0; | |
1451 | eeprom.reg_chip_select = 0; | |
1452 | ||
1453 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, | |
1454 | EEPROM_SIZE / sizeof(u16)); | |
1455 | ||
1456 | /* | |
1457 | * Start validation of the data that has been read. | |
1458 | */ | |
1459 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
1460 | if (!is_valid_ether_addr(mac)) { | |
f4f7f414 | 1461 | eth_random_addr(mac); |
ec9c4989 | 1462 | rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac); |
95ea3627 ID |
1463 | } |
1464 | ||
1465 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
1466 | if (word == 0xffff) { | |
ec9c4989 | 1467 | rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n"); |
95ea3627 ID |
1468 | return -EINVAL; |
1469 | } | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
1475 | { | |
1476 | u32 reg; | |
1477 | u16 value; | |
1478 | u16 eeprom; | |
1479 | ||
1480 | /* | |
1481 | * Read EEPROM word for configuration. | |
1482 | */ | |
1483 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
1484 | ||
1485 | /* | |
1486 | * Identify RF chipset. | |
1487 | */ | |
1488 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
172c5911 | 1489 | rt2x00mmio_register_read(rt2x00dev, CSR0, ®); |
49e721ec GW |
1490 | rt2x00_set_chip(rt2x00dev, RT2460, value, |
1491 | rt2x00_get_field32(reg, CSR0_REVISION)); | |
95ea3627 | 1492 | |
5122d898 | 1493 | if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) { |
ec9c4989 | 1494 | rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); |
95ea3627 ID |
1495 | return -ENODEV; |
1496 | } | |
1497 | ||
1498 | /* | |
1499 | * Identify default antenna configuration. | |
1500 | */ | |
addc81bd | 1501 | rt2x00dev->default_ant.tx = |
95ea3627 | 1502 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
addc81bd | 1503 | rt2x00dev->default_ant.rx = |
95ea3627 ID |
1504 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
1505 | ||
addc81bd ID |
1506 | /* |
1507 | * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead. | |
1508 | * I am not 100% sure about this, but the legacy drivers do not | |
1509 | * indicate antenna swapping in software is required when | |
1510 | * diversity is enabled. | |
1511 | */ | |
1512 | if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY) | |
1513 | rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; | |
1514 | if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY) | |
1515 | rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; | |
1516 | ||
95ea3627 ID |
1517 | /* |
1518 | * Store led mode, for correct led behaviour. | |
1519 | */ | |
771fd565 | 1520 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a9450b70 ID |
1521 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); |
1522 | ||
475433be | 1523 | rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
3d3e451f ID |
1524 | if (value == LED_MODE_TXRX_ACTIVITY || |
1525 | value == LED_MODE_DEFAULT || | |
1526 | value == LED_MODE_ASUS) | |
475433be ID |
1527 | rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual, |
1528 | LED_TYPE_ACTIVITY); | |
771fd565 | 1529 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
1530 | |
1531 | /* | |
1532 | * Detect if this device has an hardware controlled radio. | |
1533 | */ | |
1534 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) | |
7dab73b3 | 1535 | __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); |
95ea3627 ID |
1536 | |
1537 | /* | |
1538 | * Check if the BBP tuning should be enabled. | |
1539 | */ | |
27df2a9c | 1540 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING)) |
7dab73b3 | 1541 | __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); |
95ea3627 ID |
1542 | |
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | /* | |
1547 | * RF value list for RF2420 & RF2421 | |
1548 | * Supports: 2.4 GHz | |
1549 | */ | |
8c5e7a5f | 1550 | static const struct rf_channel rf_vals_b[] = { |
95ea3627 ID |
1551 | { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 }, |
1552 | { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 }, | |
1553 | { 3, 0x00022058, 0x000c2002, 0x00000101, 0 }, | |
1554 | { 4, 0x00022058, 0x000c2016, 0x00000101, 0 }, | |
1555 | { 5, 0x00022058, 0x000c202a, 0x00000101, 0 }, | |
1556 | { 6, 0x00022058, 0x000c203e, 0x00000101, 0 }, | |
1557 | { 7, 0x00022058, 0x000c2052, 0x00000101, 0 }, | |
1558 | { 8, 0x00022058, 0x000c2066, 0x00000101, 0 }, | |
1559 | { 9, 0x00022058, 0x000c207a, 0x00000101, 0 }, | |
1560 | { 10, 0x00022058, 0x000c208e, 0x00000101, 0 }, | |
1561 | { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 }, | |
1562 | { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 }, | |
1563 | { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 }, | |
1564 | { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 }, | |
1565 | }; | |
1566 | ||
8c5e7a5f | 1567 | static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1568 | { |
1569 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
8c5e7a5f ID |
1570 | struct channel_info *info; |
1571 | char *tx_power; | |
95ea3627 ID |
1572 | unsigned int i; |
1573 | ||
1574 | /* | |
1575 | * Initialize all hw fields. | |
1576 | */ | |
30686bf7 JB |
1577 | ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); |
1578 | ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); | |
1579 | ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); | |
1580 | ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); | |
95ea3627 | 1581 | |
14a3bf89 | 1582 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
95ea3627 ID |
1583 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
1584 | rt2x00_eeprom_addr(rt2x00dev, | |
1585 | EEPROM_MAC_ADDR_0)); | |
1586 | ||
95ea3627 ID |
1587 | /* |
1588 | * Initialize hw_mode information. | |
1589 | */ | |
31562e80 ID |
1590 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
1591 | spec->supported_rates = SUPPORT_RATE_CCK; | |
95ea3627 | 1592 | |
8c5e7a5f ID |
1593 | spec->num_channels = ARRAY_SIZE(rf_vals_b); |
1594 | spec->channels = rf_vals_b; | |
1595 | ||
1596 | /* | |
1597 | * Create channel information array | |
1598 | */ | |
baeb2ffa | 1599 | info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); |
8c5e7a5f ID |
1600 | if (!info) |
1601 | return -ENOMEM; | |
1602 | ||
1603 | spec->channels_info = info; | |
1604 | ||
1605 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); | |
8d1331b3 ID |
1606 | for (i = 0; i < 14; i++) { |
1607 | info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER); | |
1608 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
1609 | } | |
8c5e7a5f ID |
1610 | |
1611 | return 0; | |
95ea3627 ID |
1612 | } |
1613 | ||
1614 | static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev) | |
1615 | { | |
1616 | int retval; | |
a396e100 | 1617 | u32 reg; |
95ea3627 ID |
1618 | |
1619 | /* | |
1620 | * Allocate eeprom data. | |
1621 | */ | |
1622 | retval = rt2400pci_validate_eeprom(rt2x00dev); | |
1623 | if (retval) | |
1624 | return retval; | |
1625 | ||
1626 | retval = rt2400pci_init_eeprom(rt2x00dev); | |
1627 | if (retval) | |
1628 | return retval; | |
1629 | ||
a396e100 GW |
1630 | /* |
1631 | * Enable rfkill polling by setting GPIO direction of the | |
1632 | * rfkill switch GPIO pin correctly. | |
1633 | */ | |
172c5911 | 1634 | rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); |
99bdf51a | 1635 | rt2x00_set_field32(®, GPIOCSR_DIR0, 1); |
172c5911 | 1636 | rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); |
a396e100 | 1637 | |
95ea3627 ID |
1638 | /* |
1639 | * Initialize hw specifications. | |
1640 | */ | |
8c5e7a5f ID |
1641 | retval = rt2400pci_probe_hw_mode(rt2x00dev); |
1642 | if (retval) | |
1643 | return retval; | |
95ea3627 ID |
1644 | |
1645 | /* | |
c4da0048 | 1646 | * This device requires the atim queue and DMA-mapped skbs. |
95ea3627 | 1647 | */ |
7dab73b3 ID |
1648 | __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); |
1649 | __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); | |
1650 | __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags); | |
95ea3627 ID |
1651 | |
1652 | /* | |
1653 | * Set the rssi offset. | |
1654 | */ | |
1655 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
1660 | /* | |
1661 | * IEEE80211 stack callback functions. | |
1662 | */ | |
8a3a3c85 EP |
1663 | static int rt2400pci_conf_tx(struct ieee80211_hw *hw, |
1664 | struct ieee80211_vif *vif, u16 queue, | |
95ea3627 ID |
1665 | const struct ieee80211_tx_queue_params *params) |
1666 | { | |
1667 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1668 | ||
1669 | /* | |
1670 | * We don't support variating cw_min and cw_max variables | |
1671 | * per queue. So by default we only configure the TX queue, | |
1672 | * and ignore all other configurations. | |
1673 | */ | |
e100bb64 | 1674 | if (queue != 0) |
95ea3627 ID |
1675 | return -EINVAL; |
1676 | ||
8a3a3c85 | 1677 | if (rt2x00mac_conf_tx(hw, vif, queue, params)) |
95ea3627 ID |
1678 | return -EINVAL; |
1679 | ||
1680 | /* | |
1681 | * Write configuration to register. | |
1682 | */ | |
181d6902 ID |
1683 | rt2400pci_config_cw(rt2x00dev, |
1684 | rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max); | |
95ea3627 ID |
1685 | |
1686 | return 0; | |
1687 | } | |
1688 | ||
37a41b4a EP |
1689 | static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw, |
1690 | struct ieee80211_vif *vif) | |
95ea3627 ID |
1691 | { |
1692 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1693 | u64 tsf; | |
1694 | u32 reg; | |
1695 | ||
172c5911 | 1696 | rt2x00mmio_register_read(rt2x00dev, CSR17, ®); |
95ea3627 | 1697 | tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; |
172c5911 | 1698 | rt2x00mmio_register_read(rt2x00dev, CSR16, ®); |
95ea3627 ID |
1699 | tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); |
1700 | ||
1701 | return tsf; | |
1702 | } | |
1703 | ||
95ea3627 ID |
1704 | static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw) |
1705 | { | |
1706 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1707 | u32 reg; | |
1708 | ||
172c5911 | 1709 | rt2x00mmio_register_read(rt2x00dev, CSR15, ®); |
95ea3627 ID |
1710 | return rt2x00_get_field32(reg, CSR15_BEACON_SENT); |
1711 | } | |
1712 | ||
1713 | static const struct ieee80211_ops rt2400pci_mac80211_ops = { | |
1714 | .tx = rt2x00mac_tx, | |
4150c572 JB |
1715 | .start = rt2x00mac_start, |
1716 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
1717 | .add_interface = rt2x00mac_add_interface, |
1718 | .remove_interface = rt2x00mac_remove_interface, | |
1719 | .config = rt2x00mac_config, | |
3a643d24 | 1720 | .configure_filter = rt2x00mac_configure_filter, |
d8147f9d ID |
1721 | .sw_scan_start = rt2x00mac_sw_scan_start, |
1722 | .sw_scan_complete = rt2x00mac_sw_scan_complete, | |
95ea3627 | 1723 | .get_stats = rt2x00mac_get_stats, |
471b3efd | 1724 | .bss_info_changed = rt2x00mac_bss_info_changed, |
95ea3627 | 1725 | .conf_tx = rt2400pci_conf_tx, |
95ea3627 | 1726 | .get_tsf = rt2400pci_get_tsf, |
95ea3627 | 1727 | .tx_last_beacon = rt2400pci_tx_last_beacon, |
e47a5cdd | 1728 | .rfkill_poll = rt2x00mac_rfkill_poll, |
f44df18c | 1729 | .flush = rt2x00mac_flush, |
0ed7b3c0 ID |
1730 | .set_antenna = rt2x00mac_set_antenna, |
1731 | .get_antenna = rt2x00mac_get_antenna, | |
e7dee444 | 1732 | .get_ringparam = rt2x00mac_get_ringparam, |
5f0dd296 | 1733 | .tx_frames_pending = rt2x00mac_tx_frames_pending, |
95ea3627 ID |
1734 | }; |
1735 | ||
1736 | static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = { | |
1737 | .irq_handler = rt2400pci_interrupt, | |
bcf3cfd0 HS |
1738 | .txstatus_tasklet = rt2400pci_txstatus_tasklet, |
1739 | .tbtt_tasklet = rt2400pci_tbtt_tasklet, | |
1740 | .rxdone_tasklet = rt2400pci_rxdone_tasklet, | |
95ea3627 | 1741 | .probe_hw = rt2400pci_probe_hw, |
172c5911 GJ |
1742 | .initialize = rt2x00mmio_initialize, |
1743 | .uninitialize = rt2x00mmio_uninitialize, | |
798b7adb ID |
1744 | .get_entry_state = rt2400pci_get_entry_state, |
1745 | .clear_entry = rt2400pci_clear_entry, | |
95ea3627 | 1746 | .set_device_state = rt2400pci_set_device_state, |
95ea3627 | 1747 | .rfkill_poll = rt2400pci_rfkill_poll, |
95ea3627 ID |
1748 | .link_stats = rt2400pci_link_stats, |
1749 | .reset_tuner = rt2400pci_reset_tuner, | |
1750 | .link_tuner = rt2400pci_link_tuner, | |
dbba306f ID |
1751 | .start_queue = rt2400pci_start_queue, |
1752 | .kick_queue = rt2400pci_kick_queue, | |
1753 | .stop_queue = rt2400pci_stop_queue, | |
172c5911 | 1754 | .flush_queue = rt2x00mmio_flush_queue, |
95ea3627 | 1755 | .write_tx_desc = rt2400pci_write_tx_desc, |
bd88a781 | 1756 | .write_beacon = rt2400pci_write_beacon, |
95ea3627 | 1757 | .fill_rxdone = rt2400pci_fill_rxdone, |
3a643d24 | 1758 | .config_filter = rt2400pci_config_filter, |
6bb40dd1 | 1759 | .config_intf = rt2400pci_config_intf, |
72810379 | 1760 | .config_erp = rt2400pci_config_erp, |
e4ea1c40 | 1761 | .config_ant = rt2400pci_config_ant, |
95ea3627 ID |
1762 | .config = rt2400pci_config, |
1763 | }; | |
1764 | ||
3d8979ba GJ |
1765 | static void rt2400pci_queue_init(struct data_queue *queue) |
1766 | { | |
1767 | switch (queue->qid) { | |
1768 | case QID_RX: | |
1769 | queue->limit = 24; | |
1770 | queue->data_size = DATA_FRAME_SIZE; | |
1771 | queue->desc_size = RXD_DESC_SIZE; | |
1772 | queue->priv_size = sizeof(struct queue_entry_priv_mmio); | |
1773 | break; | |
181d6902 | 1774 | |
3d8979ba GJ |
1775 | case QID_AC_VO: |
1776 | case QID_AC_VI: | |
1777 | case QID_AC_BE: | |
1778 | case QID_AC_BK: | |
1779 | queue->limit = 24; | |
1780 | queue->data_size = DATA_FRAME_SIZE; | |
1781 | queue->desc_size = TXD_DESC_SIZE; | |
1782 | queue->priv_size = sizeof(struct queue_entry_priv_mmio); | |
1783 | break; | |
181d6902 | 1784 | |
3d8979ba GJ |
1785 | case QID_BEACON: |
1786 | queue->limit = 1; | |
1787 | queue->data_size = MGMT_FRAME_SIZE; | |
1788 | queue->desc_size = TXD_DESC_SIZE; | |
1789 | queue->priv_size = sizeof(struct queue_entry_priv_mmio); | |
1790 | break; | |
181d6902 | 1791 | |
3d8979ba GJ |
1792 | case QID_ATIM: |
1793 | queue->limit = 8; | |
1794 | queue->data_size = DATA_FRAME_SIZE; | |
1795 | queue->desc_size = TXD_DESC_SIZE; | |
1796 | queue->priv_size = sizeof(struct queue_entry_priv_mmio); | |
1797 | break; | |
1798 | ||
1799 | default: | |
1800 | BUG(); | |
1801 | break; | |
1802 | } | |
1803 | } | |
181d6902 | 1804 | |
95ea3627 | 1805 | static const struct rt2x00_ops rt2400pci_ops = { |
04d0362e | 1806 | .name = KBUILD_MODNAME, |
04d0362e GW |
1807 | .max_ap_intf = 1, |
1808 | .eeprom_size = EEPROM_SIZE, | |
1809 | .rf_size = RF_SIZE, | |
1810 | .tx_queues = NUM_TX_QUEUES, | |
3d8979ba | 1811 | .queue_init = rt2400pci_queue_init, |
04d0362e GW |
1812 | .lib = &rt2400pci_rt2x00_ops, |
1813 | .hw = &rt2400pci_mac80211_ops, | |
95ea3627 | 1814 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
04d0362e | 1815 | .debugfs = &rt2400pci_rt2x00debug, |
95ea3627 ID |
1816 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
1817 | }; | |
1818 | ||
1819 | /* | |
1820 | * RT2400pci module information. | |
1821 | */ | |
9baa3c34 | 1822 | static const struct pci_device_id rt2400pci_device_table[] = { |
e01ae27f | 1823 | { PCI_DEVICE(0x1814, 0x0101) }, |
95ea3627 ID |
1824 | { 0, } |
1825 | }; | |
1826 | ||
e01ae27f | 1827 | |
95ea3627 ID |
1828 | MODULE_AUTHOR(DRV_PROJECT); |
1829 | MODULE_VERSION(DRV_VERSION); | |
1830 | MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver."); | |
1831 | MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards"); | |
1832 | MODULE_DEVICE_TABLE(pci, rt2400pci_device_table); | |
1833 | MODULE_LICENSE("GPL"); | |
1834 | ||
e01ae27f GW |
1835 | static int rt2400pci_probe(struct pci_dev *pci_dev, |
1836 | const struct pci_device_id *id) | |
1837 | { | |
1838 | return rt2x00pci_probe(pci_dev, &rt2400pci_ops); | |
1839 | } | |
1840 | ||
95ea3627 | 1841 | static struct pci_driver rt2400pci_driver = { |
2360157c | 1842 | .name = KBUILD_MODNAME, |
95ea3627 | 1843 | .id_table = rt2400pci_device_table, |
e01ae27f | 1844 | .probe = rt2400pci_probe, |
69202359 | 1845 | .remove = rt2x00pci_remove, |
95ea3627 ID |
1846 | .suspend = rt2x00pci_suspend, |
1847 | .resume = rt2x00pci_resume, | |
1848 | }; | |
1849 | ||
5b0a3b7e | 1850 | module_pci_driver(rt2400pci_driver); |