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usb: dwc2: host: Correct snpsid checking for GDFIFOCFG
[mirror_ubuntu-disco-kernel.git] / drivers / usb / dwc2 / params.c
CommitLineData
323230ef
JY		 1/*
2 * Copyright (C) 2004-2016 Synopsys, Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions, and the following disclaimer,
9 * without modification.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. The names of the above-listed copyright holders may not be used
14 * to endorse or promote products derived from this software without
15 * specific prior written permission.
16 *
17 * ALTERNATIVELY, this software may be distributed under the terms of the
18 * GNU General Public License ("GPL") as published by the Free Software
19 * Foundation; either version 2 of the License, or (at your option) any
20 * later version.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
23 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
30 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/of_device.h>
38
39#include "core.h"
40
7de1debc
JY		 41static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
42{
43 struct dwc2_core_params *p = &hsotg->params;
323230ef 44
7de1debc 45 p->host_rx_fifo_size = 774;
7de1debc
JY		 46 p->max_transfer_size = 65535;
47 p->max_packet_count = 511;
7de1debc
JY		 48 p->ahbcfg = 0x10;
49 p->uframe_sched = false;
50}
323230ef 51
7de1debc
JY		 52static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
53{
54 struct dwc2_core_params *p = &hsotg->params;
323230ef 55
7de1debc
JY		 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
57 p->speed = DWC2_SPEED_PARAM_HIGH;
58 p->host_rx_fifo_size = 512;
59 p->host_nperio_tx_fifo_size = 512;
60 p->host_perio_tx_fifo_size = 512;
61 p->max_transfer_size = 65535;
62 p->max_packet_count = 511;
63 p->host_channels = 16;
64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
65 p->phy_utmi_width = 8;
66 p->i2c_enable = false;
7de1debc
JY		 67 p->reload_ctl = false;
68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
69 GAHBCFG_HBSTLEN_SHIFT;
70 p->uframe_sched = false;
ca8b0332 71 p->change_speed_quirk = true;
7de1debc 72}
323230ef 73
7de1debc
JY		 74static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
75{
76 struct dwc2_core_params *p = &hsotg->params;
77
78 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
79 p->host_rx_fifo_size = 525;
80 p->host_nperio_tx_fifo_size = 128;
81 p->host_perio_tx_fifo_size = 256;
82 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
83 GAHBCFG_HBSTLEN_SHIFT;
84}
85
86static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
87{
88 struct dwc2_core_params *p = &hsotg->params;
89
90 p->otg_cap = 2;
91 p->host_rx_fifo_size = 288;
92 p->host_nperio_tx_fifo_size = 128;
93 p->host_perio_tx_fifo_size = 96;
94 p->max_transfer_size = 65535;
95 p->max_packet_count = 511;
96 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
97 GAHBCFG_HBSTLEN_SHIFT;
98}
99
100static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
101{
102 struct dwc2_core_params *p = &hsotg->params;
103
104 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
105 p->speed = DWC2_SPEED_PARAM_HIGH;
106 p->host_rx_fifo_size = 512;
107 p->host_nperio_tx_fifo_size = 500;
108 p->host_perio_tx_fifo_size = 500;
109 p->host_channels = 16;
110 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
111 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
112 GAHBCFG_HBSTLEN_SHIFT;
113 p->uframe_sched = false;
114}
115
116static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
117{
118 struct dwc2_core_params *p = &hsotg->params;
119
120 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
121}
323230ef
JY		 122
123const struct of_device_id dwc2_of_match_table[] = {
7de1debc
JY		 124 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
125 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
126 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
127 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
128 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
129 { .compatible = "snps,dwc2" },
130 { .compatible = "samsung,s3c6400-hsotg" },
131 { .compatible = "amlogic,meson8b-usb",
132 .data = dwc2_set_amlogic_params },
133 { .compatible = "amlogic,meson-gxbb-usb",
134 .data = dwc2_set_amlogic_params },
135 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
323230ef
JY		 136 {},
137};
138MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
139
245977c9 140static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
05ee799f 141{
245977c9 142 u8 val;
05ee799f 143
245977c9
JY		 144 switch (hsotg->hw_params.op_mode) {
145 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
146 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
05ee799f 147 break;
245977c9
JY		 148 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
149 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
150 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
151 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
05ee799f
JY		 152 break;
153 default:
245977c9 154 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
05ee799f 155 break;
323230ef
JY		 156 }
157
bea8e86c 158 hsotg->params.otg_cap = val;
323230ef
JY		 159}
160
245977c9 161static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
323230ef 162{
245977c9
JY		 163 int val;
164 u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
323230ef 165
245977c9
JY		 166 val = DWC2_PHY_TYPE_PARAM_FS;
167 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
168 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
169 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
170 val = DWC2_PHY_TYPE_PARAM_UTMI;
171 else
172 val = DWC2_PHY_TYPE_PARAM_ULPI;
323230ef
JY		 173 }
174
245977c9
JY		 175 if (dwc2_is_fs_iot(hsotg))
176 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
323230ef 177
bea8e86c 178 hsotg->params.phy_type = val;
323230ef
JY		 179}
180
245977c9 181static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
323230ef 182{
245977c9 183 int val;
323230ef 184
245977c9
JY		 185 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
186 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
323230ef 187
245977c9
JY		 188 if (dwc2_is_fs_iot(hsotg))
189 val = DWC2_SPEED_PARAM_FULL;
38e9002b 190
245977c9
JY		 191 if (dwc2_is_hs_iot(hsotg))
192 val = DWC2_SPEED_PARAM_HIGH;
323230ef 193
bea8e86c 194 hsotg->params.speed = val;
323230ef
JY		 195}
196
245977c9 197static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
323230ef 198{
245977c9 199 int val;
323230ef 200
245977c9
JY		 201 val = (hsotg->hw_params.utmi_phy_data_width ==
202 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
323230ef 203
bea8e86c 204 hsotg->params.phy_utmi_width = val;
323230ef
JY		 205}
206
05ee799f
JY		 207static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
208{
05ee799f 209 struct dwc2_core_params *p = &hsotg->params;
245977c9 210 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
05ee799f
JY		 211
212 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
245977c9
JY		 213 memcpy(&p->g_tx_fifo_size[1],
214 p_tx_fifo,
215 sizeof(p_tx_fifo));
9962b62f
JY		 216}
217
05ee799f 218/**
245977c9
JY		 219 * dwc2_set_default_params() - Set all core parameters to their
220 * auto-detected default values.
323230ef 221 */
245977c9 222static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
323230ef 223{
05ee799f
JY		 224 struct dwc2_hw_params *hw = &hsotg->hw_params;
225 struct dwc2_core_params *p = &hsotg->params;
6b66ce51 226 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
323230ef 227
245977c9
JY		 228 dwc2_set_param_otg_cap(hsotg);
229 dwc2_set_param_phy_type(hsotg);
230 dwc2_set_param_speed(hsotg);
231 dwc2_set_param_phy_utmi_width(hsotg);
232 p->phy_ulpi_ddr = false;
233 p->phy_ulpi_ext_vbus = false;
234
235 p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
236 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
237 p->i2c_enable = hw->i2c_enable;
238 p->ulpi_fs_ls = false;
239 p->ts_dline = false;
240 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
241 p->uframe_sched = true;
242 p->external_id_pin_ctl = false;
243 p->hibernation = false;
244 p->max_packet_count = hw->max_packet_count;
245 p->max_transfer_size = hw->max_transfer_size;
246 p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT;
247
6b66ce51
JY		 248 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
249 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
245977c9
JY		 250 p->host_dma = dma_capable;
251 p->dma_desc_enable = false;
252 p->dma_desc_fs_enable = false;
253 p->host_support_fs_ls_low_power = false;
254 p->host_ls_low_power_phy_clk = false;
255 p->host_channels = hw->host_channels;
256 p->host_rx_fifo_size = hw->rx_fifo_size;
257 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
258 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
6b66ce51
JY		 259 }
260
05ee799f
JY		 261 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
262 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
245977c9
JY		 263 p->g_dma = dma_capable;
264 p->g_dma_desc = hw->dma_desc_enable;
05ee799f
JY		 265
266 /*
267 * The values for g_rx_fifo_size (2048) and
268 * g_np_tx_fifo_size (1024) come from the legacy s3c
269 * gadget driver. These defaults have been hard-coded
270 * for some time so many platforms depend on these
271 * values. Leave them as defaults for now and only
272 * auto-detect if the hardware does not support the
273 * default.
274 */
245977c9
JY		 275 p->g_rx_fifo_size = 2048;
276 p->g_np_tx_fifo_size = 1024;
05ee799f
JY		 277 dwc2_set_param_tx_fifo_sizes(hsotg);
278 }
323230ef
JY		 279}
280
f9f93cbb
JY		 281/**
282 * dwc2_get_device_properties() - Read in device properties.
283 *
284 * Read in the device properties and adjust core parameters if needed.
285 */
286static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
287{
288 struct dwc2_core_params *p = &hsotg->params;
289 int num;
290
291 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
292 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
293 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
294 &p->g_rx_fifo_size);
295
296 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
297 &p->g_np_tx_fifo_size);
298
299 num = device_property_read_u32_array(hsotg->dev,
300 "g-tx-fifo-size",
301 NULL, 0);
302
303 if (num > 0) {
304 num = min(num, 15);
305 memset(p->g_tx_fifo_size, 0,
306 sizeof(p->g_tx_fifo_size));
307 device_property_read_u32_array(hsotg->dev,
308 "g-tx-fifo-size",
309 &p->g_tx_fifo_size[1],
310 num);
311 }
312 }
313}
314
d936e666
JY		 315static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
316{
317 int valid = 1;
318
319 switch (hsotg->params.otg_cap) {
320 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
321 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
322 valid = 0;
323 break;
324 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
325 switch (hsotg->hw_params.op_mode) {
326 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
327 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
328 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
329 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
330 break;
331 default:
332 valid = 0;
333 break;
334 }
335 break;
336 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
337 /* always valid */
338 break;
339 default:
340 valid = 0;
341 break;
342 }
343
344 if (!valid)
345 dwc2_set_param_otg_cap(hsotg);
346}
347
348static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
349{
350 int valid = 0;
351 u32 hs_phy_type;
352 u32 fs_phy_type;
353
354 hs_phy_type = hsotg->hw_params.hs_phy_type;
355 fs_phy_type = hsotg->hw_params.fs_phy_type;
356
357 switch (hsotg->params.phy_type) {
358 case DWC2_PHY_TYPE_PARAM_FS:
359 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
360 valid = 1;
361 break;
362 case DWC2_PHY_TYPE_PARAM_UTMI:
363 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
364 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
365 valid = 1;
366 break;
367 case DWC2_PHY_TYPE_PARAM_ULPI:
368 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
369 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
370 valid = 1;
371 break;
372 default:
373 break;
374 }
375
376 if (!valid)
377 dwc2_set_param_phy_type(hsotg);
378}
379
380static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
381{
382 int valid = 1;
383 int phy_type = hsotg->params.phy_type;
384 int speed = hsotg->params.speed;
385
386 switch (speed) {
387 case DWC2_SPEED_PARAM_HIGH:
388 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
389 (phy_type == DWC2_PHY_TYPE_PARAM_FS))
390 valid = 0;
391 break;
392 case DWC2_SPEED_PARAM_FULL:
393 case DWC2_SPEED_PARAM_LOW:
394 break;
395 default:
396 valid = 0;
397 break;
398 }
399
400 if (!valid)
401 dwc2_set_param_speed(hsotg);
402}
403
404static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
405{
406 int valid = 0;
407 int param = hsotg->params.phy_utmi_width;
408 int width = hsotg->hw_params.utmi_phy_data_width;
409
410 switch (width) {
411 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
412 valid = (param == 8);
413 break;
414 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
415 valid = (param == 16);
416 break;
417 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
418 valid = (param == 8 || param == 16);
419 break;
420 }
421
422 if (!valid)
423 dwc2_set_param_phy_utmi_width(hsotg);
424}
425
426#define CHECK_RANGE(_param, _min, _max, _def) do { \
427 if ((hsotg->params._param) < (_min) || \
428 (hsotg->params._param) > (_max)) { \
429 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
430 __func__, #_param, hsotg->params._param); \
431 hsotg->params._param = (_def); \
432 } \
433 } while (0)
434
435#define CHECK_BOOL(_param, _check) do { \
436 if (hsotg->params._param && !(_check)) { \
437 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
438 __func__, #_param, hsotg->params._param); \
439 hsotg->params._param = false; \
440 } \
441 } while (0)
442
443static void dwc2_check_params(struct dwc2_hsotg *hsotg)
444{
445 struct dwc2_hw_params *hw = &hsotg->hw_params;
446 struct dwc2_core_params *p = &hsotg->params;
447 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
448
449 dwc2_check_param_otg_cap(hsotg);
450 dwc2_check_param_phy_type(hsotg);
451 dwc2_check_param_speed(hsotg);
452 dwc2_check_param_phy_utmi_width(hsotg);
453 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
454 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
455 CHECK_BOOL(i2c_enable, hw->i2c_enable);
456 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
457 CHECK_RANGE(max_packet_count,
458 15, hw->max_packet_count,
459 hw->max_packet_count);
460 CHECK_RANGE(max_transfer_size,
461 2047, hw->max_transfer_size,
462 hw->max_transfer_size);
463
464 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
465 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
466 CHECK_BOOL(host_dma, dma_capable);
467 CHECK_BOOL(dma_desc_enable, p->host_dma);
468 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
469 CHECK_BOOL(host_ls_low_power_phy_clk,
470 p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
471 CHECK_RANGE(host_channels,
472 1, hw->host_channels,
473 hw->host_channels);
474 CHECK_RANGE(host_rx_fifo_size,
475 16, hw->rx_fifo_size,
476 hw->rx_fifo_size);
477 CHECK_RANGE(host_nperio_tx_fifo_size,
478 16, hw->host_nperio_tx_fifo_size,
479 hw->host_nperio_tx_fifo_size);
480 CHECK_RANGE(host_perio_tx_fifo_size,
481 16, hw->host_perio_tx_fifo_size,
482 hw->host_perio_tx_fifo_size);
483 }
484
485 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
486 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
487 CHECK_BOOL(g_dma, dma_capable);
488 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
489 CHECK_RANGE(g_rx_fifo_size,
490 16, hw->rx_fifo_size,
491 hw->rx_fifo_size);
492 CHECK_RANGE(g_np_tx_fifo_size,
493 16, hw->dev_nperio_tx_fifo_size,
494 hw->dev_nperio_tx_fifo_size);
495 }
496}
497
323230ef
JY		 498/*
499 * Gets host hardware parameters. Forces host mode if not currently in
500 * host mode. Should be called immediately after a core soft reset in
501 * order to get the reset values.
502 */
503static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
504{
505 struct dwc2_hw_params *hw = &hsotg->hw_params;
506 u32 gnptxfsiz;
507 u32 hptxfsiz;
508 bool forced;
509
510 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
511 return;
512
513 forced = dwc2_force_mode_if_needed(hsotg, true);
514
515 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
516 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
323230ef
JY		 517
518 if (forced)
519 dwc2_clear_force_mode(hsotg);
520
521 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
522 FIFOSIZE_DEPTH_SHIFT;
523 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
524 FIFOSIZE_DEPTH_SHIFT;
525}
526
527/*
528 * Gets device hardware parameters. Forces device mode if not
529 * currently in device mode. Should be called immediately after a core
530 * soft reset in order to get the reset values.
531 */
532static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
533{
534 struct dwc2_hw_params *hw = &hsotg->hw_params;
535 bool forced;
536 u32 gnptxfsiz;
537
538 if (hsotg->dr_mode == USB_DR_MODE_HOST)
539 return;
540
541 forced = dwc2_force_mode_if_needed(hsotg, false);
542
543 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
323230ef
JY		 544
545 if (forced)
546 dwc2_clear_force_mode(hsotg);
547
548 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
549 FIFOSIZE_DEPTH_SHIFT;
550}
551
552/**
553 * During device initialization, read various hardware configuration
554 * registers and interpret the contents.
555 */
556int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
557{
558 struct dwc2_hw_params *hw = &hsotg->hw_params;
559 unsigned int width;
560 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
561 u32 grxfsiz;
562
563 /*
564 * Attempt to ensure this device is really a DWC_otg Controller.
565 * Read and verify the GSNPSID register contents. The value should be
566 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
567 * as in "OTG version 2.xx" or "OTG version 3.xx".
568 */
569 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
570 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
1e6b98eb
VM		 571 (hw->snpsid & 0xfffff000) != 0x4f543000 &&
572 (hw->snpsid & 0xffff0000) != 0x55310000 &&
573 (hw->snpsid & 0xffff0000) != 0x55320000) {
323230ef
JY		 574 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
575 hw->snpsid);
576 return -ENODEV;
577 }
578
579 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
580 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
581 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
582
583 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
584 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
585 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
586 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
587 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
588
323230ef
JY		 589 /*
590 * Host specific hardware parameters. Reading these parameters
591 * requires the controller to be in host mode. The mode will
592 * be forced, if necessary, to read these values.
593 */
594 dwc2_get_host_hwparams(hsotg);
595 dwc2_get_dev_hwparams(hsotg);
596
597 /* hwcfg1 */
598 hw->dev_ep_dirs = hwcfg1;
599
600 /* hwcfg2 */
601 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
602 GHWCFG2_OP_MODE_SHIFT;
603 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
604 GHWCFG2_ARCHITECTURE_SHIFT;
605 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
606 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
607 GHWCFG2_NUM_HOST_CHAN_SHIFT);
608 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
609 GHWCFG2_HS_PHY_TYPE_SHIFT;
610 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
611 GHWCFG2_FS_PHY_TYPE_SHIFT;
612 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
613 GHWCFG2_NUM_DEV_EP_SHIFT;
614 hw->nperio_tx_q_depth =
615 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
616 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
617 hw->host_perio_tx_q_depth =
618 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
619 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
620 hw->dev_token_q_depth =
621 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
622 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
623
624 /* hwcfg3 */
625 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
626 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
627 hw->max_transfer_size = (1 << (width + 11)) - 1;
628 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
629 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
630 hw->max_packet_count = (1 << (width + 4)) - 1;
631 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
632 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
633 GHWCFG3_DFIFO_DEPTH_SHIFT;
634
635 /* hwcfg4 */
636 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
637 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
638 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
639 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
640 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
641 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
642 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
643
644 /* fifo sizes */
d1531319 645 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
323230ef
JY		 646 GRXFSIZ_DEPTH_SHIFT;
647
323230ef
JY		 648 return 0;
649}
650
334bbd4e
JY		 651int dwc2_init_params(struct dwc2_hsotg *hsotg)
652{
7de1debc
JY		 653 const struct of_device_id *match;
654 void (*set_params)(void *data);
655
245977c9 656 dwc2_set_default_params(hsotg);
f9f93cbb 657 dwc2_get_device_properties(hsotg);
334bbd4e 658
7de1debc
JY		 659 match = of_match_device(dwc2_of_match_table, hsotg->dev);
660 if (match && match->data) {
661 set_params = match->data;
662 set_params(hsotg);
663 }
664
d936e666
JY		 665 dwc2_check_params(hsotg);
666
334bbd4e
JY		 667 return 0;
668}
Ubuntu Disco kernel mirror for Proxmox VE and PMG