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Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
72246da4 FB |
2 | /** |
3 | * core.c - DesignWare USB3 DRD Controller Core file | |
4 | * | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
fa0ea13e | 11 | #include <linux/version.h> |
a72e658b | 12 | #include <linux/module.h> |
72246da4 FB |
13 | #include <linux/kernel.h> |
14 | #include <linux/slab.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/pm_runtime.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/dma-mapping.h> | |
457e84b6 | 24 | #include <linux/of.h> |
404905a6 | 25 | #include <linux/acpi.h> |
6344475f | 26 | #include <linux/pinctrl/consumer.h> |
72246da4 FB |
27 | |
28 | #include <linux/usb/ch9.h> | |
29 | #include <linux/usb/gadget.h> | |
f7e846f0 | 30 | #include <linux/usb/of.h> |
a45c82b8 | 31 | #include <linux/usb/otg.h> |
72246da4 FB |
32 | |
33 | #include "core.h" | |
34 | #include "gadget.h" | |
35 | #include "io.h" | |
36 | ||
37 | #include "debug.h" | |
38 | ||
fc8bb91b | 39 | #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ |
8300dd23 | 40 | |
9d6173e1 TN |
41 | /** |
42 | * dwc3_get_dr_mode - Validates and sets dr_mode | |
43 | * @dwc: pointer to our context structure | |
44 | */ | |
45 | static int dwc3_get_dr_mode(struct dwc3 *dwc) | |
46 | { | |
47 | enum usb_dr_mode mode; | |
48 | struct device *dev = dwc->dev; | |
49 | unsigned int hw_mode; | |
50 | ||
51 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
52 | dwc->dr_mode = USB_DR_MODE_OTG; | |
53 | ||
54 | mode = dwc->dr_mode; | |
55 | hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); | |
56 | ||
57 | switch (hw_mode) { | |
58 | case DWC3_GHWPARAMS0_MODE_GADGET: | |
59 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { | |
60 | dev_err(dev, | |
61 | "Controller does not support host mode.\n"); | |
62 | return -EINVAL; | |
63 | } | |
64 | mode = USB_DR_MODE_PERIPHERAL; | |
65 | break; | |
66 | case DWC3_GHWPARAMS0_MODE_HOST: | |
67 | if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { | |
68 | dev_err(dev, | |
69 | "Controller does not support device mode.\n"); | |
70 | return -EINVAL; | |
71 | } | |
72 | mode = USB_DR_MODE_HOST; | |
73 | break; | |
74 | default: | |
75 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) | |
76 | mode = USB_DR_MODE_HOST; | |
77 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
78 | mode = USB_DR_MODE_PERIPHERAL; | |
79 | } | |
80 | ||
81 | if (mode != dwc->dr_mode) { | |
82 | dev_warn(dev, | |
83 | "Configuration mismatch. dr_mode forced to %s\n", | |
84 | mode == USB_DR_MODE_HOST ? "host" : "gadget"); | |
85 | ||
86 | dwc->dr_mode = mode; | |
87 | } | |
88 | ||
89 | return 0; | |
90 | } | |
91 | ||
41ce1456 RQ |
92 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc); |
93 | static int dwc3_event_buffers_setup(struct dwc3 *dwc); | |
94 | ||
95 | static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) | |
3140e8cb SAS |
96 | { |
97 | u32 reg; | |
98 | ||
99 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
100 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
101 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
102 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
04c51994 MG |
103 | |
104 | dwc->current_dr_role = mode; | |
41ce1456 RQ |
105 | } |
106 | ||
107 | static void __dwc3_set_mode(struct work_struct *work) | |
108 | { | |
109 | struct dwc3 *dwc = work_to_dwc(work); | |
110 | unsigned long flags; | |
111 | int ret; | |
112 | ||
113 | if (!dwc->desired_dr_role) | |
114 | return; | |
115 | ||
116 | if (dwc->desired_dr_role == dwc->current_dr_role) | |
117 | return; | |
118 | ||
119 | if (dwc->dr_mode != USB_DR_MODE_OTG) | |
120 | return; | |
121 | ||
b058f25d RQ |
122 | if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG) |
123 | return; | |
124 | ||
41ce1456 RQ |
125 | switch (dwc->current_dr_role) { |
126 | case DWC3_GCTL_PRTCAP_HOST: | |
127 | dwc3_host_exit(dwc); | |
128 | break; | |
129 | case DWC3_GCTL_PRTCAP_DEVICE: | |
130 | dwc3_gadget_exit(dwc); | |
131 | dwc3_event_buffers_cleanup(dwc); | |
132 | break; | |
133 | default: | |
134 | break; | |
135 | } | |
136 | ||
137 | spin_lock_irqsave(&dwc->lock, flags); | |
138 | ||
139 | dwc3_set_prtcap(dwc, dwc->desired_dr_role); | |
6b3261a2 | 140 | |
41ce1456 RQ |
141 | spin_unlock_irqrestore(&dwc->lock, flags); |
142 | ||
143 | switch (dwc->desired_dr_role) { | |
144 | case DWC3_GCTL_PRTCAP_HOST: | |
145 | ret = dwc3_host_init(dwc); | |
958d1a4c | 146 | if (ret) { |
41ce1456 | 147 | dev_err(dwc->dev, "failed to initialize host\n"); |
958d1a4c FB |
148 | } else { |
149 | if (dwc->usb2_phy) | |
150 | otg_set_vbus(dwc->usb2_phy->otg, true); | |
644cbbc3 MG |
151 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); |
152 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); | |
958d1a4c | 153 | } |
41ce1456 RQ |
154 | break; |
155 | case DWC3_GCTL_PRTCAP_DEVICE: | |
156 | dwc3_event_buffers_setup(dwc); | |
958d1a4c FB |
157 | |
158 | if (dwc->usb2_phy) | |
159 | otg_set_vbus(dwc->usb2_phy->otg, false); | |
644cbbc3 MG |
160 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); |
161 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); | |
958d1a4c | 162 | |
41ce1456 RQ |
163 | ret = dwc3_gadget_init(dwc); |
164 | if (ret) | |
165 | dev_err(dwc->dev, "failed to initialize peripheral\n"); | |
166 | break; | |
167 | default: | |
168 | break; | |
169 | } | |
170 | } | |
171 | ||
172 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) | |
173 | { | |
174 | unsigned long flags; | |
175 | ||
176 | spin_lock_irqsave(&dwc->lock, flags); | |
177 | dwc->desired_dr_role = mode; | |
178 | spin_unlock_irqrestore(&dwc->lock, flags); | |
179 | ||
9c3818a3 | 180 | queue_work(system_freezable_wq, &dwc->drd_work); |
3140e8cb | 181 | } |
8300dd23 | 182 | |
cf6d867d FB |
183 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) |
184 | { | |
185 | struct dwc3 *dwc = dep->dwc; | |
186 | u32 reg; | |
187 | ||
188 | dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, | |
189 | DWC3_GDBGFIFOSPACE_NUM(dep->number) | | |
190 | DWC3_GDBGFIFOSPACE_TYPE(type)); | |
191 | ||
192 | reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); | |
193 | ||
194 | return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); | |
195 | } | |
196 | ||
72246da4 FB |
197 | /** |
198 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
199 | * @dwc: pointer to our context structure | |
200 | */ | |
57303488 | 201 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
202 | { |
203 | u32 reg; | |
f59dcab1 | 204 | int retries = 1000; |
57303488 | 205 | int ret; |
72246da4 | 206 | |
51e1e7bc FB |
207 | usb_phy_init(dwc->usb2_phy); |
208 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
209 | ret = phy_init(dwc->usb2_generic_phy); |
210 | if (ret < 0) | |
211 | return ret; | |
212 | ||
213 | ret = phy_init(dwc->usb3_generic_phy); | |
214 | if (ret < 0) { | |
215 | phy_exit(dwc->usb2_generic_phy); | |
216 | return ret; | |
217 | } | |
72246da4 | 218 | |
f59dcab1 FB |
219 | /* |
220 | * We're resetting only the device side because, if we're in host mode, | |
221 | * XHCI driver will reset the host block. If dwc3 was configured for | |
222 | * host-only mode, then we can return early. | |
223 | */ | |
04c51994 | 224 | if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) |
f59dcab1 | 225 | return 0; |
72246da4 | 226 | |
f59dcab1 FB |
227 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
228 | reg |= DWC3_DCTL_CSFTRST; | |
229 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 230 | |
f59dcab1 FB |
231 | do { |
232 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
233 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
922b9e0d | 234 | goto done; |
45627ac6 | 235 | |
f59dcab1 FB |
236 | udelay(1); |
237 | } while (--retries); | |
57303488 | 238 | |
55616e44 BN |
239 | phy_exit(dwc->usb3_generic_phy); |
240 | phy_exit(dwc->usb2_generic_phy); | |
241 | ||
f59dcab1 | 242 | return -ETIMEDOUT; |
922b9e0d TN |
243 | |
244 | done: | |
245 | /* | |
246 | * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared, | |
247 | * we must wait at least 50ms before accessing the PHY domain | |
248 | * (synchronization delay). DWC_usb31 programming guide section 1.3.2. | |
249 | */ | |
250 | if (dwc3_is_usb31(dwc)) | |
251 | msleep(50); | |
252 | ||
253 | return 0; | |
72246da4 FB |
254 | } |
255 | ||
db2be4e9 NB |
256 | /* |
257 | * dwc3_frame_length_adjustment - Adjusts frame length if required | |
258 | * @dwc3: Pointer to our controller context structure | |
db2be4e9 | 259 | */ |
bcdb3272 | 260 | static void dwc3_frame_length_adjustment(struct dwc3 *dwc) |
db2be4e9 NB |
261 | { |
262 | u32 reg; | |
263 | u32 dft; | |
264 | ||
265 | if (dwc->revision < DWC3_REVISION_250A) | |
266 | return; | |
267 | ||
bcdb3272 | 268 | if (dwc->fladj == 0) |
db2be4e9 NB |
269 | return; |
270 | ||
271 | reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); | |
272 | dft = reg & DWC3_GFLADJ_30MHZ_MASK; | |
02d8adb3 | 273 | if (dft != dwc->fladj) { |
db2be4e9 | 274 | reg &= ~DWC3_GFLADJ_30MHZ_MASK; |
bcdb3272 | 275 | reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; |
db2be4e9 NB |
276 | dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); |
277 | } | |
278 | } | |
279 | ||
72246da4 FB |
280 | /** |
281 | * dwc3_free_one_event_buffer - Frees one event buffer | |
282 | * @dwc: Pointer to our controller context structure | |
283 | * @evt: Pointer to event buffer to be freed | |
284 | */ | |
285 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
286 | struct dwc3_event_buffer *evt) | |
287 | { | |
d64ff406 | 288 | dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); |
72246da4 FB |
289 | } |
290 | ||
291 | /** | |
1d046793 | 292 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
293 | * @dwc: Pointer to our controller context structure |
294 | * @length: size of the event buffer | |
295 | * | |
1d046793 | 296 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
297 | * otherwise ERR_PTR(errno). |
298 | */ | |
67d0b500 FB |
299 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
300 | unsigned length) | |
72246da4 FB |
301 | { |
302 | struct dwc3_event_buffer *evt; | |
303 | ||
380f0d28 | 304 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
305 | if (!evt) |
306 | return ERR_PTR(-ENOMEM); | |
307 | ||
308 | evt->dwc = dwc; | |
309 | evt->length = length; | |
d9fa4c63 JY |
310 | evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); |
311 | if (!evt->cache) | |
312 | return ERR_PTR(-ENOMEM); | |
313 | ||
d64ff406 | 314 | evt->buf = dma_alloc_coherent(dwc->sysdev, length, |
72246da4 | 315 | &evt->dma, GFP_KERNEL); |
e32672f0 | 316 | if (!evt->buf) |
72246da4 | 317 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
318 | |
319 | return evt; | |
320 | } | |
321 | ||
322 | /** | |
323 | * dwc3_free_event_buffers - frees all allocated event buffers | |
324 | * @dwc: Pointer to our controller context structure | |
325 | */ | |
326 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
327 | { | |
328 | struct dwc3_event_buffer *evt; | |
72246da4 | 329 | |
696c8b12 | 330 | evt = dwc->ev_buf; |
660e9bde FB |
331 | if (evt) |
332 | dwc3_free_one_event_buffer(dwc, evt); | |
72246da4 FB |
333 | } |
334 | ||
335 | /** | |
336 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 337 | * @dwc: pointer to our controller context structure |
72246da4 FB |
338 | * @length: size of event buffer |
339 | * | |
1d046793 | 340 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
341 | * may contain some buffers allocated but not all which were requested. |
342 | */ | |
41ac7b3a | 343 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 344 | { |
660e9bde | 345 | struct dwc3_event_buffer *evt; |
72246da4 | 346 | |
660e9bde FB |
347 | evt = dwc3_alloc_one_event_buffer(dwc, length); |
348 | if (IS_ERR(evt)) { | |
349 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
350 | return PTR_ERR(evt); | |
72246da4 | 351 | } |
696c8b12 | 352 | dwc->ev_buf = evt; |
72246da4 FB |
353 | |
354 | return 0; | |
355 | } | |
356 | ||
357 | /** | |
358 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 359 | * @dwc: pointer to our controller context structure |
72246da4 FB |
360 | * |
361 | * Returns 0 on success otherwise negative errno. | |
362 | */ | |
7acd85e0 | 363 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
364 | { |
365 | struct dwc3_event_buffer *evt; | |
72246da4 | 366 | |
696c8b12 | 367 | evt = dwc->ev_buf; |
660e9bde | 368 | evt->lpos = 0; |
660e9bde FB |
369 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), |
370 | lower_32_bits(evt->dma)); | |
371 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), | |
372 | upper_32_bits(evt->dma)); | |
373 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), | |
374 | DWC3_GEVNTSIZ_SIZE(evt->length)); | |
375 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
376 | |
377 | return 0; | |
378 | } | |
379 | ||
380 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
381 | { | |
382 | struct dwc3_event_buffer *evt; | |
72246da4 | 383 | |
696c8b12 | 384 | evt = dwc->ev_buf; |
7acd85e0 | 385 | |
660e9bde | 386 | evt->lpos = 0; |
7acd85e0 | 387 | |
660e9bde FB |
388 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); |
389 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); | |
390 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK | |
391 | | DWC3_GEVNTSIZ_SIZE(0)); | |
392 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); | |
72246da4 FB |
393 | } |
394 | ||
0ffcaf37 FB |
395 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
396 | { | |
397 | if (!dwc->has_hibernation) | |
398 | return 0; | |
399 | ||
400 | if (!dwc->nr_scratch) | |
401 | return 0; | |
402 | ||
403 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
404 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
405 | if (!dwc->scratchbuf) | |
406 | return -ENOMEM; | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
411 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
412 | { | |
413 | dma_addr_t scratch_addr; | |
414 | u32 param; | |
415 | int ret; | |
416 | ||
417 | if (!dwc->has_hibernation) | |
418 | return 0; | |
419 | ||
420 | if (!dwc->nr_scratch) | |
421 | return 0; | |
422 | ||
423 | /* should never fall here */ | |
424 | if (!WARN_ON(dwc->scratchbuf)) | |
425 | return 0; | |
426 | ||
d64ff406 | 427 | scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, |
0ffcaf37 FB |
428 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, |
429 | DMA_BIDIRECTIONAL); | |
d64ff406 AB |
430 | if (dma_mapping_error(dwc->sysdev, scratch_addr)) { |
431 | dev_err(dwc->sysdev, "failed to map scratch buffer\n"); | |
0ffcaf37 FB |
432 | ret = -EFAULT; |
433 | goto err0; | |
434 | } | |
435 | ||
436 | dwc->scratch_addr = scratch_addr; | |
437 | ||
438 | param = lower_32_bits(scratch_addr); | |
439 | ||
440 | ret = dwc3_send_gadget_generic_command(dwc, | |
441 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
442 | if (ret < 0) | |
443 | goto err1; | |
444 | ||
445 | param = upper_32_bits(scratch_addr); | |
446 | ||
447 | ret = dwc3_send_gadget_generic_command(dwc, | |
448 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
449 | if (ret < 0) | |
450 | goto err1; | |
451 | ||
452 | return 0; | |
453 | ||
454 | err1: | |
d64ff406 | 455 | dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * |
0ffcaf37 FB |
456 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); |
457 | ||
458 | err0: | |
459 | return ret; | |
460 | } | |
461 | ||
462 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
463 | { | |
464 | if (!dwc->has_hibernation) | |
465 | return; | |
466 | ||
467 | if (!dwc->nr_scratch) | |
468 | return; | |
469 | ||
470 | /* should never fall here */ | |
471 | if (!WARN_ON(dwc->scratchbuf)) | |
472 | return; | |
473 | ||
d64ff406 | 474 | dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * |
0ffcaf37 FB |
475 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); |
476 | kfree(dwc->scratchbuf); | |
477 | } | |
478 | ||
789451f6 FB |
479 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
480 | { | |
481 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
482 | ||
47d3946e | 483 | dwc->num_eps = DWC3_NUM_EPS(parms); |
789451f6 FB |
484 | } |
485 | ||
41ac7b3a | 486 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
487 | { |
488 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
489 | ||
490 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
491 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
492 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
493 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
494 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
495 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
496 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
497 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
498 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
499 | } | |
500 | ||
12882e86 RQ |
501 | static int dwc3_core_ulpi_init(struct dwc3 *dwc) |
502 | { | |
503 | int intf; | |
504 | int ret = 0; | |
505 | ||
506 | intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); | |
507 | ||
508 | if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || | |
509 | (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && | |
510 | dwc->hsphy_interface && | |
511 | !strncmp(dwc->hsphy_interface, "ulpi", 4))) | |
512 | ret = dwc3_ulpi_init(dwc); | |
513 | ||
514 | return ret; | |
515 | } | |
516 | ||
b5a65c40 HR |
517 | /** |
518 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
519 | * @dwc: Pointer to our controller context structure | |
88bc9d19 HK |
520 | * |
521 | * Returns 0 on success. The USB PHY interfaces are configured but not | |
522 | * initialized. The PHY interfaces and the PHYs get initialized together with | |
523 | * the core in dwc3_core_init. | |
b5a65c40 | 524 | */ |
88bc9d19 | 525 | static int dwc3_phy_setup(struct dwc3 *dwc) |
b5a65c40 HR |
526 | { |
527 | u32 reg; | |
528 | ||
529 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
530 | ||
1966b865 FB |
531 | /* |
532 | * Make sure UX_EXIT_PX is cleared as that causes issues with some | |
533 | * PHYs. Also, this bit is not supposed to be used in normal operation. | |
534 | */ | |
535 | reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; | |
536 | ||
2164a476 HR |
537 | /* |
538 | * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY | |
539 | * to '0' during coreConsultant configuration. So default value | |
540 | * will be '0' when the core is reset. Application needs to set it | |
541 | * to '1' after the core initialization is completed. | |
542 | */ | |
543 | if (dwc->revision > DWC3_REVISION_194A) | |
544 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
545 | ||
b5a65c40 HR |
546 | if (dwc->u2ss_inp3_quirk) |
547 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
548 | ||
e58dd357 RB |
549 | if (dwc->dis_rxdet_inp3_quirk) |
550 | reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; | |
551 | ||
df31f5b3 HR |
552 | if (dwc->req_p1p2p3_quirk) |
553 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
554 | ||
a2a1d0f5 HR |
555 | if (dwc->del_p1p2p3_quirk) |
556 | reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; | |
557 | ||
41c06ffd HR |
558 | if (dwc->del_phy_power_chg_quirk) |
559 | reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
560 | ||
fb67afca HR |
561 | if (dwc->lfps_filter_quirk) |
562 | reg |= DWC3_GUSB3PIPECTL_LFPSFILT; | |
563 | ||
14f4ac53 HR |
564 | if (dwc->rx_detect_poll_quirk) |
565 | reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; | |
566 | ||
6b6a0c9a HR |
567 | if (dwc->tx_de_emphasis_quirk) |
568 | reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); | |
569 | ||
cd72f890 | 570 | if (dwc->dis_u3_susphy_quirk) |
59acfa20 HR |
571 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; |
572 | ||
00fe081d WW |
573 | if (dwc->dis_del_phy_power_chg_quirk) |
574 | reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
575 | ||
b5a65c40 HR |
576 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
577 | ||
2164a476 HR |
578 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
579 | ||
3e10a2ce HK |
580 | /* Select the HS PHY interface */ |
581 | switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { | |
582 | case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: | |
43cacb03 FB |
583 | if (dwc->hsphy_interface && |
584 | !strncmp(dwc->hsphy_interface, "utmi", 4)) { | |
3e10a2ce | 585 | reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 586 | break; |
43cacb03 FB |
587 | } else if (dwc->hsphy_interface && |
588 | !strncmp(dwc->hsphy_interface, "ulpi", 4)) { | |
3e10a2ce | 589 | reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 590 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
3e10a2ce | 591 | } else { |
88bc9d19 HK |
592 | /* Relying on default value. */ |
593 | if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) | |
594 | break; | |
3e10a2ce HK |
595 | } |
596 | /* FALLTHROUGH */ | |
88bc9d19 | 597 | case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: |
88bc9d19 | 598 | /* FALLTHROUGH */ |
3e10a2ce HK |
599 | default: |
600 | break; | |
601 | } | |
602 | ||
32f2ed86 WW |
603 | switch (dwc->hsphy_mode) { |
604 | case USBPHY_INTERFACE_MODE_UTMI: | |
605 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
606 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
607 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | | |
608 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); | |
609 | break; | |
610 | case USBPHY_INTERFACE_MODE_UTMIW: | |
611 | reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | | |
612 | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); | |
613 | reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | | |
614 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); | |
615 | break; | |
616 | default: | |
617 | break; | |
618 | } | |
619 | ||
2164a476 HR |
620 | /* |
621 | * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to | |
622 | * '0' during coreConsultant configuration. So default value will | |
623 | * be '0' when the core is reset. Application needs to set it to | |
624 | * '1' after the core initialization is completed. | |
625 | */ | |
626 | if (dwc->revision > DWC3_REVISION_194A) | |
627 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
628 | ||
cd72f890 | 629 | if (dwc->dis_u2_susphy_quirk) |
0effe0a3 HR |
630 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
631 | ||
ec791d14 JY |
632 | if (dwc->dis_enblslpm_quirk) |
633 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
634 | ||
16199f33 WW |
635 | if (dwc->dis_u2_freeclk_exists_quirk) |
636 | reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; | |
637 | ||
2164a476 | 638 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
88bc9d19 HK |
639 | |
640 | return 0; | |
b5a65c40 HR |
641 | } |
642 | ||
c499ff71 FB |
643 | static void dwc3_core_exit(struct dwc3 *dwc) |
644 | { | |
645 | dwc3_event_buffers_cleanup(dwc); | |
646 | ||
647 | usb_phy_shutdown(dwc->usb2_phy); | |
648 | usb_phy_shutdown(dwc->usb3_phy); | |
649 | phy_exit(dwc->usb2_generic_phy); | |
650 | phy_exit(dwc->usb3_generic_phy); | |
651 | ||
652 | usb_phy_set_suspend(dwc->usb2_phy, 1); | |
653 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
654 | phy_power_off(dwc->usb2_generic_phy); | |
655 | phy_power_off(dwc->usb3_generic_phy); | |
656 | } | |
657 | ||
0759956f | 658 | static bool dwc3_core_is_valid(struct dwc3 *dwc) |
72246da4 | 659 | { |
0759956f | 660 | u32 reg; |
72246da4 | 661 | |
7650bd74 | 662 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
0759956f | 663 | |
7650bd74 | 664 | /* This should read as U3 followed by revision number */ |
690fb371 JY |
665 | if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { |
666 | /* Detected DWC_usb3 IP */ | |
667 | dwc->revision = reg; | |
668 | } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { | |
669 | /* Detected DWC_usb31 IP */ | |
670 | dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); | |
671 | dwc->revision |= DWC3_REVISION_IS_DWC31; | |
672 | } else { | |
0759956f | 673 | return false; |
7650bd74 | 674 | } |
7650bd74 | 675 | |
0759956f FB |
676 | return true; |
677 | } | |
58a0f23f | 678 | |
941f918e | 679 | static void dwc3_core_setup_global_control(struct dwc3 *dwc) |
0759956f | 680 | { |
941f918e FB |
681 | u32 hwparams4 = dwc->hwparams.hwparams4; |
682 | u32 reg; | |
c499ff71 | 683 | |
4878a028 | 684 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 685 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 | 686 | |
164d7731 | 687 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 688 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
689 | /** |
690 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
691 | * issue which would cause xHCI compliance tests to fail. | |
692 | * | |
693 | * Because of that we cannot enable clock gating on such | |
694 | * configurations. | |
695 | * | |
696 | * Refers to: | |
697 | * | |
698 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
699 | * SOF/ITP Mode Used | |
700 | */ | |
701 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
702 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
703 | (dwc->revision >= DWC3_REVISION_210A && | |
704 | dwc->revision <= DWC3_REVISION_250A)) | |
705 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
706 | else | |
707 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 708 | break; |
0ffcaf37 FB |
709 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
710 | /* enable hibernation here */ | |
711 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
2eac3992 HR |
712 | |
713 | /* | |
714 | * REVISIT Enabling this bit so that host-mode hibernation | |
715 | * will work. Device-mode hibernation is not yet implemented. | |
716 | */ | |
717 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
0ffcaf37 | 718 | break; |
4878a028 | 719 | default: |
5eb30ced FB |
720 | /* nothing */ |
721 | break; | |
4878a028 SAS |
722 | } |
723 | ||
946bd579 HR |
724 | /* check if current dwc3 is on simulation board */ |
725 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
5eb30ced | 726 | dev_info(dwc->dev, "Running with FPGA optmizations\n"); |
946bd579 HR |
727 | dwc->is_fpga = true; |
728 | } | |
729 | ||
3b81221a HR |
730 | WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, |
731 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
732 | ||
733 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
734 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
735 | else | |
736 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
737 | ||
9a5b2f31 HR |
738 | if (dwc->u2exit_lfps_quirk) |
739 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
740 | ||
4878a028 SAS |
741 | /* |
742 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 743 | * where the device can fail to connect at SuperSpeed |
4878a028 | 744 | * and falls back to high-speed mode which causes |
1d046793 | 745 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
746 | */ |
747 | if (dwc->revision < DWC3_REVISION_190A) | |
748 | reg |= DWC3_GCTL_U2RSTECN; | |
749 | ||
750 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
941f918e FB |
751 | } |
752 | ||
f54edb53 | 753 | static int dwc3_core_get_phy(struct dwc3 *dwc); |
12882e86 | 754 | static int dwc3_core_ulpi_init(struct dwc3 *dwc); |
f54edb53 | 755 | |
941f918e FB |
756 | /** |
757 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
758 | * @dwc: Pointer to our controller context structure | |
759 | * | |
760 | * Returns 0 on success otherwise negative errno. | |
761 | */ | |
762 | static int dwc3_core_init(struct dwc3 *dwc) | |
763 | { | |
764 | u32 reg; | |
765 | int ret; | |
766 | ||
767 | if (!dwc3_core_is_valid(dwc)) { | |
768 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
769 | ret = -ENODEV; | |
770 | goto err0; | |
771 | } | |
772 | ||
773 | /* | |
774 | * Write Linux Version Code to our GUID register so it's easy to figure | |
775 | * out which kernel version a bug was found. | |
776 | */ | |
777 | dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); | |
778 | ||
779 | /* Handle USB2.0-only core configuration */ | |
780 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
781 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
782 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
783 | dwc->maximum_speed = USB_SPEED_HIGH; | |
784 | } | |
785 | ||
12882e86 | 786 | ret = dwc3_phy_setup(dwc); |
941f918e FB |
787 | if (ret) |
788 | goto err0; | |
4878a028 | 789 | |
12882e86 RQ |
790 | if (!dwc->ulpi_ready) { |
791 | ret = dwc3_core_ulpi_init(dwc); | |
792 | if (ret) | |
793 | goto err0; | |
794 | dwc->ulpi_ready = true; | |
795 | } | |
4878a028 | 796 | |
12882e86 RQ |
797 | if (!dwc->phys_ready) { |
798 | ret = dwc3_core_get_phy(dwc); | |
799 | if (ret) | |
800 | goto err0a; | |
801 | dwc->phys_ready = true; | |
802 | } | |
803 | ||
804 | ret = dwc3_core_soft_reset(dwc); | |
f54edb53 | 805 | if (ret) |
12882e86 | 806 | goto err0a; |
f54edb53 | 807 | |
941f918e | 808 | dwc3_core_setup_global_control(dwc); |
c499ff71 | 809 | dwc3_core_num_eps(dwc); |
0ffcaf37 FB |
810 | |
811 | ret = dwc3_setup_scratch_buffers(dwc); | |
812 | if (ret) | |
c499ff71 FB |
813 | goto err1; |
814 | ||
815 | /* Adjust Frame Length */ | |
816 | dwc3_frame_length_adjustment(dwc); | |
817 | ||
818 | usb_phy_set_suspend(dwc->usb2_phy, 0); | |
819 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
820 | ret = phy_power_on(dwc->usb2_generic_phy); | |
821 | if (ret < 0) | |
0ffcaf37 FB |
822 | goto err2; |
823 | ||
c499ff71 FB |
824 | ret = phy_power_on(dwc->usb3_generic_phy); |
825 | if (ret < 0) | |
826 | goto err3; | |
827 | ||
828 | ret = dwc3_event_buffers_setup(dwc); | |
829 | if (ret) { | |
830 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
831 | goto err4; | |
832 | } | |
833 | ||
06281d46 JY |
834 | /* |
835 | * ENDXFER polling is available on version 3.10a and later of | |
836 | * the DWC_usb3 controller. It is NOT available in the | |
837 | * DWC_usb31 controller. | |
838 | */ | |
839 | if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { | |
840 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); | |
841 | reg |= DWC3_GUCTL2_RST_ACTBITLATER; | |
842 | dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); | |
843 | } | |
844 | ||
65db7a0c | 845 | if (dwc->revision >= DWC3_REVISION_250A) { |
0bb39ca1 | 846 | reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); |
65db7a0c WW |
847 | |
848 | /* | |
849 | * Enable hardware control of sending remote wakeup | |
850 | * in HS when the device is in the L1 state. | |
851 | */ | |
852 | if (dwc->revision >= DWC3_REVISION_290A) | |
853 | reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; | |
854 | ||
855 | if (dwc->dis_tx_ipgap_linecheck_quirk) | |
856 | reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; | |
857 | ||
0bb39ca1 JY |
858 | dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); |
859 | } | |
860 | ||
72246da4 FB |
861 | return 0; |
862 | ||
c499ff71 | 863 | err4: |
9b9d7cdd | 864 | phy_power_off(dwc->usb3_generic_phy); |
c499ff71 FB |
865 | |
866 | err3: | |
9b9d7cdd | 867 | phy_power_off(dwc->usb2_generic_phy); |
c499ff71 | 868 | |
0ffcaf37 | 869 | err2: |
c499ff71 FB |
870 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
871 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
0ffcaf37 FB |
872 | |
873 | err1: | |
874 | usb_phy_shutdown(dwc->usb2_phy); | |
875 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
876 | phy_exit(dwc->usb2_generic_phy); |
877 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 878 | |
12882e86 RQ |
879 | err0a: |
880 | dwc3_ulpi_exit(dwc); | |
881 | ||
72246da4 FB |
882 | err0: |
883 | return ret; | |
884 | } | |
885 | ||
3c9f94ac | 886 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 887 | { |
3c9f94ac | 888 | struct device *dev = dwc->dev; |
941ea361 | 889 | struct device_node *node = dev->of_node; |
3c9f94ac | 890 | int ret; |
72246da4 | 891 | |
5088b6f5 KVA |
892 | if (node) { |
893 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
894 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
895 | } else { |
896 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
897 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
898 | } |
899 | ||
d105e7f8 FB |
900 | if (IS_ERR(dwc->usb2_phy)) { |
901 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
902 | if (ret == -ENXIO || ret == -ENODEV) { |
903 | dwc->usb2_phy = NULL; | |
904 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 905 | return ret; |
122f06e6 KVA |
906 | } else { |
907 | dev_err(dev, "no usb2 phy configured\n"); | |
908 | return ret; | |
909 | } | |
51e1e7bc FB |
910 | } |
911 | ||
d105e7f8 | 912 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 913 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
914 | if (ret == -ENXIO || ret == -ENODEV) { |
915 | dwc->usb3_phy = NULL; | |
916 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 917 | return ret; |
122f06e6 KVA |
918 | } else { |
919 | dev_err(dev, "no usb3 phy configured\n"); | |
920 | return ret; | |
921 | } | |
51e1e7bc FB |
922 | } |
923 | ||
57303488 KVA |
924 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
925 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
926 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
927 | if (ret == -ENOSYS || ret == -ENODEV) { | |
928 | dwc->usb2_generic_phy = NULL; | |
929 | } else if (ret == -EPROBE_DEFER) { | |
930 | return ret; | |
931 | } else { | |
932 | dev_err(dev, "no usb2 phy configured\n"); | |
933 | return ret; | |
934 | } | |
935 | } | |
936 | ||
937 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
938 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
939 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
940 | if (ret == -ENOSYS || ret == -ENODEV) { | |
941 | dwc->usb3_generic_phy = NULL; | |
942 | } else if (ret == -EPROBE_DEFER) { | |
943 | return ret; | |
944 | } else { | |
945 | dev_err(dev, "no usb3 phy configured\n"); | |
946 | return ret; | |
947 | } | |
948 | } | |
949 | ||
3c9f94ac FB |
950 | return 0; |
951 | } | |
952 | ||
5f94adfe FB |
953 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
954 | { | |
955 | struct device *dev = dwc->dev; | |
956 | int ret; | |
957 | ||
958 | switch (dwc->dr_mode) { | |
959 | case USB_DR_MODE_PERIPHERAL: | |
41ce1456 | 960 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
958d1a4c FB |
961 | |
962 | if (dwc->usb2_phy) | |
963 | otg_set_vbus(dwc->usb2_phy->otg, false); | |
644cbbc3 MG |
964 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); |
965 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); | |
958d1a4c | 966 | |
5f94adfe FB |
967 | ret = dwc3_gadget_init(dwc); |
968 | if (ret) { | |
9522def4 RQ |
969 | if (ret != -EPROBE_DEFER) |
970 | dev_err(dev, "failed to initialize gadget\n"); | |
5f94adfe FB |
971 | return ret; |
972 | } | |
973 | break; | |
974 | case USB_DR_MODE_HOST: | |
41ce1456 | 975 | dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); |
958d1a4c FB |
976 | |
977 | if (dwc->usb2_phy) | |
978 | otg_set_vbus(dwc->usb2_phy->otg, true); | |
644cbbc3 MG |
979 | phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); |
980 | phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); | |
958d1a4c | 981 | |
5f94adfe FB |
982 | ret = dwc3_host_init(dwc); |
983 | if (ret) { | |
9522def4 RQ |
984 | if (ret != -EPROBE_DEFER) |
985 | dev_err(dev, "failed to initialize host\n"); | |
5f94adfe FB |
986 | return ret; |
987 | } | |
988 | break; | |
989 | case USB_DR_MODE_OTG: | |
41ce1456 | 990 | INIT_WORK(&dwc->drd_work, __dwc3_set_mode); |
9840354f RQ |
991 | ret = dwc3_drd_init(dwc); |
992 | if (ret) { | |
993 | if (ret != -EPROBE_DEFER) | |
994 | dev_err(dev, "failed to initialize dual-role\n"); | |
995 | return ret; | |
996 | } | |
5f94adfe FB |
997 | break; |
998 | default: | |
999 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
1000 | return -EINVAL; | |
1001 | } | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
1007 | { | |
1008 | switch (dwc->dr_mode) { | |
1009 | case USB_DR_MODE_PERIPHERAL: | |
1010 | dwc3_gadget_exit(dwc); | |
1011 | break; | |
1012 | case USB_DR_MODE_HOST: | |
1013 | dwc3_host_exit(dwc); | |
1014 | break; | |
1015 | case USB_DR_MODE_OTG: | |
9840354f | 1016 | dwc3_drd_exit(dwc); |
5f94adfe FB |
1017 | break; |
1018 | default: | |
1019 | /* do nothing */ | |
1020 | break; | |
1021 | } | |
1022 | } | |
1023 | ||
c5ac6116 | 1024 | static void dwc3_get_properties(struct dwc3 *dwc) |
3c9f94ac | 1025 | { |
c5ac6116 | 1026 | struct device *dev = dwc->dev; |
80caf7d2 | 1027 | u8 lpm_nyet_threshold; |
6b6a0c9a | 1028 | u8 tx_de_emphasis; |
460d098c | 1029 | u8 hird_threshold; |
3c9f94ac | 1030 | |
80caf7d2 | 1031 | /* default to highest possible threshold */ |
d313505a | 1032 | lpm_nyet_threshold = 0xf; |
80caf7d2 | 1033 | |
6b6a0c9a HR |
1034 | /* default to -3.5dB de-emphasis */ |
1035 | tx_de_emphasis = 1; | |
1036 | ||
460d098c HR |
1037 | /* |
1038 | * default to assert utmi_sleep_n and use maximum allowed HIRD | |
1039 | * threshold value of 0b1100 | |
1040 | */ | |
1041 | hird_threshold = 12; | |
1042 | ||
63863b98 | 1043 | dwc->maximum_speed = usb_get_maximum_speed(dev); |
06e7114f | 1044 | dwc->dr_mode = usb_get_dr_mode(dev); |
32f2ed86 | 1045 | dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); |
63863b98 | 1046 | |
d64ff406 AB |
1047 | dwc->sysdev_is_parent = device_property_read_bool(dev, |
1048 | "linux,sysdev_is_parent"); | |
1049 | if (dwc->sysdev_is_parent) | |
1050 | dwc->sysdev = dwc->dev->parent; | |
1051 | else | |
1052 | dwc->sysdev = dwc->dev; | |
1053 | ||
3d128919 | 1054 | dwc->has_lpm_erratum = device_property_read_bool(dev, |
80caf7d2 | 1055 | "snps,has-lpm-erratum"); |
3d128919 | 1056 | device_property_read_u8(dev, "snps,lpm-nyet-threshold", |
80caf7d2 | 1057 | &lpm_nyet_threshold); |
3d128919 | 1058 | dwc->is_utmi_l1_suspend = device_property_read_bool(dev, |
460d098c | 1059 | "snps,is-utmi-l1-suspend"); |
3d128919 | 1060 | device_property_read_u8(dev, "snps,hird-threshold", |
460d098c | 1061 | &hird_threshold); |
3d128919 | 1062 | dwc->usb3_lpm_capable = device_property_read_bool(dev, |
eac68e8f | 1063 | "snps,usb3_lpm_capable"); |
3c9f94ac | 1064 | |
3d128919 | 1065 | dwc->disable_scramble_quirk = device_property_read_bool(dev, |
3b81221a | 1066 | "snps,disable_scramble_quirk"); |
3d128919 | 1067 | dwc->u2exit_lfps_quirk = device_property_read_bool(dev, |
9a5b2f31 | 1068 | "snps,u2exit_lfps_quirk"); |
3d128919 | 1069 | dwc->u2ss_inp3_quirk = device_property_read_bool(dev, |
b5a65c40 | 1070 | "snps,u2ss_inp3_quirk"); |
3d128919 | 1071 | dwc->req_p1p2p3_quirk = device_property_read_bool(dev, |
df31f5b3 | 1072 | "snps,req_p1p2p3_quirk"); |
3d128919 | 1073 | dwc->del_p1p2p3_quirk = device_property_read_bool(dev, |
a2a1d0f5 | 1074 | "snps,del_p1p2p3_quirk"); |
3d128919 | 1075 | dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, |
41c06ffd | 1076 | "snps,del_phy_power_chg_quirk"); |
3d128919 | 1077 | dwc->lfps_filter_quirk = device_property_read_bool(dev, |
fb67afca | 1078 | "snps,lfps_filter_quirk"); |
3d128919 | 1079 | dwc->rx_detect_poll_quirk = device_property_read_bool(dev, |
14f4ac53 | 1080 | "snps,rx_detect_poll_quirk"); |
3d128919 | 1081 | dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, |
59acfa20 | 1082 | "snps,dis_u3_susphy_quirk"); |
3d128919 | 1083 | dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, |
0effe0a3 | 1084 | "snps,dis_u2_susphy_quirk"); |
ec791d14 JY |
1085 | dwc->dis_enblslpm_quirk = device_property_read_bool(dev, |
1086 | "snps,dis_enblslpm_quirk"); | |
e58dd357 RB |
1087 | dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, |
1088 | "snps,dis_rxdet_inp3_quirk"); | |
16199f33 WW |
1089 | dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, |
1090 | "snps,dis-u2-freeclk-exists-quirk"); | |
00fe081d WW |
1091 | dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, |
1092 | "snps,dis-del-phy-power-chg-quirk"); | |
65db7a0c WW |
1093 | dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, |
1094 | "snps,dis-tx-ipgap-linecheck-quirk"); | |
6b6a0c9a | 1095 | |
3d128919 | 1096 | dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, |
6b6a0c9a | 1097 | "snps,tx_de_emphasis_quirk"); |
3d128919 | 1098 | device_property_read_u8(dev, "snps,tx_de_emphasis", |
6b6a0c9a | 1099 | &tx_de_emphasis); |
3d128919 HK |
1100 | device_property_read_string(dev, "snps,hsphy_interface", |
1101 | &dwc->hsphy_interface); | |
1102 | device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", | |
bcdb3272 | 1103 | &dwc->fladj); |
3d128919 | 1104 | |
b998c1bd RQ |
1105 | dwc->dis_metastability_quirk = device_property_read_bool(dev, |
1106 | "snps,dis_metastability_quirk"); | |
1107 | ||
80caf7d2 | 1108 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; |
6b6a0c9a | 1109 | dwc->tx_de_emphasis = tx_de_emphasis; |
80caf7d2 | 1110 | |
460d098c HR |
1111 | dwc->hird_threshold = hird_threshold |
1112 | | (dwc->is_utmi_l1_suspend << 4); | |
1113 | ||
cf40b86b JY |
1114 | dwc->imod_interval = 0; |
1115 | } | |
1116 | ||
1117 | /* check whether the core supports IMOD */ | |
1118 | bool dwc3_has_imod(struct dwc3 *dwc) | |
1119 | { | |
1120 | return ((dwc3_is_usb3(dwc) && | |
1121 | dwc->revision >= DWC3_REVISION_300A) || | |
1122 | (dwc3_is_usb31(dwc) && | |
1123 | dwc->revision >= DWC3_USB31_REVISION_120A)); | |
c5ac6116 FB |
1124 | } |
1125 | ||
7ac51a12 JY |
1126 | static void dwc3_check_params(struct dwc3 *dwc) |
1127 | { | |
1128 | struct device *dev = dwc->dev; | |
1129 | ||
cf40b86b JY |
1130 | /* Check for proper value of imod_interval */ |
1131 | if (dwc->imod_interval && !dwc3_has_imod(dwc)) { | |
1132 | dev_warn(dwc->dev, "Interrupt moderation not supported\n"); | |
1133 | dwc->imod_interval = 0; | |
1134 | } | |
1135 | ||
28632b44 JY |
1136 | /* |
1137 | * Workaround for STAR 9000961433 which affects only version | |
1138 | * 3.00a of the DWC_usb3 core. This prevents the controller | |
1139 | * interrupt from being masked while handling events. IMOD | |
1140 | * allows us to work around this issue. Enable it for the | |
1141 | * affected version. | |
1142 | */ | |
1143 | if (!dwc->imod_interval && | |
1144 | (dwc->revision == DWC3_REVISION_300A)) | |
1145 | dwc->imod_interval = 1; | |
1146 | ||
7ac51a12 JY |
1147 | /* Check the maximum_speed parameter */ |
1148 | switch (dwc->maximum_speed) { | |
1149 | case USB_SPEED_LOW: | |
1150 | case USB_SPEED_FULL: | |
1151 | case USB_SPEED_HIGH: | |
1152 | case USB_SPEED_SUPER: | |
1153 | case USB_SPEED_SUPER_PLUS: | |
1154 | break; | |
1155 | default: | |
1156 | dev_err(dev, "invalid maximum_speed parameter %d\n", | |
1157 | dwc->maximum_speed); | |
1158 | /* fall through */ | |
1159 | case USB_SPEED_UNKNOWN: | |
1160 | /* default to superspeed */ | |
1161 | dwc->maximum_speed = USB_SPEED_SUPER; | |
1162 | ||
1163 | /* | |
1164 | * default to superspeed plus if we are capable. | |
1165 | */ | |
1166 | if (dwc3_is_usb31(dwc) && | |
1167 | (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
1168 | DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) | |
1169 | dwc->maximum_speed = USB_SPEED_SUPER_PLUS; | |
1170 | ||
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | ||
c5ac6116 FB |
1175 | static int dwc3_probe(struct platform_device *pdev) |
1176 | { | |
1177 | struct device *dev = &pdev->dev; | |
1178 | struct resource *res; | |
1179 | struct dwc3 *dwc; | |
1180 | ||
1181 | int ret; | |
1182 | ||
1183 | void __iomem *regs; | |
1184 | ||
1185 | dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); | |
1186 | if (!dwc) | |
1187 | return -ENOMEM; | |
1188 | ||
1189 | dwc->dev = dev; | |
1190 | ||
1191 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1192 | if (!res) { | |
1193 | dev_err(dev, "missing memory resource\n"); | |
1194 | return -ENODEV; | |
1195 | } | |
1196 | ||
1197 | dwc->xhci_resources[0].start = res->start; | |
1198 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
1199 | DWC3_XHCI_REGS_END; | |
1200 | dwc->xhci_resources[0].flags = res->flags; | |
1201 | dwc->xhci_resources[0].name = res->name; | |
1202 | ||
1203 | res->start += DWC3_GLOBALS_REGS_START; | |
1204 | ||
1205 | /* | |
1206 | * Request memory region but exclude xHCI regs, | |
1207 | * since it will be requested by the xhci-plat driver. | |
1208 | */ | |
1209 | regs = devm_ioremap_resource(dev, res); | |
1210 | if (IS_ERR(regs)) { | |
1211 | ret = PTR_ERR(regs); | |
1212 | goto err0; | |
1213 | } | |
1214 | ||
1215 | dwc->regs = regs; | |
1216 | dwc->regs_size = resource_size(res); | |
1217 | ||
1218 | dwc3_get_properties(dwc); | |
1219 | ||
6c89cce0 | 1220 | platform_set_drvdata(pdev, dwc); |
2917e718 | 1221 | dwc3_cache_hwparams(dwc); |
6c89cce0 | 1222 | |
72246da4 | 1223 | spin_lock_init(&dwc->lock); |
72246da4 | 1224 | |
fc8bb91b FB |
1225 | pm_runtime_set_active(dev); |
1226 | pm_runtime_use_autosuspend(dev); | |
1227 | pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); | |
802ca850 | 1228 | pm_runtime_enable(dev); |
32808237 RQ |
1229 | ret = pm_runtime_get_sync(dev); |
1230 | if (ret < 0) | |
1231 | goto err1; | |
1232 | ||
802ca850 | 1233 | pm_runtime_forbid(dev); |
72246da4 | 1234 | |
3921426b FB |
1235 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
1236 | if (ret) { | |
1237 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
1238 | ret = -ENOMEM; | |
32808237 | 1239 | goto err2; |
3921426b FB |
1240 | } |
1241 | ||
9d6173e1 TN |
1242 | ret = dwc3_get_dr_mode(dwc); |
1243 | if (ret) | |
1244 | goto err3; | |
32a4a135 | 1245 | |
c499ff71 FB |
1246 | ret = dwc3_alloc_scratch_buffers(dwc); |
1247 | if (ret) | |
32808237 | 1248 | goto err3; |
c499ff71 | 1249 | |
72246da4 FB |
1250 | ret = dwc3_core_init(dwc); |
1251 | if (ret) { | |
ff14139d BN |
1252 | if (ret != -EPROBE_DEFER) |
1253 | dev_err(dev, "failed to initialize core: %d\n", ret); | |
32808237 | 1254 | goto err4; |
72246da4 FB |
1255 | } |
1256 | ||
7ac51a12 | 1257 | dwc3_check_params(dwc); |
2c7f1bd9 | 1258 | |
5f94adfe FB |
1259 | ret = dwc3_core_init_mode(dwc); |
1260 | if (ret) | |
32808237 | 1261 | goto err5; |
72246da4 | 1262 | |
4e9f3118 | 1263 | dwc3_debugfs_init(dwc); |
fc8bb91b | 1264 | pm_runtime_put(dev); |
72246da4 FB |
1265 | |
1266 | return 0; | |
1267 | ||
32808237 | 1268 | err5: |
c499ff71 | 1269 | dwc3_event_buffers_cleanup(dwc); |
2579ffe0 | 1270 | dwc3_ulpi_exit(dwc); |
57303488 | 1271 | |
32808237 | 1272 | err4: |
c499ff71 | 1273 | dwc3_free_scratch_buffers(dwc); |
72246da4 | 1274 | |
32808237 | 1275 | err3: |
3921426b FB |
1276 | dwc3_free_event_buffers(dwc); |
1277 | ||
32808237 RQ |
1278 | err2: |
1279 | pm_runtime_allow(&pdev->dev); | |
1280 | ||
1281 | err1: | |
1282 | pm_runtime_put_sync(&pdev->dev); | |
1283 | pm_runtime_disable(&pdev->dev); | |
1284 | ||
3da1f6ee FB |
1285 | err0: |
1286 | /* | |
1287 | * restore res->start back to its original value so that, in case the | |
1288 | * probe is deferred, we don't end up getting error in request the | |
1289 | * memory region the next time probe is called. | |
1290 | */ | |
1291 | res->start -= DWC3_GLOBALS_REGS_START; | |
1292 | ||
72246da4 FB |
1293 | return ret; |
1294 | } | |
1295 | ||
fb4e98ab | 1296 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 1297 | { |
72246da4 | 1298 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
3da1f6ee FB |
1299 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1300 | ||
fc8bb91b | 1301 | pm_runtime_get_sync(&pdev->dev); |
3da1f6ee FB |
1302 | /* |
1303 | * restore res->start back to its original value so that, in case the | |
1304 | * probe is deferred, we don't end up getting error in request the | |
1305 | * memory region the next time probe is called. | |
1306 | */ | |
1307 | res->start -= DWC3_GLOBALS_REGS_START; | |
72246da4 | 1308 | |
dc99f16f FB |
1309 | dwc3_debugfs_exit(dwc); |
1310 | dwc3_core_exit_mode(dwc); | |
8ba007a9 | 1311 | |
72246da4 | 1312 | dwc3_core_exit(dwc); |
88bc9d19 | 1313 | dwc3_ulpi_exit(dwc); |
72246da4 | 1314 | |
16b972a5 | 1315 | pm_runtime_put_sync(&pdev->dev); |
fc8bb91b | 1316 | pm_runtime_allow(&pdev->dev); |
72246da4 FB |
1317 | pm_runtime_disable(&pdev->dev); |
1318 | ||
fc8bb91b FB |
1319 | dwc3_free_event_buffers(dwc); |
1320 | dwc3_free_scratch_buffers(dwc); | |
1321 | ||
72246da4 FB |
1322 | return 0; |
1323 | } | |
1324 | ||
fc8bb91b | 1325 | #ifdef CONFIG_PM |
04c51994 | 1326 | static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) |
7415f17c | 1327 | { |
fc8bb91b | 1328 | unsigned long flags; |
7415f17c | 1329 | |
689bf72c MG |
1330 | switch (dwc->current_dr_role) { |
1331 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fc8bb91b | 1332 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1333 | dwc3_gadget_suspend(dwc); |
fc8bb91b | 1334 | spin_unlock_irqrestore(&dwc->lock, flags); |
689bf72c | 1335 | dwc3_core_exit(dwc); |
51f5d49a | 1336 | break; |
689bf72c | 1337 | case DWC3_GCTL_PRTCAP_HOST: |
04c51994 MG |
1338 | /* do nothing during host runtime_suspend */ |
1339 | if (!PMSG_IS_AUTO(msg)) | |
1340 | dwc3_core_exit(dwc); | |
1341 | break; | |
7415f17c | 1342 | default: |
51f5d49a | 1343 | /* do nothing */ |
7415f17c FB |
1344 | break; |
1345 | } | |
1346 | ||
7415f17c FB |
1347 | return 0; |
1348 | } | |
1349 | ||
04c51994 | 1350 | static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) |
7415f17c | 1351 | { |
fc8bb91b | 1352 | unsigned long flags; |
57303488 | 1353 | int ret; |
7415f17c | 1354 | |
689bf72c MG |
1355 | switch (dwc->current_dr_role) { |
1356 | case DWC3_GCTL_PRTCAP_DEVICE: | |
1357 | ret = dwc3_core_init(dwc); | |
1358 | if (ret) | |
1359 | return ret; | |
5c4ad318 | 1360 | |
fc8bb91b | 1361 | spin_lock_irqsave(&dwc->lock, flags); |
7415f17c | 1362 | dwc3_gadget_resume(dwc); |
fc8bb91b | 1363 | spin_unlock_irqrestore(&dwc->lock, flags); |
689bf72c MG |
1364 | break; |
1365 | case DWC3_GCTL_PRTCAP_HOST: | |
04c51994 MG |
1366 | /* nothing to do on host runtime_resume */ |
1367 | if (!PMSG_IS_AUTO(msg)) { | |
1368 | ret = dwc3_core_init(dwc); | |
1369 | if (ret) | |
1370 | return ret; | |
1371 | } | |
1372 | break; | |
7415f17c FB |
1373 | default: |
1374 | /* do nothing */ | |
1375 | break; | |
1376 | } | |
1377 | ||
fc8bb91b FB |
1378 | return 0; |
1379 | } | |
1380 | ||
1381 | static int dwc3_runtime_checks(struct dwc3 *dwc) | |
1382 | { | |
689bf72c | 1383 | switch (dwc->current_dr_role) { |
04c51994 | 1384 | case DWC3_GCTL_PRTCAP_DEVICE: |
fc8bb91b FB |
1385 | if (dwc->connected) |
1386 | return -EBUSY; | |
1387 | break; | |
04c51994 | 1388 | case DWC3_GCTL_PRTCAP_HOST: |
fc8bb91b FB |
1389 | default: |
1390 | /* do nothing */ | |
1391 | break; | |
1392 | } | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
1397 | static int dwc3_runtime_suspend(struct device *dev) | |
1398 | { | |
1399 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1400 | int ret; | |
1401 | ||
1402 | if (dwc3_runtime_checks(dwc)) | |
1403 | return -EBUSY; | |
1404 | ||
04c51994 | 1405 | ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); |
fc8bb91b FB |
1406 | if (ret) |
1407 | return ret; | |
1408 | ||
1409 | device_init_wakeup(dev, true); | |
1410 | ||
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | static int dwc3_runtime_resume(struct device *dev) | |
1415 | { | |
1416 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1417 | int ret; | |
1418 | ||
1419 | device_init_wakeup(dev, false); | |
1420 | ||
04c51994 | 1421 | ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); |
fc8bb91b FB |
1422 | if (ret) |
1423 | return ret; | |
1424 | ||
689bf72c MG |
1425 | switch (dwc->current_dr_role) { |
1426 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fc8bb91b FB |
1427 | dwc3_gadget_process_pending_events(dwc); |
1428 | break; | |
689bf72c | 1429 | case DWC3_GCTL_PRTCAP_HOST: |
fc8bb91b FB |
1430 | default: |
1431 | /* do nothing */ | |
1432 | break; | |
1433 | } | |
1434 | ||
1435 | pm_runtime_mark_last_busy(dev); | |
1436 | ||
1437 | return 0; | |
1438 | } | |
1439 | ||
1440 | static int dwc3_runtime_idle(struct device *dev) | |
1441 | { | |
1442 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1443 | ||
689bf72c MG |
1444 | switch (dwc->current_dr_role) { |
1445 | case DWC3_GCTL_PRTCAP_DEVICE: | |
fc8bb91b FB |
1446 | if (dwc3_runtime_checks(dwc)) |
1447 | return -EBUSY; | |
1448 | break; | |
689bf72c | 1449 | case DWC3_GCTL_PRTCAP_HOST: |
fc8bb91b FB |
1450 | default: |
1451 | /* do nothing */ | |
1452 | break; | |
1453 | } | |
1454 | ||
1455 | pm_runtime_mark_last_busy(dev); | |
1456 | pm_runtime_autosuspend(dev); | |
1457 | ||
1458 | return 0; | |
1459 | } | |
1460 | #endif /* CONFIG_PM */ | |
1461 | ||
1462 | #ifdef CONFIG_PM_SLEEP | |
1463 | static int dwc3_suspend(struct device *dev) | |
1464 | { | |
1465 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1466 | int ret; | |
1467 | ||
04c51994 | 1468 | ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); |
fc8bb91b FB |
1469 | if (ret) |
1470 | return ret; | |
1471 | ||
1472 | pinctrl_pm_select_sleep_state(dev); | |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static int dwc3_resume(struct device *dev) | |
1478 | { | |
1479 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1480 | int ret; | |
1481 | ||
1482 | pinctrl_pm_select_default_state(dev); | |
1483 | ||
04c51994 | 1484 | ret = dwc3_resume_common(dwc, PMSG_RESUME); |
fc8bb91b FB |
1485 | if (ret) |
1486 | return ret; | |
1487 | ||
7415f17c FB |
1488 | pm_runtime_disable(dev); |
1489 | pm_runtime_set_active(dev); | |
1490 | pm_runtime_enable(dev); | |
1491 | ||
1492 | return 0; | |
1493 | } | |
7f370ed0 | 1494 | #endif /* CONFIG_PM_SLEEP */ |
7415f17c FB |
1495 | |
1496 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
7415f17c | 1497 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) |
fc8bb91b FB |
1498 | SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, |
1499 | dwc3_runtime_idle) | |
7415f17c FB |
1500 | }; |
1501 | ||
5088b6f5 KVA |
1502 | #ifdef CONFIG_OF |
1503 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
1504 | { |
1505 | .compatible = "snps,dwc3" | |
1506 | }, | |
5088b6f5 KVA |
1507 | { |
1508 | .compatible = "synopsys,dwc3" | |
1509 | }, | |
1510 | { }, | |
1511 | }; | |
1512 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
1513 | #endif | |
1514 | ||
404905a6 HK |
1515 | #ifdef CONFIG_ACPI |
1516 | ||
1517 | #define ACPI_ID_INTEL_BSW "808622B7" | |
1518 | ||
1519 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
1520 | { ACPI_ID_INTEL_BSW, 0 }, | |
1521 | { }, | |
1522 | }; | |
1523 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
1524 | #endif | |
1525 | ||
72246da4 FB |
1526 | static struct platform_driver dwc3_driver = { |
1527 | .probe = dwc3_probe, | |
7690417d | 1528 | .remove = dwc3_remove, |
72246da4 FB |
1529 | .driver = { |
1530 | .name = "dwc3", | |
5088b6f5 | 1531 | .of_match_table = of_match_ptr(of_dwc3_match), |
404905a6 | 1532 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), |
7f370ed0 | 1533 | .pm = &dwc3_dev_pm_ops, |
72246da4 | 1534 | }, |
72246da4 FB |
1535 | }; |
1536 | ||
b1116dcc TK |
1537 | module_platform_driver(dwc3_driver); |
1538 | ||
7ae4fc4d | 1539 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 1540 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 1541 | MODULE_LICENSE("GPL v2"); |
72246da4 | 1542 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |