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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
66d4eadd SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
66d4eadd SS |
9 | */ |
10 | ||
11 | #include <linux/usb.h> | |
0ebbab37 | 12 | #include <linux/pci.h> |
5a0e3ad6 | 13 | #include <linux/slab.h> |
527c6d7f | 14 | #include <linux/dmapool.h> |
008eb957 | 15 | #include <linux/dma-mapping.h> |
66d4eadd SS |
16 | |
17 | #include "xhci.h" | |
3a7fa5be | 18 | #include "xhci-trace.h" |
02b6fdc2 | 19 | #include "xhci-debugfs.h" |
66d4eadd | 20 | |
0ebbab37 SS |
21 | /* |
22 | * Allocates a generic ring segment from the ring pool, sets the dma address, | |
23 | * initializes the segment to zero, and sets the private next pointer to NULL. | |
24 | * | |
25 | * Section 4.11.1.1: | |
26 | * "All components of all Command and Transfer TRBs shall be initialized to '0'" | |
27 | */ | |
186a7ef1 | 28 | static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, |
f9c589e1 MN |
29 | unsigned int cycle_state, |
30 | unsigned int max_packet, | |
31 | gfp_t flags) | |
0ebbab37 SS |
32 | { |
33 | struct xhci_segment *seg; | |
34 | dma_addr_t dma; | |
186a7ef1 | 35 | int i; |
0ebbab37 SS |
36 | |
37 | seg = kzalloc(sizeof *seg, flags); | |
38 | if (!seg) | |
326b4810 | 39 | return NULL; |
0ebbab37 | 40 | |
84c1eeb0 | 41 | seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma); |
0ebbab37 SS |
42 | if (!seg->trbs) { |
43 | kfree(seg); | |
326b4810 | 44 | return NULL; |
0ebbab37 | 45 | } |
0ebbab37 | 46 | |
f9c589e1 | 47 | if (max_packet) { |
5db851cf | 48 | seg->bounce_buf = kzalloc(max_packet, flags); |
f9c589e1 MN |
49 | if (!seg->bounce_buf) { |
50 | dma_pool_free(xhci->segment_pool, seg->trbs, dma); | |
51 | kfree(seg); | |
52 | return NULL; | |
53 | } | |
54 | } | |
186a7ef1 AX |
55 | /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */ |
56 | if (cycle_state == 0) { | |
57 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
58719487 | 58 | seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE); |
186a7ef1 | 59 | } |
0ebbab37 SS |
60 | seg->dma = dma; |
61 | seg->next = NULL; | |
62 | ||
63 | return seg; | |
64 | } | |
65 | ||
66 | static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) | |
67 | { | |
0ebbab37 | 68 | if (seg->trbs) { |
0ebbab37 SS |
69 | dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); |
70 | seg->trbs = NULL; | |
71 | } | |
f9c589e1 | 72 | kfree(seg->bounce_buf); |
0ebbab37 SS |
73 | kfree(seg); |
74 | } | |
75 | ||
70d43601 AX |
76 | static void xhci_free_segments_for_ring(struct xhci_hcd *xhci, |
77 | struct xhci_segment *first) | |
78 | { | |
79 | struct xhci_segment *seg; | |
80 | ||
81 | seg = first->next; | |
82 | while (seg != first) { | |
83 | struct xhci_segment *next = seg->next; | |
84 | xhci_segment_free(xhci, seg); | |
85 | seg = next; | |
86 | } | |
87 | xhci_segment_free(xhci, first); | |
88 | } | |
89 | ||
0ebbab37 SS |
90 | /* |
91 | * Make the prev segment point to the next segment. | |
92 | * | |
93 | * Change the last TRB in the prev segment to be a Link TRB which points to the | |
94 | * DMA address of the next segment. The caller needs to set any Link TRB | |
95 | * related flags, such as End TRB, Toggle Cycle, and no snoop. | |
96 | */ | |
97 | static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, | |
3b72fca0 | 98 | struct xhci_segment *next, enum xhci_ring_type type) |
0ebbab37 SS |
99 | { |
100 | u32 val; | |
101 | ||
102 | if (!prev || !next) | |
103 | return; | |
104 | prev->next = next; | |
3b72fca0 | 105 | if (type != TYPE_EVENT) { |
f5960b69 ME |
106 | prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = |
107 | cpu_to_le64(next->dma); | |
0ebbab37 SS |
108 | |
109 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ | |
28ccd296 | 110 | val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); |
0ebbab37 SS |
111 | val &= ~TRB_TYPE_BITMASK; |
112 | val |= TRB_TYPE(TRB_LINK); | |
b0567b3f | 113 | /* Always set the chain bit with 0.95 hardware */ |
7e393a83 AX |
114 | /* Set chain bit for isoc rings on AMD 0.96 host */ |
115 | if (xhci_link_trb_quirk(xhci) || | |
3b72fca0 AX |
116 | (type == TYPE_ISOC && |
117 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
b0567b3f | 118 | val |= TRB_CHAIN; |
28ccd296 | 119 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); |
0ebbab37 | 120 | } |
0ebbab37 SS |
121 | } |
122 | ||
8dfec614 AX |
123 | /* |
124 | * Link the ring to the new segments. | |
125 | * Set Toggle Cycle for the new ring if needed. | |
126 | */ | |
127 | static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
128 | struct xhci_segment *first, struct xhci_segment *last, | |
129 | unsigned int num_segs) | |
130 | { | |
131 | struct xhci_segment *next; | |
132 | ||
133 | if (!ring || !first || !last) | |
134 | return; | |
135 | ||
136 | next = ring->enq_seg->next; | |
137 | xhci_link_segments(xhci, ring->enq_seg, first, ring->type); | |
138 | xhci_link_segments(xhci, last, next, ring->type); | |
139 | ring->num_segs += num_segs; | |
140 | ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs; | |
141 | ||
142 | if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) { | |
143 | ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control | |
144 | &= ~cpu_to_le32(LINK_TOGGLE); | |
145 | last->trbs[TRBS_PER_SEGMENT-1].link.control | |
146 | |= cpu_to_le32(LINK_TOGGLE); | |
147 | ring->last_seg = last; | |
148 | } | |
149 | } | |
150 | ||
15341303 GH |
151 | /* |
152 | * We need a radix tree for mapping physical addresses of TRBs to which stream | |
153 | * ID they belong to. We need to do this because the host controller won't tell | |
154 | * us which stream ring the TRB came from. We could store the stream ID in an | |
155 | * event data TRB, but that doesn't help us for the cancellation case, since the | |
156 | * endpoint may stop before it reaches that event data TRB. | |
157 | * | |
158 | * The radix tree maps the upper portion of the TRB DMA address to a ring | |
159 | * segment that has the same upper portion of DMA addresses. For example, say I | |
84c1e40f | 160 | * have segments of size 1KB, that are always 1KB aligned. A segment may |
15341303 GH |
161 | * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the |
162 | * key to the stream ID is 0x43244. I can use the DMA address of the TRB to | |
163 | * pass the radix tree a key to get the right stream ID: | |
164 | * | |
165 | * 0x10c90fff >> 10 = 0x43243 | |
166 | * 0x10c912c0 >> 10 = 0x43244 | |
167 | * 0x10c91400 >> 10 = 0x43245 | |
168 | * | |
169 | * Obviously, only those TRBs with DMA addresses that are within the segment | |
170 | * will make the radix tree return the stream ID for that ring. | |
171 | * | |
172 | * Caveats for the radix tree: | |
173 | * | |
174 | * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an | |
175 | * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be | |
176 | * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the | |
177 | * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit | |
178 | * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit | |
179 | * extended systems (where the DMA address can be bigger than 32-bits), | |
180 | * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. | |
181 | */ | |
d5734223 SS |
182 | static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map, |
183 | struct xhci_ring *ring, | |
184 | struct xhci_segment *seg, | |
185 | gfp_t mem_flags) | |
15341303 | 186 | { |
15341303 GH |
187 | unsigned long key; |
188 | int ret; | |
189 | ||
d5734223 SS |
190 | key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); |
191 | /* Skip any segments that were already added. */ | |
192 | if (radix_tree_lookup(trb_address_map, key)) | |
15341303 GH |
193 | return 0; |
194 | ||
d5734223 SS |
195 | ret = radix_tree_maybe_preload(mem_flags); |
196 | if (ret) | |
197 | return ret; | |
198 | ret = radix_tree_insert(trb_address_map, | |
199 | key, ring); | |
200 | radix_tree_preload_end(); | |
201 | return ret; | |
202 | } | |
15341303 | 203 | |
d5734223 SS |
204 | static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map, |
205 | struct xhci_segment *seg) | |
206 | { | |
207 | unsigned long key; | |
208 | ||
209 | key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); | |
210 | if (radix_tree_lookup(trb_address_map, key)) | |
211 | radix_tree_delete(trb_address_map, key); | |
212 | } | |
213 | ||
214 | static int xhci_update_stream_segment_mapping( | |
215 | struct radix_tree_root *trb_address_map, | |
216 | struct xhci_ring *ring, | |
217 | struct xhci_segment *first_seg, | |
218 | struct xhci_segment *last_seg, | |
219 | gfp_t mem_flags) | |
220 | { | |
221 | struct xhci_segment *seg; | |
222 | struct xhci_segment *failed_seg; | |
223 | int ret; | |
224 | ||
225 | if (WARN_ON_ONCE(trb_address_map == NULL)) | |
226 | return 0; | |
227 | ||
228 | seg = first_seg; | |
229 | do { | |
230 | ret = xhci_insert_segment_mapping(trb_address_map, | |
231 | ring, seg, mem_flags); | |
15341303 | 232 | if (ret) |
d5734223 SS |
233 | goto remove_streams; |
234 | if (seg == last_seg) | |
235 | return 0; | |
15341303 | 236 | seg = seg->next; |
d5734223 | 237 | } while (seg != first_seg); |
15341303 GH |
238 | |
239 | return 0; | |
d5734223 SS |
240 | |
241 | remove_streams: | |
242 | failed_seg = seg; | |
243 | seg = first_seg; | |
244 | do { | |
245 | xhci_remove_segment_mapping(trb_address_map, seg); | |
246 | if (seg == failed_seg) | |
247 | return ret; | |
248 | seg = seg->next; | |
249 | } while (seg != first_seg); | |
250 | ||
251 | return ret; | |
15341303 GH |
252 | } |
253 | ||
254 | static void xhci_remove_stream_mapping(struct xhci_ring *ring) | |
255 | { | |
256 | struct xhci_segment *seg; | |
15341303 GH |
257 | |
258 | if (WARN_ON_ONCE(ring->trb_address_map == NULL)) | |
259 | return; | |
260 | ||
261 | seg = ring->first_seg; | |
262 | do { | |
d5734223 | 263 | xhci_remove_segment_mapping(ring->trb_address_map, seg); |
15341303 GH |
264 | seg = seg->next; |
265 | } while (seg != ring->first_seg); | |
266 | } | |
267 | ||
d5734223 SS |
268 | static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags) |
269 | { | |
270 | return xhci_update_stream_segment_mapping(ring->trb_address_map, ring, | |
271 | ring->first_seg, ring->last_seg, mem_flags); | |
272 | } | |
273 | ||
0ebbab37 | 274 | /* XXX: Do we need the hcd structure in all these functions? */ |
f94e0186 | 275 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) |
0ebbab37 | 276 | { |
0e6c7f74 | 277 | if (!ring) |
0ebbab37 | 278 | return; |
70d43601 | 279 | |
b2d6edbb LB |
280 | trace_xhci_ring_free(ring); |
281 | ||
15341303 GH |
282 | if (ring->first_seg) { |
283 | if (ring->type == TYPE_STREAM) | |
284 | xhci_remove_stream_mapping(ring); | |
70d43601 | 285 | xhci_free_segments_for_ring(xhci, ring->first_seg); |
15341303 | 286 | } |
70d43601 | 287 | |
0ebbab37 SS |
288 | kfree(ring); |
289 | } | |
290 | ||
186a7ef1 AX |
291 | static void xhci_initialize_ring_info(struct xhci_ring *ring, |
292 | unsigned int cycle_state) | |
74f9fe21 SS |
293 | { |
294 | /* The ring is empty, so the enqueue pointer == dequeue pointer */ | |
295 | ring->enqueue = ring->first_seg->trbs; | |
296 | ring->enq_seg = ring->first_seg; | |
297 | ring->dequeue = ring->enqueue; | |
298 | ring->deq_seg = ring->first_seg; | |
299 | /* The ring is initialized to 0. The producer must write 1 to the cycle | |
300 | * bit to handover ownership of the TRB, so PCS = 1. The consumer must | |
301 | * compare CCS to the cycle bit to check ownership, so CCS = 1. | |
186a7ef1 AX |
302 | * |
303 | * New rings are initialized with cycle state equal to 1; if we are | |
304 | * handling ring expansion, set the cycle state equal to the old ring. | |
74f9fe21 | 305 | */ |
186a7ef1 | 306 | ring->cycle_state = cycle_state; |
b008df60 AX |
307 | |
308 | /* | |
309 | * Each segment has a link TRB, and leave an extra TRB for SW | |
310 | * accounting purpose | |
311 | */ | |
312 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; | |
74f9fe21 SS |
313 | } |
314 | ||
70d43601 AX |
315 | /* Allocate segments and link them for a ring */ |
316 | static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci, | |
317 | struct xhci_segment **first, struct xhci_segment **last, | |
186a7ef1 | 318 | unsigned int num_segs, unsigned int cycle_state, |
f9c589e1 | 319 | enum xhci_ring_type type, unsigned int max_packet, gfp_t flags) |
70d43601 AX |
320 | { |
321 | struct xhci_segment *prev; | |
322 | ||
f9c589e1 | 323 | prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags); |
70d43601 AX |
324 | if (!prev) |
325 | return -ENOMEM; | |
326 | num_segs--; | |
327 | ||
328 | *first = prev; | |
329 | while (num_segs > 0) { | |
330 | struct xhci_segment *next; | |
331 | ||
f9c589e1 | 332 | next = xhci_segment_alloc(xhci, cycle_state, max_packet, flags); |
70d43601 | 333 | if (!next) { |
68e5254a JW |
334 | prev = *first; |
335 | while (prev) { | |
336 | next = prev->next; | |
337 | xhci_segment_free(xhci, prev); | |
338 | prev = next; | |
339 | } | |
70d43601 AX |
340 | return -ENOMEM; |
341 | } | |
342 | xhci_link_segments(xhci, prev, next, type); | |
343 | ||
344 | prev = next; | |
345 | num_segs--; | |
346 | } | |
347 | xhci_link_segments(xhci, prev, *first, type); | |
348 | *last = prev; | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
0ebbab37 SS |
353 | /** |
354 | * Create a new ring with zero or more segments. | |
355 | * | |
356 | * Link each segment together into a ring. | |
357 | * Set the end flag and the cycle toggle bit on the last segment. | |
358 | * See section 4.9.1 and figures 15 and 16. | |
359 | */ | |
360 | static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, | |
186a7ef1 | 361 | unsigned int num_segs, unsigned int cycle_state, |
f9c589e1 | 362 | enum xhci_ring_type type, unsigned int max_packet, gfp_t flags) |
0ebbab37 SS |
363 | { |
364 | struct xhci_ring *ring; | |
70d43601 | 365 | int ret; |
0ebbab37 SS |
366 | |
367 | ring = kzalloc(sizeof *(ring), flags); | |
0ebbab37 | 368 | if (!ring) |
326b4810 | 369 | return NULL; |
0ebbab37 | 370 | |
3fe4fe08 | 371 | ring->num_segs = num_segs; |
f9c589e1 | 372 | ring->bounce_buf_len = max_packet; |
d0e96f5a | 373 | INIT_LIST_HEAD(&ring->td_list); |
3b72fca0 | 374 | ring->type = type; |
0ebbab37 SS |
375 | if (num_segs == 0) |
376 | return ring; | |
377 | ||
70d43601 | 378 | ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg, |
f9c589e1 MN |
379 | &ring->last_seg, num_segs, cycle_state, type, |
380 | max_packet, flags); | |
70d43601 | 381 | if (ret) |
0ebbab37 | 382 | goto fail; |
0ebbab37 | 383 | |
3b72fca0 AX |
384 | /* Only event ring does not use link TRB */ |
385 | if (type != TYPE_EVENT) { | |
0ebbab37 | 386 | /* See section 4.9.2.1 and 6.4.4.1 */ |
70d43601 | 387 | ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= |
f5960b69 | 388 | cpu_to_le32(LINK_TOGGLE); |
0ebbab37 | 389 | } |
186a7ef1 | 390 | xhci_initialize_ring_info(ring, cycle_state); |
b2d6edbb | 391 | trace_xhci_ring_alloc(ring); |
0ebbab37 SS |
392 | return ring; |
393 | ||
394 | fail: | |
68e5254a | 395 | kfree(ring); |
326b4810 | 396 | return NULL; |
0ebbab37 SS |
397 | } |
398 | ||
c5628a2a | 399 | void xhci_free_endpoint_ring(struct xhci_hcd *xhci, |
412566bd SS |
400 | struct xhci_virt_device *virt_dev, |
401 | unsigned int ep_index) | |
402 | { | |
c5628a2a | 403 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); |
412566bd SS |
404 | virt_dev->eps[ep_index].ring = NULL; |
405 | } | |
406 | ||
8dfec614 AX |
407 | /* |
408 | * Expand an existing ring. | |
c5628a2a | 409 | * Allocate a new ring which has same segment numbers and link the two rings. |
8dfec614 AX |
410 | */ |
411 | int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
412 | unsigned int num_trbs, gfp_t flags) | |
413 | { | |
414 | struct xhci_segment *first; | |
415 | struct xhci_segment *last; | |
416 | unsigned int num_segs; | |
417 | unsigned int num_segs_needed; | |
418 | int ret; | |
419 | ||
420 | num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) / | |
421 | (TRBS_PER_SEGMENT - 1); | |
422 | ||
423 | /* Allocate number of segments we needed, or double the ring size */ | |
424 | num_segs = ring->num_segs > num_segs_needed ? | |
425 | ring->num_segs : num_segs_needed; | |
426 | ||
427 | ret = xhci_alloc_segments_for_ring(xhci, &first, &last, | |
f9c589e1 MN |
428 | num_segs, ring->cycle_state, ring->type, |
429 | ring->bounce_buf_len, flags); | |
8dfec614 AX |
430 | if (ret) |
431 | return -ENOMEM; | |
432 | ||
d5734223 SS |
433 | if (ring->type == TYPE_STREAM) |
434 | ret = xhci_update_stream_segment_mapping(ring->trb_address_map, | |
435 | ring, first, last, flags); | |
436 | if (ret) { | |
437 | struct xhci_segment *next; | |
438 | do { | |
439 | next = first->next; | |
440 | xhci_segment_free(xhci, first); | |
441 | if (first == last) | |
442 | break; | |
443 | first = next; | |
444 | } while (true); | |
445 | return ret; | |
446 | } | |
447 | ||
8dfec614 | 448 | xhci_link_rings(xhci, ring, first, last, num_segs); |
b2d6edbb | 449 | trace_xhci_ring_expansion(ring); |
68ffb011 XR |
450 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
451 | "ring expansion succeed, now has %d segments", | |
8dfec614 AX |
452 | ring->num_segs); |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
326b4810 | 457 | static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
458 | int type, gfp_t flags) |
459 | { | |
29f9d54b SS |
460 | struct xhci_container_ctx *ctx; |
461 | ||
462 | if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)) | |
463 | return NULL; | |
464 | ||
465 | ctx = kzalloc(sizeof(*ctx), flags); | |
d115b048 JY |
466 | if (!ctx) |
467 | return NULL; | |
468 | ||
d115b048 JY |
469 | ctx->type = type; |
470 | ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; | |
471 | if (type == XHCI_CTX_TYPE_INPUT) | |
472 | ctx->size += CTX_SIZE(xhci->hcc_params); | |
473 | ||
84c1eeb0 | 474 | ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma); |
025f880c MN |
475 | if (!ctx->bytes) { |
476 | kfree(ctx); | |
477 | return NULL; | |
478 | } | |
d115b048 JY |
479 | return ctx; |
480 | } | |
481 | ||
326b4810 | 482 | static void xhci_free_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
483 | struct xhci_container_ctx *ctx) |
484 | { | |
a1d78c16 SS |
485 | if (!ctx) |
486 | return; | |
d115b048 JY |
487 | dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); |
488 | kfree(ctx); | |
489 | } | |
490 | ||
4daf9df5 | 491 | struct xhci_input_control_ctx *xhci_get_input_control_ctx( |
d115b048 JY |
492 | struct xhci_container_ctx *ctx) |
493 | { | |
92f8e767 SS |
494 | if (ctx->type != XHCI_CTX_TYPE_INPUT) |
495 | return NULL; | |
496 | ||
d115b048 JY |
497 | return (struct xhci_input_control_ctx *)ctx->bytes; |
498 | } | |
499 | ||
500 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, | |
501 | struct xhci_container_ctx *ctx) | |
502 | { | |
503 | if (ctx->type == XHCI_CTX_TYPE_DEVICE) | |
504 | return (struct xhci_slot_ctx *)ctx->bytes; | |
505 | ||
506 | return (struct xhci_slot_ctx *) | |
507 | (ctx->bytes + CTX_SIZE(xhci->hcc_params)); | |
508 | } | |
509 | ||
510 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, | |
511 | struct xhci_container_ctx *ctx, | |
512 | unsigned int ep_index) | |
513 | { | |
514 | /* increment ep index by offset of start of ep ctx array */ | |
515 | ep_index++; | |
516 | if (ctx->type == XHCI_CTX_TYPE_INPUT) | |
517 | ep_index++; | |
518 | ||
519 | return (struct xhci_ep_ctx *) | |
520 | (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); | |
521 | } | |
522 | ||
8df75f42 SS |
523 | |
524 | /***************** Streams structures manipulation *************************/ | |
525 | ||
8212a49d | 526 | static void xhci_free_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
527 | unsigned int num_stream_ctxs, |
528 | struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) | |
529 | { | |
4c39d4b9 | 530 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
ee4aa54b | 531 | size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; |
8df75f42 | 532 | |
ee4aa54b HG |
533 | if (size > MEDIUM_STREAM_ARRAY_SIZE) |
534 | dma_free_coherent(dev, size, | |
8df75f42 | 535 | stream_ctx, dma); |
ee4aa54b | 536 | else if (size <= SMALL_STREAM_ARRAY_SIZE) |
8df75f42 SS |
537 | return dma_pool_free(xhci->small_streams_pool, |
538 | stream_ctx, dma); | |
539 | else | |
540 | return dma_pool_free(xhci->medium_streams_pool, | |
541 | stream_ctx, dma); | |
542 | } | |
543 | ||
544 | /* | |
545 | * The stream context array for each endpoint with bulk streams enabled can | |
546 | * vary in size, based on: | |
547 | * - how many streams the endpoint supports, | |
548 | * - the maximum primary stream array size the host controller supports, | |
549 | * - and how many streams the device driver asks for. | |
550 | * | |
551 | * The stream context array must be a power of 2, and can be as small as | |
552 | * 64 bytes or as large as 1MB. | |
553 | */ | |
8212a49d | 554 | static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
555 | unsigned int num_stream_ctxs, dma_addr_t *dma, |
556 | gfp_t mem_flags) | |
557 | { | |
4c39d4b9 | 558 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
ee4aa54b | 559 | size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; |
8df75f42 | 560 | |
ee4aa54b HG |
561 | if (size > MEDIUM_STREAM_ARRAY_SIZE) |
562 | return dma_alloc_coherent(dev, size, | |
22d45f01 | 563 | dma, mem_flags); |
ee4aa54b | 564 | else if (size <= SMALL_STREAM_ARRAY_SIZE) |
8df75f42 SS |
565 | return dma_pool_alloc(xhci->small_streams_pool, |
566 | mem_flags, dma); | |
567 | else | |
568 | return dma_pool_alloc(xhci->medium_streams_pool, | |
569 | mem_flags, dma); | |
570 | } | |
571 | ||
e9df17eb SS |
572 | struct xhci_ring *xhci_dma_to_transfer_ring( |
573 | struct xhci_virt_ep *ep, | |
574 | u64 address) | |
575 | { | |
576 | if (ep->ep_state & EP_HAS_STREAMS) | |
577 | return radix_tree_lookup(&ep->stream_info->trb_address_map, | |
eb8ccd2b | 578 | address >> TRB_SEGMENT_SHIFT); |
e9df17eb SS |
579 | return ep->ring; |
580 | } | |
581 | ||
e9df17eb SS |
582 | struct xhci_ring *xhci_stream_id_to_ring( |
583 | struct xhci_virt_device *dev, | |
584 | unsigned int ep_index, | |
585 | unsigned int stream_id) | |
586 | { | |
587 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; | |
588 | ||
589 | if (stream_id == 0) | |
590 | return ep->ring; | |
591 | if (!ep->stream_info) | |
592 | return NULL; | |
593 | ||
594 | if (stream_id > ep->stream_info->num_streams) | |
595 | return NULL; | |
596 | return ep->stream_info->stream_rings[stream_id]; | |
597 | } | |
598 | ||
8df75f42 SS |
599 | /* |
600 | * Change an endpoint's internal structure so it supports stream IDs. The | |
601 | * number of requested streams includes stream 0, which cannot be used by device | |
602 | * drivers. | |
603 | * | |
604 | * The number of stream contexts in the stream context array may be bigger than | |
605 | * the number of streams the driver wants to use. This is because the number of | |
606 | * stream context array entries must be a power of two. | |
8df75f42 SS |
607 | */ |
608 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, | |
609 | unsigned int num_stream_ctxs, | |
f9c589e1 MN |
610 | unsigned int num_streams, |
611 | unsigned int max_packet, gfp_t mem_flags) | |
8df75f42 SS |
612 | { |
613 | struct xhci_stream_info *stream_info; | |
614 | u32 cur_stream; | |
615 | struct xhci_ring *cur_ring; | |
8df75f42 SS |
616 | u64 addr; |
617 | int ret; | |
618 | ||
619 | xhci_dbg(xhci, "Allocating %u streams and %u " | |
620 | "stream context array entries.\n", | |
621 | num_streams, num_stream_ctxs); | |
622 | if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) { | |
623 | xhci_dbg(xhci, "Command ring has no reserved TRBs available\n"); | |
624 | return NULL; | |
625 | } | |
626 | xhci->cmd_ring_reserved_trbs++; | |
627 | ||
628 | stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags); | |
629 | if (!stream_info) | |
630 | goto cleanup_trbs; | |
631 | ||
632 | stream_info->num_streams = num_streams; | |
633 | stream_info->num_stream_ctxs = num_stream_ctxs; | |
634 | ||
635 | /* Initialize the array of virtual pointers to stream rings. */ | |
636 | stream_info->stream_rings = kzalloc( | |
637 | sizeof(struct xhci_ring *)*num_streams, | |
638 | mem_flags); | |
639 | if (!stream_info->stream_rings) | |
640 | goto cleanup_info; | |
641 | ||
642 | /* Initialize the array of DMA addresses for stream rings for the HW. */ | |
643 | stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci, | |
644 | num_stream_ctxs, &stream_info->ctx_array_dma, | |
645 | mem_flags); | |
646 | if (!stream_info->stream_ctx_array) | |
647 | goto cleanup_ctx; | |
648 | memset(stream_info->stream_ctx_array, 0, | |
649 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs); | |
650 | ||
651 | /* Allocate everything needed to free the stream rings later */ | |
652 | stream_info->free_streams_command = | |
653 | xhci_alloc_command(xhci, true, true, mem_flags); | |
654 | if (!stream_info->free_streams_command) | |
655 | goto cleanup_ctx; | |
656 | ||
657 | INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); | |
658 | ||
659 | /* Allocate rings for all the streams that the driver will use, | |
660 | * and add their segment DMA addresses to the radix tree. | |
661 | * Stream 0 is reserved. | |
662 | */ | |
f9c589e1 | 663 | |
8df75f42 SS |
664 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { |
665 | stream_info->stream_rings[cur_stream] = | |
f9c589e1 MN |
666 | xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, max_packet, |
667 | mem_flags); | |
8df75f42 SS |
668 | cur_ring = stream_info->stream_rings[cur_stream]; |
669 | if (!cur_ring) | |
670 | goto cleanup_rings; | |
e9df17eb | 671 | cur_ring->stream_id = cur_stream; |
15341303 | 672 | cur_ring->trb_address_map = &stream_info->trb_address_map; |
8df75f42 SS |
673 | /* Set deq ptr, cycle bit, and stream context type */ |
674 | addr = cur_ring->first_seg->dma | | |
675 | SCT_FOR_CTX(SCT_PRI_TR) | | |
676 | cur_ring->cycle_state; | |
f5960b69 ME |
677 | stream_info->stream_ctx_array[cur_stream].stream_ring = |
678 | cpu_to_le64(addr); | |
8df75f42 SS |
679 | xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", |
680 | cur_stream, (unsigned long long) addr); | |
681 | ||
15341303 | 682 | ret = xhci_update_stream_mapping(cur_ring, mem_flags); |
8df75f42 SS |
683 | if (ret) { |
684 | xhci_ring_free(xhci, cur_ring); | |
685 | stream_info->stream_rings[cur_stream] = NULL; | |
686 | goto cleanup_rings; | |
687 | } | |
688 | } | |
689 | /* Leave the other unused stream ring pointers in the stream context | |
690 | * array initialized to zero. This will cause the xHC to give us an | |
691 | * error if the device asks for a stream ID we don't have setup (if it | |
692 | * was any other way, the host controller would assume the ring is | |
693 | * "empty" and wait forever for data to be queued to that stream ID). | |
694 | */ | |
8df75f42 SS |
695 | |
696 | return stream_info; | |
697 | ||
698 | cleanup_rings: | |
699 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
700 | cur_ring = stream_info->stream_rings[cur_stream]; | |
701 | if (cur_ring) { | |
8df75f42 SS |
702 | xhci_ring_free(xhci, cur_ring); |
703 | stream_info->stream_rings[cur_stream] = NULL; | |
704 | } | |
705 | } | |
706 | xhci_free_command(xhci, stream_info->free_streams_command); | |
707 | cleanup_ctx: | |
708 | kfree(stream_info->stream_rings); | |
709 | cleanup_info: | |
710 | kfree(stream_info); | |
711 | cleanup_trbs: | |
712 | xhci->cmd_ring_reserved_trbs--; | |
713 | return NULL; | |
714 | } | |
715 | /* | |
716 | * Sets the MaxPStreams field and the Linear Stream Array field. | |
717 | * Sets the dequeue pointer to the stream context array. | |
718 | */ | |
719 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
720 | struct xhci_ep_ctx *ep_ctx, | |
721 | struct xhci_stream_info *stream_info) | |
722 | { | |
723 | u32 max_primary_streams; | |
724 | /* MaxPStreams is the number of stream context array entries, not the | |
725 | * number we're actually using. Must be in 2^(MaxPstreams + 1) format. | |
726 | * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. | |
727 | */ | |
728 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; | |
3a7fa5be XR |
729 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
730 | "Setting number of stream ctx array entries to %u", | |
8df75f42 | 731 | 1 << (max_primary_streams + 1)); |
28ccd296 ME |
732 | ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); |
733 | ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) | |
734 | | EP_HAS_LSA); | |
735 | ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); | |
8df75f42 SS |
736 | } |
737 | ||
738 | /* | |
739 | * Sets the MaxPStreams field and the Linear Stream Array field to 0. | |
740 | * Reinstalls the "normal" endpoint ring (at its previous dequeue mark, | |
741 | * not at the beginning of the ring). | |
742 | */ | |
4daf9df5 | 743 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, |
8df75f42 SS |
744 | struct xhci_virt_ep *ep) |
745 | { | |
746 | dma_addr_t addr; | |
28ccd296 | 747 | ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA)); |
8df75f42 | 748 | addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); |
28ccd296 | 749 | ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state); |
8df75f42 SS |
750 | } |
751 | ||
752 | /* Frees all stream contexts associated with the endpoint, | |
753 | * | |
754 | * Caller should fix the endpoint context streams fields. | |
755 | */ | |
756 | void xhci_free_stream_info(struct xhci_hcd *xhci, | |
757 | struct xhci_stream_info *stream_info) | |
758 | { | |
759 | int cur_stream; | |
760 | struct xhci_ring *cur_ring; | |
8df75f42 SS |
761 | |
762 | if (!stream_info) | |
763 | return; | |
764 | ||
765 | for (cur_stream = 1; cur_stream < stream_info->num_streams; | |
766 | cur_stream++) { | |
767 | cur_ring = stream_info->stream_rings[cur_stream]; | |
768 | if (cur_ring) { | |
8df75f42 SS |
769 | xhci_ring_free(xhci, cur_ring); |
770 | stream_info->stream_rings[cur_stream] = NULL; | |
771 | } | |
772 | } | |
773 | xhci_free_command(xhci, stream_info->free_streams_command); | |
774 | xhci->cmd_ring_reserved_trbs--; | |
775 | if (stream_info->stream_ctx_array) | |
776 | xhci_free_stream_ctx(xhci, | |
777 | stream_info->num_stream_ctxs, | |
778 | stream_info->stream_ctx_array, | |
779 | stream_info->ctx_array_dma); | |
780 | ||
0d3703be | 781 | kfree(stream_info->stream_rings); |
8df75f42 SS |
782 | kfree(stream_info); |
783 | } | |
784 | ||
785 | ||
786 | /***************** Device context manipulation *************************/ | |
787 | ||
6f5165cf SS |
788 | static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, |
789 | struct xhci_virt_ep *ep) | |
790 | { | |
66a45503 KC |
791 | timer_setup(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog, |
792 | 0); | |
6f5165cf SS |
793 | ep->xhci = xhci; |
794 | } | |
795 | ||
839c817c SS |
796 | static void xhci_free_tt_info(struct xhci_hcd *xhci, |
797 | struct xhci_virt_device *virt_dev, | |
798 | int slot_id) | |
799 | { | |
839c817c | 800 | struct list_head *tt_list_head; |
46ed8f00 TI |
801 | struct xhci_tt_bw_info *tt_info, *next; |
802 | bool slot_found = false; | |
839c817c SS |
803 | |
804 | /* If the device never made it past the Set Address stage, | |
805 | * it may not have the real_port set correctly. | |
806 | */ | |
807 | if (virt_dev->real_port == 0 || | |
808 | virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { | |
809 | xhci_dbg(xhci, "Bad real port.\n"); | |
810 | return; | |
811 | } | |
812 | ||
813 | tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts); | |
46ed8f00 TI |
814 | list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { |
815 | /* Multi-TT hubs will have more than one entry */ | |
816 | if (tt_info->slot_id == slot_id) { | |
817 | slot_found = true; | |
818 | list_del(&tt_info->tt_list); | |
819 | kfree(tt_info); | |
820 | } else if (slot_found) { | |
839c817c | 821 | break; |
46ed8f00 | 822 | } |
839c817c | 823 | } |
839c817c SS |
824 | } |
825 | ||
826 | int xhci_alloc_tt_info(struct xhci_hcd *xhci, | |
827 | struct xhci_virt_device *virt_dev, | |
828 | struct usb_device *hdev, | |
829 | struct usb_tt *tt, gfp_t mem_flags) | |
830 | { | |
831 | struct xhci_tt_bw_info *tt_info; | |
832 | unsigned int num_ports; | |
833 | int i, j; | |
834 | ||
835 | if (!tt->multi) | |
836 | num_ports = 1; | |
837 | else | |
838 | num_ports = hdev->maxchild; | |
839 | ||
840 | for (i = 0; i < num_ports; i++, tt_info++) { | |
841 | struct xhci_interval_bw_table *bw_table; | |
842 | ||
843 | tt_info = kzalloc(sizeof(*tt_info), mem_flags); | |
844 | if (!tt_info) | |
845 | goto free_tts; | |
846 | INIT_LIST_HEAD(&tt_info->tt_list); | |
847 | list_add(&tt_info->tt_list, | |
848 | &xhci->rh_bw[virt_dev->real_port - 1].tts); | |
849 | tt_info->slot_id = virt_dev->udev->slot_id; | |
850 | if (tt->multi) | |
851 | tt_info->ttport = i+1; | |
852 | bw_table = &tt_info->bw_table; | |
853 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
854 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
855 | } | |
856 | return 0; | |
857 | ||
858 | free_tts: | |
859 | xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id); | |
860 | return -ENOMEM; | |
861 | } | |
862 | ||
863 | ||
864 | /* All the xhci_tds in the ring's TD list should be freed at this point. | |
865 | * Should be called with xhci->lock held if there is any chance the TT lists | |
866 | * will be manipulated by the configure endpoint, allocate device, or update | |
867 | * hub functions while this function is removing the TT entries from the list. | |
868 | */ | |
3ffbba95 SS |
869 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) |
870 | { | |
871 | struct xhci_virt_device *dev; | |
872 | int i; | |
2e27980e | 873 | int old_active_eps = 0; |
3ffbba95 SS |
874 | |
875 | /* Slot ID 0 is reserved */ | |
876 | if (slot_id == 0 || !xhci->devs[slot_id]) | |
877 | return; | |
878 | ||
879 | dev = xhci->devs[slot_id]; | |
a711edee FB |
880 | |
881 | trace_xhci_free_virt_device(dev); | |
882 | ||
8e595a5d | 883 | xhci->dcbaa->dev_context_ptrs[slot_id] = 0; |
3ffbba95 SS |
884 | if (!dev) |
885 | return; | |
886 | ||
2e27980e SS |
887 | if (dev->tt_info) |
888 | old_active_eps = dev->tt_info->active_eps; | |
889 | ||
98871e94 | 890 | for (i = 0; i < 31; i++) { |
63a0d9ab SS |
891 | if (dev->eps[i].ring) |
892 | xhci_ring_free(xhci, dev->eps[i].ring); | |
8df75f42 SS |
893 | if (dev->eps[i].stream_info) |
894 | xhci_free_stream_info(xhci, | |
895 | dev->eps[i].stream_info); | |
2e27980e SS |
896 | /* Endpoints on the TT/root port lists should have been removed |
897 | * when usb_disable_device() was called for the device. | |
898 | * We can't drop them anyway, because the udev might have gone | |
899 | * away by this point, and we can't tell what speed it was. | |
900 | */ | |
901 | if (!list_empty(&dev->eps[i].bw_endpoint_list)) | |
902 | xhci_warn(xhci, "Slot %u endpoint %u " | |
903 | "not removed from BW list!\n", | |
904 | slot_id, i); | |
8df75f42 | 905 | } |
839c817c SS |
906 | /* If this is a hub, free the TT(s) from the TT list */ |
907 | xhci_free_tt_info(xhci, dev, slot_id); | |
2e27980e SS |
908 | /* If necessary, update the number of active TTs on this root port */ |
909 | xhci_update_tt_active_eps(xhci, dev, old_active_eps); | |
3ffbba95 SS |
910 | |
911 | if (dev->in_ctx) | |
d115b048 | 912 | xhci_free_container_ctx(xhci, dev->in_ctx); |
3ffbba95 | 913 | if (dev->out_ctx) |
d115b048 JY |
914 | xhci_free_container_ctx(xhci, dev->out_ctx); |
915 | ||
3ffbba95 | 916 | kfree(xhci->devs[slot_id]); |
326b4810 | 917 | xhci->devs[slot_id] = NULL; |
3ffbba95 SS |
918 | } |
919 | ||
ee8665e2 MN |
920 | /* |
921 | * Free a virt_device structure. | |
922 | * If the virt_device added a tt_info (a hub) and has children pointing to | |
923 | * that tt_info, then free the child first. Recursive. | |
924 | * We can't rely on udev at this point to find child-parent relationships. | |
925 | */ | |
926 | void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id) | |
927 | { | |
928 | struct xhci_virt_device *vdev; | |
929 | struct list_head *tt_list_head; | |
930 | struct xhci_tt_bw_info *tt_info, *next; | |
931 | int i; | |
932 | ||
933 | vdev = xhci->devs[slot_id]; | |
934 | if (!vdev) | |
935 | return; | |
936 | ||
80e45769 YC |
937 | if (vdev->real_port == 0 || |
938 | vdev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { | |
939 | xhci_dbg(xhci, "Bad vdev->real_port.\n"); | |
940 | goto out; | |
941 | } | |
942 | ||
ee8665e2 MN |
943 | tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts); |
944 | list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { | |
945 | /* is this a hub device that added a tt_info to the tts list */ | |
946 | if (tt_info->slot_id == slot_id) { | |
947 | /* are any devices using this tt_info? */ | |
948 | for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
949 | vdev = xhci->devs[i]; | |
950 | if (vdev && (vdev->tt_info == tt_info)) | |
951 | xhci_free_virt_devices_depth_first( | |
952 | xhci, i); | |
953 | } | |
954 | } | |
955 | } | |
80e45769 | 956 | out: |
ee8665e2 | 957 | /* we are now at a leaf device */ |
02b6fdc2 | 958 | xhci_debugfs_remove_slot(xhci, slot_id); |
ee8665e2 MN |
959 | xhci_free_virt_device(xhci, slot_id); |
960 | } | |
961 | ||
3ffbba95 SS |
962 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, |
963 | struct usb_device *udev, gfp_t flags) | |
964 | { | |
3ffbba95 | 965 | struct xhci_virt_device *dev; |
63a0d9ab | 966 | int i; |
3ffbba95 SS |
967 | |
968 | /* Slot ID 0 is reserved */ | |
969 | if (slot_id == 0 || xhci->devs[slot_id]) { | |
970 | xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); | |
971 | return 0; | |
972 | } | |
973 | ||
5d9b70f7 MN |
974 | dev = kzalloc(sizeof(*dev), flags); |
975 | if (!dev) | |
3ffbba95 | 976 | return 0; |
3ffbba95 | 977 | |
d115b048 JY |
978 | /* Allocate the (output) device context that will be used in the HC. */ |
979 | dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); | |
3ffbba95 SS |
980 | if (!dev->out_ctx) |
981 | goto fail; | |
d115b048 | 982 | |
700e2052 | 983 | xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 984 | (unsigned long long)dev->out_ctx->dma); |
3ffbba95 SS |
985 | |
986 | /* Allocate the (input) device context for address device command */ | |
d115b048 | 987 | dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); |
3ffbba95 SS |
988 | if (!dev->in_ctx) |
989 | goto fail; | |
d115b048 | 990 | |
700e2052 | 991 | xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 992 | (unsigned long long)dev->in_ctx->dma); |
3ffbba95 | 993 | |
6f5165cf SS |
994 | /* Initialize the cancellation list and watchdog timers for each ep */ |
995 | for (i = 0; i < 31; i++) { | |
996 | xhci_init_endpoint_timer(xhci, &dev->eps[i]); | |
63a0d9ab | 997 | INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); |
2e27980e | 998 | INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list); |
6f5165cf | 999 | } |
63a0d9ab | 1000 | |
3ffbba95 | 1001 | /* Allocate endpoint 0 ring */ |
f9c589e1 | 1002 | dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, 0, flags); |
63a0d9ab | 1003 | if (!dev->eps[0].ring) |
3ffbba95 SS |
1004 | goto fail; |
1005 | ||
64927730 | 1006 | dev->udev = udev; |
f94e0186 | 1007 | |
28c2d2ef | 1008 | /* Point to output device context in dcbaa. */ |
28ccd296 | 1009 | xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); |
700e2052 | 1010 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", |
28ccd296 ME |
1011 | slot_id, |
1012 | &xhci->dcbaa->dev_context_ptrs[slot_id], | |
f5960b69 | 1013 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); |
3ffbba95 | 1014 | |
a711edee FB |
1015 | trace_xhci_alloc_virt_device(dev); |
1016 | ||
5d9b70f7 MN |
1017 | xhci->devs[slot_id] = dev; |
1018 | ||
3ffbba95 SS |
1019 | return 1; |
1020 | fail: | |
5d9b70f7 MN |
1021 | |
1022 | if (dev->in_ctx) | |
1023 | xhci_free_container_ctx(xhci, dev->in_ctx); | |
1024 | if (dev->out_ctx) | |
1025 | xhci_free_container_ctx(xhci, dev->out_ctx); | |
1026 | kfree(dev); | |
1027 | ||
3ffbba95 SS |
1028 | return 0; |
1029 | } | |
1030 | ||
2d1ee590 SS |
1031 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
1032 | struct usb_device *udev) | |
1033 | { | |
1034 | struct xhci_virt_device *virt_dev; | |
1035 | struct xhci_ep_ctx *ep0_ctx; | |
1036 | struct xhci_ring *ep_ring; | |
1037 | ||
1038 | virt_dev = xhci->devs[udev->slot_id]; | |
1039 | ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0); | |
1040 | ep_ring = virt_dev->eps[0].ring; | |
1041 | /* | |
1042 | * FIXME we don't keep track of the dequeue pointer very well after a | |
1043 | * Set TR dequeue pointer, so we're setting the dequeue pointer of the | |
1044 | * host to our enqueue pointer. This should only be called after a | |
1045 | * configured device has reset, so all control transfers should have | |
1046 | * been completed or cancelled before the reset. | |
1047 | */ | |
28ccd296 ME |
1048 | ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg, |
1049 | ep_ring->enqueue) | |
1050 | | ep_ring->cycle_state); | |
2d1ee590 SS |
1051 | } |
1052 | ||
f6ff0ac8 SS |
1053 | /* |
1054 | * The xHCI roothub may have ports of differing speeds in any order in the port | |
1055 | * status registers. xhci->port_array provides an array of the port speed for | |
1056 | * each offset into the port status registers. | |
1057 | * | |
1058 | * The xHCI hardware wants to know the roothub port number that the USB device | |
1059 | * is attached to (or the roothub port its ancestor hub is attached to). All we | |
1060 | * know is the index of that port under either the USB 2.0 or the USB 3.0 | |
1061 | * roothub, but that doesn't give us the real index into the HW port status | |
3f5eb141 | 1062 | * registers. Call xhci_find_raw_port_number() to get real index. |
f6ff0ac8 SS |
1063 | */ |
1064 | static u32 xhci_find_real_port_number(struct xhci_hcd *xhci, | |
1065 | struct usb_device *udev) | |
1066 | { | |
1067 | struct usb_device *top_dev; | |
3f5eb141 LT |
1068 | struct usb_hcd *hcd; |
1069 | ||
0caf6b33 | 1070 | if (udev->speed >= USB_SPEED_SUPER) |
3f5eb141 LT |
1071 | hcd = xhci->shared_hcd; |
1072 | else | |
1073 | hcd = xhci->main_hcd; | |
f6ff0ac8 SS |
1074 | |
1075 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | |
1076 | top_dev = top_dev->parent) | |
1077 | /* Found device below root hub */; | |
f6ff0ac8 | 1078 | |
3f5eb141 | 1079 | return xhci_find_raw_port_number(hcd, top_dev->portnum); |
f6ff0ac8 SS |
1080 | } |
1081 | ||
3ffbba95 SS |
1082 | /* Setup an xHCI virtual device for a Set Address command */ |
1083 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) | |
1084 | { | |
1085 | struct xhci_virt_device *dev; | |
1086 | struct xhci_ep_ctx *ep0_ctx; | |
d115b048 | 1087 | struct xhci_slot_ctx *slot_ctx; |
f6ff0ac8 | 1088 | u32 port_num; |
bd18fd5c | 1089 | u32 max_packets; |
f6ff0ac8 | 1090 | struct usb_device *top_dev; |
3ffbba95 SS |
1091 | |
1092 | dev = xhci->devs[udev->slot_id]; | |
1093 | /* Slot ID 0 is reserved */ | |
1094 | if (udev->slot_id == 0 || !dev) { | |
1095 | xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", | |
1096 | udev->slot_id); | |
1097 | return -EINVAL; | |
1098 | } | |
d115b048 | 1099 | ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); |
d115b048 | 1100 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); |
3ffbba95 | 1101 | |
3ffbba95 | 1102 | /* 3) Only the control endpoint is valid - one endpoint context */ |
f5960b69 | 1103 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route); |
3ffbba95 | 1104 | switch (udev->speed) { |
0caf6b33 | 1105 | case USB_SPEED_SUPER_PLUS: |
d7854041 MN |
1106 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP); |
1107 | max_packets = MAX_PACKET(512); | |
1108 | break; | |
3ffbba95 | 1109 | case USB_SPEED_SUPER: |
f5960b69 | 1110 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); |
bd18fd5c | 1111 | max_packets = MAX_PACKET(512); |
3ffbba95 SS |
1112 | break; |
1113 | case USB_SPEED_HIGH: | |
f5960b69 | 1114 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); |
bd18fd5c | 1115 | max_packets = MAX_PACKET(64); |
3ffbba95 | 1116 | break; |
bd18fd5c | 1117 | /* USB core guesses at a 64-byte max packet first for FS devices */ |
3ffbba95 | 1118 | case USB_SPEED_FULL: |
f5960b69 | 1119 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); |
bd18fd5c | 1120 | max_packets = MAX_PACKET(64); |
3ffbba95 SS |
1121 | break; |
1122 | case USB_SPEED_LOW: | |
f5960b69 | 1123 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS); |
bd18fd5c | 1124 | max_packets = MAX_PACKET(8); |
3ffbba95 | 1125 | break; |
551cdbbe | 1126 | case USB_SPEED_WIRELESS: |
3ffbba95 SS |
1127 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
1128 | return -EINVAL; | |
1129 | break; | |
1130 | default: | |
1131 | /* Speed was set earlier, this shouldn't happen. */ | |
bd18fd5c | 1132 | return -EINVAL; |
3ffbba95 SS |
1133 | } |
1134 | /* Find the root hub port this device is under */ | |
f6ff0ac8 SS |
1135 | port_num = xhci_find_real_port_number(xhci, udev); |
1136 | if (!port_num) | |
1137 | return -EINVAL; | |
f5960b69 | 1138 | slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num)); |
f6ff0ac8 | 1139 | /* Set the port number in the virtual_device to the faked port number */ |
3ffbba95 SS |
1140 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; |
1141 | top_dev = top_dev->parent) | |
1142 | /* Found device below root hub */; | |
fe30182c | 1143 | dev->fake_port = top_dev->portnum; |
66381755 | 1144 | dev->real_port = port_num; |
f6ff0ac8 | 1145 | xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num); |
fe30182c | 1146 | xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port); |
3ffbba95 | 1147 | |
839c817c SS |
1148 | /* Find the right bandwidth table that this device will be a part of. |
1149 | * If this is a full speed device attached directly to a root port (or a | |
1150 | * decendent of one), it counts as a primary bandwidth domain, not a | |
1151 | * secondary bandwidth domain under a TT. An xhci_tt_info structure | |
1152 | * will never be created for the HS root hub. | |
1153 | */ | |
1154 | if (!udev->tt || !udev->tt->hub->parent) { | |
1155 | dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table; | |
1156 | } else { | |
1157 | struct xhci_root_port_bw_info *rh_bw; | |
1158 | struct xhci_tt_bw_info *tt_bw; | |
1159 | ||
1160 | rh_bw = &xhci->rh_bw[port_num - 1]; | |
1161 | /* Find the right TT. */ | |
1162 | list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) { | |
1163 | if (tt_bw->slot_id != udev->tt->hub->slot_id) | |
1164 | continue; | |
1165 | ||
1166 | if (!dev->udev->tt->multi || | |
1167 | (udev->tt->multi && | |
1168 | tt_bw->ttport == dev->udev->ttport)) { | |
1169 | dev->bw_table = &tt_bw->bw_table; | |
1170 | dev->tt_info = tt_bw; | |
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | if (!dev->tt_info) | |
1175 | xhci_warn(xhci, "WARN: Didn't find a matching TT\n"); | |
1176 | } | |
1177 | ||
aa1b13ef SS |
1178 | /* Is this a LS/FS device under an external HS hub? */ |
1179 | if (udev->tt && udev->tt->hub->parent) { | |
28ccd296 ME |
1180 | slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id | |
1181 | (udev->ttport << 8)); | |
07b6de10 | 1182 | if (udev->tt->multi) |
28ccd296 | 1183 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
3ffbba95 | 1184 | } |
700e2052 | 1185 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); |
3ffbba95 SS |
1186 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); |
1187 | ||
1188 | /* Step 4 - ring already allocated */ | |
1189 | /* Step 5 */ | |
28ccd296 | 1190 | ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); |
bd18fd5c | 1191 | |
3ffbba95 | 1192 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ |
bd18fd5c MN |
1193 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) | |
1194 | max_packets); | |
3ffbba95 | 1195 | |
28ccd296 ME |
1196 | ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | |
1197 | dev->eps[0].ring->cycle_state); | |
3ffbba95 | 1198 | |
a711edee FB |
1199 | trace_xhci_setup_addressable_virt_device(dev); |
1200 | ||
3ffbba95 SS |
1201 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ |
1202 | ||
1203 | return 0; | |
1204 | } | |
1205 | ||
dfa49c4a DT |
1206 | /* |
1207 | * Convert interval expressed as 2^(bInterval - 1) == interval into | |
1208 | * straight exponent value 2^n == interval. | |
1209 | * | |
1210 | */ | |
1211 | static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, | |
1212 | struct usb_host_endpoint *ep) | |
1213 | { | |
1214 | unsigned int interval; | |
1215 | ||
1216 | interval = clamp_val(ep->desc.bInterval, 1, 16) - 1; | |
1217 | if (interval != ep->desc.bInterval - 1) | |
1218 | dev_warn(&udev->dev, | |
cd3c18ba | 1219 | "ep %#x - rounding interval to %d %sframes\n", |
dfa49c4a | 1220 | ep->desc.bEndpointAddress, |
cd3c18ba DT |
1221 | 1 << interval, |
1222 | udev->speed == USB_SPEED_FULL ? "" : "micro"); | |
1223 | ||
1224 | if (udev->speed == USB_SPEED_FULL) { | |
1225 | /* | |
1226 | * Full speed isoc endpoints specify interval in frames, | |
1227 | * not microframes. We are using microframes everywhere, | |
1228 | * so adjust accordingly. | |
1229 | */ | |
1230 | interval += 3; /* 1 frame = 2^3 uframes */ | |
1231 | } | |
dfa49c4a DT |
1232 | |
1233 | return interval; | |
1234 | } | |
1235 | ||
1236 | /* | |
340a3504 | 1237 | * Convert bInterval expressed in microframes (in 1-255 range) to exponent of |
dfa49c4a DT |
1238 | * microframes, rounded down to nearest power of 2. |
1239 | */ | |
340a3504 SS |
1240 | static unsigned int xhci_microframes_to_exponent(struct usb_device *udev, |
1241 | struct usb_host_endpoint *ep, unsigned int desc_interval, | |
1242 | unsigned int min_exponent, unsigned int max_exponent) | |
dfa49c4a DT |
1243 | { |
1244 | unsigned int interval; | |
1245 | ||
340a3504 SS |
1246 | interval = fls(desc_interval) - 1; |
1247 | interval = clamp_val(interval, min_exponent, max_exponent); | |
1248 | if ((1 << interval) != desc_interval) | |
a5da9568 | 1249 | dev_dbg(&udev->dev, |
dfa49c4a DT |
1250 | "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n", |
1251 | ep->desc.bEndpointAddress, | |
1252 | 1 << interval, | |
340a3504 | 1253 | desc_interval); |
dfa49c4a DT |
1254 | |
1255 | return interval; | |
1256 | } | |
1257 | ||
340a3504 SS |
1258 | static unsigned int xhci_parse_microframe_interval(struct usb_device *udev, |
1259 | struct usb_host_endpoint *ep) | |
1260 | { | |
55c1945e SS |
1261 | if (ep->desc.bInterval == 0) |
1262 | return 0; | |
340a3504 SS |
1263 | return xhci_microframes_to_exponent(udev, ep, |
1264 | ep->desc.bInterval, 0, 15); | |
1265 | } | |
1266 | ||
1267 | ||
1268 | static unsigned int xhci_parse_frame_interval(struct usb_device *udev, | |
1269 | struct usb_host_endpoint *ep) | |
1270 | { | |
1271 | return xhci_microframes_to_exponent(udev, ep, | |
1272 | ep->desc.bInterval * 8, 3, 10); | |
1273 | } | |
1274 | ||
f94e0186 SS |
1275 | /* Return the polling or NAK interval. |
1276 | * | |
1277 | * The polling interval is expressed in "microframes". If xHCI's Interval field | |
1278 | * is set to N, it will service the endpoint every 2^(Interval)*125us. | |
1279 | * | |
1280 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval | |
1281 | * is set to 0. | |
1282 | */ | |
575688e1 | 1283 | static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, |
f94e0186 SS |
1284 | struct usb_host_endpoint *ep) |
1285 | { | |
1286 | unsigned int interval = 0; | |
1287 | ||
1288 | switch (udev->speed) { | |
1289 | case USB_SPEED_HIGH: | |
1290 | /* Max NAK rate */ | |
1291 | if (usb_endpoint_xfer_control(&ep->desc) || | |
dfa49c4a | 1292 | usb_endpoint_xfer_bulk(&ep->desc)) { |
340a3504 | 1293 | interval = xhci_parse_microframe_interval(udev, ep); |
dfa49c4a DT |
1294 | break; |
1295 | } | |
f94e0186 | 1296 | /* Fall through - SS and HS isoc/int have same decoding */ |
dfa49c4a | 1297 | |
0caf6b33 | 1298 | case USB_SPEED_SUPER_PLUS: |
f94e0186 SS |
1299 | case USB_SPEED_SUPER: |
1300 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1301 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1302 | interval = xhci_parse_exponent_interval(udev, ep); | |
f94e0186 SS |
1303 | } |
1304 | break; | |
dfa49c4a | 1305 | |
f94e0186 | 1306 | case USB_SPEED_FULL: |
b513d447 | 1307 | if (usb_endpoint_xfer_isoc(&ep->desc)) { |
dfa49c4a DT |
1308 | interval = xhci_parse_exponent_interval(udev, ep); |
1309 | break; | |
1310 | } | |
1311 | /* | |
b513d447 | 1312 | * Fall through for interrupt endpoint interval decoding |
dfa49c4a DT |
1313 | * since it uses the same rules as low speed interrupt |
1314 | * endpoints. | |
1315 | */ | |
1356cedd | 1316 | /* fall through */ |
dfa49c4a | 1317 | |
f94e0186 SS |
1318 | case USB_SPEED_LOW: |
1319 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1320 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1321 | ||
1322 | interval = xhci_parse_frame_interval(udev, ep); | |
f94e0186 SS |
1323 | } |
1324 | break; | |
dfa49c4a | 1325 | |
f94e0186 SS |
1326 | default: |
1327 | BUG(); | |
1328 | } | |
def4e6f7 | 1329 | return interval; |
f94e0186 SS |
1330 | } |
1331 | ||
c30c791c | 1332 | /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. |
1cf62246 SS |
1333 | * High speed endpoint descriptors can define "the number of additional |
1334 | * transaction opportunities per microframe", but that goes in the Max Burst | |
1335 | * endpoint context field. | |
1336 | */ | |
575688e1 | 1337 | static u32 xhci_get_endpoint_mult(struct usb_device *udev, |
1cf62246 SS |
1338 | struct usb_host_endpoint *ep) |
1339 | { | |
0caf6b33 | 1340 | if (udev->speed < USB_SPEED_SUPER || |
c30c791c | 1341 | !usb_endpoint_xfer_isoc(&ep->desc)) |
1cf62246 | 1342 | return 0; |
842f1690 | 1343 | return ep->ss_ep_comp.bmAttributes; |
1cf62246 SS |
1344 | } |
1345 | ||
def4e6f7 MN |
1346 | static u32 xhci_get_endpoint_max_burst(struct usb_device *udev, |
1347 | struct usb_host_endpoint *ep) | |
1348 | { | |
1349 | /* Super speed and Plus have max burst in ep companion desc */ | |
1350 | if (udev->speed >= USB_SPEED_SUPER) | |
1351 | return ep->ss_ep_comp.bMaxBurst; | |
1352 | ||
1353 | if (udev->speed == USB_SPEED_HIGH && | |
1354 | (usb_endpoint_xfer_isoc(&ep->desc) || | |
1355 | usb_endpoint_xfer_int(&ep->desc))) | |
dcf5228c | 1356 | return usb_endpoint_maxp_mult(&ep->desc) - 1; |
def4e6f7 MN |
1357 | |
1358 | return 0; | |
1359 | } | |
1360 | ||
4daf9df5 | 1361 | static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep) |
f94e0186 SS |
1362 | { |
1363 | int in; | |
f94e0186 SS |
1364 | |
1365 | in = usb_endpoint_dir_in(&ep->desc); | |
def4e6f7 | 1366 | |
c0e625c4 FB |
1367 | switch (usb_endpoint_type(&ep->desc)) { |
1368 | case USB_ENDPOINT_XFER_CONTROL: | |
def4e6f7 | 1369 | return CTRL_EP; |
c0e625c4 | 1370 | case USB_ENDPOINT_XFER_BULK: |
def4e6f7 | 1371 | return in ? BULK_IN_EP : BULK_OUT_EP; |
c0e625c4 | 1372 | case USB_ENDPOINT_XFER_ISOC: |
def4e6f7 | 1373 | return in ? ISOC_IN_EP : ISOC_OUT_EP; |
c0e625c4 | 1374 | case USB_ENDPOINT_XFER_INT: |
def4e6f7 | 1375 | return in ? INT_IN_EP : INT_OUT_EP; |
c0e625c4 | 1376 | } |
def4e6f7 | 1377 | return 0; |
f94e0186 SS |
1378 | } |
1379 | ||
9238f25d SS |
1380 | /* Return the maximum endpoint service interval time (ESIT) payload. |
1381 | * Basically, this is the maxpacket size, multiplied by the burst size | |
1382 | * and mult size. | |
1383 | */ | |
4daf9df5 | 1384 | static u32 xhci_get_max_esit_payload(struct usb_device *udev, |
9238f25d SS |
1385 | struct usb_host_endpoint *ep) |
1386 | { | |
1387 | int max_burst; | |
1388 | int max_packet; | |
1389 | ||
1390 | /* Only applies for interrupt or isochronous endpoints */ | |
1391 | if (usb_endpoint_xfer_control(&ep->desc) || | |
1392 | usb_endpoint_xfer_bulk(&ep->desc)) | |
1393 | return 0; | |
1394 | ||
8ef8a9f5 MN |
1395 | /* SuperSpeedPlus Isoc ep sending over 48k per esit */ |
1396 | if ((udev->speed >= USB_SPEED_SUPER_PLUS) && | |
1397 | USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes)) | |
1398 | return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval); | |
1399 | /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */ | |
1400 | else if (udev->speed >= USB_SPEED_SUPER) | |
64b3c304 | 1401 | return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); |
9238f25d | 1402 | |
734d3ddd | 1403 | max_packet = usb_endpoint_maxp(&ep->desc); |
dcf5228c | 1404 | max_burst = usb_endpoint_maxp_mult(&ep->desc); |
9238f25d | 1405 | /* A 0 in max burst means 1 transfer per ESIT */ |
dcf5228c | 1406 | return max_packet * max_burst; |
9238f25d SS |
1407 | } |
1408 | ||
8df75f42 SS |
1409 | /* Set up an endpoint with one ring segment. Do not allocate stream rings. |
1410 | * Drivers will have to call usb_alloc_streams() to do that. | |
1411 | */ | |
f94e0186 SS |
1412 | int xhci_endpoint_init(struct xhci_hcd *xhci, |
1413 | struct xhci_virt_device *virt_dev, | |
1414 | struct usb_device *udev, | |
f88ba78d SS |
1415 | struct usb_host_endpoint *ep, |
1416 | gfp_t mem_flags) | |
f94e0186 SS |
1417 | { |
1418 | unsigned int ep_index; | |
1419 | struct xhci_ep_ctx *ep_ctx; | |
1420 | struct xhci_ring *ep_ring; | |
1421 | unsigned int max_packet; | |
def4e6f7 | 1422 | enum xhci_ring_type ring_type; |
9238f25d | 1423 | u32 max_esit_payload; |
17d65554 | 1424 | u32 endpoint_type; |
def4e6f7 MN |
1425 | unsigned int max_burst; |
1426 | unsigned int interval; | |
1427 | unsigned int mult; | |
1428 | unsigned int avg_trb_len; | |
1429 | unsigned int err_count = 0; | |
f94e0186 SS |
1430 | |
1431 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1432 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 | 1433 | |
4daf9df5 | 1434 | endpoint_type = xhci_get_endpoint_type(ep); |
17d65554 MN |
1435 | if (!endpoint_type) |
1436 | return -EINVAL; | |
17d65554 | 1437 | |
def4e6f7 | 1438 | ring_type = usb_endpoint_type(&ep->desc); |
f94e0186 | 1439 | |
def4e6f7 MN |
1440 | /* |
1441 | * Get values to fill the endpoint context, mostly from ep descriptor. | |
1442 | * The average TRB buffer lengt for bulk endpoints is unclear as we | |
1443 | * have no clue on scatter gather list entry size. For Isoc and Int, | |
1444 | * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details. | |
1445 | */ | |
1446 | max_esit_payload = xhci_get_max_esit_payload(udev, ep); | |
1447 | interval = xhci_get_endpoint_interval(udev, ep); | |
69307ccb RQ |
1448 | |
1449 | /* Periodic endpoint bInterval limit quirk */ | |
1450 | if (usb_endpoint_xfer_int(&ep->desc) || | |
1451 | usb_endpoint_xfer_isoc(&ep->desc)) { | |
1452 | if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) && | |
1453 | udev->speed >= USB_SPEED_HIGH && | |
1454 | interval >= 7) { | |
1455 | interval = 6; | |
1456 | } | |
1457 | } | |
1458 | ||
def4e6f7 | 1459 | mult = xhci_get_endpoint_mult(udev, ep); |
734d3ddd | 1460 | max_packet = usb_endpoint_maxp(&ep->desc); |
def4e6f7 MN |
1461 | max_burst = xhci_get_endpoint_max_burst(udev, ep); |
1462 | avg_trb_len = max_esit_payload; | |
f94e0186 SS |
1463 | |
1464 | /* FIXME dig Mult and streams info out of ep companion desc */ | |
1465 | ||
def4e6f7 | 1466 | /* Allow 3 retries for everything but isoc, set CErr = 3 */ |
f94e0186 | 1467 | if (!usb_endpoint_xfer_isoc(&ep->desc)) |
def4e6f7 MN |
1468 | err_count = 3; |
1469 | /* Some devices get this wrong */ | |
1470 | if (usb_endpoint_xfer_bulk(&ep->desc) && udev->speed == USB_SPEED_HIGH) | |
1471 | max_packet = 512; | |
1472 | /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */ | |
dca77945 | 1473 | if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100) |
def4e6f7 | 1474 | avg_trb_len = 8; |
8ef8a9f5 MN |
1475 | /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */ |
1476 | if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2)) | |
1477 | mult = 0; | |
def4e6f7 | 1478 | |
f9c589e1 MN |
1479 | /* Set up the endpoint ring */ |
1480 | virt_dev->eps[ep_index].new_ring = | |
1481 | xhci_ring_alloc(xhci, 2, 1, ring_type, max_packet, mem_flags); | |
c5628a2a MN |
1482 | if (!virt_dev->eps[ep_index].new_ring) |
1483 | return -ENOMEM; | |
1484 | ||
f9c589e1 MN |
1485 | virt_dev->eps[ep_index].skip = false; |
1486 | ep_ring = virt_dev->eps[ep_index].new_ring; | |
1487 | ||
def4e6f7 | 1488 | /* Fill the endpoint context */ |
8ef8a9f5 MN |
1489 | ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) | |
1490 | EP_INTERVAL(interval) | | |
def4e6f7 MN |
1491 | EP_MULT(mult)); |
1492 | ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) | | |
1493 | MAX_PACKET(max_packet) | | |
1494 | MAX_BURST(max_burst) | | |
1495 | ERROR_COUNT(err_count)); | |
1496 | ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | | |
1497 | ep_ring->cycle_state); | |
1498 | ||
1499 | ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) | | |
1500 | EP_AVG_TRB_LENGTH(avg_trb_len)); | |
9238f25d | 1501 | |
f94e0186 SS |
1502 | return 0; |
1503 | } | |
1504 | ||
1505 | void xhci_endpoint_zero(struct xhci_hcd *xhci, | |
1506 | struct xhci_virt_device *virt_dev, | |
1507 | struct usb_host_endpoint *ep) | |
1508 | { | |
1509 | unsigned int ep_index; | |
1510 | struct xhci_ep_ctx *ep_ctx; | |
1511 | ||
1512 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1513 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
1514 | |
1515 | ep_ctx->ep_info = 0; | |
1516 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1517 | ep_ctx->deq = 0; |
f94e0186 SS |
1518 | ep_ctx->tx_info = 0; |
1519 | /* Don't free the endpoint ring until the set interface or configuration | |
1520 | * request succeeds. | |
1521 | */ | |
1522 | } | |
1523 | ||
9af5d71d SS |
1524 | void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info) |
1525 | { | |
1526 | bw_info->ep_interval = 0; | |
1527 | bw_info->mult = 0; | |
1528 | bw_info->num_packets = 0; | |
1529 | bw_info->max_packet_size = 0; | |
1530 | bw_info->type = 0; | |
1531 | bw_info->max_esit_payload = 0; | |
1532 | } | |
1533 | ||
1534 | void xhci_update_bw_info(struct xhci_hcd *xhci, | |
1535 | struct xhci_container_ctx *in_ctx, | |
1536 | struct xhci_input_control_ctx *ctrl_ctx, | |
1537 | struct xhci_virt_device *virt_dev) | |
1538 | { | |
1539 | struct xhci_bw_info *bw_info; | |
1540 | struct xhci_ep_ctx *ep_ctx; | |
1541 | unsigned int ep_type; | |
1542 | int i; | |
1543 | ||
98871e94 | 1544 | for (i = 1; i < 31; i++) { |
9af5d71d SS |
1545 | bw_info = &virt_dev->eps[i].bw_info; |
1546 | ||
1547 | /* We can't tell what endpoint type is being dropped, but | |
1548 | * unconditionally clearing the bandwidth info for non-periodic | |
1549 | * endpoints should be harmless because the info will never be | |
1550 | * set in the first place. | |
1551 | */ | |
1552 | if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) { | |
1553 | /* Dropped endpoint */ | |
1554 | xhci_clear_endpoint_bw_info(bw_info); | |
1555 | continue; | |
1556 | } | |
1557 | ||
1558 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
1559 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i); | |
1560 | ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2)); | |
1561 | ||
1562 | /* Ignore non-periodic endpoints */ | |
1563 | if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
1564 | ep_type != ISOC_IN_EP && | |
1565 | ep_type != INT_IN_EP) | |
1566 | continue; | |
1567 | ||
1568 | /* Added or changed endpoint */ | |
1569 | bw_info->ep_interval = CTX_TO_EP_INTERVAL( | |
1570 | le32_to_cpu(ep_ctx->ep_info)); | |
170c0263 SS |
1571 | /* Number of packets and mult are zero-based in the |
1572 | * input context, but we want one-based for the | |
1573 | * interval table. | |
9af5d71d | 1574 | */ |
170c0263 SS |
1575 | bw_info->mult = CTX_TO_EP_MULT( |
1576 | le32_to_cpu(ep_ctx->ep_info)) + 1; | |
9af5d71d SS |
1577 | bw_info->num_packets = CTX_TO_MAX_BURST( |
1578 | le32_to_cpu(ep_ctx->ep_info2)) + 1; | |
1579 | bw_info->max_packet_size = MAX_PACKET_DECODED( | |
1580 | le32_to_cpu(ep_ctx->ep_info2)); | |
1581 | bw_info->type = ep_type; | |
1582 | bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD( | |
1583 | le32_to_cpu(ep_ctx->tx_info)); | |
1584 | } | |
1585 | } | |
1586 | } | |
1587 | ||
f2217e8e SS |
1588 | /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. |
1589 | * Useful when you want to change one particular aspect of the endpoint and then | |
1590 | * issue a configure endpoint command. | |
1591 | */ | |
1592 | void xhci_endpoint_copy(struct xhci_hcd *xhci, | |
913a8a34 SS |
1593 | struct xhci_container_ctx *in_ctx, |
1594 | struct xhci_container_ctx *out_ctx, | |
1595 | unsigned int ep_index) | |
f2217e8e SS |
1596 | { |
1597 | struct xhci_ep_ctx *out_ep_ctx; | |
1598 | struct xhci_ep_ctx *in_ep_ctx; | |
1599 | ||
913a8a34 SS |
1600 | out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
1601 | in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); | |
f2217e8e SS |
1602 | |
1603 | in_ep_ctx->ep_info = out_ep_ctx->ep_info; | |
1604 | in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; | |
1605 | in_ep_ctx->deq = out_ep_ctx->deq; | |
1606 | in_ep_ctx->tx_info = out_ep_ctx->tx_info; | |
1607 | } | |
1608 | ||
1609 | /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. | |
1610 | * Useful when you want to change one particular aspect of the endpoint and then | |
1611 | * issue a configure endpoint command. Only the context entries field matters, | |
1612 | * but we'll copy the whole thing anyway. | |
1613 | */ | |
913a8a34 SS |
1614 | void xhci_slot_copy(struct xhci_hcd *xhci, |
1615 | struct xhci_container_ctx *in_ctx, | |
1616 | struct xhci_container_ctx *out_ctx) | |
f2217e8e SS |
1617 | { |
1618 | struct xhci_slot_ctx *in_slot_ctx; | |
1619 | struct xhci_slot_ctx *out_slot_ctx; | |
1620 | ||
913a8a34 SS |
1621 | in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
1622 | out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); | |
f2217e8e SS |
1623 | |
1624 | in_slot_ctx->dev_info = out_slot_ctx->dev_info; | |
1625 | in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; | |
1626 | in_slot_ctx->tt_info = out_slot_ctx->tt_info; | |
1627 | in_slot_ctx->dev_state = out_slot_ctx->dev_state; | |
1628 | } | |
1629 | ||
254c80a3 JY |
1630 | /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ |
1631 | static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
1632 | { | |
1633 | int i; | |
4c39d4b9 | 1634 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
254c80a3 JY |
1635 | int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); |
1636 | ||
d195fcff XR |
1637 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1638 | "Allocating %d scratchpad buffers", num_sp); | |
254c80a3 JY |
1639 | |
1640 | if (!num_sp) | |
1641 | return 0; | |
1642 | ||
1643 | xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags); | |
1644 | if (!xhci->scratchpad) | |
1645 | goto fail_sp; | |
1646 | ||
22d45f01 | 1647 | xhci->scratchpad->sp_array = dma_alloc_coherent(dev, |
254c80a3 | 1648 | num_sp * sizeof(u64), |
22d45f01 | 1649 | &xhci->scratchpad->sp_dma, flags); |
254c80a3 JY |
1650 | if (!xhci->scratchpad->sp_array) |
1651 | goto fail_sp2; | |
1652 | ||
1653 | xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); | |
1654 | if (!xhci->scratchpad->sp_buffers) | |
1655 | goto fail_sp3; | |
1656 | ||
28ccd296 | 1657 | xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); |
254c80a3 JY |
1658 | for (i = 0; i < num_sp; i++) { |
1659 | dma_addr_t dma; | |
7480d912 | 1660 | void *buf = dma_zalloc_coherent(dev, xhci->page_size, &dma, |
22d45f01 | 1661 | flags); |
254c80a3 | 1662 | if (!buf) |
314eaf7d | 1663 | goto fail_sp4; |
254c80a3 JY |
1664 | |
1665 | xhci->scratchpad->sp_array[i] = dma; | |
1666 | xhci->scratchpad->sp_buffers[i] = buf; | |
254c80a3 JY |
1667 | } |
1668 | ||
1669 | return 0; | |
1670 | ||
314eaf7d | 1671 | fail_sp4: |
254c80a3 | 1672 | for (i = i - 1; i >= 0; i--) { |
22d45f01 | 1673 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 | 1674 | xhci->scratchpad->sp_buffers[i], |
314eaf7d | 1675 | xhci->scratchpad->sp_array[i]); |
254c80a3 | 1676 | } |
254c80a3 | 1677 | |
254c80a3 JY |
1678 | kfree(xhci->scratchpad->sp_buffers); |
1679 | ||
1680 | fail_sp3: | |
22d45f01 | 1681 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1682 | xhci->scratchpad->sp_array, |
1683 | xhci->scratchpad->sp_dma); | |
1684 | ||
1685 | fail_sp2: | |
1686 | kfree(xhci->scratchpad); | |
1687 | xhci->scratchpad = NULL; | |
1688 | ||
1689 | fail_sp: | |
1690 | return -ENOMEM; | |
1691 | } | |
1692 | ||
1693 | static void scratchpad_free(struct xhci_hcd *xhci) | |
1694 | { | |
1695 | int num_sp; | |
1696 | int i; | |
4c39d4b9 | 1697 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
254c80a3 JY |
1698 | |
1699 | if (!xhci->scratchpad) | |
1700 | return; | |
1701 | ||
1702 | num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1703 | ||
1704 | for (i = 0; i < num_sp; i++) { | |
2a100047 | 1705 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 | 1706 | xhci->scratchpad->sp_buffers[i], |
314eaf7d | 1707 | xhci->scratchpad->sp_array[i]); |
254c80a3 | 1708 | } |
254c80a3 | 1709 | kfree(xhci->scratchpad->sp_buffers); |
2a100047 | 1710 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1711 | xhci->scratchpad->sp_array, |
1712 | xhci->scratchpad->sp_dma); | |
1713 | kfree(xhci->scratchpad); | |
1714 | xhci->scratchpad = NULL; | |
1715 | } | |
1716 | ||
913a8a34 | 1717 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
a1d78c16 SS |
1718 | bool allocate_in_ctx, bool allocate_completion, |
1719 | gfp_t mem_flags) | |
913a8a34 SS |
1720 | { |
1721 | struct xhci_command *command; | |
1722 | ||
1723 | command = kzalloc(sizeof(*command), mem_flags); | |
1724 | if (!command) | |
1725 | return NULL; | |
1726 | ||
a1d78c16 SS |
1727 | if (allocate_in_ctx) { |
1728 | command->in_ctx = | |
1729 | xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, | |
1730 | mem_flags); | |
1731 | if (!command->in_ctx) { | |
1732 | kfree(command); | |
1733 | return NULL; | |
1734 | } | |
06e18291 | 1735 | } |
913a8a34 SS |
1736 | |
1737 | if (allocate_completion) { | |
1738 | command->completion = | |
1739 | kzalloc(sizeof(struct completion), mem_flags); | |
1740 | if (!command->completion) { | |
1741 | xhci_free_container_ctx(xhci, command->in_ctx); | |
06e18291 | 1742 | kfree(command); |
913a8a34 SS |
1743 | return NULL; |
1744 | } | |
1745 | init_completion(command->completion); | |
1746 | } | |
1747 | ||
1748 | command->status = 0; | |
1749 | INIT_LIST_HEAD(&command->cmd_list); | |
1750 | return command; | |
1751 | } | |
1752 | ||
4daf9df5 | 1753 | void xhci_urb_free_priv(struct urb_priv *urb_priv) |
8e51adcc | 1754 | { |
7e64b037 | 1755 | kfree(urb_priv); |
8e51adcc AX |
1756 | } |
1757 | ||
913a8a34 SS |
1758 | void xhci_free_command(struct xhci_hcd *xhci, |
1759 | struct xhci_command *command) | |
1760 | { | |
1761 | xhci_free_container_ctx(xhci, | |
1762 | command->in_ctx); | |
1763 | kfree(command->completion); | |
1764 | kfree(command); | |
1765 | } | |
1766 | ||
66d4eadd SS |
1767 | void xhci_mem_cleanup(struct xhci_hcd *xhci) |
1768 | { | |
4c39d4b9 | 1769 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
0ebbab37 | 1770 | int size; |
32f1d2c5 | 1771 | int i, j, num_ports; |
0ebbab37 | 1772 | |
cb4d5ce5 | 1773 | cancel_delayed_work_sync(&xhci->cmd_timer); |
c311e391 | 1774 | |
0ebbab37 | 1775 | /* Free the Event Ring Segment Table and the actual Event Ring */ |
0ebbab37 SS |
1776 | size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); |
1777 | if (xhci->erst.entries) | |
2a100047 | 1778 | dma_free_coherent(dev, size, |
0ebbab37 SS |
1779 | xhci->erst.entries, xhci->erst.erst_dma_addr); |
1780 | xhci->erst.entries = NULL; | |
d195fcff | 1781 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST"); |
0ebbab37 SS |
1782 | if (xhci->event_ring) |
1783 | xhci_ring_free(xhci, xhci->event_ring); | |
1784 | xhci->event_ring = NULL; | |
d195fcff | 1785 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring"); |
0ebbab37 | 1786 | |
dbc33303 SS |
1787 | if (xhci->lpm_command) |
1788 | xhci_free_command(xhci, xhci->lpm_command); | |
0eda06c7 | 1789 | xhci->lpm_command = NULL; |
0ebbab37 SS |
1790 | if (xhci->cmd_ring) |
1791 | xhci_ring_free(xhci, xhci->cmd_ring); | |
1792 | xhci->cmd_ring = NULL; | |
d195fcff | 1793 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring"); |
c9aa1a2d | 1794 | xhci_cleanup_command_queue(xhci); |
3ffbba95 | 1795 | |
5dc2808c | 1796 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
c207e7c5 | 1797 | for (i = 0; i < num_ports && xhci->rh_bw; i++) { |
5dc2808c MN |
1798 | struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table; |
1799 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) { | |
1800 | struct list_head *ep = &bwt->interval_bw[j].endpoints; | |
1801 | while (!list_empty(ep)) | |
1802 | list_del_init(ep->next); | |
1803 | } | |
1804 | } | |
1805 | ||
ee8665e2 MN |
1806 | for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--) |
1807 | xhci_free_virt_devices_depth_first(xhci, i); | |
3ffbba95 | 1808 | |
c7360b34 | 1809 | dma_pool_destroy(xhci->segment_pool); |
0ebbab37 | 1810 | xhci->segment_pool = NULL; |
d195fcff | 1811 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool"); |
3ffbba95 | 1812 | |
c7360b34 | 1813 | dma_pool_destroy(xhci->device_pool); |
3ffbba95 | 1814 | xhci->device_pool = NULL; |
d195fcff | 1815 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool"); |
3ffbba95 | 1816 | |
c7360b34 | 1817 | dma_pool_destroy(xhci->small_streams_pool); |
8df75f42 | 1818 | xhci->small_streams_pool = NULL; |
d195fcff XR |
1819 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1820 | "Freed small stream array pool"); | |
8df75f42 | 1821 | |
c7360b34 | 1822 | dma_pool_destroy(xhci->medium_streams_pool); |
8df75f42 | 1823 | xhci->medium_streams_pool = NULL; |
d195fcff XR |
1824 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1825 | "Freed medium stream array pool"); | |
8df75f42 | 1826 | |
a74588f9 | 1827 | if (xhci->dcbaa) |
2a100047 | 1828 | dma_free_coherent(dev, sizeof(*xhci->dcbaa), |
a74588f9 SS |
1829 | xhci->dcbaa, xhci->dcbaa->dma); |
1830 | xhci->dcbaa = NULL; | |
3ffbba95 | 1831 | |
5294bea4 | 1832 | scratchpad_free(xhci); |
da6699ce | 1833 | |
88696ae4 VM |
1834 | if (!xhci->rh_bw) |
1835 | goto no_bw; | |
1836 | ||
32f1d2c5 TI |
1837 | for (i = 0; i < num_ports; i++) { |
1838 | struct xhci_tt_bw_info *tt, *n; | |
1839 | list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) { | |
1840 | list_del(&tt->tt_list); | |
1841 | kfree(tt); | |
1842 | } | |
f8a9e72d ON |
1843 | } |
1844 | ||
88696ae4 | 1845 | no_bw: |
127329d7 | 1846 | xhci->cmd_ring_reserved_trbs = 0; |
da6699ce SS |
1847 | xhci->num_usb2_ports = 0; |
1848 | xhci->num_usb3_ports = 0; | |
f8a9e72d | 1849 | xhci->num_active_eps = 0; |
da6699ce SS |
1850 | kfree(xhci->usb2_ports); |
1851 | kfree(xhci->usb3_ports); | |
1852 | kfree(xhci->port_array); | |
839c817c | 1853 | kfree(xhci->rh_bw); |
b630d4b9 | 1854 | kfree(xhci->ext_caps); |
da6699ce | 1855 | |
71504062 LB |
1856 | xhci->usb2_ports = NULL; |
1857 | xhci->usb3_ports = NULL; | |
1858 | xhci->port_array = NULL; | |
1859 | xhci->rh_bw = NULL; | |
1860 | xhci->ext_caps = NULL; | |
1861 | ||
66d4eadd SS |
1862 | xhci->page_size = 0; |
1863 | xhci->page_shift = 0; | |
20b67cf5 | 1864 | xhci->bus_state[0].bus_suspended = 0; |
f6ff0ac8 | 1865 | xhci->bus_state[1].bus_suspended = 0; |
66d4eadd SS |
1866 | } |
1867 | ||
6648f29d SS |
1868 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, |
1869 | struct xhci_segment *input_seg, | |
1870 | union xhci_trb *start_trb, | |
1871 | union xhci_trb *end_trb, | |
1872 | dma_addr_t input_dma, | |
1873 | struct xhci_segment *result_seg, | |
1874 | char *test_name, int test_number) | |
1875 | { | |
1876 | unsigned long long start_dma; | |
1877 | unsigned long long end_dma; | |
1878 | struct xhci_segment *seg; | |
1879 | ||
1880 | start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); | |
1881 | end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); | |
1882 | ||
cffb9be8 | 1883 | seg = trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, false); |
6648f29d SS |
1884 | if (seg != result_seg) { |
1885 | xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", | |
1886 | test_name, test_number); | |
1887 | xhci_warn(xhci, "Tested TRB math w/ seg %p and " | |
1888 | "input DMA 0x%llx\n", | |
1889 | input_seg, | |
1890 | (unsigned long long) input_dma); | |
1891 | xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " | |
1892 | "ending TRB %p (0x%llx DMA)\n", | |
1893 | start_trb, start_dma, | |
1894 | end_trb, end_dma); | |
1895 | xhci_warn(xhci, "Expected seg %p, got seg %p\n", | |
1896 | result_seg, seg); | |
cffb9be8 HG |
1897 | trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, |
1898 | true); | |
6648f29d SS |
1899 | return -1; |
1900 | } | |
1901 | return 0; | |
1902 | } | |
1903 | ||
1904 | /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ | |
4daf9df5 | 1905 | static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci) |
6648f29d SS |
1906 | { |
1907 | struct { | |
1908 | dma_addr_t input_dma; | |
1909 | struct xhci_segment *result_seg; | |
1910 | } simple_test_vector [] = { | |
1911 | /* A zeroed DMA field should fail */ | |
1912 | { 0, NULL }, | |
1913 | /* One TRB before the ring start should fail */ | |
1914 | { xhci->event_ring->first_seg->dma - 16, NULL }, | |
1915 | /* One byte before the ring start should fail */ | |
1916 | { xhci->event_ring->first_seg->dma - 1, NULL }, | |
1917 | /* Starting TRB should succeed */ | |
1918 | { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, | |
1919 | /* Ending TRB should succeed */ | |
1920 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, | |
1921 | xhci->event_ring->first_seg }, | |
1922 | /* One byte after the ring end should fail */ | |
1923 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, | |
1924 | /* One TRB after the ring end should fail */ | |
1925 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, | |
1926 | /* An address of all ones should fail */ | |
1927 | { (dma_addr_t) (~0), NULL }, | |
1928 | }; | |
1929 | struct { | |
1930 | struct xhci_segment *input_seg; | |
1931 | union xhci_trb *start_trb; | |
1932 | union xhci_trb *end_trb; | |
1933 | dma_addr_t input_dma; | |
1934 | struct xhci_segment *result_seg; | |
1935 | } complex_test_vector [] = { | |
1936 | /* Test feeding a valid DMA address from a different ring */ | |
1937 | { .input_seg = xhci->event_ring->first_seg, | |
1938 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1939 | .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1940 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1941 | .result_seg = NULL, | |
1942 | }, | |
1943 | /* Test feeding a valid end TRB from a different ring */ | |
1944 | { .input_seg = xhci->event_ring->first_seg, | |
1945 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1946 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1947 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1948 | .result_seg = NULL, | |
1949 | }, | |
1950 | /* Test feeding a valid start and end TRB from a different ring */ | |
1951 | { .input_seg = xhci->event_ring->first_seg, | |
1952 | .start_trb = xhci->cmd_ring->first_seg->trbs, | |
1953 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1954 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1955 | .result_seg = NULL, | |
1956 | }, | |
1957 | /* TRB in this ring, but after this TD */ | |
1958 | { .input_seg = xhci->event_ring->first_seg, | |
1959 | .start_trb = &xhci->event_ring->first_seg->trbs[0], | |
1960 | .end_trb = &xhci->event_ring->first_seg->trbs[3], | |
1961 | .input_dma = xhci->event_ring->first_seg->dma + 4*16, | |
1962 | .result_seg = NULL, | |
1963 | }, | |
1964 | /* TRB in this ring, but before this TD */ | |
1965 | { .input_seg = xhci->event_ring->first_seg, | |
1966 | .start_trb = &xhci->event_ring->first_seg->trbs[3], | |
1967 | .end_trb = &xhci->event_ring->first_seg->trbs[6], | |
1968 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1969 | .result_seg = NULL, | |
1970 | }, | |
1971 | /* TRB in this ring, but after this wrapped TD */ | |
1972 | { .input_seg = xhci->event_ring->first_seg, | |
1973 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1974 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1975 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1976 | .result_seg = NULL, | |
1977 | }, | |
1978 | /* TRB in this ring, but before this wrapped TD */ | |
1979 | { .input_seg = xhci->event_ring->first_seg, | |
1980 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1981 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1982 | .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, | |
1983 | .result_seg = NULL, | |
1984 | }, | |
1985 | /* TRB not in this ring, and we have a wrapped TD */ | |
1986 | { .input_seg = xhci->event_ring->first_seg, | |
1987 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1988 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1989 | .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, | |
1990 | .result_seg = NULL, | |
1991 | }, | |
1992 | }; | |
1993 | ||
1994 | unsigned int num_tests; | |
1995 | int i, ret; | |
1996 | ||
e10fa478 | 1997 | num_tests = ARRAY_SIZE(simple_test_vector); |
6648f29d SS |
1998 | for (i = 0; i < num_tests; i++) { |
1999 | ret = xhci_test_trb_in_td(xhci, | |
2000 | xhci->event_ring->first_seg, | |
2001 | xhci->event_ring->first_seg->trbs, | |
2002 | &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2003 | simple_test_vector[i].input_dma, | |
2004 | simple_test_vector[i].result_seg, | |
2005 | "Simple", i); | |
2006 | if (ret < 0) | |
2007 | return ret; | |
2008 | } | |
2009 | ||
e10fa478 | 2010 | num_tests = ARRAY_SIZE(complex_test_vector); |
6648f29d SS |
2011 | for (i = 0; i < num_tests; i++) { |
2012 | ret = xhci_test_trb_in_td(xhci, | |
2013 | complex_test_vector[i].input_seg, | |
2014 | complex_test_vector[i].start_trb, | |
2015 | complex_test_vector[i].end_trb, | |
2016 | complex_test_vector[i].input_dma, | |
2017 | complex_test_vector[i].result_seg, | |
2018 | "Complex", i); | |
2019 | if (ret < 0) | |
2020 | return ret; | |
2021 | } | |
2022 | xhci_dbg(xhci, "TRB math tests passed.\n"); | |
2023 | return 0; | |
2024 | } | |
2025 | ||
257d585a SS |
2026 | static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
2027 | { | |
2028 | u64 temp; | |
2029 | dma_addr_t deq; | |
2030 | ||
2031 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2032 | xhci->event_ring->dequeue); | |
2033 | if (deq == 0 && !in_interrupt()) | |
2034 | xhci_warn(xhci, "WARN something wrong with SW event ring " | |
2035 | "dequeue ptr.\n"); | |
2036 | /* Update HC event ring dequeue pointer */ | |
f7b2e403 | 2037 | temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
257d585a SS |
2038 | temp &= ERST_PTR_MASK; |
2039 | /* Don't clear the EHB bit (which is RW1C) because | |
2040 | * there might be more events to service. | |
2041 | */ | |
2042 | temp &= ~ERST_EHB; | |
d195fcff XR |
2043 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2044 | "// Write event ring dequeue pointer, " | |
2045 | "preserving EHB bit"); | |
477632df | 2046 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, |
257d585a SS |
2047 | &xhci->ir_set->erst_dequeue); |
2048 | } | |
2049 | ||
da6699ce | 2050 | static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, |
d5ddcdf4 | 2051 | __le32 __iomem *addr, int max_caps) |
da6699ce SS |
2052 | { |
2053 | u32 temp, port_offset, port_count; | |
2054 | int i; | |
b72eb843 | 2055 | u8 major_revision, minor_revision; |
47189098 | 2056 | struct xhci_hub *rhub; |
da6699ce | 2057 | |
47189098 | 2058 | temp = readl(addr); |
d5ddcdf4 | 2059 | major_revision = XHCI_EXT_PORT_MAJOR(temp); |
b72eb843 | 2060 | minor_revision = XHCI_EXT_PORT_MINOR(temp); |
47189098 | 2061 | |
d5ddcdf4 | 2062 | if (major_revision == 0x03) { |
47189098 | 2063 | rhub = &xhci->usb3_rhub; |
d5ddcdf4 | 2064 | } else if (major_revision <= 0x02) { |
47189098 MN |
2065 | rhub = &xhci->usb2_rhub; |
2066 | } else { | |
da6699ce SS |
2067 | xhci_warn(xhci, "Ignoring unknown port speed, " |
2068 | "Ext Cap %p, revision = 0x%x\n", | |
2069 | addr, major_revision); | |
2070 | /* Ignoring port protocol we can't understand. FIXME */ | |
2071 | return; | |
2072 | } | |
47189098 | 2073 | rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp); |
b72eb843 YT |
2074 | |
2075 | if (rhub->min_rev < minor_revision) | |
2076 | rhub->min_rev = minor_revision; | |
da6699ce SS |
2077 | |
2078 | /* Port offset and count in the third dword, see section 7.2 */ | |
b0ba9720 | 2079 | temp = readl(addr + 2); |
da6699ce SS |
2080 | port_offset = XHCI_EXT_PORT_OFF(temp); |
2081 | port_count = XHCI_EXT_PORT_COUNT(temp); | |
d195fcff XR |
2082 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2083 | "Ext Cap %p, port offset = %u, " | |
2084 | "count = %u, revision = 0x%x", | |
da6699ce SS |
2085 | addr, port_offset, port_count, major_revision); |
2086 | /* Port count includes the current port offset */ | |
2087 | if (port_offset == 0 || (port_offset + port_count - 1) > num_ports) | |
2088 | /* WTF? "Valid values are ‘1’ to MaxPorts" */ | |
2089 | return; | |
fc71ff75 | 2090 | |
47189098 MN |
2091 | rhub->psi_count = XHCI_EXT_PORT_PSIC(temp); |
2092 | if (rhub->psi_count) { | |
2093 | rhub->psi = kcalloc(rhub->psi_count, sizeof(*rhub->psi), | |
2094 | GFP_KERNEL); | |
2095 | if (!rhub->psi) | |
2096 | rhub->psi_count = 0; | |
2097 | ||
2098 | rhub->psi_uid_count++; | |
2099 | for (i = 0; i < rhub->psi_count; i++) { | |
2100 | rhub->psi[i] = readl(addr + 4 + i); | |
2101 | ||
2102 | /* count unique ID values, two consecutive entries can | |
2103 | * have the same ID if link is assymetric | |
2104 | */ | |
2105 | if (i && (XHCI_EXT_PORT_PSIV(rhub->psi[i]) != | |
2106 | XHCI_EXT_PORT_PSIV(rhub->psi[i - 1]))) | |
2107 | rhub->psi_uid_count++; | |
2108 | ||
2109 | xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n", | |
2110 | XHCI_EXT_PORT_PSIV(rhub->psi[i]), | |
2111 | XHCI_EXT_PORT_PSIE(rhub->psi[i]), | |
2112 | XHCI_EXT_PORT_PLT(rhub->psi[i]), | |
2113 | XHCI_EXT_PORT_PFD(rhub->psi[i]), | |
2114 | XHCI_EXT_PORT_LP(rhub->psi[i]), | |
2115 | XHCI_EXT_PORT_PSIM(rhub->psi[i])); | |
2116 | } | |
2117 | } | |
b630d4b9 MN |
2118 | /* cache usb2 port capabilities */ |
2119 | if (major_revision < 0x03 && xhci->num_ext_caps < max_caps) | |
2120 | xhci->ext_caps[xhci->num_ext_caps++] = temp; | |
2121 | ||
fc71ff75 AX |
2122 | /* Check the host's USB2 LPM capability */ |
2123 | if ((xhci->hci_version == 0x96) && (major_revision != 0x03) && | |
2124 | (temp & XHCI_L1C)) { | |
d195fcff XR |
2125 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2126 | "xHCI 0.96: support USB2 software lpm"); | |
fc71ff75 AX |
2127 | xhci->sw_lpm_support = 1; |
2128 | } | |
2129 | ||
2130 | if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) { | |
d195fcff XR |
2131 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2132 | "xHCI 1.0: support USB2 software lpm"); | |
fc71ff75 AX |
2133 | xhci->sw_lpm_support = 1; |
2134 | if (temp & XHCI_HLC) { | |
d195fcff XR |
2135 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2136 | "xHCI 1.0: support USB2 hardware lpm"); | |
fc71ff75 AX |
2137 | xhci->hw_lpm_support = 1; |
2138 | } | |
2139 | } | |
2140 | ||
da6699ce SS |
2141 | port_offset--; |
2142 | for (i = port_offset; i < (port_offset + port_count); i++) { | |
2143 | /* Duplicate entry. Ignore the port if the revisions differ. */ | |
2144 | if (xhci->port_array[i] != 0) { | |
2145 | xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," | |
2146 | " port %u\n", addr, i); | |
2147 | xhci_warn(xhci, "Port was marked as USB %u, " | |
2148 | "duplicated as USB %u\n", | |
2149 | xhci->port_array[i], major_revision); | |
2150 | /* Only adjust the roothub port counts if we haven't | |
2151 | * found a similar duplicate. | |
2152 | */ | |
2153 | if (xhci->port_array[i] != major_revision && | |
22e04870 | 2154 | xhci->port_array[i] != DUPLICATE_ENTRY) { |
da6699ce SS |
2155 | if (xhci->port_array[i] == 0x03) |
2156 | xhci->num_usb3_ports--; | |
2157 | else | |
2158 | xhci->num_usb2_ports--; | |
22e04870 | 2159 | xhci->port_array[i] = DUPLICATE_ENTRY; |
da6699ce SS |
2160 | } |
2161 | /* FIXME: Should we disable the port? */ | |
f8bbeabc | 2162 | continue; |
da6699ce SS |
2163 | } |
2164 | xhci->port_array[i] = major_revision; | |
2165 | if (major_revision == 0x03) | |
2166 | xhci->num_usb3_ports++; | |
2167 | else | |
2168 | xhci->num_usb2_ports++; | |
2169 | } | |
2170 | /* FIXME: Should we disable ports not in the Extended Capabilities? */ | |
2171 | } | |
2172 | ||
2173 | /* | |
2174 | * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that | |
2175 | * specify what speeds each port is supposed to be. We can't count on the port | |
2176 | * speed bits in the PORTSC register being correct until a device is connected, | |
2177 | * but we need to set up the two fake roothubs with the correct number of USB | |
2178 | * 3.0 and USB 2.0 ports at host controller initialization time. | |
2179 | */ | |
2180 | static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) | |
2181 | { | |
d5ddcdf4 MN |
2182 | void __iomem *base; |
2183 | u32 offset; | |
da6699ce | 2184 | unsigned int num_ports; |
2e27980e | 2185 | int i, j, port_index; |
b630d4b9 | 2186 | int cap_count = 0; |
d5ddcdf4 | 2187 | u32 cap_start; |
da6699ce SS |
2188 | |
2189 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); | |
2190 | xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags); | |
2191 | if (!xhci->port_array) | |
2192 | return -ENOMEM; | |
2193 | ||
839c817c SS |
2194 | xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags); |
2195 | if (!xhci->rh_bw) | |
2196 | return -ENOMEM; | |
2e27980e SS |
2197 | for (i = 0; i < num_ports; i++) { |
2198 | struct xhci_interval_bw_table *bw_table; | |
2199 | ||
839c817c | 2200 | INIT_LIST_HEAD(&xhci->rh_bw[i].tts); |
2e27980e SS |
2201 | bw_table = &xhci->rh_bw[i].bw_table; |
2202 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
2203 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
2204 | } | |
d5ddcdf4 | 2205 | base = &xhci->cap_regs->hc_capbase; |
839c817c | 2206 | |
d5ddcdf4 MN |
2207 | cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL); |
2208 | if (!cap_start) { | |
2209 | xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n"); | |
2210 | return -ENODEV; | |
2211 | } | |
b630d4b9 | 2212 | |
d5ddcdf4 | 2213 | offset = cap_start; |
b630d4b9 | 2214 | /* count extended protocol capability entries for later caching */ |
d5ddcdf4 MN |
2215 | while (offset) { |
2216 | cap_count++; | |
2217 | offset = xhci_find_next_ext_cap(base, offset, | |
2218 | XHCI_EXT_CAPS_PROTOCOL); | |
2219 | } | |
b630d4b9 MN |
2220 | |
2221 | xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags); | |
2222 | if (!xhci->ext_caps) | |
2223 | return -ENOMEM; | |
2224 | ||
d5ddcdf4 MN |
2225 | offset = cap_start; |
2226 | ||
2227 | while (offset) { | |
2228 | xhci_add_in_port(xhci, num_ports, base + offset, cap_count); | |
2229 | if (xhci->num_usb2_ports + xhci->num_usb3_ports == num_ports) | |
da6699ce | 2230 | break; |
d5ddcdf4 MN |
2231 | offset = xhci_find_next_ext_cap(base, offset, |
2232 | XHCI_EXT_CAPS_PROTOCOL); | |
da6699ce SS |
2233 | } |
2234 | ||
2235 | if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) { | |
2236 | xhci_warn(xhci, "No ports on the roothubs?\n"); | |
2237 | return -ENODEV; | |
2238 | } | |
d195fcff XR |
2239 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2240 | "Found %u USB 2.0 ports and %u USB 3.0 ports.", | |
da6699ce | 2241 | xhci->num_usb2_ports, xhci->num_usb3_ports); |
d30b2a20 SS |
2242 | |
2243 | /* Place limits on the number of roothub ports so that the hub | |
2244 | * descriptors aren't longer than the USB core will allocate. | |
2245 | */ | |
5120a266 | 2246 | if (xhci->num_usb3_ports > USB_SS_MAXPORTS) { |
d195fcff | 2247 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
5120a266 JH |
2248 | "Limiting USB 3.0 roothub ports to %u.", |
2249 | USB_SS_MAXPORTS); | |
2250 | xhci->num_usb3_ports = USB_SS_MAXPORTS; | |
d30b2a20 SS |
2251 | } |
2252 | if (xhci->num_usb2_ports > USB_MAXCHILDREN) { | |
d195fcff XR |
2253 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2254 | "Limiting USB 2.0 roothub ports to %u.", | |
d30b2a20 SS |
2255 | USB_MAXCHILDREN); |
2256 | xhci->num_usb2_ports = USB_MAXCHILDREN; | |
2257 | } | |
2258 | ||
da6699ce SS |
2259 | /* |
2260 | * Note we could have all USB 3.0 ports, or all USB 2.0 ports. | |
2261 | * Not sure how the USB core will handle a hub with no ports... | |
2262 | */ | |
2263 | if (xhci->num_usb2_ports) { | |
2264 | xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)* | |
2265 | xhci->num_usb2_ports, flags); | |
2266 | if (!xhci->usb2_ports) | |
2267 | return -ENOMEM; | |
2268 | ||
2269 | port_index = 0; | |
f8bbeabc SS |
2270 | for (i = 0; i < num_ports; i++) { |
2271 | if (xhci->port_array[i] == 0x03 || | |
2272 | xhci->port_array[i] == 0 || | |
22e04870 | 2273 | xhci->port_array[i] == DUPLICATE_ENTRY) |
f8bbeabc SS |
2274 | continue; |
2275 | ||
2276 | xhci->usb2_ports[port_index] = | |
2277 | &xhci->op_regs->port_status_base + | |
2278 | NUM_PORT_REGS*i; | |
d195fcff XR |
2279 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2280 | "USB 2.0 port at index %u, " | |
2281 | "addr = %p", i, | |
f8bbeabc SS |
2282 | xhci->usb2_ports[port_index]); |
2283 | port_index++; | |
d30b2a20 SS |
2284 | if (port_index == xhci->num_usb2_ports) |
2285 | break; | |
f8bbeabc | 2286 | } |
da6699ce SS |
2287 | } |
2288 | if (xhci->num_usb3_ports) { | |
2289 | xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)* | |
2290 | xhci->num_usb3_ports, flags); | |
2291 | if (!xhci->usb3_ports) | |
2292 | return -ENOMEM; | |
2293 | ||
2294 | port_index = 0; | |
2295 | for (i = 0; i < num_ports; i++) | |
2296 | if (xhci->port_array[i] == 0x03) { | |
2297 | xhci->usb3_ports[port_index] = | |
2298 | &xhci->op_regs->port_status_base + | |
2299 | NUM_PORT_REGS*i; | |
d195fcff XR |
2300 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2301 | "USB 3.0 port at index %u, " | |
2302 | "addr = %p", i, | |
da6699ce SS |
2303 | xhci->usb3_ports[port_index]); |
2304 | port_index++; | |
d30b2a20 SS |
2305 | if (port_index == xhci->num_usb3_ports) |
2306 | break; | |
da6699ce SS |
2307 | } |
2308 | } | |
2309 | return 0; | |
2310 | } | |
6648f29d | 2311 | |
66d4eadd SS |
2312 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) |
2313 | { | |
0ebbab37 | 2314 | dma_addr_t dma; |
4c39d4b9 | 2315 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
66d4eadd | 2316 | unsigned int val, val2; |
8e595a5d | 2317 | u64 val_64; |
0ebbab37 | 2318 | struct xhci_segment *seg; |
623bef9e | 2319 | u32 page_size, temp; |
66d4eadd SS |
2320 | int i; |
2321 | ||
c9aa1a2d | 2322 | INIT_LIST_HEAD(&xhci->cmd_list); |
331de00a | 2323 | |
cb4d5ce5 OH |
2324 | /* init command timeout work */ |
2325 | INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout); | |
1c111b6c | 2326 | init_completion(&xhci->cmd_ring_stop_completion); |
cc8e4fc0 | 2327 | |
b0ba9720 | 2328 | page_size = readl(&xhci->op_regs->page_size); |
d195fcff XR |
2329 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2330 | "Supported page size register = 0x%x", page_size); | |
66d4eadd SS |
2331 | for (i = 0; i < 16; i++) { |
2332 | if ((0x1 & page_size) != 0) | |
2333 | break; | |
2334 | page_size = page_size >> 1; | |
2335 | } | |
2336 | if (i < 16) | |
d195fcff XR |
2337 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2338 | "Supported page size of %iK", (1 << (i+12)) / 1024); | |
66d4eadd SS |
2339 | else |
2340 | xhci_warn(xhci, "WARN: no supported page size\n"); | |
2341 | /* Use 4K pages, since that's common and the minimum the HC supports */ | |
2342 | xhci->page_shift = 12; | |
2343 | xhci->page_size = 1 << xhci->page_shift; | |
d195fcff XR |
2344 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2345 | "HCD page size set to %iK", xhci->page_size / 1024); | |
66d4eadd SS |
2346 | |
2347 | /* | |
2348 | * Program the Number of Device Slots Enabled field in the CONFIG | |
2349 | * register with the max value of slots the HC can handle. | |
2350 | */ | |
b0ba9720 | 2351 | val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1)); |
d195fcff XR |
2352 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2353 | "// xHC can handle at most %d device slots.", val); | |
b0ba9720 | 2354 | val2 = readl(&xhci->op_regs->config_reg); |
66d4eadd | 2355 | val |= (val2 & ~HCS_SLOTS_MASK); |
d195fcff XR |
2356 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2357 | "// Setting Max device slots reg = 0x%x.", val); | |
204b7793 | 2358 | writel(val, &xhci->op_regs->config_reg); |
66d4eadd | 2359 | |
a74588f9 | 2360 | /* |
724e882d | 2361 | * xHCI section 5.4.6 - doorbell array must be |
a74588f9 SS |
2362 | * "physically contiguous and 64-byte (cache line) aligned". |
2363 | */ | |
22d45f01 | 2364 | xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, |
c95a9f83 | 2365 | flags); |
a74588f9 SS |
2366 | if (!xhci->dcbaa) |
2367 | goto fail; | |
2368 | memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); | |
2369 | xhci->dcbaa->dma = dma; | |
d195fcff XR |
2370 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2371 | "// Device context base array address = 0x%llx (DMA), %p (virt)", | |
700e2052 | 2372 | (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); |
477632df | 2373 | xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); |
a74588f9 | 2374 | |
0ebbab37 SS |
2375 | /* |
2376 | * Initialize the ring segment pool. The ring must be a contiguous | |
2377 | * structure comprised of TRBs. The TRBs must be 16 byte aligned, | |
84c1e40f HG |
2378 | * however, the command ring segment needs 64-byte aligned segments |
2379 | * and our use of dma addresses in the trb_address_map radix tree needs | |
2380 | * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need. | |
0ebbab37 SS |
2381 | */ |
2382 | xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, | |
84c1e40f | 2383 | TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size); |
d115b048 | 2384 | |
3ffbba95 | 2385 | /* See Table 46 and Note on Figure 55 */ |
3ffbba95 | 2386 | xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, |
d115b048 | 2387 | 2112, 64, xhci->page_size); |
3ffbba95 | 2388 | if (!xhci->segment_pool || !xhci->device_pool) |
0ebbab37 SS |
2389 | goto fail; |
2390 | ||
8df75f42 SS |
2391 | /* Linear stream context arrays don't have any boundary restrictions, |
2392 | * and only need to be 16-byte aligned. | |
2393 | */ | |
2394 | xhci->small_streams_pool = | |
2395 | dma_pool_create("xHCI 256 byte stream ctx arrays", | |
2396 | dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); | |
2397 | xhci->medium_streams_pool = | |
2398 | dma_pool_create("xHCI 1KB stream ctx arrays", | |
2399 | dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); | |
2400 | /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE | |
22d45f01 | 2401 | * will be allocated with dma_alloc_coherent() |
8df75f42 SS |
2402 | */ |
2403 | ||
2404 | if (!xhci->small_streams_pool || !xhci->medium_streams_pool) | |
2405 | goto fail; | |
2406 | ||
0ebbab37 | 2407 | /* Set up the command ring to have one segments for now. */ |
f9c589e1 | 2408 | xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, 0, flags); |
0ebbab37 SS |
2409 | if (!xhci->cmd_ring) |
2410 | goto fail; | |
d195fcff XR |
2411 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2412 | "Allocated command ring at %p", xhci->cmd_ring); | |
2413 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx", | |
700e2052 | 2414 | (unsigned long long)xhci->cmd_ring->first_seg->dma); |
0ebbab37 SS |
2415 | |
2416 | /* Set the address in the Command Ring Control register */ | |
f7b2e403 | 2417 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
8e595a5d SS |
2418 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
2419 | (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | | |
0ebbab37 | 2420 | xhci->cmd_ring->cycle_state; |
d195fcff | 2421 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
6fc091fb | 2422 | "// Setting command ring address to 0x%016llx", val_64); |
477632df | 2423 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
0ebbab37 SS |
2424 | xhci_dbg_cmd_ptrs(xhci); |
2425 | ||
dbc33303 SS |
2426 | xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags); |
2427 | if (!xhci->lpm_command) | |
2428 | goto fail; | |
2429 | ||
2430 | /* Reserve one command ring TRB for disabling LPM. | |
2431 | * Since the USB core grabs the shared usb_bus bandwidth mutex before | |
2432 | * disabling LPM, we only need to reserve one TRB for all devices. | |
2433 | */ | |
2434 | xhci->cmd_ring_reserved_trbs++; | |
2435 | ||
b0ba9720 | 2436 | val = readl(&xhci->cap_regs->db_off); |
0ebbab37 | 2437 | val &= DBOFF_MASK; |
d195fcff XR |
2438 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2439 | "// Doorbell array is located at offset 0x%x" | |
2440 | " from cap regs base addr", val); | |
c50a00f8 | 2441 | xhci->dba = (void __iomem *) xhci->cap_regs + val; |
0ebbab37 SS |
2442 | xhci_dbg_regs(xhci); |
2443 | xhci_print_run_regs(xhci); | |
2444 | /* Set ir_set to interrupt register set 0 */ | |
c50a00f8 | 2445 | xhci->ir_set = &xhci->run_regs->ir_set[0]; |
0ebbab37 SS |
2446 | |
2447 | /* | |
2448 | * Event ring setup: Allocate a normal ring, but also setup | |
2449 | * the event ring segment table (ERST). Section 4.9.3. | |
2450 | */ | |
d195fcff | 2451 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring"); |
186a7ef1 | 2452 | xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT, |
f9c589e1 | 2453 | 0, flags); |
0ebbab37 SS |
2454 | if (!xhci->event_ring) |
2455 | goto fail; | |
4daf9df5 | 2456 | if (xhci_check_trb_in_td_math(xhci) < 0) |
6648f29d | 2457 | goto fail; |
0ebbab37 | 2458 | |
22d45f01 SAS |
2459 | xhci->erst.entries = dma_alloc_coherent(dev, |
2460 | sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma, | |
c95a9f83 | 2461 | flags); |
0ebbab37 SS |
2462 | if (!xhci->erst.entries) |
2463 | goto fail; | |
d195fcff XR |
2464 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2465 | "// Allocated event ring segment table at 0x%llx", | |
700e2052 | 2466 | (unsigned long long)dma); |
0ebbab37 SS |
2467 | |
2468 | memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); | |
2469 | xhci->erst.num_entries = ERST_NUM_SEGS; | |
2470 | xhci->erst.erst_dma_addr = dma; | |
d195fcff XR |
2471 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2472 | "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx", | |
0ebbab37 | 2473 | xhci->erst.num_entries, |
700e2052 GKH |
2474 | xhci->erst.entries, |
2475 | (unsigned long long)xhci->erst.erst_dma_addr); | |
0ebbab37 SS |
2476 | |
2477 | /* set ring base address and size for each segment table entry */ | |
2478 | for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { | |
2479 | struct xhci_erst_entry *entry = &xhci->erst.entries[val]; | |
28ccd296 ME |
2480 | entry->seg_addr = cpu_to_le64(seg->dma); |
2481 | entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); | |
0ebbab37 SS |
2482 | entry->rsvd = 0; |
2483 | seg = seg->next; | |
2484 | } | |
2485 | ||
2486 | /* set ERST count with the number of entries in the segment table */ | |
b0ba9720 | 2487 | val = readl(&xhci->ir_set->erst_size); |
0ebbab37 SS |
2488 | val &= ERST_SIZE_MASK; |
2489 | val |= ERST_NUM_SEGS; | |
d195fcff XR |
2490 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2491 | "// Write ERST size = %i to ir_set 0 (some bits preserved)", | |
0ebbab37 | 2492 | val); |
204b7793 | 2493 | writel(val, &xhci->ir_set->erst_size); |
0ebbab37 | 2494 | |
d195fcff XR |
2495 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2496 | "// Set ERST entries to point to event ring."); | |
0ebbab37 | 2497 | /* set the segment table base address */ |
d195fcff XR |
2498 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2499 | "// Set ERST base address for ir_set 0 = 0x%llx", | |
700e2052 | 2500 | (unsigned long long)xhci->erst.erst_dma_addr); |
f7b2e403 | 2501 | val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
8e595a5d SS |
2502 | val_64 &= ERST_PTR_MASK; |
2503 | val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); | |
477632df | 2504 | xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); |
0ebbab37 SS |
2505 | |
2506 | /* Set the event ring dequeue address */ | |
23e3be11 | 2507 | xhci_set_hc_event_deq(xhci); |
d195fcff XR |
2508 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2509 | "Wrote ERST address to ir_set 0."); | |
09ece30e | 2510 | xhci_print_ir_set(xhci, 0); |
0ebbab37 SS |
2511 | |
2512 | /* | |
2513 | * XXX: Might need to set the Interrupter Moderation Register to | |
2514 | * something other than the default (~1ms minimum between interrupts). | |
2515 | * See section 5.5.1.2. | |
2516 | */ | |
98871e94 | 2517 | for (i = 0; i < MAX_HC_SLOTS; i++) |
326b4810 | 2518 | xhci->devs[i] = NULL; |
98871e94 | 2519 | for (i = 0; i < USB_MAXCHILDREN; i++) { |
20b67cf5 | 2520 | xhci->bus_state[0].resume_done[i] = 0; |
f6ff0ac8 | 2521 | xhci->bus_state[1].resume_done[i] = 0; |
8b3d4570 SS |
2522 | /* Only the USB 2.0 completions will ever be used. */ |
2523 | init_completion(&xhci->bus_state[1].rexit_done[i]); | |
f6ff0ac8 | 2524 | } |
66d4eadd | 2525 | |
254c80a3 JY |
2526 | if (scratchpad_alloc(xhci, flags)) |
2527 | goto fail; | |
da6699ce SS |
2528 | if (xhci_setup_port_arrays(xhci, flags)) |
2529 | goto fail; | |
254c80a3 | 2530 | |
623bef9e SS |
2531 | /* Enable USB 3.0 device notifications for function remote wake, which |
2532 | * is necessary for allowing USB 3.0 devices to do remote wakeup from | |
2533 | * U3 (device suspend). | |
2534 | */ | |
b0ba9720 | 2535 | temp = readl(&xhci->op_regs->dev_notification); |
623bef9e SS |
2536 | temp &= ~DEV_NOTE_MASK; |
2537 | temp |= DEV_NOTE_FWAKE; | |
204b7793 | 2538 | writel(temp, &xhci->op_regs->dev_notification); |
623bef9e | 2539 | |
66d4eadd | 2540 | return 0; |
254c80a3 | 2541 | |
66d4eadd | 2542 | fail: |
159e1fcc SS |
2543 | xhci_halt(xhci); |
2544 | xhci_reset(xhci); | |
66d4eadd SS |
2545 | xhci_mem_cleanup(xhci); |
2546 | return -ENOMEM; | |
2547 | } |