[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

#ifndef glue
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s)	tostring(s)
#define tostring(s)	#s
#endif

#if GCC_MAJOR < 3
#define __builtin_expect(x, n) (x)
#endif

#ifdef __i386__
#define REGPARM(n) __attribute((regparm(n)))
#else
#define REGPARM(n)
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
extern uint32_t gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);
                    
#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb, 
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb, 
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(void);
int page_unprotect(unsigned long address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page(CPUState *env, target_ulong vaddr, 
                 target_phys_addr_t paddr, int prot, 
                 int is_user, int is_softmmu);

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_HASH_BITS     15
#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
#define CODE_GEN_BUFFER_SIZE     (8 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__) 
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    struct TranslationBlock *hash_next; /* next matching tb for virtual address */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next; 
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2]; 
    target_ulong page_addr[2]; 

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2]; 
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_HASH_SIZE - 1);
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(unsigned long pc);
void tb_flush(CPUState *env);
void tb_link(TranslationBlock *tb);
void tb_link_phys(TranslationBlock *tb, 
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

/* find a translation block in the translation cache. If not found,
   return NULL and the pointer to the last element of the list in pptb */
static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
                                        target_ulong pc, 
                                        target_ulong cs_base,
                                        unsigned int flags)
{
    TranslationBlock **ptb, *tb;
    unsigned int h;
 
    h = tb_hash_func(pc);
    ptb = &tb_hash[h];
    for(;;) {
        tb = *ptb;
        if (!tb)
            break;
        if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
            return tb;
        ptb = &tb->hash_next;
    }
    *pptb = ptb;
    return NULL;
}


#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n, 
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
        
        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#define ASM_NAME(x) "_" #x
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#define ASM_NAME(x) stringify(x)
#endif

#if defined(__powerpc__)

/* we patch the jump instruction directly */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    asm volatile (ASM_DATA_SECTION\
		  ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "b " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
    EXIT_TB();\
} while (0)

#define JUMP_TB2(opname, tbparam, n)\
do {\
    asm volatile ("b " ASM_NAME(__op_jmp) #n "\n");\
} while (0)

#elif defined(__i386__) && defined(USE_DIRECT_JUMP)

/* we patch the jump instruction directly */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    asm volatile (".section .data\n"\
		  ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "jmp " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
    EXIT_TB();\
} while (0)

#define JUMP_TB2(opname, tbparam, n)\
do {\
    asm volatile ("jmp " ASM_NAME(__op_jmp) #n "\n");\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n:\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
dummy_label ## n:\
    EXIT_TB();\
} while (0)

/* second jump to same destination 'n' */
#define JUMP_TB2(opname, tbparam, n)\
do {\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
} while (0)

#endif

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1\n"
                          "      xor. %0,%3,%0\n"
                          "      bne 1f\n"
                          "      stwcx. %2,0,%1\n"
                          "      bne- 0b\n"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    char ret;
    long int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __x86_64__
static inline int testandset (int *p)
{
    char ret;
    int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

#ifdef __arm__
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));
    
    return ret;
}
#endif

#ifdef __mc68000
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret == 0;
}
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(unsigned long addr, int is_write, int is_user, 
              void *retaddr);

#define ACCESS_TYPE 3
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
/* XXX: i386 target specific */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int is_user, index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
#if defined(TARGET_I386)
    is_user = ((env->hflags & HF_CPL_MASK) == 3);
#elif defined (TARGET_PPC)
    is_user = msr_pr;
#elif defined (TARGET_SPARC)
    is_user = (env->psrs == 0);
#else
#error "Unimplemented !"
#endif
    if (__builtin_expect(env->tlb_read[is_user][index].address != 
                         (addr & TARGET_PAGE_MASK), 0)) {
#if defined (TARGET_PPC)
	env->access_type = ACCESS_CODE;
	ldub_code((void *)addr);
	env->access_type = ACCESS_INT;
#else
        ldub_code((void *)addr);
#endif
    }
    return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
}
#endif
Commit	Line	Data
d4e8164f FB	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
33417e70 FB	24	#ifndef glue
	25	#define xglue(x, y) x ## y
	26	#define glue(x, y) xglue(x, y)
	27	#define stringify(s) tostring(s)
	28	#define tostring(s) #s
	29	#endif
	30
	31	#if GCC_MAJOR < 3
	32	#define __builtin_expect(x, n) (x)
	33	#endif
	34
e2222c39 FB	35	#ifdef __i386__
	36	#define REGPARM(n) __attribute((regparm(n)))
	37	#else
	38	#define REGPARM(n)
	39	#endif
	40
b346ff46 FB	41	/* is_jmp field values */
	42	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	43	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	44	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	45	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	46
	47	struct TranslationBlock;
	48
	49	/* XXX: make safe guess about sizes */
	50	#define MAX_OP_PER_INSTR 32
	51	#define OPC_BUF_SIZE 512
	52	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	53
	54	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	55
	56	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	57	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
	58	extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
e95c8d51	59	extern uint32_t gen_opc_npc[OPC_BUF_SIZE];
66e85a21	60	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46 FB	61	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
b346ff46 FB	62
9886cc16 FB	63	typedef void (GenOpFunc)(void);
	64	typedef void (GenOpFunc1)(long);
	65	typedef void (GenOpFunc2)(long, long);
	66	typedef void (GenOpFunc3)(long, long, long);
	67
b346ff46 FB	68	#if defined(TARGET_I386)
b346ff46 FB	69
33417e70	70	void optimize_flags_init(void);
d4e8164f	71
b346ff46 FB	72	#endif
	73
	74	extern FILE *logfile;
	75	extern int loglevel;
	76
4c3a88a2 FB	77	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	78	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
b346ff46	79	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
4c3a88a2	80	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
b346ff46	81	int max_code_size, int *gen_code_size_ptr);
66e85a21	82	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	83	CPUState *env, unsigned long searched_pc,
	84	void *puc);
	85	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	86	int max_code_size, int *gen_code_size_ptr);
	87	int cpu_restore_state_copy(struct TranslationBlock *tb,
	88	CPUState *env, unsigned long searched_pc,
	89	void *puc);
2e12669a	90	void cpu_resume_from_signal(CPUState env1, void puc);
b346ff46	91	void cpu_exec_init(void);
2e12669a FB	92	int page_unprotect(unsigned long address, unsigned long pc, void *puc);
	93	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
	94	int is_cpu_write_access);
4390df51	95	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	96	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	97	void tlb_flush(CPUState *env, int flush_global);
2e12669a FB	98	int tlb_set_page(CPUState *env, target_ulong vaddr,
2e12669a FB	99	target_phys_addr_t paddr, int prot,
4390df51	100	int is_user, int is_softmmu);
d4e8164f FB	101
	102	#define CODE_GEN_MAX_SIZE 65536
	103	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	104
	105	#define CODE_GEN_HASH_BITS 15
	106	#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
	107
4390df51 FB	108	#define CODE_GEN_PHYS_HASH_BITS 15
	109	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	110
d4e8164f	111	/* maximum total translate dcode allocated */
4390df51 FB	112
4390df51 FB	113	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	114	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	115	summary of the ranges:
	116
	117	i386 : signed 32 bits
	118	arm : signed 26 bits
	119	ppc : signed 24 bits
	120	sparc : signed 32 bits
	121	alpha : signed 23 bits
	122	*/
	123
	124	#if defined(__alpha__)
	125	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
	126	#elif defined(__powerpc__)
c4c7e3e6	127	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51 FB	128	#else
	129	#define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024)
	130	#endif
	131
d4e8164f FB	132	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	133
4390df51 FB	134	/* estimated block size for TB allocation */
	135	/* XXX: use a per code average code fragment size and modulate it
	136	according to the host CPU */
	137	#if defined(CONFIG_SOFTMMU)
	138	#define CODE_GEN_AVG_BLOCK_SIZE 128
	139	#else
	140	#define CODE_GEN_AVG_BLOCK_SIZE 64
	141	#endif
	142
	143	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	144
	145	#if defined(__powerpc__)
	146	#define USE_DIRECT_JUMP
	147	#endif
67b915a5	148	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	149	#define USE_DIRECT_JUMP
	150	#endif
	151
	152	typedef struct TranslationBlock {
2e12669a FB	153	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	154	target_ulong cs_base; /* CS base for this block */
d4e8164f FB	155	unsigned int flags; /* flags defining in which context the code was generated */
	156	uint16_t size; /* size of target code for this block (1 <=
	157	size <= TARGET_PAGE_SIZE) */
58fe2f10	158	uint16_t cflags; /* compile flags */
bf088061 FB	159	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	160	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
	161	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	162	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	163
d4e8164f	164	uint8_t tc_ptr; / pointer to the translated code */
4390df51 FB	165	struct TranslationBlock hash_next; / next matching tb for virtual address */
	166	/* next matching tb for physical address. */
	167	struct TranslationBlock *phys_hash_next;
	168	/* first and second physical page containing code. The lower bit
	169	of the pointer tells the index in page_next[] */
	170	struct TranslationBlock *page_next[2];
	171	target_ulong page_addr[2];
	172
d4e8164f FB	173	/* the following data are used to directly call another TB from
	174	the code of this one. */
	175	uint16_t tb_next_offset[2]; /* offset of original jump target */
	176	#ifdef USE_DIRECT_JUMP
4cbb86e1	177	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	178	#else
95f7652d	179	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	180	#endif
	181	/* list of TBs jumping to this one. This is a circular list using
	182	the two least significant bits of the pointers to tell what is
	183	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	184	jmp_first */
	185	struct TranslationBlock *jmp_next[2];
	186	struct TranslationBlock *jmp_first;
	187	} TranslationBlock;
	188
	189	static inline unsigned int tb_hash_func(unsigned long pc)
	190	{
	191	return pc & (CODE_GEN_HASH_SIZE - 1);
	192	}
	193
4390df51 FB	194	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	195	{
	196	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	197	}
	198
d4e8164f	199	TranslationBlock *tb_alloc(unsigned long pc);
0124311e	200	void tb_flush(CPUState *env);
d4e8164f	201	void tb_link(TranslationBlock *tb);
4390df51 FB	202	void tb_link_phys(TranslationBlock *tb,
4390df51 FB	203	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f FB	204
d4e8164f FB	205	extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
4390df51	206	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	207
	208	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	209	extern uint8_t *code_gen_ptr;
	210
	211	/* find a translation block in the translation cache. If not found,
	212	return NULL and the pointer to the last element of the list in pptb */
	213	static inline TranslationBlock tb_find(TranslationBlock **pptb,
2e12669a FB	214	target_ulong pc,
2e12669a FB	215	target_ulong cs_base,
d4e8164f FB	216	unsigned int flags)
	217	{
	218	TranslationBlock *ptb, tb;
	219	unsigned int h;
	220
	221	h = tb_hash_func(pc);
	222	ptb = &tb_hash[h];
	223	for(;;) {
	224	tb = *ptb;
	225	if (!tb)
	226	break;
	227	if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
	228	return tb;
	229	ptb = &tb->hash_next;
	230	}
	231	*pptb = ptb;
	232	return NULL;
	233	}
	234
d4e8164f	235
4390df51 FB	236	#if defined(USE_DIRECT_JUMP)
	237
	238	#if defined(__powerpc__)
4cbb86e1	239	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	240	{
d4e8164f FB	241	uint32_t val, *ptr;
d4e8164f FB	242
d4e8164f FB	243	/* patch the branch destination */
4cbb86e1	244	ptr = (uint32_t *)jmp_addr;
d4e8164f	245	val = *ptr;
4cbb86e1	246	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	247	*ptr = val;
	248	/* flush icache */
	249	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	250	asm volatile ("sync" : : : "memory");
	251	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	252	asm volatile ("sync" : : : "memory");
	253	asm volatile ("isync" : : : "memory");
	254	}
4390df51 FB	255	#elif defined(__i386__)
	256	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	257	{
	258	/* patch the branch destination */
	259	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	260	/* no need to flush icache explicitely */
	261	}
	262	#endif
d4e8164f	263
4cbb86e1 FB	264	static inline void tb_set_jmp_target(TranslationBlock *tb,
	265	int n, unsigned long addr)
	266	{
	267	unsigned long offset;
	268
	269	offset = tb->tb_jmp_offset[n];
	270	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	271	offset = tb->tb_jmp_offset[n + 2];
	272	if (offset != 0xffff)
	273	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	274	}
	275
d4e8164f FB	276	#else
	277
	278	/* set the jump target */
	279	static inline void tb_set_jmp_target(TranslationBlock *tb,
	280	int n, unsigned long addr)
	281	{
95f7652d	282	tb->tb_next[n] = addr;
d4e8164f FB	283	}
	284
	285	#endif
	286
	287	static inline void tb_add_jump(TranslationBlock *tb, int n,
	288	TranslationBlock *tb_next)
	289	{
cf25629d FB	290	/* NOTE: this test is only needed for thread safety */
	291	if (!tb->jmp_next[n]) {
	292	/* patch the native jump address */
	293	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	294
	295	/* add in TB jmp circular list */
	296	tb->jmp_next[n] = tb_next->jmp_first;
	297	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	298	}
d4e8164f FB	299	}
d4e8164f FB	300
a513fe19 FB	301	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	302
d4e8164f FB	303	#ifndef offsetof
	304	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	305	#endif
	306
d549f7d9 FB	307	#if defined(_WIN32)
	308	#define ASM_DATA_SECTION ".section \".data\"\n"
	309	#define ASM_PREVIOUS_SECTION ".section .text\n"
	310	#elif defined(__APPLE__)
	311	#define ASM_DATA_SECTION ".data\n"
	312	#define ASM_PREVIOUS_SECTION ".text\n"
	313	#define ASM_NAME(x) "_" #x
	314	#else
	315	#define ASM_DATA_SECTION ".section \".data\"\n"
	316	#define ASM_PREVIOUS_SECTION ".previous\n"
	317	#define ASM_NAME(x) stringify(x)
	318	#endif
	319
b346ff46 FB	320	#if defined(__powerpc__)
b346ff46 FB	321
4390df51	322	/* we patch the jump instruction directly */
9257a9e4	323	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46	324	do {\
d549f7d9 FB	325	asm volatile (ASM_DATA_SECTION\
d549f7d9 FB	326	ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
9257a9e4	327	".long 1f\n"\
d549f7d9 FB	328	ASM_PREVIOUS_SECTION \
d549f7d9 FB	329	"b " ASM_NAME(__op_jmp) #n "\n"\
9257a9e4	330	"1:\n");\
b346ff46 FB	331	T0 = (long)(tbparam) + (n);\
b346ff46 FB	332	EIP = eip;\
31e8f3c8	333	EXIT_TB();\
b346ff46 FB	334	} while (0)
b346ff46 FB	335
4cbb86e1 FB	336	#define JUMP_TB2(opname, tbparam, n)\
4cbb86e1 FB	337	do {\
d549f7d9	338	asm volatile ("b " ASM_NAME(__op_jmp) #n "\n");\
4390df51 FB	339	} while (0)
	340
	341	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
	342
	343	/* we patch the jump instruction directly */
	344	#define JUMP_TB(opname, tbparam, n, eip)\
	345	do {\
67b915a5	346	asm volatile (".section .data\n"\
d549f7d9	347	ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
4390df51	348	".long 1f\n"\
67b915a5	349	ASM_PREVIOUS_SECTION \
d549f7d9	350	"jmp " ASM_NAME(__op_jmp) #n "\n"\
4390df51 FB	351	"1:\n");\
	352	T0 = (long)(tbparam) + (n);\
	353	EIP = eip;\
	354	EXIT_TB();\
	355	} while (0)
	356
	357	#define JUMP_TB2(opname, tbparam, n)\
	358	do {\
d549f7d9	359	asm volatile ("jmp " ASM_NAME(__op_jmp) #n "\n");\
4cbb86e1 FB	360	} while (0)
4cbb86e1 FB	361
b346ff46 FB	362	#else
	363
	364	/* jump to next block operations (more portable code, does not need
	365	cache flushing, but slower because of indirect jump) */
9257a9e4	366	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46 FB	367	do {\
b346ff46 FB	368	static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
2f62b397	369	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
b346ff46 FB	370	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
	371	label ## n:\
	372	T0 = (long)(tbparam) + (n);\
	373	EIP = eip;\
2f62b397	374	dummy_label ## n:\
9621339d	375	EXIT_TB();\
b346ff46 FB	376	} while (0)
b346ff46 FB	377
4cbb86e1 FB	378	/* second jump to same destination 'n' */
	379	#define JUMP_TB2(opname, tbparam, n)\
	380	do {\
4390df51	381	goto (void )(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
4cbb86e1 FB	382	} while (0)
4cbb86e1 FB	383
b346ff46 FB	384	#endif
b346ff46 FB	385
33417e70 FB	386	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	387	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	388	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	389
d4e8164f FB	390	#ifdef __powerpc__
	391	static inline int testandset (int *p)
	392	{
	393	int ret;
	394	__asm__ __volatile__ (
02e1ec9b FB	395	"0: lwarx %0,0,%1\n"
	396	" xor. %0,%3,%0\n"
	397	" bne 1f\n"
	398	" stwcx. %2,0,%1\n"
	399	" bne- 0b\n"
d4e8164f FB	400	"1: "
	401	: "=&r" (ret)
	402	: "r" (p), "r" (1), "r" (0)
	403	: "cr0", "memory");
	404	return ret;
	405	}
	406	#endif
	407
	408	#ifdef __i386__
	409	static inline int testandset (int *p)
	410	{
	411	char ret;
	412	long int readval;
	413
	414	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	415	: "=q" (ret), "=m" (*p), "=a" (readval)
	416	: "r" (1), "m" (*p), "a" (0)
	417	: "memory");
	418	return ret;
	419	}
	420	#endif
	421
bc51c5c9 FB	422	#ifdef __x86_64__
	423	static inline int testandset (int *p)
	424	{
	425	char ret;
	426	int readval;
	427
	428	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	429	: "=q" (ret), "=m" (*p), "=a" (readval)
	430	: "r" (1), "m" (*p), "a" (0)
	431	: "memory");
	432	return ret;
	433	}
	434	#endif
	435
d4e8164f FB	436	#ifdef __s390__
	437	static inline int testandset (int *p)
	438	{
	439	int ret;
	440
	441	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	442	" jl 0b"
	443	: "=&d" (ret)
	444	: "r" (1), "a" (p), "0" (*p)
	445	: "cc", "memory" );
	446	return ret;
	447	}
	448	#endif
	449
	450	#ifdef __alpha__
2f87c607	451	static inline int testandset (int *p)
d4e8164f FB	452	{
	453	int ret;
	454	unsigned long one;
	455
	456	__asm__ __volatile__ ("0: mov 1,%2\n"
	457	" ldl_l %0,%1\n"
	458	" stl_c %2,%1\n"
	459	" beq %2,1f\n"
	460	".subsection 2\n"
	461	"1: br 0b\n"
	462	".previous"
	463	: "=r" (ret), "=m" (*p), "=r" (one)
	464	: "m" (*p));
	465	return ret;
	466	}
	467	#endif
	468
	469	#ifdef __sparc__
	470	static inline int testandset (int *p)
	471	{
	472	int ret;
	473
	474	__asm__ __volatile__("ldstub [%1], %0"
	475	: "=r" (ret)
	476	: "r" (p)
	477	: "memory");
	478
	479	return (ret ? 1 : 0);
	480	}
	481	#endif
	482
a95c6790 FB	483	#ifdef __arm__
	484	static inline int testandset (int *spinlock)
	485	{
	486	register unsigned int ret;
	487	__asm__ __volatile__("swp %0, %1, [%2]"
	488	: "=r"(ret)
	489	: "0"(1), "r"(spinlock));
	490
	491	return ret;
	492	}
	493	#endif
	494
38e584a0 FB	495	#ifdef __mc68000
	496	static inline int testandset (int *p)
	497	{
	498	char ret;
	499	__asm__ __volatile__("tas %1; sne %0"
	500	: "=r" (ret)
	501	: "m" (p)
	502	: "cc","memory");
	503	return ret == 0;
	504	}
	505	#endif
	506
d4e8164f FB	507	typedef int spinlock_t;
	508
	509	#define SPIN_LOCK_UNLOCKED 0
	510
aebcb60e	511	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	512	static inline void spin_lock(spinlock_t *lock)
	513	{
	514	while (testandset(lock));
	515	}
	516
	517	static inline void spin_unlock(spinlock_t *lock)
	518	{
	519	*lock = 0;
	520	}
	521
	522	static inline int spin_trylock(spinlock_t *lock)
	523	{
	524	return !testandset(lock);
	525	}
3c1cf9fa FB	526	#else
	527	static inline void spin_lock(spinlock_t *lock)
	528	{
	529	}
	530
	531	static inline void spin_unlock(spinlock_t *lock)
	532	{
	533	}
	534
	535	static inline int spin_trylock(spinlock_t *lock)
	536	{
	537	return 1;
	538	}
	539	#endif
d4e8164f FB	540
	541	extern spinlock_t tb_lock;
	542
36bdbe54	543	extern int tb_invalidated_flag;
6e59c1db	544
e95c8d51	545	#if !defined(CONFIG_USER_ONLY)
6e59c1db FB	546
	547	void tlb_fill(unsigned long addr, int is_write, int is_user,
	548	void *retaddr);
	549
	550	#define ACCESS_TYPE 3
	551	#define MEMSUFFIX _code
	552	#define env cpu_single_env
	553
	554	#define DATA_SIZE 1
	555	#include "softmmu_header.h"
	556
	557	#define DATA_SIZE 2
	558	#include "softmmu_header.h"
	559
	560	#define DATA_SIZE 4
	561	#include "softmmu_header.h"
	562
	563	#undef ACCESS_TYPE
	564	#undef MEMSUFFIX
	565	#undef env
	566
	567	#endif
4390df51 FB	568
	569	#if defined(CONFIG_USER_ONLY)
	570	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	571	{
	572	return addr;
	573	}
	574	#else
	575	/* NOTE: this function can trigger an exception */
1ccde1cb FB	576	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	577	is the offset relative to phys_ram_base */
4390df51 FB	578	/* XXX: i386 target specific */
	579	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	580	{
	581	int is_user, index;
	582
	583	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
3f5dcc34	584	#if defined(TARGET_I386)
4390df51	585	is_user = ((env->hflags & HF_CPL_MASK) == 3);
3f5dcc34 FB	586	#elif defined (TARGET_PPC)
3f5dcc34 FB	587	is_user = msr_pr;
e95c8d51 FB	588	#elif defined (TARGET_SPARC)
e95c8d51 FB	589	is_user = (env->psrs == 0);
3f5dcc34 FB	590	#else
	591	#error "Unimplemented !"
	592	#endif
4390df51 FB	593	if (__builtin_expect(env->tlb_read[is_user][index].address !=
4390df51 FB	594	(addr & TARGET_PAGE_MASK), 0)) {
a541f297 FB	595	#if defined (TARGET_PPC)
	596	env->access_type = ACCESS_CODE;
	597	ldub_code((void *)addr);
	598	env->access_type = ACCESS_INT;
	599	#else
4390df51	600	ldub_code((void *)addr);
a541f297	601	#endif
4390df51 FB	602	}
	603	return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
	604	}
	605	#endif