]>
Commit | Line | Data |
---|---|---|
d4e8164f FB |
1 | /* |
2 | * internal execution defines for qemu | |
5fafdf24 | 3 | * |
d4e8164f FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
b346ff46 | 21 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
cb7cca1a | 22 | #define DEBUG_DISAS |
b346ff46 FB |
23 | |
24 | /* is_jmp field values */ | |
25 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ | |
26 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ | |
27 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ | |
28 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ | |
29 | ||
2e70f6ef | 30 | typedef struct TranslationBlock TranslationBlock; |
b346ff46 FB |
31 | |
32 | /* XXX: make safe guess about sizes */ | |
e83a8673 | 33 | #define MAX_OP_PER_INSTR 64 |
0115be31 PB |
34 | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */ |
35 | #define MAX_OPC_PARAM 10 | |
b346ff46 FB |
36 | #define OPC_BUF_SIZE 512 |
37 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) | |
38 | ||
a208e54a PB |
39 | /* Maximum size a TCG op can expand to. This is complicated because a |
40 | single op may require several host instructions and regirster reloads. | |
41 | For now take a wild guess at 128 bytes, which should allow at least | |
42 | a couple of fixup instructions per argument. */ | |
43 | #define TCG_MAX_OP_SIZE 128 | |
44 | ||
0115be31 | 45 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) |
b346ff46 | 46 | |
c27004ec FB |
47 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE]; |
48 | extern target_ulong gen_opc_npc[OPC_BUF_SIZE]; | |
66e85a21 | 49 | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
b346ff46 | 50 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; |
2e70f6ef | 51 | extern uint16_t gen_opc_icount[OPC_BUF_SIZE]; |
c3278b7b | 52 | extern target_ulong gen_opc_jump_pc[2]; |
30d6cb84 | 53 | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE]; |
b346ff46 | 54 | |
9886cc16 FB |
55 | typedef void (GenOpFunc)(void); |
56 | typedef void (GenOpFunc1)(long); | |
57 | typedef void (GenOpFunc2)(long, long); | |
58 | typedef void (GenOpFunc3)(long, long, long); | |
3b46e624 | 59 | |
b346ff46 FB |
60 | extern FILE *logfile; |
61 | extern int loglevel; | |
62 | ||
4c3a88a2 FB |
63 | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
64 | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); | |
d2856f1a AJ |
65 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
66 | unsigned long searched_pc, int pc_pos, void *puc); | |
67 | ||
d07bde88 | 68 | unsigned long code_gen_max_block_size(void); |
57fec1fe | 69 | void cpu_gen_init(void); |
4c3a88a2 | 70 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
d07bde88 | 71 | int *gen_code_size_ptr); |
5fafdf24 | 72 | int cpu_restore_state(struct TranslationBlock *tb, |
58fe2f10 FB |
73 | CPUState *env, unsigned long searched_pc, |
74 | void *puc); | |
5fafdf24 | 75 | int cpu_restore_state_copy(struct TranslationBlock *tb, |
58fe2f10 FB |
76 | CPUState *env, unsigned long searched_pc, |
77 | void *puc); | |
2e12669a | 78 | void cpu_resume_from_signal(CPUState *env1, void *puc); |
2e70f6ef PB |
79 | void cpu_io_recompile(CPUState *env, void *retaddr); |
80 | TranslationBlock *tb_gen_code(CPUState *env, | |
81 | target_ulong pc, target_ulong cs_base, int flags, | |
82 | int cflags); | |
6a00d601 | 83 | void cpu_exec_init(CPUState *env); |
53a5960a | 84 | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
00f82b8a | 85 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
2e12669a | 86 | int is_cpu_write_access); |
4390df51 | 87 | void tb_invalidate_page_range(target_ulong start, target_ulong end); |
2e12669a | 88 | void tlb_flush_page(CPUState *env, target_ulong addr); |
ee8b7021 | 89 | void tlb_flush(CPUState *env, int flush_global); |
5fafdf24 TS |
90 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
91 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 92 | int mmu_idx, int is_softmmu); |
4d7a0880 | 93 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, |
5fafdf24 | 94 | target_phys_addr_t paddr, int prot, |
6ebbf390 | 95 | int mmu_idx, int is_softmmu) |
84b7b8e7 FB |
96 | { |
97 | if (prot & PAGE_READ) | |
98 | prot |= PAGE_EXEC; | |
4d7a0880 | 99 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu); |
84b7b8e7 | 100 | } |
d4e8164f | 101 | |
d4e8164f FB |
102 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
103 | ||
4390df51 FB |
104 | #define CODE_GEN_PHYS_HASH_BITS 15 |
105 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) | |
106 | ||
26a5f13b | 107 | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
d4e8164f | 108 | |
4390df51 FB |
109 | /* estimated block size for TB allocation */ |
110 | /* XXX: use a per code average code fragment size and modulate it | |
111 | according to the host CPU */ | |
112 | #if defined(CONFIG_SOFTMMU) | |
113 | #define CODE_GEN_AVG_BLOCK_SIZE 128 | |
114 | #else | |
115 | #define CODE_GEN_AVG_BLOCK_SIZE 64 | |
116 | #endif | |
117 | ||
811d4cf4 | 118 | #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__) |
4390df51 FB |
119 | #define USE_DIRECT_JUMP |
120 | #endif | |
67b915a5 | 121 | #if defined(__i386__) && !defined(_WIN32) |
d4e8164f FB |
122 | #define USE_DIRECT_JUMP |
123 | #endif | |
124 | ||
2e70f6ef | 125 | struct TranslationBlock { |
2e12669a FB |
126 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
127 | target_ulong cs_base; /* CS base for this block */ | |
c068688b | 128 | uint64_t flags; /* flags defining in which context the code was generated */ |
d4e8164f FB |
129 | uint16_t size; /* size of target code for this block (1 <= |
130 | size <= TARGET_PAGE_SIZE) */ | |
58fe2f10 | 131 | uint16_t cflags; /* compile flags */ |
2e70f6ef PB |
132 | #define CF_COUNT_MASK 0x7fff |
133 | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ | |
58fe2f10 | 134 | |
d4e8164f | 135 | uint8_t *tc_ptr; /* pointer to the translated code */ |
4390df51 | 136 | /* next matching tb for physical address. */ |
5fafdf24 | 137 | struct TranslationBlock *phys_hash_next; |
4390df51 FB |
138 | /* first and second physical page containing code. The lower bit |
139 | of the pointer tells the index in page_next[] */ | |
5fafdf24 TS |
140 | struct TranslationBlock *page_next[2]; |
141 | target_ulong page_addr[2]; | |
4390df51 | 142 | |
d4e8164f FB |
143 | /* the following data are used to directly call another TB from |
144 | the code of this one. */ | |
145 | uint16_t tb_next_offset[2]; /* offset of original jump target */ | |
146 | #ifdef USE_DIRECT_JUMP | |
4cbb86e1 | 147 | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
d4e8164f | 148 | #else |
57fec1fe | 149 | unsigned long tb_next[2]; /* address of jump generated code */ |
d4e8164f FB |
150 | #endif |
151 | /* list of TBs jumping to this one. This is a circular list using | |
152 | the two least significant bits of the pointers to tell what is | |
153 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = | |
154 | jmp_first */ | |
5fafdf24 | 155 | struct TranslationBlock *jmp_next[2]; |
d4e8164f | 156 | struct TranslationBlock *jmp_first; |
2e70f6ef PB |
157 | uint32_t icount; |
158 | }; | |
d4e8164f | 159 | |
b362e5e0 PB |
160 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
161 | { | |
162 | target_ulong tmp; | |
163 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
b5e19d4c | 164 | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK; |
b362e5e0 PB |
165 | } |
166 | ||
8a40a180 | 167 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
d4e8164f | 168 | { |
b362e5e0 PB |
169 | target_ulong tmp; |
170 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
b5e19d4c EI |
171 | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) |
172 | | (tmp & TB_JMP_ADDR_MASK)); | |
d4e8164f FB |
173 | } |
174 | ||
4390df51 FB |
175 | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
176 | { | |
177 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); | |
178 | } | |
179 | ||
c27004ec | 180 | TranslationBlock *tb_alloc(target_ulong pc); |
2e70f6ef | 181 | void tb_free(TranslationBlock *tb); |
0124311e | 182 | void tb_flush(CPUState *env); |
5fafdf24 | 183 | void tb_link_phys(TranslationBlock *tb, |
4390df51 | 184 | target_ulong phys_pc, target_ulong phys_page2); |
2e70f6ef | 185 | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr); |
d4e8164f | 186 | |
4390df51 | 187 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
d4e8164f | 188 | extern uint8_t *code_gen_ptr; |
26a5f13b | 189 | extern int code_gen_max_blocks; |
d4e8164f | 190 | |
4390df51 FB |
191 | #if defined(USE_DIRECT_JUMP) |
192 | ||
193 | #if defined(__powerpc__) | |
0a878c47 | 194 | static inline void flush_icache_range(unsigned long start, unsigned long stop); |
4cbb86e1 | 195 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
d4e8164f | 196 | { |
0a878c47 | 197 | /* This must be in concord with INDEX_op_goto_tb inside tcg_out_op */ |
198 | uint32_t *ptr; | |
932a6909 | 199 | long disp = addr - jmp_addr; |
0a878c47 | 200 | unsigned long patch_size; |
d4e8164f | 201 | |
4cbb86e1 | 202 | ptr = (uint32_t *)jmp_addr; |
932a6909 FB |
203 | |
204 | if ((disp << 6) >> 6 != disp) { | |
0a878c47 | 205 | ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */ |
206 | ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */ | |
207 | ptr[2] = 0x7c0903a6; /* mtctr 0 */ | |
208 | ptr[3] = 0x4e800420; /* brctr */ | |
209 | patch_size = 16; | |
932a6909 FB |
210 | } else { |
211 | /* patch the branch destination */ | |
0a878c47 | 212 | if (disp != 16) { |
213 | *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */ | |
214 | patch_size = 4; | |
215 | } else { | |
216 | ptr[0] = 0x60000000; /* nop */ | |
217 | ptr[1] = 0x60000000; | |
218 | ptr[2] = 0x60000000; | |
219 | ptr[3] = 0x60000000; | |
220 | patch_size = 16; | |
221 | } | |
932a6909 | 222 | } |
d4e8164f | 223 | /* flush icache */ |
0a878c47 | 224 | flush_icache_range(jmp_addr, jmp_addr + patch_size); |
d4e8164f | 225 | } |
57fec1fe | 226 | #elif defined(__i386__) || defined(__x86_64__) |
4390df51 FB |
227 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
228 | { | |
229 | /* patch the branch destination */ | |
230 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); | |
1235fc06 | 231 | /* no need to flush icache explicitly */ |
4390df51 | 232 | } |
811d4cf4 AZ |
233 | #elif defined(__arm__) |
234 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) | |
235 | { | |
236 | register unsigned long _beg __asm ("a1"); | |
237 | register unsigned long _end __asm ("a2"); | |
238 | register unsigned long _flg __asm ("a3"); | |
239 | ||
240 | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ | |
241 | *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff; | |
242 | ||
243 | /* flush icache */ | |
244 | _beg = jmp_addr; | |
245 | _end = jmp_addr + 4; | |
246 | _flg = 0; | |
247 | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); | |
248 | } | |
4390df51 | 249 | #endif |
d4e8164f | 250 | |
5fafdf24 | 251 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
4cbb86e1 FB |
252 | int n, unsigned long addr) |
253 | { | |
254 | unsigned long offset; | |
255 | ||
256 | offset = tb->tb_jmp_offset[n]; | |
257 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
258 | offset = tb->tb_jmp_offset[n + 2]; | |
259 | if (offset != 0xffff) | |
260 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
261 | } | |
262 | ||
d4e8164f FB |
263 | #else |
264 | ||
265 | /* set the jump target */ | |
5fafdf24 | 266 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
d4e8164f FB |
267 | int n, unsigned long addr) |
268 | { | |
95f7652d | 269 | tb->tb_next[n] = addr; |
d4e8164f FB |
270 | } |
271 | ||
272 | #endif | |
273 | ||
5fafdf24 | 274 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
d4e8164f FB |
275 | TranslationBlock *tb_next) |
276 | { | |
cf25629d FB |
277 | /* NOTE: this test is only needed for thread safety */ |
278 | if (!tb->jmp_next[n]) { | |
279 | /* patch the native jump address */ | |
280 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); | |
3b46e624 | 281 | |
cf25629d FB |
282 | /* add in TB jmp circular list */ |
283 | tb->jmp_next[n] = tb_next->jmp_first; | |
284 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n)); | |
285 | } | |
d4e8164f FB |
286 | } |
287 | ||
a513fe19 FB |
288 | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
289 | ||
d4e8164f FB |
290 | #ifndef offsetof |
291 | #define offsetof(type, field) ((size_t) &((type *)0)->field) | |
292 | #endif | |
293 | ||
d549f7d9 FB |
294 | #if defined(_WIN32) |
295 | #define ASM_DATA_SECTION ".section \".data\"\n" | |
296 | #define ASM_PREVIOUS_SECTION ".section .text\n" | |
297 | #elif defined(__APPLE__) | |
298 | #define ASM_DATA_SECTION ".data\n" | |
299 | #define ASM_PREVIOUS_SECTION ".text\n" | |
d549f7d9 FB |
300 | #else |
301 | #define ASM_DATA_SECTION ".section \".data\"\n" | |
302 | #define ASM_PREVIOUS_SECTION ".previous\n" | |
d549f7d9 FB |
303 | #endif |
304 | ||
75913b72 FB |
305 | #define ASM_OP_LABEL_NAME(n, opname) \ |
306 | ASM_NAME(__op_label) #n "." ASM_NAME(opname) | |
307 | ||
33417e70 FB |
308 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
309 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 310 | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
33417e70 | 311 | |
d5975363 | 312 | #include "qemu-lock.h" |
d4e8164f FB |
313 | |
314 | extern spinlock_t tb_lock; | |
315 | ||
36bdbe54 | 316 | extern int tb_invalidated_flag; |
6e59c1db | 317 | |
e95c8d51 | 318 | #if !defined(CONFIG_USER_ONLY) |
6e59c1db | 319 | |
6ebbf390 | 320 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
6e59c1db FB |
321 | void *retaddr); |
322 | ||
6ebbf390 | 323 | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
6e59c1db FB |
324 | #define MEMSUFFIX _code |
325 | #define env cpu_single_env | |
326 | ||
327 | #define DATA_SIZE 1 | |
328 | #include "softmmu_header.h" | |
329 | ||
330 | #define DATA_SIZE 2 | |
331 | #include "softmmu_header.h" | |
332 | ||
333 | #define DATA_SIZE 4 | |
334 | #include "softmmu_header.h" | |
335 | ||
c27004ec FB |
336 | #define DATA_SIZE 8 |
337 | #include "softmmu_header.h" | |
338 | ||
6e59c1db FB |
339 | #undef ACCESS_TYPE |
340 | #undef MEMSUFFIX | |
341 | #undef env | |
342 | ||
343 | #endif | |
4390df51 FB |
344 | |
345 | #if defined(CONFIG_USER_ONLY) | |
4d7a0880 | 346 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
4390df51 FB |
347 | { |
348 | return addr; | |
349 | } | |
350 | #else | |
351 | /* NOTE: this function can trigger an exception */ | |
1ccde1cb FB |
352 | /* NOTE2: the returned address is not exactly the physical address: it |
353 | is the offset relative to phys_ram_base */ | |
4d7a0880 | 354 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
4390df51 | 355 | { |
4d7a0880 | 356 | int mmu_idx, page_index, pd; |
4390df51 | 357 | |
4d7a0880 BS |
358 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
359 | mmu_idx = cpu_mmu_index(env1); | |
360 | if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code != | |
4390df51 | 361 | (addr & TARGET_PAGE_MASK), 0)) { |
c27004ec FB |
362 | ldub_code(addr); |
363 | } | |
4d7a0880 | 364 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
2a4188a3 | 365 | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
647de6ca | 366 | #if defined(TARGET_SPARC) || defined(TARGET_MIPS) |
6c36d3fa BS |
367 | do_unassigned_access(addr, 0, 1, 0); |
368 | #else | |
4d7a0880 | 369 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
6c36d3fa | 370 | #endif |
4390df51 | 371 | } |
4d7a0880 | 372 | return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base; |
4390df51 | 373 | } |
2e70f6ef | 374 | |
bf20dc07 | 375 | /* Deterministic execution requires that IO only be performed on the last |
2e70f6ef PB |
376 | instruction of a TB so that interrupts take effect immediately. */ |
377 | static inline int can_do_io(CPUState *env) | |
378 | { | |
379 | if (!use_icount) | |
380 | return 1; | |
381 | ||
382 | /* If not executing code then assume we are ok. */ | |
383 | if (!env->current_tb) | |
384 | return 1; | |
385 | ||
386 | return env->can_do_io != 0; | |
387 | } | |
4390df51 | 388 | #endif |
9df217a3 | 389 | |
9df217a3 | 390 | #ifdef USE_KQEMU |
f32fc648 FB |
391 | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
392 | ||
da260249 FB |
393 | #define MSR_QPI_COMMBASE 0xfabe0010 |
394 | ||
9df217a3 FB |
395 | int kqemu_init(CPUState *env); |
396 | int kqemu_cpu_exec(CPUState *env); | |
397 | void kqemu_flush_page(CPUState *env, target_ulong addr); | |
398 | void kqemu_flush(CPUState *env, int global); | |
4b7df22f | 399 | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr); |
f32fc648 | 400 | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr); |
da260249 FB |
401 | void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size, |
402 | ram_addr_t phys_offset); | |
a332e112 | 403 | void kqemu_cpu_interrupt(CPUState *env); |
f32fc648 | 404 | void kqemu_record_dump(void); |
9df217a3 | 405 | |
da260249 FB |
406 | extern uint32_t kqemu_comm_base; |
407 | ||
9df217a3 FB |
408 | static inline int kqemu_is_ok(CPUState *env) |
409 | { | |
410 | return(env->kqemu_enabled && | |
5fafdf24 | 411 | (env->cr[0] & CR0_PE_MASK) && |
f32fc648 | 412 | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
9df217a3 | 413 | (env->eflags & IF_MASK) && |
f32fc648 | 414 | !(env->eflags & VM_MASK) && |
5fafdf24 | 415 | (env->kqemu_enabled == 2 || |
f32fc648 FB |
416 | ((env->hflags & HF_CPL_MASK) == 3 && |
417 | (env->eflags & IOPL_MASK) != IOPL_MASK))); | |
9df217a3 FB |
418 | } |
419 | ||
420 | #endif |