[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

typedef struct TranslationBlock TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 64
/* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
#define MAX_OPC_PARAM 10
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

/* Maximum size a TCG op can expand to.  This is complicated because a
   single op may require several host instructions and regirster reloads.
   For now take a wild guess at 128 bytes, which should allow at least
   a couple of fixup instructions per argument.  */
#define TCG_MAX_OP_SIZE 128

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)

extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
extern target_ulong gen_opc_jump_pc[2];
extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);

extern FILE *logfile;
extern int loglevel;

void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
                 unsigned long searched_pc, int pc_pos, void *puc);

unsigned long code_gen_max_block_size(void);
void cpu_gen_init(void);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb,
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_restore_state_copy(struct TranslationBlock *tb,
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_io_recompile(CPUState *env, void *retaddr);
TranslationBlock *tb_gen_code(CPUState *env, 
                              target_ulong pc, target_ulong cs_base, int flags,
                              int cflags);
void cpu_exec_init(CPUState *env);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
                      target_phys_addr_t paddr, int prot,
                      int mmu_idx, int is_softmmu);
static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
                               target_phys_addr_t paddr, int prot,
                               int mmu_idx, int is_softmmu)
{
    if (prot & PAGE_READ)
        prot |= PAGE_EXEC;
    return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
}

#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

#define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    uint64_t flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_COUNT_MASK  0x7fff
#define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next;
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2];
    target_ulong page_addr[2];

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    unsigned long tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2];
    struct TranslationBlock *jmp_first;
    uint32_t icount;
};

static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
}

static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
	    | (tmp & TB_JMP_ADDR_MASK));
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(target_ulong pc);
void tb_free(TranslationBlock *tb);
void tb_flush(CPUState *env);
void tb_link_phys(TranslationBlock *tb,
                  target_ulong phys_pc, target_ulong phys_page2);
void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
extern uint8_t *code_gen_ptr;
extern int code_gen_max_blocks;

#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
#if defined(__powerpc64__)
extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
#define tb_set_jmp_target1 ppc_tb_set_jmp_target
#else
static inline void flush_icache_range(unsigned long start, unsigned long stop);
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* This must be in concord with INDEX_op_goto_tb inside tcg_out_op */
    uint32_t *ptr;
    long disp = addr - jmp_addr;
    unsigned long patch_size;

    ptr = (uint32_t *)jmp_addr;

    if ((disp << 6) >> 6 != disp) {
        ptr[0] = 0x3c000000 | (addr >> 16);    /* lis 0,addr@ha */
        ptr[1] = 0x60000000 | (addr & 0xffff); /* la  0,addr@l(0) */
        ptr[2] = 0x7c0903a6;                   /* mtctr 0 */
        ptr[3] = 0x4e800420;                   /* brctr */
        patch_size = 16;
    } else {
        /* patch the branch destination */
        if (disp != 16) {
            *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
            patch_size = 4;
        } else {
            ptr[0] = 0x60000000; /* nop */
            ptr[1] = 0x60000000;
            ptr[2] = 0x60000000;
            ptr[3] = 0x60000000;
            patch_size = 16;
        }
    }
    /* flush icache */
    flush_icache_range(jmp_addr, jmp_addr + patch_size);
}
#endif
#elif defined(__i386__) || defined(__x86_64__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitly */
}
#elif defined(__arm__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    register unsigned long _beg __asm ("a1");
    register unsigned long _end __asm ("a2");
    register unsigned long _flg __asm ("a3");

    /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
    *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;

    /* flush icache */
    _beg = jmp_addr;
    _end = jmp_addr + 4;
    _flg = 0;
    __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n,
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);

        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#endif

#define ASM_OP_LABEL_NAME(n, opname) \
    ASM_NAME(__op_label) #n "." ASM_NAME(opname)

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#include "qemu-lock.h"

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
              void *retaddr);

#define ACCESS_TYPE (NB_MMU_MODES + 1)
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
{
    int mmu_idx, page_index, pd;

    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = cpu_mmu_index(env1);
    if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
                 (addr & TARGET_PAGE_MASK))) {
        ldub_code(addr);
    }
    pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
        do_unassigned_access(addr, 0, 1, 0);
#else
        cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
#endif
    }
    return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
}

/* Deterministic execution requires that IO only be performed on the last
   instruction of a TB so that interrupts take effect immediately.  */
static inline int can_do_io(CPUState *env)
{
    if (!use_icount)
        return 1;

    /* If not executing code then assume we are ok.  */
    if (!env->current_tb)
        return 1;

    return env->can_do_io != 0;
}
#endif

#ifdef USE_KQEMU
#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))

#define MSR_QPI_COMMBASE 0xfabe0010

int kqemu_init(CPUState *env);
int kqemu_cpu_exec(CPUState *env);
void kqemu_flush_page(CPUState *env, target_ulong addr);
void kqemu_flush(CPUState *env, int global);
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size, 
                        ram_addr_t phys_offset);
void kqemu_cpu_interrupt(CPUState *env);
void kqemu_record_dump(void);

extern uint32_t kqemu_comm_base;

static inline int kqemu_is_ok(CPUState *env)
{
    return(env->kqemu_enabled &&
           (env->cr[0] & CR0_PE_MASK) &&
           !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
           (env->eflags & IF_MASK) &&
           !(env->eflags & VM_MASK) &&
           (env->kqemu_enabled == 2 ||
            ((env->hflags & HF_CPL_MASK) == 3 &&
             (env->eflags & IOPL_MASK) != IOPL_MASK)));
}

#endif
Commit	Line	Data
d4e8164f FB	1	/*
d4e8164f FB	2	* internal execution defines for qemu
5fafdf24	3	*
d4e8164f FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
cb7cca1a	22	#define DEBUG_DISAS
b346ff46 FB	23
	24	/* is_jmp field values */
	25	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	26	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	27	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	28	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	29
2e70f6ef	30	typedef struct TranslationBlock TranslationBlock;
b346ff46 FB	31
b346ff46 FB	32	/* XXX: make safe guess about sizes */
e83a8673	33	#define MAX_OP_PER_INSTR 64
0115be31 PB	34	/* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
0115be31 PB	35	#define MAX_OPC_PARAM 10
b346ff46 FB	36	#define OPC_BUF_SIZE 512
	37	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	38
a208e54a PB	39	/* Maximum size a TCG op can expand to. This is complicated because a
	40	single op may require several host instructions and regirster reloads.
	41	For now take a wild guess at 128 bytes, which should allow at least
	42	a couple of fixup instructions per argument. */
	43	#define TCG_MAX_OP_SIZE 128
	44
0115be31	45	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
b346ff46	46
c27004ec FB	47	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
c27004ec FB	48	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
66e85a21	49	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46	50	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
2e70f6ef	51	extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
c3278b7b	52	extern target_ulong gen_opc_jump_pc[2];
30d6cb84	53	extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
b346ff46	54
9886cc16 FB	55	typedef void (GenOpFunc)(void);
	56	typedef void (GenOpFunc1)(long);
	57	typedef void (GenOpFunc2)(long, long);
	58	typedef void (GenOpFunc3)(long, long, long);
3b46e624	59
b346ff46 FB	60	extern FILE *logfile;
	61	extern int loglevel;
	62
2cfc5f17 TS	63	void gen_intermediate_code(CPUState env, struct TranslationBlock tb);
2cfc5f17 TS	64	void gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
d2856f1a AJ	65	void gen_pc_load(CPUState env, struct TranslationBlock tb,
	66	unsigned long searched_pc, int pc_pos, void *puc);
	67
d07bde88	68	unsigned long code_gen_max_block_size(void);
57fec1fe	69	void cpu_gen_init(void);
4c3a88a2	70	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
d07bde88	71	int *gen_code_size_ptr);
5fafdf24	72	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	73	CPUState *env, unsigned long searched_pc,
58fe2f10 FB	74	void *puc);
5fafdf24	75	int cpu_restore_state_copy(struct TranslationBlock *tb,
58fe2f10 FB	76	CPUState *env, unsigned long searched_pc,
58fe2f10 FB	77	void *puc);
2e12669a	78	void cpu_resume_from_signal(CPUState env1, void puc);
2e70f6ef PB	79	void cpu_io_recompile(CPUState env, void retaddr);
	80	TranslationBlock tb_gen_code(CPUState env,
	81	target_ulong pc, target_ulong cs_base, int flags,
	82	int cflags);
6a00d601	83	void cpu_exec_init(CPUState *env);
53a5960a	84	int page_unprotect(target_ulong address, unsigned long pc, void *puc);
00f82b8a	85	void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
2e12669a	86	int is_cpu_write_access);
4390df51	87	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	88	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	89	void tlb_flush(CPUState *env, int flush_global);
5fafdf24 TS	90	int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
5fafdf24 TS	91	target_phys_addr_t paddr, int prot,
6ebbf390	92	int mmu_idx, int is_softmmu);
4d7a0880	93	static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
5fafdf24	94	target_phys_addr_t paddr, int prot,
6ebbf390	95	int mmu_idx, int is_softmmu)
84b7b8e7 FB	96	{
	97	if (prot & PAGE_READ)
	98	prot \|= PAGE_EXEC;
4d7a0880	99	return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
84b7b8e7	100	}
d4e8164f	101
d4e8164f FB	102	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
d4e8164f FB	103
4390df51 FB	104	#define CODE_GEN_PHYS_HASH_BITS 15
	105	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	106
26a5f13b	107	#define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
d4e8164f	108
4390df51 FB	109	/* estimated block size for TB allocation */
	110	/* XXX: use a per code average code fragment size and modulate it
	111	according to the host CPU */
	112	#if defined(CONFIG_SOFTMMU)
	113	#define CODE_GEN_AVG_BLOCK_SIZE 128
	114	#else
	115	#define CODE_GEN_AVG_BLOCK_SIZE 64
	116	#endif
	117
811d4cf4	118	#if defined(__powerpc__) \|\| defined(__x86_64__) \|\| defined(__arm__)
4390df51 FB	119	#define USE_DIRECT_JUMP
4390df51 FB	120	#endif
67b915a5	121	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	122	#define USE_DIRECT_JUMP
	123	#endif
	124
2e70f6ef	125	struct TranslationBlock {
2e12669a FB	126	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	127	target_ulong cs_base; /* CS base for this block */
c068688b	128	uint64_t flags; /* flags defining in which context the code was generated */
d4e8164f FB	129	uint16_t size; /* size of target code for this block (1 <=
d4e8164f FB	130	size <= TARGET_PAGE_SIZE) */
58fe2f10	131	uint16_t cflags; /* compile flags */
2e70f6ef PB	132	#define CF_COUNT_MASK 0x7fff
2e70f6ef PB	133	#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
58fe2f10	134
d4e8164f	135	uint8_t tc_ptr; / pointer to the translated code */
4390df51	136	/* next matching tb for physical address. */
5fafdf24	137	struct TranslationBlock *phys_hash_next;
4390df51 FB	138	/* first and second physical page containing code. The lower bit
4390df51 FB	139	of the pointer tells the index in page_next[] */
5fafdf24 TS	140	struct TranslationBlock *page_next[2];
5fafdf24 TS	141	target_ulong page_addr[2];
4390df51	142
d4e8164f FB	143	/* the following data are used to directly call another TB from
	144	the code of this one. */
	145	uint16_t tb_next_offset[2]; /* offset of original jump target */
	146	#ifdef USE_DIRECT_JUMP
4cbb86e1	147	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	148	#else
57fec1fe	149	unsigned long tb_next[2]; /* address of jump generated code */
d4e8164f FB	150	#endif
	151	/* list of TBs jumping to this one. This is a circular list using
	152	the two least significant bits of the pointers to tell what is
	153	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	154	jmp_first */
5fafdf24	155	struct TranslationBlock *jmp_next[2];
d4e8164f	156	struct TranslationBlock *jmp_first;
2e70f6ef PB	157	uint32_t icount;
2e70f6ef PB	158	};
d4e8164f	159
b362e5e0 PB	160	static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
	161	{
	162	target_ulong tmp;
	163	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
b5e19d4c	164	return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
b362e5e0 PB	165	}
b362e5e0 PB	166
8a40a180	167	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
d4e8164f	168	{
b362e5e0 PB	169	target_ulong tmp;
b362e5e0 PB	170	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
b5e19d4c EI	171	return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
b5e19d4c EI	172	\| (tmp & TB_JMP_ADDR_MASK));
d4e8164f FB	173	}
d4e8164f FB	174
4390df51 FB	175	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	176	{
	177	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	178	}
	179
c27004ec	180	TranslationBlock *tb_alloc(target_ulong pc);
2e70f6ef	181	void tb_free(TranslationBlock *tb);
0124311e	182	void tb_flush(CPUState *env);
5fafdf24	183	void tb_link_phys(TranslationBlock *tb,
4390df51	184	target_ulong phys_pc, target_ulong phys_page2);
2e70f6ef	185	void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
d4e8164f	186
4390df51	187	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f	188	extern uint8_t *code_gen_ptr;
26a5f13b	189	extern int code_gen_max_blocks;
d4e8164f	190
4390df51 FB	191	#if defined(USE_DIRECT_JUMP)
	192
	193	#if defined(__powerpc__)
810260a8	194	#if defined(__powerpc64__)
	195	extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
	196	#define tb_set_jmp_target1 ppc_tb_set_jmp_target
	197	#else
0a878c47	198	static inline void flush_icache_range(unsigned long start, unsigned long stop);
4cbb86e1	199	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f	200	{
0a878c47	201	/* This must be in concord with INDEX_op_goto_tb inside tcg_out_op */
0a878c47	202	uint32_t *ptr;
932a6909	203	long disp = addr - jmp_addr;
0a878c47	204	unsigned long patch_size;
d4e8164f	205
4cbb86e1	206	ptr = (uint32_t *)jmp_addr;
932a6909 FB	207
932a6909 FB	208	if ((disp << 6) >> 6 != disp) {
0a878c47	209	ptr[0] = 0x3c000000 \| (addr >> 16); /* lis 0,addr@ha */
	210	ptr[1] = 0x60000000 \| (addr & 0xffff); /* la 0,addr@l(0) */
	211	ptr[2] = 0x7c0903a6; /* mtctr 0 */
	212	ptr[3] = 0x4e800420; /* brctr */
	213	patch_size = 16;
932a6909 FB	214	} else {
932a6909 FB	215	/* patch the branch destination */
0a878c47	216	if (disp != 16) {
	217	ptr = 0x48000000 \| (disp & 0x03fffffc); / b disp */
	218	patch_size = 4;
	219	} else {
	220	ptr[0] = 0x60000000; /* nop */
	221	ptr[1] = 0x60000000;
	222	ptr[2] = 0x60000000;
	223	ptr[3] = 0x60000000;
	224	patch_size = 16;
	225	}
932a6909	226	}
d4e8164f	227	/* flush icache */
0a878c47	228	flush_icache_range(jmp_addr, jmp_addr + patch_size);
d4e8164f	229	}
810260a8	230	#endif
57fec1fe	231	#elif defined(__i386__) \|\| defined(__x86_64__)
4390df51 FB	232	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	233	{
	234	/* patch the branch destination */
	235	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
1235fc06	236	/* no need to flush icache explicitly */
4390df51	237	}
811d4cf4 AZ	238	#elif defined(__arm__)
	239	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	240	{
	241	register unsigned long _beg __asm ("a1");
	242	register unsigned long _end __asm ("a2");
	243	register unsigned long _flg __asm ("a3");
	244
	245	/* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
	246	(uint32_t )jmp_addr \|= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
	247
	248	/* flush icache */
	249	_beg = jmp_addr;
	250	_end = jmp_addr + 4;
	251	_flg = 0;
	252	__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
	253	}
4390df51	254	#endif
d4e8164f	255
5fafdf24	256	static inline void tb_set_jmp_target(TranslationBlock *tb,
4cbb86e1 FB	257	int n, unsigned long addr)
	258	{
	259	unsigned long offset;
	260
	261	offset = tb->tb_jmp_offset[n];
	262	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	263	offset = tb->tb_jmp_offset[n + 2];
	264	if (offset != 0xffff)
	265	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	266	}
	267
d4e8164f FB	268	#else
	269
	270	/* set the jump target */
5fafdf24	271	static inline void tb_set_jmp_target(TranslationBlock *tb,
d4e8164f FB	272	int n, unsigned long addr)
d4e8164f FB	273	{
95f7652d	274	tb->tb_next[n] = addr;
d4e8164f FB	275	}
	276
	277	#endif
	278
5fafdf24	279	static inline void tb_add_jump(TranslationBlock *tb, int n,
d4e8164f FB	280	TranslationBlock *tb_next)
d4e8164f FB	281	{
cf25629d FB	282	/* NOTE: this test is only needed for thread safety */
	283	if (!tb->jmp_next[n]) {
	284	/* patch the native jump address */
	285	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
3b46e624	286
cf25629d FB	287	/* add in TB jmp circular list */
	288	tb->jmp_next[n] = tb_next->jmp_first;
	289	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	290	}
d4e8164f FB	291	}
d4e8164f FB	292
a513fe19 FB	293	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	294
d4e8164f FB	295	#ifndef offsetof
	296	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	297	#endif
	298
d549f7d9 FB	299	#if defined(_WIN32)
	300	#define ASM_DATA_SECTION ".section \".data\"\n"
	301	#define ASM_PREVIOUS_SECTION ".section .text\n"
	302	#elif defined(__APPLE__)
	303	#define ASM_DATA_SECTION ".data\n"
	304	#define ASM_PREVIOUS_SECTION ".text\n"
d549f7d9 FB	305	#else
	306	#define ASM_DATA_SECTION ".section \".data\"\n"
	307	#define ASM_PREVIOUS_SECTION ".previous\n"
d549f7d9 FB	308	#endif
d549f7d9 FB	309
75913b72 FB	310	#define ASM_OP_LABEL_NAME(n, opname) \
	311	ASM_NAME(__op_label) #n "." ASM_NAME(opname)
	312
33417e70 FB	313	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	314	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	315	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	316
d5975363	317	#include "qemu-lock.h"
d4e8164f FB	318
	319	extern spinlock_t tb_lock;
	320
36bdbe54	321	extern int tb_invalidated_flag;
6e59c1db	322
e95c8d51	323	#if !defined(CONFIG_USER_ONLY)
6e59c1db	324
6ebbf390	325	void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
6e59c1db FB	326	void *retaddr);
6e59c1db FB	327
6ebbf390	328	#define ACCESS_TYPE (NB_MMU_MODES + 1)
6e59c1db FB	329	#define MEMSUFFIX _code
	330	#define env cpu_single_env
	331
	332	#define DATA_SIZE 1
	333	#include "softmmu_header.h"
	334
	335	#define DATA_SIZE 2
	336	#include "softmmu_header.h"
	337
	338	#define DATA_SIZE 4
	339	#include "softmmu_header.h"
	340
c27004ec FB	341	#define DATA_SIZE 8
	342	#include "softmmu_header.h"
	343
6e59c1db FB	344	#undef ACCESS_TYPE
	345	#undef MEMSUFFIX
	346	#undef env
	347
	348	#endif
4390df51 FB	349
4390df51 FB	350	#if defined(CONFIG_USER_ONLY)
4d7a0880	351	static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
4390df51 FB	352	{
	353	return addr;
	354	}
	355	#else
	356	/* NOTE: this function can trigger an exception */
1ccde1cb FB	357	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	358	is the offset relative to phys_ram_base */
4d7a0880	359	static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
4390df51	360	{
4d7a0880	361	int mmu_idx, page_index, pd;
4390df51	362
4d7a0880 BS	363	page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
4d7a0880 BS	364	mmu_idx = cpu_mmu_index(env1);
551bd27f TS	365	if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
551bd27f TS	366	(addr & TARGET_PAGE_MASK))) {
c27004ec FB	367	ldub_code(addr);
c27004ec FB	368	}
4d7a0880	369	pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
2a4188a3	370	if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
647de6ca	371	#if defined(TARGET_SPARC) \|\| defined(TARGET_MIPS)
6c36d3fa BS	372	do_unassigned_access(addr, 0, 1, 0);
6c36d3fa BS	373	#else
4d7a0880	374	cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
6c36d3fa	375	#endif
4390df51	376	}
4d7a0880	377	return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
4390df51	378	}
2e70f6ef	379
bf20dc07	380	/* Deterministic execution requires that IO only be performed on the last
2e70f6ef PB	381	instruction of a TB so that interrupts take effect immediately. */
	382	static inline int can_do_io(CPUState *env)
	383	{
	384	if (!use_icount)
	385	return 1;
	386
	387	/* If not executing code then assume we are ok. */
	388	if (!env->current_tb)
	389	return 1;
	390
	391	return env->can_do_io != 0;
	392	}
4390df51	393	#endif
9df217a3	394
9df217a3	395	#ifdef USE_KQEMU
f32fc648 FB	396	#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG \| CODE_DIRTY_FLAG))
f32fc648 FB	397
da260249 FB	398	#define MSR_QPI_COMMBASE 0xfabe0010
da260249 FB	399
9df217a3 FB	400	int kqemu_init(CPUState *env);
	401	int kqemu_cpu_exec(CPUState *env);
	402	void kqemu_flush_page(CPUState *env, target_ulong addr);
	403	void kqemu_flush(CPUState *env, int global);
4b7df22f	404	void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
f32fc648	405	void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
da260249 FB	406	void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
da260249 FB	407	ram_addr_t phys_offset);
a332e112	408	void kqemu_cpu_interrupt(CPUState *env);
f32fc648	409	void kqemu_record_dump(void);
9df217a3	410
da260249 FB	411	extern uint32_t kqemu_comm_base;
da260249 FB	412
9df217a3 FB	413	static inline int kqemu_is_ok(CPUState *env)
	414	{
	415	return(env->kqemu_enabled &&
5fafdf24	416	(env->cr[0] & CR0_PE_MASK) &&
f32fc648	417	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
9df217a3	418	(env->eflags & IF_MASK) &&
f32fc648	419	!(env->eflags & VM_MASK) &&
5fafdf24	420	(env->kqemu_enabled == 2 \|\|
f32fc648 FB	421	((env->hflags & HF_CPL_MASK) == 3 &&
f32fc648 FB	422	(env->eflags & IOPL_MASK) != IOPL_MASK)));
9df217a3 FB	423	}
	424
	425	#endif