]>
Commit | Line | Data |
---|---|---|
d4e8164f FB |
1 | /* |
2 | * internal execution defines for qemu | |
5fafdf24 | 3 | * |
d4e8164f FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
b346ff46 | 21 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
cb7cca1a | 22 | #define DEBUG_DISAS |
b346ff46 FB |
23 | |
24 | /* is_jmp field values */ | |
25 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ | |
26 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ | |
27 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ | |
28 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ | |
29 | ||
30 | struct TranslationBlock; | |
31 | ||
32 | /* XXX: make safe guess about sizes */ | |
e83a8673 | 33 | #define MAX_OP_PER_INSTR 64 |
0115be31 PB |
34 | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */ |
35 | #define MAX_OPC_PARAM 10 | |
b346ff46 FB |
36 | #define OPC_BUF_SIZE 512 |
37 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) | |
38 | ||
a208e54a PB |
39 | /* Maximum size a TCG op can expand to. This is complicated because a |
40 | single op may require several host instructions and regirster reloads. | |
41 | For now take a wild guess at 128 bytes, which should allow at least | |
42 | a couple of fixup instructions per argument. */ | |
43 | #define TCG_MAX_OP_SIZE 128 | |
44 | ||
0115be31 | 45 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) |
b346ff46 | 46 | |
c27004ec FB |
47 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE]; |
48 | extern target_ulong gen_opc_npc[OPC_BUF_SIZE]; | |
66e85a21 | 49 | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
b346ff46 | 50 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; |
c3278b7b | 51 | extern target_ulong gen_opc_jump_pc[2]; |
30d6cb84 | 52 | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE]; |
b346ff46 | 53 | |
9886cc16 FB |
54 | typedef void (GenOpFunc)(void); |
55 | typedef void (GenOpFunc1)(long); | |
56 | typedef void (GenOpFunc2)(long, long); | |
57 | typedef void (GenOpFunc3)(long, long, long); | |
3b46e624 | 58 | |
b346ff46 FB |
59 | extern FILE *logfile; |
60 | extern int loglevel; | |
61 | ||
4c3a88a2 FB |
62 | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
63 | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); | |
d2856f1a AJ |
64 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
65 | unsigned long searched_pc, int pc_pos, void *puc); | |
66 | ||
d07bde88 | 67 | unsigned long code_gen_max_block_size(void); |
57fec1fe | 68 | void cpu_gen_init(void); |
4c3a88a2 | 69 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
d07bde88 | 70 | int *gen_code_size_ptr); |
5fafdf24 | 71 | int cpu_restore_state(struct TranslationBlock *tb, |
58fe2f10 FB |
72 | CPUState *env, unsigned long searched_pc, |
73 | void *puc); | |
5fafdf24 | 74 | int cpu_restore_state_copy(struct TranslationBlock *tb, |
58fe2f10 FB |
75 | CPUState *env, unsigned long searched_pc, |
76 | void *puc); | |
2e12669a | 77 | void cpu_resume_from_signal(CPUState *env1, void *puc); |
6a00d601 | 78 | void cpu_exec_init(CPUState *env); |
53a5960a | 79 | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
00f82b8a | 80 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
2e12669a | 81 | int is_cpu_write_access); |
4390df51 | 82 | void tb_invalidate_page_range(target_ulong start, target_ulong end); |
2e12669a | 83 | void tlb_flush_page(CPUState *env, target_ulong addr); |
ee8b7021 | 84 | void tlb_flush(CPUState *env, int flush_global); |
5fafdf24 TS |
85 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
86 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 87 | int mmu_idx, int is_softmmu); |
4d7a0880 | 88 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, |
5fafdf24 | 89 | target_phys_addr_t paddr, int prot, |
6ebbf390 | 90 | int mmu_idx, int is_softmmu) |
84b7b8e7 FB |
91 | { |
92 | if (prot & PAGE_READ) | |
93 | prot |= PAGE_EXEC; | |
4d7a0880 | 94 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu); |
84b7b8e7 | 95 | } |
d4e8164f | 96 | |
d4e8164f FB |
97 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
98 | ||
4390df51 FB |
99 | #define CODE_GEN_PHYS_HASH_BITS 15 |
100 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) | |
101 | ||
26a5f13b | 102 | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
d4e8164f | 103 | |
4390df51 FB |
104 | /* estimated block size for TB allocation */ |
105 | /* XXX: use a per code average code fragment size and modulate it | |
106 | according to the host CPU */ | |
107 | #if defined(CONFIG_SOFTMMU) | |
108 | #define CODE_GEN_AVG_BLOCK_SIZE 128 | |
109 | #else | |
110 | #define CODE_GEN_AVG_BLOCK_SIZE 64 | |
111 | #endif | |
112 | ||
811d4cf4 | 113 | #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__) |
4390df51 FB |
114 | #define USE_DIRECT_JUMP |
115 | #endif | |
67b915a5 | 116 | #if defined(__i386__) && !defined(_WIN32) |
d4e8164f FB |
117 | #define USE_DIRECT_JUMP |
118 | #endif | |
119 | ||
120 | typedef struct TranslationBlock { | |
2e12669a FB |
121 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
122 | target_ulong cs_base; /* CS base for this block */ | |
c068688b | 123 | uint64_t flags; /* flags defining in which context the code was generated */ |
d4e8164f FB |
124 | uint16_t size; /* size of target code for this block (1 <= |
125 | size <= TARGET_PAGE_SIZE) */ | |
58fe2f10 | 126 | uint16_t cflags; /* compile flags */ |
bf088061 FB |
127 | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
128 | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ | |
2e12669a | 129 | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
58fe2f10 | 130 | |
d4e8164f | 131 | uint8_t *tc_ptr; /* pointer to the translated code */ |
4390df51 | 132 | /* next matching tb for physical address. */ |
5fafdf24 | 133 | struct TranslationBlock *phys_hash_next; |
4390df51 FB |
134 | /* first and second physical page containing code. The lower bit |
135 | of the pointer tells the index in page_next[] */ | |
5fafdf24 TS |
136 | struct TranslationBlock *page_next[2]; |
137 | target_ulong page_addr[2]; | |
4390df51 | 138 | |
d4e8164f FB |
139 | /* the following data are used to directly call another TB from |
140 | the code of this one. */ | |
141 | uint16_t tb_next_offset[2]; /* offset of original jump target */ | |
142 | #ifdef USE_DIRECT_JUMP | |
4cbb86e1 | 143 | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
d4e8164f | 144 | #else |
57fec1fe | 145 | unsigned long tb_next[2]; /* address of jump generated code */ |
d4e8164f FB |
146 | #endif |
147 | /* list of TBs jumping to this one. This is a circular list using | |
148 | the two least significant bits of the pointers to tell what is | |
149 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = | |
150 | jmp_first */ | |
5fafdf24 | 151 | struct TranslationBlock *jmp_next[2]; |
d4e8164f FB |
152 | struct TranslationBlock *jmp_first; |
153 | } TranslationBlock; | |
154 | ||
b362e5e0 PB |
155 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
156 | { | |
157 | target_ulong tmp; | |
158 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
b5e19d4c | 159 | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK; |
b362e5e0 PB |
160 | } |
161 | ||
8a40a180 | 162 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
d4e8164f | 163 | { |
b362e5e0 PB |
164 | target_ulong tmp; |
165 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
b5e19d4c EI |
166 | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) |
167 | | (tmp & TB_JMP_ADDR_MASK)); | |
d4e8164f FB |
168 | } |
169 | ||
4390df51 FB |
170 | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
171 | { | |
172 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); | |
173 | } | |
174 | ||
c27004ec | 175 | TranslationBlock *tb_alloc(target_ulong pc); |
0124311e | 176 | void tb_flush(CPUState *env); |
5fafdf24 | 177 | void tb_link_phys(TranslationBlock *tb, |
4390df51 | 178 | target_ulong phys_pc, target_ulong phys_page2); |
d4e8164f | 179 | |
4390df51 | 180 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
d4e8164f | 181 | extern uint8_t *code_gen_ptr; |
26a5f13b | 182 | extern int code_gen_max_blocks; |
d4e8164f | 183 | |
4390df51 FB |
184 | #if defined(USE_DIRECT_JUMP) |
185 | ||
186 | #if defined(__powerpc__) | |
4cbb86e1 | 187 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
d4e8164f FB |
188 | { |
189 | uint32_t val, *ptr; | |
d4e8164f FB |
190 | |
191 | /* patch the branch destination */ | |
4cbb86e1 | 192 | ptr = (uint32_t *)jmp_addr; |
d4e8164f | 193 | val = *ptr; |
4cbb86e1 | 194 | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
d4e8164f FB |
195 | *ptr = val; |
196 | /* flush icache */ | |
197 | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); | |
198 | asm volatile ("sync" : : : "memory"); | |
199 | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); | |
200 | asm volatile ("sync" : : : "memory"); | |
201 | asm volatile ("isync" : : : "memory"); | |
202 | } | |
57fec1fe | 203 | #elif defined(__i386__) || defined(__x86_64__) |
4390df51 FB |
204 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
205 | { | |
206 | /* patch the branch destination */ | |
207 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); | |
208 | /* no need to flush icache explicitely */ | |
209 | } | |
811d4cf4 AZ |
210 | #elif defined(__arm__) |
211 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) | |
212 | { | |
213 | register unsigned long _beg __asm ("a1"); | |
214 | register unsigned long _end __asm ("a2"); | |
215 | register unsigned long _flg __asm ("a3"); | |
216 | ||
217 | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ | |
218 | *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff; | |
219 | ||
220 | /* flush icache */ | |
221 | _beg = jmp_addr; | |
222 | _end = jmp_addr + 4; | |
223 | _flg = 0; | |
224 | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); | |
225 | } | |
4390df51 | 226 | #endif |
d4e8164f | 227 | |
5fafdf24 | 228 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
4cbb86e1 FB |
229 | int n, unsigned long addr) |
230 | { | |
231 | unsigned long offset; | |
232 | ||
233 | offset = tb->tb_jmp_offset[n]; | |
234 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
235 | offset = tb->tb_jmp_offset[n + 2]; | |
236 | if (offset != 0xffff) | |
237 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
238 | } | |
239 | ||
d4e8164f FB |
240 | #else |
241 | ||
242 | /* set the jump target */ | |
5fafdf24 | 243 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
d4e8164f FB |
244 | int n, unsigned long addr) |
245 | { | |
95f7652d | 246 | tb->tb_next[n] = addr; |
d4e8164f FB |
247 | } |
248 | ||
249 | #endif | |
250 | ||
5fafdf24 | 251 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
d4e8164f FB |
252 | TranslationBlock *tb_next) |
253 | { | |
cf25629d FB |
254 | /* NOTE: this test is only needed for thread safety */ |
255 | if (!tb->jmp_next[n]) { | |
256 | /* patch the native jump address */ | |
257 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); | |
3b46e624 | 258 | |
cf25629d FB |
259 | /* add in TB jmp circular list */ |
260 | tb->jmp_next[n] = tb_next->jmp_first; | |
261 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n)); | |
262 | } | |
d4e8164f FB |
263 | } |
264 | ||
a513fe19 FB |
265 | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
266 | ||
d4e8164f FB |
267 | #ifndef offsetof |
268 | #define offsetof(type, field) ((size_t) &((type *)0)->field) | |
269 | #endif | |
270 | ||
d549f7d9 FB |
271 | #if defined(_WIN32) |
272 | #define ASM_DATA_SECTION ".section \".data\"\n" | |
273 | #define ASM_PREVIOUS_SECTION ".section .text\n" | |
274 | #elif defined(__APPLE__) | |
275 | #define ASM_DATA_SECTION ".data\n" | |
276 | #define ASM_PREVIOUS_SECTION ".text\n" | |
d549f7d9 FB |
277 | #else |
278 | #define ASM_DATA_SECTION ".section \".data\"\n" | |
279 | #define ASM_PREVIOUS_SECTION ".previous\n" | |
d549f7d9 FB |
280 | #endif |
281 | ||
75913b72 FB |
282 | #define ASM_OP_LABEL_NAME(n, opname) \ |
283 | ASM_NAME(__op_label) #n "." ASM_NAME(opname) | |
284 | ||
33417e70 FB |
285 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
286 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 287 | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
33417e70 | 288 | |
15a51156 AJ |
289 | #if defined(__hppa__) |
290 | ||
291 | typedef int spinlock_t[4]; | |
292 | ||
293 | #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 } | |
294 | ||
295 | static inline void resetlock (spinlock_t *p) | |
296 | { | |
297 | (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1; | |
298 | } | |
299 | ||
300 | #else | |
301 | ||
302 | typedef int spinlock_t; | |
303 | ||
304 | #define SPIN_LOCK_UNLOCKED 0 | |
305 | ||
306 | static inline void resetlock (spinlock_t *p) | |
307 | { | |
308 | *p = SPIN_LOCK_UNLOCKED; | |
309 | } | |
310 | ||
311 | #endif | |
312 | ||
204a1b8d | 313 | #if defined(__powerpc__) |
d4e8164f FB |
314 | static inline int testandset (int *p) |
315 | { | |
316 | int ret; | |
317 | __asm__ __volatile__ ( | |
02e1ec9b FB |
318 | "0: lwarx %0,0,%1\n" |
319 | " xor. %0,%3,%0\n" | |
320 | " bne 1f\n" | |
321 | " stwcx. %2,0,%1\n" | |
322 | " bne- 0b\n" | |
d4e8164f FB |
323 | "1: " |
324 | : "=&r" (ret) | |
325 | : "r" (p), "r" (1), "r" (0) | |
326 | : "cr0", "memory"); | |
327 | return ret; | |
328 | } | |
204a1b8d | 329 | #elif defined(__i386__) |
d4e8164f FB |
330 | static inline int testandset (int *p) |
331 | { | |
4955a2cd | 332 | long int readval = 0; |
3b46e624 | 333 | |
4955a2cd FB |
334 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
335 | : "+m" (*p), "+a" (readval) | |
336 | : "r" (1) | |
337 | : "cc"); | |
338 | return readval; | |
d4e8164f | 339 | } |
204a1b8d | 340 | #elif defined(__x86_64__) |
bc51c5c9 FB |
341 | static inline int testandset (int *p) |
342 | { | |
4955a2cd | 343 | long int readval = 0; |
3b46e624 | 344 | |
4955a2cd FB |
345 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
346 | : "+m" (*p), "+a" (readval) | |
347 | : "r" (1) | |
348 | : "cc"); | |
349 | return readval; | |
bc51c5c9 | 350 | } |
204a1b8d | 351 | #elif defined(__s390__) |
d4e8164f FB |
352 | static inline int testandset (int *p) |
353 | { | |
354 | int ret; | |
355 | ||
356 | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n" | |
357 | " jl 0b" | |
358 | : "=&d" (ret) | |
5fafdf24 | 359 | : "r" (1), "a" (p), "0" (*p) |
d4e8164f FB |
360 | : "cc", "memory" ); |
361 | return ret; | |
362 | } | |
204a1b8d | 363 | #elif defined(__alpha__) |
2f87c607 | 364 | static inline int testandset (int *p) |
d4e8164f FB |
365 | { |
366 | int ret; | |
367 | unsigned long one; | |
368 | ||
369 | __asm__ __volatile__ ("0: mov 1,%2\n" | |
370 | " ldl_l %0,%1\n" | |
371 | " stl_c %2,%1\n" | |
372 | " beq %2,1f\n" | |
373 | ".subsection 2\n" | |
374 | "1: br 0b\n" | |
375 | ".previous" | |
376 | : "=r" (ret), "=m" (*p), "=r" (one) | |
377 | : "m" (*p)); | |
378 | return ret; | |
379 | } | |
204a1b8d | 380 | #elif defined(__sparc__) |
d4e8164f FB |
381 | static inline int testandset (int *p) |
382 | { | |
383 | int ret; | |
384 | ||
385 | __asm__ __volatile__("ldstub [%1], %0" | |
386 | : "=r" (ret) | |
387 | : "r" (p) | |
388 | : "memory"); | |
389 | ||
390 | return (ret ? 1 : 0); | |
391 | } | |
204a1b8d | 392 | #elif defined(__arm__) |
a95c6790 FB |
393 | static inline int testandset (int *spinlock) |
394 | { | |
395 | register unsigned int ret; | |
396 | __asm__ __volatile__("swp %0, %1, [%2]" | |
397 | : "=r"(ret) | |
398 | : "0"(1), "r"(spinlock)); | |
3b46e624 | 399 | |
a95c6790 FB |
400 | return ret; |
401 | } | |
204a1b8d | 402 | #elif defined(__mc68000) |
38e584a0 FB |
403 | static inline int testandset (int *p) |
404 | { | |
405 | char ret; | |
406 | __asm__ __volatile__("tas %1; sne %0" | |
407 | : "=r" (ret) | |
408 | : "m" (p) | |
409 | : "cc","memory"); | |
4955a2cd | 410 | return ret; |
38e584a0 | 411 | } |
15a51156 AJ |
412 | #elif defined(__hppa__) |
413 | ||
414 | /* Because malloc only guarantees 8-byte alignment for malloc'd data, | |
415 | and GCC only guarantees 8-byte alignment for stack locals, we can't | |
416 | be assured of 16-byte alignment for atomic lock data even if we | |
417 | specify "__attribute ((aligned(16)))" in the type declaration. So, | |
418 | we use a struct containing an array of four ints for the atomic lock | |
419 | type and dynamically select the 16-byte aligned int from the array | |
420 | for the semaphore. */ | |
421 | #define __PA_LDCW_ALIGNMENT 16 | |
422 | static inline void *ldcw_align (void *p) { | |
423 | unsigned long a = (unsigned long)p; | |
424 | a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); | |
425 | return (void *)a; | |
426 | } | |
427 | ||
428 | static inline int testandset (spinlock_t *p) | |
429 | { | |
430 | unsigned int ret; | |
431 | p = ldcw_align(p); | |
432 | __asm__ __volatile__("ldcw 0(%1),%0" | |
433 | : "=r" (ret) | |
434 | : "r" (p) | |
435 | : "memory" ); | |
436 | return !ret; | |
437 | } | |
438 | ||
204a1b8d | 439 | #elif defined(__ia64) |
38e584a0 | 440 | |
b8076a74 FB |
441 | #include <ia64intrin.h> |
442 | ||
443 | static inline int testandset (int *p) | |
444 | { | |
445 | return __sync_lock_test_and_set (p, 1); | |
446 | } | |
204a1b8d | 447 | #elif defined(__mips__) |
c4b89d18 TS |
448 | static inline int testandset (int *p) |
449 | { | |
450 | int ret; | |
451 | ||
452 | __asm__ __volatile__ ( | |
453 | " .set push \n" | |
454 | " .set noat \n" | |
455 | " .set mips2 \n" | |
456 | "1: li $1, 1 \n" | |
457 | " ll %0, %1 \n" | |
458 | " sc $1, %1 \n" | |
976a0d0d | 459 | " beqz $1, 1b \n" |
c4b89d18 TS |
460 | " .set pop " |
461 | : "=r" (ret), "+R" (*p) | |
462 | : | |
463 | : "memory"); | |
464 | ||
465 | return ret; | |
466 | } | |
204a1b8d TS |
467 | #else |
468 | #error unimplemented CPU support | |
c4b89d18 TS |
469 | #endif |
470 | ||
aebcb60e | 471 | #if defined(CONFIG_USER_ONLY) |
d4e8164f FB |
472 | static inline void spin_lock(spinlock_t *lock) |
473 | { | |
474 | while (testandset(lock)); | |
475 | } | |
476 | ||
477 | static inline void spin_unlock(spinlock_t *lock) | |
478 | { | |
15a51156 | 479 | resetlock(lock); |
d4e8164f FB |
480 | } |
481 | ||
482 | static inline int spin_trylock(spinlock_t *lock) | |
483 | { | |
484 | return !testandset(lock); | |
485 | } | |
3c1cf9fa FB |
486 | #else |
487 | static inline void spin_lock(spinlock_t *lock) | |
488 | { | |
489 | } | |
490 | ||
491 | static inline void spin_unlock(spinlock_t *lock) | |
492 | { | |
493 | } | |
494 | ||
495 | static inline int spin_trylock(spinlock_t *lock) | |
496 | { | |
497 | return 1; | |
498 | } | |
499 | #endif | |
d4e8164f FB |
500 | |
501 | extern spinlock_t tb_lock; | |
502 | ||
36bdbe54 | 503 | extern int tb_invalidated_flag; |
6e59c1db | 504 | |
e95c8d51 | 505 | #if !defined(CONFIG_USER_ONLY) |
6e59c1db | 506 | |
6ebbf390 | 507 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
6e59c1db FB |
508 | void *retaddr); |
509 | ||
6ebbf390 | 510 | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
6e59c1db FB |
511 | #define MEMSUFFIX _code |
512 | #define env cpu_single_env | |
513 | ||
514 | #define DATA_SIZE 1 | |
515 | #include "softmmu_header.h" | |
516 | ||
517 | #define DATA_SIZE 2 | |
518 | #include "softmmu_header.h" | |
519 | ||
520 | #define DATA_SIZE 4 | |
521 | #include "softmmu_header.h" | |
522 | ||
c27004ec FB |
523 | #define DATA_SIZE 8 |
524 | #include "softmmu_header.h" | |
525 | ||
6e59c1db FB |
526 | #undef ACCESS_TYPE |
527 | #undef MEMSUFFIX | |
528 | #undef env | |
529 | ||
530 | #endif | |
4390df51 FB |
531 | |
532 | #if defined(CONFIG_USER_ONLY) | |
4d7a0880 | 533 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
4390df51 FB |
534 | { |
535 | return addr; | |
536 | } | |
537 | #else | |
538 | /* NOTE: this function can trigger an exception */ | |
1ccde1cb FB |
539 | /* NOTE2: the returned address is not exactly the physical address: it |
540 | is the offset relative to phys_ram_base */ | |
4d7a0880 | 541 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
4390df51 | 542 | { |
4d7a0880 | 543 | int mmu_idx, page_index, pd; |
4390df51 | 544 | |
4d7a0880 BS |
545 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
546 | mmu_idx = cpu_mmu_index(env1); | |
547 | if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code != | |
4390df51 | 548 | (addr & TARGET_PAGE_MASK), 0)) { |
c27004ec FB |
549 | ldub_code(addr); |
550 | } | |
4d7a0880 | 551 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
2a4188a3 | 552 | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
647de6ca | 553 | #if defined(TARGET_SPARC) || defined(TARGET_MIPS) |
6c36d3fa BS |
554 | do_unassigned_access(addr, 0, 1, 0); |
555 | #else | |
4d7a0880 | 556 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
6c36d3fa | 557 | #endif |
4390df51 | 558 | } |
4d7a0880 | 559 | return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base; |
4390df51 FB |
560 | } |
561 | #endif | |
9df217a3 | 562 | |
9df217a3 | 563 | #ifdef USE_KQEMU |
f32fc648 FB |
564 | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
565 | ||
9df217a3 FB |
566 | int kqemu_init(CPUState *env); |
567 | int kqemu_cpu_exec(CPUState *env); | |
568 | void kqemu_flush_page(CPUState *env, target_ulong addr); | |
569 | void kqemu_flush(CPUState *env, int global); | |
4b7df22f | 570 | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr); |
f32fc648 | 571 | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr); |
a332e112 | 572 | void kqemu_cpu_interrupt(CPUState *env); |
f32fc648 | 573 | void kqemu_record_dump(void); |
9df217a3 FB |
574 | |
575 | static inline int kqemu_is_ok(CPUState *env) | |
576 | { | |
577 | return(env->kqemu_enabled && | |
5fafdf24 | 578 | (env->cr[0] & CR0_PE_MASK) && |
f32fc648 | 579 | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
9df217a3 | 580 | (env->eflags & IF_MASK) && |
f32fc648 | 581 | !(env->eflags & VM_MASK) && |
5fafdf24 | 582 | (env->kqemu_enabled == 2 || |
f32fc648 FB |
583 | ((env->hflags & HF_CPL_MASK) == 3 && |
584 | (env->eflags & IOPL_MASK) != IOPL_MASK))); | |
9df217a3 FB |
585 | } |
586 | ||
587 | #endif |