[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

#ifndef glue
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s)	tostring(s)
#define tostring(s)	#s
#endif

#if __GNUC__ < 3
#define __builtin_expect(x, n) (x)
#endif

#ifdef __i386__
#define REGPARM(n) __attribute((regparm(n)))
#else
#define REGPARM(n)
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern long gen_labels[OPC_BUF_SIZE];
extern int nb_gen_labels;
extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern target_ulong gen_opc_jump_pc[2];
extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);
                    
#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb, 
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb, 
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(CPUState *env);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr, 
                      target_phys_addr_t paddr, int prot, 
                      int is_user, int is_softmmu);
static inline int tlb_set_page(CPUState *env, target_ulong vaddr, 
                               target_phys_addr_t paddr, int prot, 
                               int is_user, int is_softmmu)
{
    if (prot & PAGE_READ)
        prot |= PAGE_EXEC;
    return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
}

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__ia64)
#define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)	/* range of addl */
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
#define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__) 
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next; 
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2]; 
    target_ulong page_addr[2]; 

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2]; 
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
    return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(target_ulong pc);
void tb_flush(CPUState *env);
void tb_link_phys(TranslationBlock *tb, 
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n, 
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
        
        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#endif

#define ASM_OP_LABEL_NAME(n, opname) \
    ASM_NAME(__op_label) #n "." ASM_NAME(opname)

#if defined(__powerpc__)

/* we patch the jump instruction directly */
#define GOTO_TB(opname, tbparam, n)\
do {\
    asm volatile (ASM_DATA_SECTION\
		  ASM_OP_LABEL_NAME(n, opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "b " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
} while (0)

#elif defined(__i386__) && defined(USE_DIRECT_JUMP)

/* we patch the jump instruction directly */
#define GOTO_TB(opname, tbparam, n)\
do {\
    asm volatile (".section .data\n"\
		  ASM_OP_LABEL_NAME(n, opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "jmp " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define GOTO_TB(opname, tbparam, n)\
do {\
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
    static void __attribute__((unused)) *__op_label ## n \
        __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n: ;\
dummy_label ## n: ;\
} while (0)

#endif

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1\n"
                          "      xor. %0,%3,%0\n"
                          "      bne 1f\n"
                          "      stwcx. %2,0,%1\n"
                          "      bne- 0b\n"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    long int readval = 0;
    
    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#endif

#ifdef __x86_64__
static inline int testandset (int *p)
{
    long int readval = 0;
    
    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

#ifdef __arm__
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));
    
    return ret;
}
#endif

#ifdef __mc68000
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret;
}
#endif

#ifdef __ia64
#include <ia64intrin.h>

static inline int testandset (int *p)
{
    return __sync_lock_test_and_set (p, 1);
}
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(target_ulong addr, int is_write, int is_user, 
              void *retaddr);

#define ACCESS_TYPE 3
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int is_user, index, pd;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
#if defined(TARGET_I386)
    is_user = ((env->hflags & HF_CPL_MASK) == 3);
#elif defined (TARGET_PPC)
    is_user = msr_pr;
#elif defined (TARGET_MIPS)
    is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
#elif defined (TARGET_SPARC)
    is_user = (env->psrs == 0);
#elif defined (TARGET_ARM)
    is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
#elif defined (TARGET_SH4)
    is_user = ((env->sr & SR_MD) == 0);
#else
#error unimplemented CPU
#endif
    if (__builtin_expect(env->tlb_table[is_user][index].addr_code != 
                         (addr & TARGET_PAGE_MASK), 0)) {
        ldub_code(addr);
    }
    pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM) {
        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
    }
    return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
}
#endif


#ifdef USE_KQEMU
#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))

int kqemu_init(CPUState *env);
int kqemu_cpu_exec(CPUState *env);
void kqemu_flush_page(CPUState *env, target_ulong addr);
void kqemu_flush(CPUState *env, int global);
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
void kqemu_cpu_interrupt(CPUState *env);
void kqemu_record_dump(void);

static inline int kqemu_is_ok(CPUState *env)
{
    return(env->kqemu_enabled &&
           (env->cr[0] & CR0_PE_MASK) && 
           !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
           (env->eflags & IF_MASK) &&
           !(env->eflags & VM_MASK) &&
           (env->kqemu_enabled == 2 || 
            ((env->hflags & HF_CPL_MASK) == 3 &&
             (env->eflags & IOPL_MASK) != IOPL_MASK)));
}

#endif
Commit	Line	Data
d4e8164f FB	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
33417e70 FB	24	#ifndef glue
	25	#define xglue(x, y) x ## y
	26	#define glue(x, y) xglue(x, y)
	27	#define stringify(s) tostring(s)
	28	#define tostring(s) #s
	29	#endif
	30
c98baaac	31	#if __GNUC__ < 3
33417e70 FB	32	#define __builtin_expect(x, n) (x)
	33	#endif
	34
e2222c39 FB	35	#ifdef __i386__
	36	#define REGPARM(n) __attribute((regparm(n)))
	37	#else
	38	#define REGPARM(n)
	39	#endif
	40
b346ff46 FB	41	/* is_jmp field values */
	42	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	43	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	44	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	45	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	46
	47	struct TranslationBlock;
	48
	49	/* XXX: make safe guess about sizes */
	50	#define MAX_OP_PER_INSTR 32
	51	#define OPC_BUF_SIZE 512
	52	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	53
	54	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	55
	56	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	57	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
c27004ec FB	58	extern long gen_labels[OPC_BUF_SIZE];
	59	extern int nb_gen_labels;
	60	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
	61	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
66e85a21	62	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46	63	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
c3278b7b	64	extern target_ulong gen_opc_jump_pc[2];
30d6cb84	65	extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
b346ff46	66
9886cc16 FB	67	typedef void (GenOpFunc)(void);
	68	typedef void (GenOpFunc1)(long);
	69	typedef void (GenOpFunc2)(long, long);
	70	typedef void (GenOpFunc3)(long, long, long);
	71
b346ff46 FB	72	#if defined(TARGET_I386)
b346ff46 FB	73
33417e70	74	void optimize_flags_init(void);
d4e8164f	75
b346ff46 FB	76	#endif
	77
	78	extern FILE *logfile;
	79	extern int loglevel;
	80
4c3a88a2 FB	81	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	82	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
b346ff46	83	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
4c3a88a2	84	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
b346ff46	85	int max_code_size, int *gen_code_size_ptr);
66e85a21	86	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	87	CPUState *env, unsigned long searched_pc,
	88	void *puc);
	89	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	90	int max_code_size, int *gen_code_size_ptr);
	91	int cpu_restore_state_copy(struct TranslationBlock *tb,
	92	CPUState *env, unsigned long searched_pc,
	93	void *puc);
2e12669a	94	void cpu_resume_from_signal(CPUState env1, void puc);
6a00d601	95	void cpu_exec_init(CPUState *env);
53a5960a	96	int page_unprotect(target_ulong address, unsigned long pc, void *puc);
2e12669a FB	97	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
2e12669a FB	98	int is_cpu_write_access);
4390df51	99	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	100	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	101	void tlb_flush(CPUState *env, int flush_global);
84b7b8e7 FB	102	int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
	103	target_phys_addr_t paddr, int prot,
	104	int is_user, int is_softmmu);
	105	static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
	106	target_phys_addr_t paddr, int prot,
	107	int is_user, int is_softmmu)
	108	{
	109	if (prot & PAGE_READ)
	110	prot \|= PAGE_EXEC;
	111	return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
	112	}
d4e8164f FB	113
	114	#define CODE_GEN_MAX_SIZE 65536
	115	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	116
4390df51 FB	117	#define CODE_GEN_PHYS_HASH_BITS 15
	118	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	119
d4e8164f	120	/* maximum total translate dcode allocated */
4390df51 FB	121
4390df51 FB	122	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	123	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	124	summary of the ranges:
	125
	126	i386 : signed 32 bits
	127	arm : signed 26 bits
	128	ppc : signed 24 bits
	129	sparc : signed 32 bits
	130	alpha : signed 23 bits
	131	*/
	132
	133	#if defined(__alpha__)
	134	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
b8076a74 FB	135	#elif defined(__ia64)
b8076a74 FB	136	#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
4390df51	137	#elif defined(__powerpc__)
c4c7e3e6	138	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51	139	#else
c98baaac	140	#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
4390df51 FB	141	#endif
4390df51 FB	142
d4e8164f FB	143	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	144
4390df51 FB	145	/* estimated block size for TB allocation */
	146	/* XXX: use a per code average code fragment size and modulate it
	147	according to the host CPU */
	148	#if defined(CONFIG_SOFTMMU)
	149	#define CODE_GEN_AVG_BLOCK_SIZE 128
	150	#else
	151	#define CODE_GEN_AVG_BLOCK_SIZE 64
	152	#endif
	153
	154	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	155
	156	#if defined(__powerpc__)
	157	#define USE_DIRECT_JUMP
	158	#endif
67b915a5	159	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	160	#define USE_DIRECT_JUMP
	161	#endif
	162
	163	typedef struct TranslationBlock {
2e12669a FB	164	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	165	target_ulong cs_base; /* CS base for this block */
d4e8164f FB	166	unsigned int flags; /* flags defining in which context the code was generated */
	167	uint16_t size; /* size of target code for this block (1 <=
	168	size <= TARGET_PAGE_SIZE) */
58fe2f10	169	uint16_t cflags; /* compile flags */
bf088061 FB	170	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	171	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
	172	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	173	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	174
d4e8164f	175	uint8_t tc_ptr; / pointer to the translated code */
4390df51 FB	176	/* next matching tb for physical address. */
	177	struct TranslationBlock *phys_hash_next;
	178	/* first and second physical page containing code. The lower bit
	179	of the pointer tells the index in page_next[] */
	180	struct TranslationBlock *page_next[2];
	181	target_ulong page_addr[2];
	182
d4e8164f FB	183	/* the following data are used to directly call another TB from
	184	the code of this one. */
	185	uint16_t tb_next_offset[2]; /* offset of original jump target */
	186	#ifdef USE_DIRECT_JUMP
4cbb86e1	187	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	188	#else
95f7652d	189	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	190	#endif
	191	/* list of TBs jumping to this one. This is a circular list using
	192	the two least significant bits of the pointers to tell what is
	193	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	194	jmp_first */
	195	struct TranslationBlock *jmp_next[2];
	196	struct TranslationBlock *jmp_first;
	197	} TranslationBlock;
	198
8a40a180	199	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
d4e8164f	200	{
8a40a180	201	return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
d4e8164f FB	202	}
d4e8164f FB	203
4390df51 FB	204	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	205	{
	206	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	207	}
	208
c27004ec	209	TranslationBlock *tb_alloc(target_ulong pc);
0124311e	210	void tb_flush(CPUState *env);
4390df51 FB	211	void tb_link_phys(TranslationBlock *tb,
4390df51 FB	212	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f	213
4390df51	214	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	215
	216	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	217	extern uint8_t *code_gen_ptr;
	218
4390df51 FB	219	#if defined(USE_DIRECT_JUMP)
	220
	221	#if defined(__powerpc__)
4cbb86e1	222	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	223	{
d4e8164f FB	224	uint32_t val, *ptr;
d4e8164f FB	225
d4e8164f FB	226	/* patch the branch destination */
4cbb86e1	227	ptr = (uint32_t *)jmp_addr;
d4e8164f	228	val = *ptr;
4cbb86e1	229	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	230	*ptr = val;
	231	/* flush icache */
	232	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	233	asm volatile ("sync" : : : "memory");
	234	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	235	asm volatile ("sync" : : : "memory");
	236	asm volatile ("isync" : : : "memory");
	237	}
4390df51 FB	238	#elif defined(__i386__)
	239	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	240	{
	241	/* patch the branch destination */
	242	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	243	/* no need to flush icache explicitely */
	244	}
	245	#endif
d4e8164f	246
4cbb86e1 FB	247	static inline void tb_set_jmp_target(TranslationBlock *tb,
	248	int n, unsigned long addr)
	249	{
	250	unsigned long offset;
	251
	252	offset = tb->tb_jmp_offset[n];
	253	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	254	offset = tb->tb_jmp_offset[n + 2];
	255	if (offset != 0xffff)
	256	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	257	}
	258
d4e8164f FB	259	#else
	260
	261	/* set the jump target */
	262	static inline void tb_set_jmp_target(TranslationBlock *tb,
	263	int n, unsigned long addr)
	264	{
95f7652d	265	tb->tb_next[n] = addr;
d4e8164f FB	266	}
	267
	268	#endif
	269
	270	static inline void tb_add_jump(TranslationBlock *tb, int n,
	271	TranslationBlock *tb_next)
	272	{
cf25629d FB	273	/* NOTE: this test is only needed for thread safety */
	274	if (!tb->jmp_next[n]) {
	275	/* patch the native jump address */
	276	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	277
	278	/* add in TB jmp circular list */
	279	tb->jmp_next[n] = tb_next->jmp_first;
	280	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	281	}
d4e8164f FB	282	}
d4e8164f FB	283
a513fe19 FB	284	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	285
d4e8164f FB	286	#ifndef offsetof
	287	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	288	#endif
	289
d549f7d9 FB	290	#if defined(_WIN32)
	291	#define ASM_DATA_SECTION ".section \".data\"\n"
	292	#define ASM_PREVIOUS_SECTION ".section .text\n"
	293	#elif defined(__APPLE__)
	294	#define ASM_DATA_SECTION ".data\n"
	295	#define ASM_PREVIOUS_SECTION ".text\n"
d549f7d9 FB	296	#else
	297	#define ASM_DATA_SECTION ".section \".data\"\n"
	298	#define ASM_PREVIOUS_SECTION ".previous\n"
d549f7d9 FB	299	#endif
d549f7d9 FB	300
75913b72 FB	301	#define ASM_OP_LABEL_NAME(n, opname) \
	302	ASM_NAME(__op_label) #n "." ASM_NAME(opname)
	303
b346ff46 FB	304	#if defined(__powerpc__)
b346ff46 FB	305
4390df51	306	/* we patch the jump instruction directly */
ae063a68	307	#define GOTO_TB(opname, tbparam, n)\
b346ff46	308	do {\
d549f7d9	309	asm volatile (ASM_DATA_SECTION\
75913b72	310	ASM_OP_LABEL_NAME(n, opname) ":\n"\
9257a9e4	311	".long 1f\n"\
d549f7d9 FB	312	ASM_PREVIOUS_SECTION \
d549f7d9 FB	313	"b " ASM_NAME(__op_jmp) #n "\n"\
9257a9e4	314	"1:\n");\
4390df51 FB	315	} while (0)
	316
	317	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
	318
	319	/* we patch the jump instruction directly */
ae063a68	320	#define GOTO_TB(opname, tbparam, n)\
c27004ec FB	321	do {\
c27004ec FB	322	asm volatile (".section .data\n"\
75913b72	323	ASM_OP_LABEL_NAME(n, opname) ":\n"\
c27004ec FB	324	".long 1f\n"\
	325	ASM_PREVIOUS_SECTION \
	326	"jmp " ASM_NAME(__op_jmp) #n "\n"\
	327	"1:\n");\
	328	} while (0)
	329
b346ff46 FB	330	#else
	331
	332	/* jump to next block operations (more portable code, does not need
	333	cache flushing, but slower because of indirect jump) */
ae063a68	334	#define GOTO_TB(opname, tbparam, n)\
b346ff46	335	do {\
2f62b397	336	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
75913b72 FB	337	static void __attribute__((unused)) *__op_label ## n \
75913b72 FB	338	__asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
b346ff46	339	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
ae063a68 FB	340	label ## n: ;\
ae063a68 FB	341	dummy_label ## n: ;\
b346ff46 FB	342	} while (0)
b346ff46 FB	343
ae063a68 FB	344	#endif
ae063a68 FB	345
33417e70 FB	346	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	347	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	348	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	349
d4e8164f FB	350	#ifdef __powerpc__
	351	static inline int testandset (int *p)
	352	{
	353	int ret;
	354	__asm__ __volatile__ (
02e1ec9b FB	355	"0: lwarx %0,0,%1\n"
	356	" xor. %0,%3,%0\n"
	357	" bne 1f\n"
	358	" stwcx. %2,0,%1\n"
	359	" bne- 0b\n"
d4e8164f FB	360	"1: "
	361	: "=&r" (ret)
	362	: "r" (p), "r" (1), "r" (0)
	363	: "cr0", "memory");
	364	return ret;
	365	}
	366	#endif
	367
	368	#ifdef __i386__
	369	static inline int testandset (int *p)
	370	{
4955a2cd	371	long int readval = 0;
d4e8164f	372
4955a2cd FB	373	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	374	: "+m" (*p), "+a" (readval)
	375	: "r" (1)
	376	: "cc");
	377	return readval;
d4e8164f FB	378	}
	379	#endif
	380
bc51c5c9 FB	381	#ifdef __x86_64__
	382	static inline int testandset (int *p)
	383	{
4955a2cd	384	long int readval = 0;
bc51c5c9	385
4955a2cd FB	386	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	387	: "+m" (*p), "+a" (readval)
	388	: "r" (1)
	389	: "cc");
	390	return readval;
bc51c5c9 FB	391	}
	392	#endif
	393
d4e8164f FB	394	#ifdef __s390__
	395	static inline int testandset (int *p)
	396	{
	397	int ret;
	398
	399	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	400	" jl 0b"
	401	: "=&d" (ret)
	402	: "r" (1), "a" (p), "0" (*p)
	403	: "cc", "memory" );
	404	return ret;
	405	}
	406	#endif
	407
	408	#ifdef __alpha__
2f87c607	409	static inline int testandset (int *p)
d4e8164f FB	410	{
	411	int ret;
	412	unsigned long one;
	413
	414	__asm__ __volatile__ ("0: mov 1,%2\n"
	415	" ldl_l %0,%1\n"
	416	" stl_c %2,%1\n"
	417	" beq %2,1f\n"
	418	".subsection 2\n"
	419	"1: br 0b\n"
	420	".previous"
	421	: "=r" (ret), "=m" (*p), "=r" (one)
	422	: "m" (*p));
	423	return ret;
	424	}
	425	#endif
	426
	427	#ifdef __sparc__
	428	static inline int testandset (int *p)
	429	{
	430	int ret;
	431
	432	__asm__ __volatile__("ldstub [%1], %0"
	433	: "=r" (ret)
	434	: "r" (p)
	435	: "memory");
	436
	437	return (ret ? 1 : 0);
	438	}
	439	#endif
	440
a95c6790 FB	441	#ifdef __arm__
	442	static inline int testandset (int *spinlock)
	443	{
	444	register unsigned int ret;
	445	__asm__ __volatile__("swp %0, %1, [%2]"
	446	: "=r"(ret)
	447	: "0"(1), "r"(spinlock));
	448
	449	return ret;
	450	}
	451	#endif
	452
38e584a0 FB	453	#ifdef __mc68000
	454	static inline int testandset (int *p)
	455	{
	456	char ret;
	457	__asm__ __volatile__("tas %1; sne %0"
	458	: "=r" (ret)
	459	: "m" (p)
	460	: "cc","memory");
4955a2cd	461	return ret;
38e584a0 FB	462	}
	463	#endif
	464
b8076a74 FB	465	#ifdef __ia64
	466	#include <ia64intrin.h>
	467
	468	static inline int testandset (int *p)
	469	{
	470	return __sync_lock_test_and_set (p, 1);
	471	}
	472	#endif
	473
d4e8164f FB	474	typedef int spinlock_t;
	475
	476	#define SPIN_LOCK_UNLOCKED 0
	477
aebcb60e	478	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	479	static inline void spin_lock(spinlock_t *lock)
	480	{
	481	while (testandset(lock));
	482	}
	483
	484	static inline void spin_unlock(spinlock_t *lock)
	485	{
	486	*lock = 0;
	487	}
	488
	489	static inline int spin_trylock(spinlock_t *lock)
	490	{
	491	return !testandset(lock);
	492	}
3c1cf9fa FB	493	#else
	494	static inline void spin_lock(spinlock_t *lock)
	495	{
	496	}
	497
	498	static inline void spin_unlock(spinlock_t *lock)
	499	{
	500	}
	501
	502	static inline int spin_trylock(spinlock_t *lock)
	503	{
	504	return 1;
	505	}
	506	#endif
d4e8164f FB	507
	508	extern spinlock_t tb_lock;
	509
36bdbe54	510	extern int tb_invalidated_flag;
6e59c1db	511
e95c8d51	512	#if !defined(CONFIG_USER_ONLY)
6e59c1db	513
c27004ec	514	void tlb_fill(target_ulong addr, int is_write, int is_user,
6e59c1db FB	515	void *retaddr);
	516
	517	#define ACCESS_TYPE 3
	518	#define MEMSUFFIX _code
	519	#define env cpu_single_env
	520
	521	#define DATA_SIZE 1
	522	#include "softmmu_header.h"
	523
	524	#define DATA_SIZE 2
	525	#include "softmmu_header.h"
	526
	527	#define DATA_SIZE 4
	528	#include "softmmu_header.h"
	529
c27004ec FB	530	#define DATA_SIZE 8
	531	#include "softmmu_header.h"
	532
6e59c1db FB	533	#undef ACCESS_TYPE
	534	#undef MEMSUFFIX
	535	#undef env
	536
	537	#endif
4390df51 FB	538
	539	#if defined(CONFIG_USER_ONLY)
	540	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	541	{
	542	return addr;
	543	}
	544	#else
	545	/* NOTE: this function can trigger an exception */
1ccde1cb FB	546	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	547	is the offset relative to phys_ram_base */
4390df51 FB	548	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
4390df51 FB	549	{
c27004ec	550	int is_user, index, pd;
4390df51 FB	551
4390df51 FB	552	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
3f5dcc34	553	#if defined(TARGET_I386)
4390df51	554	is_user = ((env->hflags & HF_CPL_MASK) == 3);
3f5dcc34 FB	555	#elif defined (TARGET_PPC)
3f5dcc34 FB	556	is_user = msr_pr;
6af0bf9c FB	557	#elif defined (TARGET_MIPS)
6af0bf9c FB	558	is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
e95c8d51 FB	559	#elif defined (TARGET_SPARC)
e95c8d51 FB	560	is_user = (env->psrs == 0);
b5ff1b31 FB	561	#elif defined (TARGET_ARM)
b5ff1b31 FB	562	is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
fdf9b3e8 FB	563	#elif defined (TARGET_SH4)
fdf9b3e8 FB	564	is_user = ((env->sr & SR_MD) == 0);
3f5dcc34	565	#else
b5ff1b31	566	#error unimplemented CPU
3f5dcc34	567	#endif
84b7b8e7	568	if (__builtin_expect(env->tlb_table[is_user][index].addr_code !=
4390df51	569	(addr & TARGET_PAGE_MASK), 0)) {
c27004ec FB	570	ldub_code(addr);
c27004ec FB	571	}
84b7b8e7	572	pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
c27004ec FB	573	if (pd > IO_MEM_ROM) {
c27004ec FB	574	cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
4390df51	575	}
84b7b8e7	576	return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
4390df51 FB	577	}
4390df51 FB	578	#endif
9df217a3 FB	579
	580
	581	#ifdef USE_KQEMU
f32fc648 FB	582	#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG \| CODE_DIRTY_FLAG))
f32fc648 FB	583
9df217a3 FB	584	int kqemu_init(CPUState *env);
	585	int kqemu_cpu_exec(CPUState *env);
	586	void kqemu_flush_page(CPUState *env, target_ulong addr);
	587	void kqemu_flush(CPUState *env, int global);
4b7df22f	588	void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
f32fc648	589	void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
a332e112	590	void kqemu_cpu_interrupt(CPUState *env);
f32fc648	591	void kqemu_record_dump(void);
9df217a3 FB	592
	593	static inline int kqemu_is_ok(CPUState *env)
	594	{
	595	return(env->kqemu_enabled &&
9df217a3	596	(env->cr[0] & CR0_PE_MASK) &&
f32fc648	597	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
9df217a3	598	(env->eflags & IF_MASK) &&
f32fc648 FB	599	!(env->eflags & VM_MASK) &&
	600	(env->kqemu_enabled == 2 \|\|
	601	((env->hflags & HF_CPL_MASK) == 3 &&
	602	(env->eflags & IOPL_MASK) != IOPL_MASK)));
9df217a3 FB	603	}
	604
	605	#endif