[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

#ifndef glue
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s)	tostring(s)
#define tostring(s)	#s
#endif

#if GCC_MAJOR < 3
#define __builtin_expect(x, n) (x)
#endif

#ifdef __i386__
#define REGPARM(n) __attribute((regparm(n)))
#else
#define REGPARM(n)
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];

#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb, 
                      CPUState *env, unsigned long searched_pc);
void cpu_exec_init(void);
int page_unprotect(unsigned long address);
void page_unmap(void);
void tlb_flush_page(CPUState *env, uint32_t addr);
void tlb_flush(CPUState *env);

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_HASH_BITS     15
#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)

/* maximum total translate dcode allocated */
#define CODE_GEN_BUFFER_SIZE     (2048 * 1024)
//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

#if defined(__powerpc__)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    unsigned long pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    unsigned long cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint8_t *tc_ptr;    /* pointer to the translated code */
    struct TranslationBlock *hash_next; /* next matching block */
    struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */
    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2]; 
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(unsigned long pc);
void tb_flush(void);
void tb_link(TranslationBlock *tb);

extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

/* find a translation block in the translation cache. If not found,
   return NULL and the pointer to the last element of the list in pptb */
static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
                                        unsigned long pc, 
                                        unsigned long cs_base,
                                        unsigned int flags)
{
    TranslationBlock **ptb, *tb;
    unsigned int h;
 
    h = tb_hash_func(pc);
    ptb = &tb_hash[h];
    for(;;) {
        tb = *ptb;
        if (!tb)
            break;
        if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
            return tb;
        ptb = &tb->hash_next;
    }
    *pptb = ptb;
    return NULL;
}

#if defined(__powerpc__)

static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}

static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n, 
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
        
        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(__powerpc__)

/* on PowerPC we patch the jump instruction directly */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    asm volatile (".section \".data\"\n"\
		  "__op_label" #n "." stringify(opname) ":\n"\
		  ".long 1f\n"\
		  ".previous\n"\
                  "b __op_jmp" #n "\n"\
		  "1:\n");\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
    EXIT_TB();\
} while (0)

#define JUMP_TB2(opname, tbparam, n)\
do {\
    asm volatile ("b __op_jmp%0\n" : : "i" (n + 2));\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n:\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
dummy_label ## n:\
    EXIT_TB();\
} while (0)

/* second jump to same destination 'n' */
#define JUMP_TB2(opname, tbparam, n)\
do {\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
} while (0)

#endif

/* physical memory access */
#define IO_MEM_NB_ENTRIES  256
#define TLB_INVALID_MASK   (1 << 3)
#define IO_MEM_SHIFT       4
#define IO_MEM_UNASSIGNED  (1 << IO_MEM_SHIFT)

unsigned long physpage_find(unsigned long page);

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1 ;"
                          "      xor. %0,%3,%0;"
                          "      bne 1f;"
                          "      stwcx. %2,0,%1;"
                          "      bne- 0b;"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    char ret;
    long int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

#ifdef __arm__
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));
    
    return ret;
}
#endif

#ifdef __mc68000
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret == 0;
}
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if 1
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;
Commit	Line	Data
d4e8164f FB	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
33417e70 FB	24	#ifndef glue
	25	#define xglue(x, y) x ## y
	26	#define glue(x, y) xglue(x, y)
	27	#define stringify(s) tostring(s)
	28	#define tostring(s) #s
	29	#endif
	30
	31	#if GCC_MAJOR < 3
	32	#define __builtin_expect(x, n) (x)
	33	#endif
	34
e2222c39 FB	35	#ifdef __i386__
	36	#define REGPARM(n) __attribute((regparm(n)))
	37	#else
	38	#define REGPARM(n)
	39	#endif
	40
b346ff46 FB	41	/* is_jmp field values */
	42	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	43	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	44	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	45	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	46
	47	struct TranslationBlock;
	48
	49	/* XXX: make safe guess about sizes */
	50	#define MAX_OP_PER_INSTR 32
	51	#define OPC_BUF_SIZE 512
	52	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	53
	54	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	55
	56	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	57	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
	58	extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
66e85a21	59	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46 FB	60	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
	61
	62	#if defined(TARGET_I386)
	63
33417e70	64	void optimize_flags_init(void);
d4e8164f	65
b346ff46 FB	66	#endif
	67
	68	extern FILE *logfile;
	69	extern int loglevel;
	70
4c3a88a2 FB	71	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	72	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
b346ff46	73	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
4c3a88a2	74	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
b346ff46	75	int max_code_size, int *gen_code_size_ptr);
66e85a21 FB	76	int cpu_restore_state(struct TranslationBlock *tb,
66e85a21 FB	77	CPUState *env, unsigned long searched_pc);
b346ff46	78	void cpu_exec_init(void);
d4e8164f	79	int page_unprotect(unsigned long address);
66e85a21	80	void page_unmap(void);
33417e70 FB	81	void tlb_flush_page(CPUState *env, uint32_t addr);
33417e70 FB	82	void tlb_flush(CPUState *env);
d4e8164f FB	83
	84	#define CODE_GEN_MAX_SIZE 65536
	85	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	86
	87	#define CODE_GEN_HASH_BITS 15
	88	#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
	89
	90	/* maximum total translate dcode allocated */
	91	#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
	92	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
	93
	94	#if defined(__powerpc__)
	95	#define USE_DIRECT_JUMP
	96	#endif
	97
	98	typedef struct TranslationBlock {
	99	unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
	100	unsigned long cs_base; /* CS base for this block */
	101	unsigned int flags; /* flags defining in which context the code was generated */
	102	uint16_t size; /* size of target code for this block (1 <=
	103	size <= TARGET_PAGE_SIZE) */
	104	uint8_t tc_ptr; / pointer to the translated code */
	105	struct TranslationBlock hash_next; / next matching block */
	106	struct TranslationBlock page_next[2]; / next blocks in even/odd page */
	107	/* the following data are used to directly call another TB from
	108	the code of this one. */
	109	uint16_t tb_next_offset[2]; /* offset of original jump target */
	110	#ifdef USE_DIRECT_JUMP
4cbb86e1	111	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	112	#else
95f7652d	113	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	114	#endif
	115	/* list of TBs jumping to this one. This is a circular list using
	116	the two least significant bits of the pointers to tell what is
	117	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	118	jmp_first */
	119	struct TranslationBlock *jmp_next[2];
	120	struct TranslationBlock *jmp_first;
	121	} TranslationBlock;
	122
	123	static inline unsigned int tb_hash_func(unsigned long pc)
	124	{
	125	return pc & (CODE_GEN_HASH_SIZE - 1);
	126	}
	127
	128	TranslationBlock *tb_alloc(unsigned long pc);
	129	void tb_flush(void);
	130	void tb_link(TranslationBlock *tb);
	131
	132	extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
	133
	134	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	135	extern uint8_t *code_gen_ptr;
	136
	137	/* find a translation block in the translation cache. If not found,
	138	return NULL and the pointer to the last element of the list in pptb */
	139	static inline TranslationBlock tb_find(TranslationBlock **pptb,
	140	unsigned long pc,
	141	unsigned long cs_base,
	142	unsigned int flags)
	143	{
	144	TranslationBlock *ptb, tb;
	145	unsigned int h;
	146
	147	h = tb_hash_func(pc);
	148	ptb = &tb_hash[h];
	149	for(;;) {
	150	tb = *ptb;
	151	if (!tb)
	152	break;
	153	if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
	154	return tb;
	155	ptb = &tb->hash_next;
	156	}
	157	*pptb = ptb;
	158	return NULL;
	159	}
	160
	161	#if defined(__powerpc__)
	162
4cbb86e1	163	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	164	{
d4e8164f FB	165	uint32_t val, *ptr;
d4e8164f FB	166
d4e8164f FB	167	/* patch the branch destination */
4cbb86e1	168	ptr = (uint32_t *)jmp_addr;
d4e8164f	169	val = *ptr;
4cbb86e1	170	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	171	*ptr = val;
	172	/* flush icache */
	173	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	174	asm volatile ("sync" : : : "memory");
	175	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	176	asm volatile ("sync" : : : "memory");
	177	asm volatile ("isync" : : : "memory");
	178	}
	179
4cbb86e1 FB	180	static inline void tb_set_jmp_target(TranslationBlock *tb,
	181	int n, unsigned long addr)
	182	{
	183	unsigned long offset;
	184
	185	offset = tb->tb_jmp_offset[n];
	186	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	187	offset = tb->tb_jmp_offset[n + 2];
	188	if (offset != 0xffff)
	189	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	190	}
	191
d4e8164f FB	192	#else
	193
	194	/* set the jump target */
	195	static inline void tb_set_jmp_target(TranslationBlock *tb,
	196	int n, unsigned long addr)
	197	{
95f7652d	198	tb->tb_next[n] = addr;
d4e8164f FB	199	}
	200
	201	#endif
	202
	203	static inline void tb_add_jump(TranslationBlock *tb, int n,
	204	TranslationBlock *tb_next)
	205	{
cf25629d FB	206	/* NOTE: this test is only needed for thread safety */
	207	if (!tb->jmp_next[n]) {
	208	/* patch the native jump address */
	209	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	210
	211	/* add in TB jmp circular list */
	212	tb->jmp_next[n] = tb_next->jmp_first;
	213	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	214	}
d4e8164f FB	215	}
d4e8164f FB	216
a513fe19 FB	217	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	218
d4e8164f FB	219	#ifndef offsetof
	220	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	221	#endif
	222
b346ff46 FB	223	#if defined(__powerpc__)
	224
	225	/* on PowerPC we patch the jump instruction directly */
9257a9e4	226	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46	227	do {\
9257a9e4 FB	228	asm volatile (".section \".data\"\n"\
	229	"__op_label" #n "." stringify(opname) ":\n"\
	230	".long 1f\n"\
	231	".previous\n"\
	232	"b __op_jmp" #n "\n"\
	233	"1:\n");\
b346ff46 FB	234	T0 = (long)(tbparam) + (n);\
b346ff46 FB	235	EIP = eip;\
31e8f3c8	236	EXIT_TB();\
b346ff46 FB	237	} while (0)
b346ff46 FB	238
4cbb86e1 FB	239	#define JUMP_TB2(opname, tbparam, n)\
	240	do {\
	241	asm volatile ("b __op_jmp%0\n" : : "i" (n + 2));\
	242	} while (0)
	243
b346ff46 FB	244	#else
	245
	246	/* jump to next block operations (more portable code, does not need
	247	cache flushing, but slower because of indirect jump) */
9257a9e4	248	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46 FB	249	do {\
b346ff46 FB	250	static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
2f62b397	251	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
b346ff46 FB	252	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
	253	label ## n:\
	254	T0 = (long)(tbparam) + (n);\
	255	EIP = eip;\
2f62b397	256	dummy_label ## n:\
9621339d	257	EXIT_TB();\
b346ff46 FB	258	} while (0)
b346ff46 FB	259
4cbb86e1 FB	260	/* second jump to same destination 'n' */
	261	#define JUMP_TB2(opname, tbparam, n)\
	262	do {\
	263	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
	264	} while (0)
	265
b346ff46 FB	266	#endif
b346ff46 FB	267
33417e70 FB	268	/* physical memory access */
	269	#define IO_MEM_NB_ENTRIES 256
	270	#define TLB_INVALID_MASK (1 << 3)
	271	#define IO_MEM_SHIFT 4
	272	#define IO_MEM_UNASSIGNED (1 << IO_MEM_SHIFT)
	273
	274	unsigned long physpage_find(unsigned long page);
	275
	276	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
	277	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
	278
d4e8164f FB	279	#ifdef __powerpc__
	280	static inline int testandset (int *p)
	281	{
	282	int ret;
	283	__asm__ __volatile__ (
	284	"0: lwarx %0,0,%1 ;"
	285	" xor. %0,%3,%0;"
	286	" bne 1f;"
	287	" stwcx. %2,0,%1;"
	288	" bne- 0b;"
	289	"1: "
	290	: "=&r" (ret)
	291	: "r" (p), "r" (1), "r" (0)
	292	: "cr0", "memory");
	293	return ret;
	294	}
	295	#endif
	296
	297	#ifdef __i386__
	298	static inline int testandset (int *p)
	299	{
	300	char ret;
	301	long int readval;
	302
	303	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	304	: "=q" (ret), "=m" (*p), "=a" (readval)
	305	: "r" (1), "m" (*p), "a" (0)
	306	: "memory");
	307	return ret;
	308	}
	309	#endif
	310
	311	#ifdef __s390__
	312	static inline int testandset (int *p)
	313	{
	314	int ret;
	315
	316	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	317	" jl 0b"
	318	: "=&d" (ret)
	319	: "r" (1), "a" (p), "0" (*p)
	320	: "cc", "memory" );
	321	return ret;
	322	}
	323	#endif
	324
	325	#ifdef __alpha__
2f87c607	326	static inline int testandset (int *p)
d4e8164f FB	327	{
	328	int ret;
	329	unsigned long one;
	330
	331	__asm__ __volatile__ ("0: mov 1,%2\n"
	332	" ldl_l %0,%1\n"
	333	" stl_c %2,%1\n"
	334	" beq %2,1f\n"
	335	".subsection 2\n"
	336	"1: br 0b\n"
	337	".previous"
	338	: "=r" (ret), "=m" (*p), "=r" (one)
	339	: "m" (*p));
	340	return ret;
	341	}
	342	#endif
	343
	344	#ifdef __sparc__
	345	static inline int testandset (int *p)
	346	{
	347	int ret;
	348
	349	__asm__ __volatile__("ldstub [%1], %0"
	350	: "=r" (ret)
	351	: "r" (p)
	352	: "memory");
	353
	354	return (ret ? 1 : 0);
	355	}
	356	#endif
	357
a95c6790 FB	358	#ifdef __arm__
	359	static inline int testandset (int *spinlock)
	360	{
	361	register unsigned int ret;
	362	__asm__ __volatile__("swp %0, %1, [%2]"
	363	: "=r"(ret)
	364	: "0"(1), "r"(spinlock));
	365
	366	return ret;
	367	}
	368	#endif
	369
38e584a0 FB	370	#ifdef __mc68000
	371	static inline int testandset (int *p)
	372	{
	373	char ret;
	374	__asm__ __volatile__("tas %1; sne %0"
	375	: "=r" (ret)
	376	: "m" (p)
	377	: "cc","memory");
	378	return ret == 0;
	379	}
	380	#endif
	381
d4e8164f FB	382	typedef int spinlock_t;
	383
	384	#define SPIN_LOCK_UNLOCKED 0
	385
3c1cf9fa	386	#if 1
d4e8164f FB	387	static inline void spin_lock(spinlock_t *lock)
	388	{
	389	while (testandset(lock));
	390	}
	391
	392	static inline void spin_unlock(spinlock_t *lock)
	393	{
	394	*lock = 0;
	395	}
	396
	397	static inline int spin_trylock(spinlock_t *lock)
	398	{
	399	return !testandset(lock);
	400	}
3c1cf9fa FB	401	#else
	402	static inline void spin_lock(spinlock_t *lock)
	403	{
	404	}
	405
	406	static inline void spin_unlock(spinlock_t *lock)
	407	{
	408	}
	409
	410	static inline int spin_trylock(spinlock_t *lock)
	411	{
	412	return 1;
	413	}
	414	#endif
d4e8164f FB	415
	416	extern spinlock_t tb_lock;
	417