[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

#ifndef glue
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s)	tostring(s)
#define tostring(s)	#s
#endif

#if GCC_MAJOR < 3
#define __builtin_expect(x, n) (x)
#endif

#ifdef __i386__
#define REGPARM(n) __attribute((regparm(n)))
#else
#define REGPARM(n)
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern long gen_labels[OPC_BUF_SIZE];
extern int nb_gen_labels;
extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);
                    
#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb, 
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb, 
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(void);
int page_unprotect(unsigned long address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page(CPUState *env, target_ulong vaddr, 
                 target_phys_addr_t paddr, int prot, 
                 int is_user, int is_softmmu);

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_HASH_BITS     15
#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
#define CODE_GEN_BUFFER_SIZE     (8 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__) 
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    struct TranslationBlock *hash_next; /* next matching tb for virtual address */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next; 
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2]; 
    target_ulong page_addr[2]; 

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2]; 
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_hash_func(target_ulong pc)
{
    return pc & (CODE_GEN_HASH_SIZE - 1);
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(target_ulong pc);
void tb_flush(CPUState *env);
void tb_link(TranslationBlock *tb);
void tb_link_phys(TranslationBlock *tb, 
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

/* find a translation block in the translation cache. If not found,
   return NULL and the pointer to the last element of the list in pptb */
static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
                                        target_ulong pc, 
                                        target_ulong cs_base,
                                        unsigned int flags)
{
    TranslationBlock **ptb, *tb;
    unsigned int h;
 
    h = tb_hash_func(pc);
    ptb = &tb_hash[h];
    for(;;) {
        tb = *ptb;
        if (!tb)
            break;
        if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
            return tb;
        ptb = &tb->hash_next;
    }
    *pptb = ptb;
    return NULL;
}


#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n, 
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
        
        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#define ASM_NAME(x) "_" #x
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#define ASM_NAME(x) stringify(x)
#endif

#if defined(__powerpc__)

/* we patch the jump instruction directly */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    asm volatile (ASM_DATA_SECTION\
		  ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "b " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
    T0 = (long)(tbparam) + (n);\
    EIP = (int32_t)eip;\
    EXIT_TB();\
} while (0)

#define JUMP_TB2(opname, tbparam, n)\
do {\
    asm volatile ("b " ASM_NAME(__op_jmp) #n "\n");\
} while (0)

#elif defined(__i386__) && defined(USE_DIRECT_JUMP)

/* we patch the jump instruction directly */
#define GOTO_TB(opname, n)\
do {\
    asm volatile (".section .data\n"\
		  ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "jmp " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
} while (0)

#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    asm volatile (".section .data\n"\
		  ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "jmp " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
    T0 = (long)(tbparam) + (n);\
    EIP = (int32_t)eip;\
    EXIT_TB();\
} while (0)

#define JUMP_TB2(opname, tbparam, n)\
do {\
    asm volatile ("jmp " ASM_NAME(__op_jmp) #n "\n");\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n:\
    T0 = (long)(tbparam) + (n);\
    EIP = (int32_t)eip;\
dummy_label ## n:\
    EXIT_TB();\
} while (0)

/* second jump to same destination 'n' */
#define JUMP_TB2(opname, tbparam, n)\
do {\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
} while (0)

#endif

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1\n"
                          "      xor. %0,%3,%0\n"
                          "      bne 1f\n"
                          "      stwcx. %2,0,%1\n"
                          "      bne- 0b\n"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    char ret;
    long int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __x86_64__
static inline int testandset (int *p)
{
    char ret;
    int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

#ifdef __arm__
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));
    
    return ret;
}
#endif

#ifdef __mc68000
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret == 0;
}
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(target_ulong addr, int is_write, int is_user, 
              void *retaddr);

#define ACCESS_TYPE 3
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
/* XXX: i386 target specific */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int is_user, index, pd;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
#if defined(TARGET_I386)
    is_user = ((env->hflags & HF_CPL_MASK) == 3);
#elif defined (TARGET_PPC)
    is_user = msr_pr;
#elif defined (TARGET_SPARC)
    is_user = (env->psrs == 0);
#else
#error "Unimplemented !"
#endif
    if (__builtin_expect(env->tlb_read[is_user][index].address != 
                         (addr & TARGET_PAGE_MASK), 0)) {
        ldub_code(addr);
    }
    pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM) {
        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
    }
    return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
}
#endif
Commit	Line	Data
d4e8164f FB	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
33417e70 FB	24	#ifndef glue
	25	#define xglue(x, y) x ## y
	26	#define glue(x, y) xglue(x, y)
	27	#define stringify(s) tostring(s)
	28	#define tostring(s) #s
	29	#endif
	30
	31	#if GCC_MAJOR < 3
	32	#define __builtin_expect(x, n) (x)
	33	#endif
	34
e2222c39 FB	35	#ifdef __i386__
	36	#define REGPARM(n) __attribute((regparm(n)))
	37	#else
	38	#define REGPARM(n)
	39	#endif
	40
b346ff46 FB	41	/* is_jmp field values */
	42	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	43	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	44	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	45	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	46
	47	struct TranslationBlock;
	48
	49	/* XXX: make safe guess about sizes */
	50	#define MAX_OP_PER_INSTR 32
	51	#define OPC_BUF_SIZE 512
	52	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	53
	54	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	55
	56	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	57	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
c27004ec FB	58	extern long gen_labels[OPC_BUF_SIZE];
	59	extern int nb_gen_labels;
	60	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
	61	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
66e85a21	62	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46 FB	63	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
b346ff46 FB	64
9886cc16 FB	65	typedef void (GenOpFunc)(void);
	66	typedef void (GenOpFunc1)(long);
	67	typedef void (GenOpFunc2)(long, long);
	68	typedef void (GenOpFunc3)(long, long, long);
	69
b346ff46 FB	70	#if defined(TARGET_I386)
b346ff46 FB	71
33417e70	72	void optimize_flags_init(void);
d4e8164f	73
b346ff46 FB	74	#endif
	75
	76	extern FILE *logfile;
	77	extern int loglevel;
	78
4c3a88a2 FB	79	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	80	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
b346ff46	81	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
4c3a88a2	82	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
b346ff46	83	int max_code_size, int *gen_code_size_ptr);
66e85a21	84	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	85	CPUState *env, unsigned long searched_pc,
	86	void *puc);
	87	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	88	int max_code_size, int *gen_code_size_ptr);
	89	int cpu_restore_state_copy(struct TranslationBlock *tb,
	90	CPUState *env, unsigned long searched_pc,
	91	void *puc);
2e12669a	92	void cpu_resume_from_signal(CPUState env1, void puc);
b346ff46	93	void cpu_exec_init(void);
2e12669a FB	94	int page_unprotect(unsigned long address, unsigned long pc, void *puc);
	95	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
	96	int is_cpu_write_access);
4390df51	97	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	98	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	99	void tlb_flush(CPUState *env, int flush_global);
2e12669a FB	100	int tlb_set_page(CPUState *env, target_ulong vaddr,
2e12669a FB	101	target_phys_addr_t paddr, int prot,
4390df51	102	int is_user, int is_softmmu);
d4e8164f FB	103
	104	#define CODE_GEN_MAX_SIZE 65536
	105	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	106
	107	#define CODE_GEN_HASH_BITS 15
	108	#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
	109
4390df51 FB	110	#define CODE_GEN_PHYS_HASH_BITS 15
	111	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	112
d4e8164f	113	/* maximum total translate dcode allocated */
4390df51 FB	114
4390df51 FB	115	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	116	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	117	summary of the ranges:
	118
	119	i386 : signed 32 bits
	120	arm : signed 26 bits
	121	ppc : signed 24 bits
	122	sparc : signed 32 bits
	123	alpha : signed 23 bits
	124	*/
	125
	126	#if defined(__alpha__)
	127	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
	128	#elif defined(__powerpc__)
c4c7e3e6	129	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51 FB	130	#else
	131	#define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024)
	132	#endif
	133
d4e8164f FB	134	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	135
4390df51 FB	136	/* estimated block size for TB allocation */
	137	/* XXX: use a per code average code fragment size and modulate it
	138	according to the host CPU */
	139	#if defined(CONFIG_SOFTMMU)
	140	#define CODE_GEN_AVG_BLOCK_SIZE 128
	141	#else
	142	#define CODE_GEN_AVG_BLOCK_SIZE 64
	143	#endif
	144
	145	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	146
	147	#if defined(__powerpc__)
	148	#define USE_DIRECT_JUMP
	149	#endif
67b915a5	150	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	151	#define USE_DIRECT_JUMP
	152	#endif
	153
	154	typedef struct TranslationBlock {
2e12669a FB	155	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	156	target_ulong cs_base; /* CS base for this block */
d4e8164f FB	157	unsigned int flags; /* flags defining in which context the code was generated */
	158	uint16_t size; /* size of target code for this block (1 <=
	159	size <= TARGET_PAGE_SIZE) */
58fe2f10	160	uint16_t cflags; /* compile flags */
bf088061 FB	161	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	162	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
	163	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	164	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	165
d4e8164f	166	uint8_t tc_ptr; / pointer to the translated code */
4390df51 FB	167	struct TranslationBlock hash_next; / next matching tb for virtual address */
	168	/* next matching tb for physical address. */
	169	struct TranslationBlock *phys_hash_next;
	170	/* first and second physical page containing code. The lower bit
	171	of the pointer tells the index in page_next[] */
	172	struct TranslationBlock *page_next[2];
	173	target_ulong page_addr[2];
	174
d4e8164f FB	175	/* the following data are used to directly call another TB from
	176	the code of this one. */
	177	uint16_t tb_next_offset[2]; /* offset of original jump target */
	178	#ifdef USE_DIRECT_JUMP
4cbb86e1	179	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	180	#else
95f7652d	181	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	182	#endif
	183	/* list of TBs jumping to this one. This is a circular list using
	184	the two least significant bits of the pointers to tell what is
	185	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	186	jmp_first */
	187	struct TranslationBlock *jmp_next[2];
	188	struct TranslationBlock *jmp_first;
	189	} TranslationBlock;
	190
c27004ec	191	static inline unsigned int tb_hash_func(target_ulong pc)
d4e8164f FB	192	{
	193	return pc & (CODE_GEN_HASH_SIZE - 1);
	194	}
	195
4390df51 FB	196	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	197	{
	198	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	199	}
	200
c27004ec	201	TranslationBlock *tb_alloc(target_ulong pc);
0124311e	202	void tb_flush(CPUState *env);
d4e8164f	203	void tb_link(TranslationBlock *tb);
4390df51 FB	204	void tb_link_phys(TranslationBlock *tb,
4390df51 FB	205	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f FB	206
d4e8164f FB	207	extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
4390df51	208	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	209
	210	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	211	extern uint8_t *code_gen_ptr;
	212
	213	/* find a translation block in the translation cache. If not found,
	214	return NULL and the pointer to the last element of the list in pptb */
	215	static inline TranslationBlock tb_find(TranslationBlock **pptb,
2e12669a FB	216	target_ulong pc,
2e12669a FB	217	target_ulong cs_base,
d4e8164f FB	218	unsigned int flags)
	219	{
	220	TranslationBlock *ptb, tb;
	221	unsigned int h;
	222
	223	h = tb_hash_func(pc);
	224	ptb = &tb_hash[h];
	225	for(;;) {
	226	tb = *ptb;
	227	if (!tb)
	228	break;
	229	if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
	230	return tb;
	231	ptb = &tb->hash_next;
	232	}
	233	*pptb = ptb;
	234	return NULL;
	235	}
	236
d4e8164f	237
4390df51 FB	238	#if defined(USE_DIRECT_JUMP)
	239
	240	#if defined(__powerpc__)
4cbb86e1	241	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	242	{
d4e8164f FB	243	uint32_t val, *ptr;
d4e8164f FB	244
d4e8164f FB	245	/* patch the branch destination */
4cbb86e1	246	ptr = (uint32_t *)jmp_addr;
d4e8164f	247	val = *ptr;
4cbb86e1	248	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	249	*ptr = val;
	250	/* flush icache */
	251	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	252	asm volatile ("sync" : : : "memory");
	253	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	254	asm volatile ("sync" : : : "memory");
	255	asm volatile ("isync" : : : "memory");
	256	}
4390df51 FB	257	#elif defined(__i386__)
	258	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	259	{
	260	/* patch the branch destination */
	261	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	262	/* no need to flush icache explicitely */
	263	}
	264	#endif
d4e8164f	265
4cbb86e1 FB	266	static inline void tb_set_jmp_target(TranslationBlock *tb,
	267	int n, unsigned long addr)
	268	{
	269	unsigned long offset;
	270
	271	offset = tb->tb_jmp_offset[n];
	272	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	273	offset = tb->tb_jmp_offset[n + 2];
	274	if (offset != 0xffff)
	275	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	276	}
	277
d4e8164f FB	278	#else
	279
	280	/* set the jump target */
	281	static inline void tb_set_jmp_target(TranslationBlock *tb,
	282	int n, unsigned long addr)
	283	{
95f7652d	284	tb->tb_next[n] = addr;
d4e8164f FB	285	}
	286
	287	#endif
	288
	289	static inline void tb_add_jump(TranslationBlock *tb, int n,
	290	TranslationBlock *tb_next)
	291	{
cf25629d FB	292	/* NOTE: this test is only needed for thread safety */
	293	if (!tb->jmp_next[n]) {
	294	/* patch the native jump address */
	295	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	296
	297	/* add in TB jmp circular list */
	298	tb->jmp_next[n] = tb_next->jmp_first;
	299	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	300	}
d4e8164f FB	301	}
d4e8164f FB	302
a513fe19 FB	303	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	304
d4e8164f FB	305	#ifndef offsetof
	306	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	307	#endif
	308
d549f7d9 FB	309	#if defined(_WIN32)
	310	#define ASM_DATA_SECTION ".section \".data\"\n"
	311	#define ASM_PREVIOUS_SECTION ".section .text\n"
	312	#elif defined(__APPLE__)
	313	#define ASM_DATA_SECTION ".data\n"
	314	#define ASM_PREVIOUS_SECTION ".text\n"
	315	#define ASM_NAME(x) "_" #x
	316	#else
	317	#define ASM_DATA_SECTION ".section \".data\"\n"
	318	#define ASM_PREVIOUS_SECTION ".previous\n"
	319	#define ASM_NAME(x) stringify(x)
	320	#endif
	321
b346ff46 FB	322	#if defined(__powerpc__)
b346ff46 FB	323
4390df51	324	/* we patch the jump instruction directly */
9257a9e4	325	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46	326	do {\
d549f7d9 FB	327	asm volatile (ASM_DATA_SECTION\
d549f7d9 FB	328	ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
9257a9e4	329	".long 1f\n"\
d549f7d9 FB	330	ASM_PREVIOUS_SECTION \
d549f7d9 FB	331	"b " ASM_NAME(__op_jmp) #n "\n"\
9257a9e4	332	"1:\n");\
b346ff46	333	T0 = (long)(tbparam) + (n);\
c27004ec	334	EIP = (int32_t)eip;\
31e8f3c8	335	EXIT_TB();\
b346ff46 FB	336	} while (0)
b346ff46 FB	337
4cbb86e1 FB	338	#define JUMP_TB2(opname, tbparam, n)\
4cbb86e1 FB	339	do {\
d549f7d9	340	asm volatile ("b " ASM_NAME(__op_jmp) #n "\n");\
4390df51 FB	341	} while (0)
	342
	343	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
	344
	345	/* we patch the jump instruction directly */
c27004ec FB	346	#define GOTO_TB(opname, n)\
	347	do {\
	348	asm volatile (".section .data\n"\
	349	ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
	350	".long 1f\n"\
	351	ASM_PREVIOUS_SECTION \
	352	"jmp " ASM_NAME(__op_jmp) #n "\n"\
	353	"1:\n");\
	354	} while (0)
	355
4390df51 FB	356	#define JUMP_TB(opname, tbparam, n, eip)\
4390df51 FB	357	do {\
67b915a5	358	asm volatile (".section .data\n"\
d549f7d9	359	ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
4390df51	360	".long 1f\n"\
67b915a5	361	ASM_PREVIOUS_SECTION \
d549f7d9	362	"jmp " ASM_NAME(__op_jmp) #n "\n"\
4390df51 FB	363	"1:\n");\
4390df51 FB	364	T0 = (long)(tbparam) + (n);\
c27004ec	365	EIP = (int32_t)eip;\
4390df51 FB	366	EXIT_TB();\
	367	} while (0)
	368
	369	#define JUMP_TB2(opname, tbparam, n)\
	370	do {\
d549f7d9	371	asm volatile ("jmp " ASM_NAME(__op_jmp) #n "\n");\
4cbb86e1 FB	372	} while (0)
4cbb86e1 FB	373
b346ff46 FB	374	#else
	375
	376	/* jump to next block operations (more portable code, does not need
	377	cache flushing, but slower because of indirect jump) */
9257a9e4	378	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46 FB	379	do {\
b346ff46 FB	380	static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
2f62b397	381	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
b346ff46 FB	382	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
	383	label ## n:\
	384	T0 = (long)(tbparam) + (n);\
c27004ec	385	EIP = (int32_t)eip;\
2f62b397	386	dummy_label ## n:\
9621339d	387	EXIT_TB();\
b346ff46 FB	388	} while (0)
b346ff46 FB	389
4cbb86e1 FB	390	/* second jump to same destination 'n' */
	391	#define JUMP_TB2(opname, tbparam, n)\
	392	do {\
4390df51	393	goto (void )(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
4cbb86e1 FB	394	} while (0)
4cbb86e1 FB	395
b346ff46 FB	396	#endif
b346ff46 FB	397
33417e70 FB	398	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	399	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	400	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	401
d4e8164f FB	402	#ifdef __powerpc__
	403	static inline int testandset (int *p)
	404	{
	405	int ret;
	406	__asm__ __volatile__ (
02e1ec9b FB	407	"0: lwarx %0,0,%1\n"
	408	" xor. %0,%3,%0\n"
	409	" bne 1f\n"
	410	" stwcx. %2,0,%1\n"
	411	" bne- 0b\n"
d4e8164f FB	412	"1: "
	413	: "=&r" (ret)
	414	: "r" (p), "r" (1), "r" (0)
	415	: "cr0", "memory");
	416	return ret;
	417	}
	418	#endif
	419
	420	#ifdef __i386__
	421	static inline int testandset (int *p)
	422	{
	423	char ret;
	424	long int readval;
	425
	426	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	427	: "=q" (ret), "=m" (*p), "=a" (readval)
	428	: "r" (1), "m" (*p), "a" (0)
	429	: "memory");
	430	return ret;
	431	}
	432	#endif
	433
bc51c5c9 FB	434	#ifdef __x86_64__
	435	static inline int testandset (int *p)
	436	{
	437	char ret;
	438	int readval;
	439
	440	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	441	: "=q" (ret), "=m" (*p), "=a" (readval)
	442	: "r" (1), "m" (*p), "a" (0)
	443	: "memory");
	444	return ret;
	445	}
	446	#endif
	447
d4e8164f FB	448	#ifdef __s390__
	449	static inline int testandset (int *p)
	450	{
	451	int ret;
	452
	453	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	454	" jl 0b"
	455	: "=&d" (ret)
	456	: "r" (1), "a" (p), "0" (*p)
	457	: "cc", "memory" );
	458	return ret;
	459	}
	460	#endif
	461
	462	#ifdef __alpha__
2f87c607	463	static inline int testandset (int *p)
d4e8164f FB	464	{
	465	int ret;
	466	unsigned long one;
	467
	468	__asm__ __volatile__ ("0: mov 1,%2\n"
	469	" ldl_l %0,%1\n"
	470	" stl_c %2,%1\n"
	471	" beq %2,1f\n"
	472	".subsection 2\n"
	473	"1: br 0b\n"
	474	".previous"
	475	: "=r" (ret), "=m" (*p), "=r" (one)
	476	: "m" (*p));
	477	return ret;
	478	}
	479	#endif
	480
	481	#ifdef __sparc__
	482	static inline int testandset (int *p)
	483	{
	484	int ret;
	485
	486	__asm__ __volatile__("ldstub [%1], %0"
	487	: "=r" (ret)
	488	: "r" (p)
	489	: "memory");
	490
	491	return (ret ? 1 : 0);
	492	}
	493	#endif
	494
a95c6790 FB	495	#ifdef __arm__
	496	static inline int testandset (int *spinlock)
	497	{
	498	register unsigned int ret;
	499	__asm__ __volatile__("swp %0, %1, [%2]"
	500	: "=r"(ret)
	501	: "0"(1), "r"(spinlock));
	502
	503	return ret;
	504	}
	505	#endif
	506
38e584a0 FB	507	#ifdef __mc68000
	508	static inline int testandset (int *p)
	509	{
	510	char ret;
	511	__asm__ __volatile__("tas %1; sne %0"
	512	: "=r" (ret)
	513	: "m" (p)
	514	: "cc","memory");
	515	return ret == 0;
	516	}
	517	#endif
	518
d4e8164f FB	519	typedef int spinlock_t;
	520
	521	#define SPIN_LOCK_UNLOCKED 0
	522
aebcb60e	523	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	524	static inline void spin_lock(spinlock_t *lock)
	525	{
	526	while (testandset(lock));
	527	}
	528
	529	static inline void spin_unlock(spinlock_t *lock)
	530	{
	531	*lock = 0;
	532	}
	533
	534	static inline int spin_trylock(spinlock_t *lock)
	535	{
	536	return !testandset(lock);
	537	}
3c1cf9fa FB	538	#else
	539	static inline void spin_lock(spinlock_t *lock)
	540	{
	541	}
	542
	543	static inline void spin_unlock(spinlock_t *lock)
	544	{
	545	}
	546
	547	static inline int spin_trylock(spinlock_t *lock)
	548	{
	549	return 1;
	550	}
	551	#endif
d4e8164f FB	552
	553	extern spinlock_t tb_lock;
	554
36bdbe54	555	extern int tb_invalidated_flag;
6e59c1db	556
e95c8d51	557	#if !defined(CONFIG_USER_ONLY)
6e59c1db	558
c27004ec	559	void tlb_fill(target_ulong addr, int is_write, int is_user,
6e59c1db FB	560	void *retaddr);
	561
	562	#define ACCESS_TYPE 3
	563	#define MEMSUFFIX _code
	564	#define env cpu_single_env
	565
	566	#define DATA_SIZE 1
	567	#include "softmmu_header.h"
	568
	569	#define DATA_SIZE 2
	570	#include "softmmu_header.h"
	571
	572	#define DATA_SIZE 4
	573	#include "softmmu_header.h"
	574
c27004ec FB	575	#define DATA_SIZE 8
	576	#include "softmmu_header.h"
	577
6e59c1db FB	578	#undef ACCESS_TYPE
	579	#undef MEMSUFFIX
	580	#undef env
	581
	582	#endif
4390df51 FB	583
	584	#if defined(CONFIG_USER_ONLY)
	585	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	586	{
	587	return addr;
	588	}
	589	#else
	590	/* NOTE: this function can trigger an exception */
1ccde1cb FB	591	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	592	is the offset relative to phys_ram_base */
4390df51 FB	593	/* XXX: i386 target specific */
	594	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	595	{
c27004ec	596	int is_user, index, pd;
4390df51 FB	597
4390df51 FB	598	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
3f5dcc34	599	#if defined(TARGET_I386)
4390df51	600	is_user = ((env->hflags & HF_CPL_MASK) == 3);
3f5dcc34 FB	601	#elif defined (TARGET_PPC)
3f5dcc34 FB	602	is_user = msr_pr;
e95c8d51 FB	603	#elif defined (TARGET_SPARC)
e95c8d51 FB	604	is_user = (env->psrs == 0);
3f5dcc34 FB	605	#else
	606	#error "Unimplemented !"
	607	#endif
4390df51 FB	608	if (__builtin_expect(env->tlb_read[is_user][index].address !=
4390df51 FB	609	(addr & TARGET_PAGE_MASK), 0)) {
c27004ec FB	610	ldub_code(addr);
	611	}
	612	pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
	613	if (pd > IO_MEM_ROM) {
	614	cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
4390df51 FB	615	}
	616	return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
	617	}
	618	#endif