[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 64
/* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
#define MAX_OPC_PARAM 10
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

/* Maximum size a TCG op can expand to.  This is complicated because a
   single op may require several host instructions and regirster reloads.
   For now take a wild guess at 128 bytes, which should allow at least
   a couple of fixup instructions per argument.  */
#define TCG_MAX_OP_SIZE 128

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)

extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern target_ulong gen_opc_jump_pc[2];
extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
                 unsigned long searched_pc, int pc_pos, void *puc);

unsigned long code_gen_max_block_size(void);
void cpu_gen_init(void);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb,
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_restore_state_copy(struct TranslationBlock *tb,
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(CPUState *env);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
                      target_phys_addr_t paddr, int prot,
                      int mmu_idx, int is_softmmu);
static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
                               target_phys_addr_t paddr, int prot,
                               int mmu_idx, int is_softmmu)
{
    if (prot & PAGE_READ)
        prot |= PAGE_EXEC;
    return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
}

#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

#define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    uint64_t flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next;
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2];
    target_ulong page_addr[2];

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    unsigned long tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2];
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
}

static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
	    | (tmp & TB_JMP_ADDR_MASK));
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(target_ulong pc);
void tb_flush(CPUState *env);
void tb_link_phys(TranslationBlock *tb,
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
extern uint8_t *code_gen_ptr;
extern int code_gen_max_blocks;

#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;
    long disp = addr - jmp_addr;

    ptr = (uint32_t *)jmp_addr;
    val = *ptr;

    if ((disp << 6) >> 6 != disp) {
        uint16_t *p1;

        p1 = (uint16_t *) ptr;
        *ptr = (val & ~0x03fffffc) | 4;
        p1[3] = addr >> 16;
        p1[5] = addr & 0xffff;
    } else {
        /* patch the branch destination */
        val = (val & ~0x03fffffc) | (disp & 0x03fffffc);
        *ptr = val;
    }
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__) || defined(__x86_64__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#elif defined(__arm__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    register unsigned long _beg __asm ("a1");
    register unsigned long _end __asm ("a2");
    register unsigned long _flg __asm ("a3");

    /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
    *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;

    /* flush icache */
    _beg = jmp_addr;
    _end = jmp_addr + 4;
    _flg = 0;
    __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n,
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);

        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#endif

#define ASM_OP_LABEL_NAME(n, opname) \
    ASM_NAME(__op_label) #n "." ASM_NAME(opname)

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#if defined(__hppa__)

typedef int spinlock_t[4];

#define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }

static inline void resetlock (spinlock_t *p)
{
    (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1;
}

#else

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

static inline void resetlock (spinlock_t *p)
{
    *p = SPIN_LOCK_UNLOCKED;
}

#endif

#if defined(__powerpc__)
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1\n"
                          "      xor. %0,%3,%0\n"
                          "      bne 1f\n"
                          "      stwcx. %2,0,%1\n"
                          "      bne- 0b\n"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#elif defined(__i386__)
static inline int testandset (int *p)
{
    long int readval = 0;

    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#elif defined(__x86_64__)
static inline int testandset (int *p)
{
    long int readval = 0;

    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#elif defined(__s390__)
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p)
			  : "cc", "memory" );
    return ret;
}
#elif defined(__alpha__)
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#elif defined(__sparc__)
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#elif defined(__arm__)
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));

    return ret;
}
#elif defined(__mc68000)
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret;
}
#elif defined(__hppa__)

/* Because malloc only guarantees 8-byte alignment for malloc'd data,
   and GCC only guarantees 8-byte alignment for stack locals, we can't
   be assured of 16-byte alignment for atomic lock data even if we
   specify "__attribute ((aligned(16)))" in the type declaration.  So,
   we use a struct containing an array of four ints for the atomic lock
   type and dynamically select the 16-byte aligned int from the array
   for the semaphore.  */
#define __PA_LDCW_ALIGNMENT 16
static inline void *ldcw_align (void *p) {
    unsigned long a = (unsigned long)p;
    a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
    return (void *)a;
}

static inline int testandset (spinlock_t *p)
{
    unsigned int ret;
    p = ldcw_align(p);
    __asm__ __volatile__("ldcw 0(%1),%0"
                         : "=r" (ret)
                         : "r" (p)
                         : "memory" );
    return !ret;
}

#elif defined(__ia64)

#include <ia64intrin.h>

static inline int testandset (int *p)
{
    return __sync_lock_test_and_set (p, 1);
}
#elif defined(__mips__)
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ (
	"	.set push		\n"
	"	.set noat		\n"
	"	.set mips2		\n"
	"1:	li	$1, 1		\n"
	"	ll	%0, %1		\n"
	"	sc	$1, %1		\n"
	"	beqz	$1, 1b		\n"
	"	.set pop		"
	: "=r" (ret), "+R" (*p)
	:
	: "memory");

    return ret;
}
#else
#error unimplemented CPU support
#endif

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    resetlock(lock);
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
              void *retaddr);

#define ACCESS_TYPE (NB_MMU_MODES + 1)
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
{
    int mmu_idx, page_index, pd;

    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = cpu_mmu_index(env1);
    if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
                         (addr & TARGET_PAGE_MASK), 0)) {
        ldub_code(addr);
    }
    pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
        do_unassigned_access(addr, 0, 1, 0);
#else
        cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
#endif
    }
    return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
}
#endif

#ifdef USE_KQEMU
#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))

#define MSR_QPI_COMMBASE 0xfabe0010

int kqemu_init(CPUState *env);
int kqemu_cpu_exec(CPUState *env);
void kqemu_flush_page(CPUState *env, target_ulong addr);
void kqemu_flush(CPUState *env, int global);
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size, 
                        ram_addr_t phys_offset);
void kqemu_cpu_interrupt(CPUState *env);
void kqemu_record_dump(void);

extern uint32_t kqemu_comm_base;

static inline int kqemu_is_ok(CPUState *env)
{
    return(env->kqemu_enabled &&
           (env->cr[0] & CR0_PE_MASK) &&
           !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
           (env->eflags & IF_MASK) &&
           !(env->eflags & VM_MASK) &&
           (env->kqemu_enabled == 2 ||
            ((env->hflags & HF_CPL_MASK) == 3 &&
             (env->eflags & IOPL_MASK) != IOPL_MASK)));
}

#endif
Commit	Line	Data
d4e8164f FB	1	/*
d4e8164f FB	2	* internal execution defines for qemu
5fafdf24	3	*
d4e8164f FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
cb7cca1a	22	#define DEBUG_DISAS
b346ff46 FB	23
	24	/* is_jmp field values */
	25	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	26	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	27	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	28	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	29
	30	struct TranslationBlock;
	31
	32	/* XXX: make safe guess about sizes */
e83a8673	33	#define MAX_OP_PER_INSTR 64
0115be31 PB	34	/* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
0115be31 PB	35	#define MAX_OPC_PARAM 10
b346ff46 FB	36	#define OPC_BUF_SIZE 512
	37	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	38
a208e54a PB	39	/* Maximum size a TCG op can expand to. This is complicated because a
	40	single op may require several host instructions and regirster reloads.
	41	For now take a wild guess at 128 bytes, which should allow at least
	42	a couple of fixup instructions per argument. */
	43	#define TCG_MAX_OP_SIZE 128
	44
0115be31	45	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
b346ff46	46
c27004ec FB	47	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
c27004ec FB	48	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
66e85a21	49	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46	50	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
c3278b7b	51	extern target_ulong gen_opc_jump_pc[2];
30d6cb84	52	extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
b346ff46	53
9886cc16 FB	54	typedef void (GenOpFunc)(void);
	55	typedef void (GenOpFunc1)(long);
	56	typedef void (GenOpFunc2)(long, long);
	57	typedef void (GenOpFunc3)(long, long, long);
3b46e624	58
b346ff46 FB	59	extern FILE *logfile;
	60	extern int loglevel;
	61
4c3a88a2 FB	62	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	63	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
d2856f1a AJ	64	void gen_pc_load(CPUState env, struct TranslationBlock tb,
	65	unsigned long searched_pc, int pc_pos, void *puc);
	66
d07bde88	67	unsigned long code_gen_max_block_size(void);
57fec1fe	68	void cpu_gen_init(void);
4c3a88a2	69	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
d07bde88	70	int *gen_code_size_ptr);
5fafdf24	71	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	72	CPUState *env, unsigned long searched_pc,
58fe2f10 FB	73	void *puc);
5fafdf24	74	int cpu_restore_state_copy(struct TranslationBlock *tb,
58fe2f10 FB	75	CPUState *env, unsigned long searched_pc,
58fe2f10 FB	76	void *puc);
2e12669a	77	void cpu_resume_from_signal(CPUState env1, void puc);
6a00d601	78	void cpu_exec_init(CPUState *env);
53a5960a	79	int page_unprotect(target_ulong address, unsigned long pc, void *puc);
00f82b8a	80	void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
2e12669a	81	int is_cpu_write_access);
4390df51	82	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	83	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	84	void tlb_flush(CPUState *env, int flush_global);
5fafdf24 TS	85	int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
5fafdf24 TS	86	target_phys_addr_t paddr, int prot,
6ebbf390	87	int mmu_idx, int is_softmmu);
4d7a0880	88	static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
5fafdf24	89	target_phys_addr_t paddr, int prot,
6ebbf390	90	int mmu_idx, int is_softmmu)
84b7b8e7 FB	91	{
	92	if (prot & PAGE_READ)
	93	prot \|= PAGE_EXEC;
4d7a0880	94	return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
84b7b8e7	95	}
d4e8164f	96
d4e8164f FB	97	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
d4e8164f FB	98
4390df51 FB	99	#define CODE_GEN_PHYS_HASH_BITS 15
	100	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	101
26a5f13b	102	#define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
d4e8164f	103
4390df51 FB	104	/* estimated block size for TB allocation */
	105	/* XXX: use a per code average code fragment size and modulate it
	106	according to the host CPU */
	107	#if defined(CONFIG_SOFTMMU)
	108	#define CODE_GEN_AVG_BLOCK_SIZE 128
	109	#else
	110	#define CODE_GEN_AVG_BLOCK_SIZE 64
	111	#endif
	112
811d4cf4	113	#if defined(__powerpc__) \|\| defined(__x86_64__) \|\| defined(__arm__)
4390df51 FB	114	#define USE_DIRECT_JUMP
4390df51 FB	115	#endif
67b915a5	116	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	117	#define USE_DIRECT_JUMP
	118	#endif
	119
	120	typedef struct TranslationBlock {
2e12669a FB	121	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	122	target_ulong cs_base; /* CS base for this block */
c068688b	123	uint64_t flags; /* flags defining in which context the code was generated */
d4e8164f FB	124	uint16_t size; /* size of target code for this block (1 <=
d4e8164f FB	125	size <= TARGET_PAGE_SIZE) */
58fe2f10	126	uint16_t cflags; /* compile flags */
bf088061 FB	127	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
bf088061 FB	128	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	129	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	130
d4e8164f	131	uint8_t tc_ptr; / pointer to the translated code */
4390df51	132	/* next matching tb for physical address. */
5fafdf24	133	struct TranslationBlock *phys_hash_next;
4390df51 FB	134	/* first and second physical page containing code. The lower bit
4390df51 FB	135	of the pointer tells the index in page_next[] */
5fafdf24 TS	136	struct TranslationBlock *page_next[2];
5fafdf24 TS	137	target_ulong page_addr[2];
4390df51	138
d4e8164f FB	139	/* the following data are used to directly call another TB from
	140	the code of this one. */
	141	uint16_t tb_next_offset[2]; /* offset of original jump target */
	142	#ifdef USE_DIRECT_JUMP
4cbb86e1	143	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	144	#else
57fec1fe	145	unsigned long tb_next[2]; /* address of jump generated code */
d4e8164f FB	146	#endif
	147	/* list of TBs jumping to this one. This is a circular list using
	148	the two least significant bits of the pointers to tell what is
	149	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	150	jmp_first */
5fafdf24	151	struct TranslationBlock *jmp_next[2];
d4e8164f FB	152	struct TranslationBlock *jmp_first;
	153	} TranslationBlock;
	154
b362e5e0 PB	155	static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
	156	{
	157	target_ulong tmp;
	158	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
b5e19d4c	159	return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
b362e5e0 PB	160	}
b362e5e0 PB	161
8a40a180	162	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
d4e8164f	163	{
b362e5e0 PB	164	target_ulong tmp;
b362e5e0 PB	165	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
b5e19d4c EI	166	return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
b5e19d4c EI	167	\| (tmp & TB_JMP_ADDR_MASK));
d4e8164f FB	168	}
d4e8164f FB	169
4390df51 FB	170	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	171	{
	172	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	173	}
	174
c27004ec	175	TranslationBlock *tb_alloc(target_ulong pc);
0124311e	176	void tb_flush(CPUState *env);
5fafdf24	177	void tb_link_phys(TranslationBlock *tb,
4390df51	178	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f	179
4390df51	180	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f	181	extern uint8_t *code_gen_ptr;
26a5f13b	182	extern int code_gen_max_blocks;
d4e8164f	183
4390df51 FB	184	#if defined(USE_DIRECT_JUMP)
	185
	186	#if defined(__powerpc__)
4cbb86e1	187	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	188	{
d4e8164f FB	189	uint32_t val, *ptr;
932a6909	190	long disp = addr - jmp_addr;
d4e8164f	191
4cbb86e1	192	ptr = (uint32_t *)jmp_addr;
d4e8164f	193	val = *ptr;
932a6909 FB	194
	195	if ((disp << 6) >> 6 != disp) {
	196	uint16_t *p1;
	197
	198	p1 = (uint16_t *) ptr;
	199	*ptr = (val & ~0x03fffffc) \| 4;
	200	p1[3] = addr >> 16;
	201	p1[5] = addr & 0xffff;
	202	} else {
	203	/* patch the branch destination */
	204	val = (val & ~0x03fffffc) \| (disp & 0x03fffffc);
	205	*ptr = val;
	206	}
d4e8164f FB	207	/* flush icache */
	208	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	209	asm volatile ("sync" : : : "memory");
	210	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	211	asm volatile ("sync" : : : "memory");
	212	asm volatile ("isync" : : : "memory");
	213	}
57fec1fe	214	#elif defined(__i386__) \|\| defined(__x86_64__)
4390df51 FB	215	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	216	{
	217	/* patch the branch destination */
	218	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	219	/* no need to flush icache explicitely */
	220	}
811d4cf4 AZ	221	#elif defined(__arm__)
	222	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	223	{
	224	register unsigned long _beg __asm ("a1");
	225	register unsigned long _end __asm ("a2");
	226	register unsigned long _flg __asm ("a3");
	227
	228	/* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
	229	(uint32_t )jmp_addr \|= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
	230
	231	/* flush icache */
	232	_beg = jmp_addr;
	233	_end = jmp_addr + 4;
	234	_flg = 0;
	235	__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
	236	}
4390df51	237	#endif
d4e8164f	238
5fafdf24	239	static inline void tb_set_jmp_target(TranslationBlock *tb,
4cbb86e1 FB	240	int n, unsigned long addr)
	241	{
	242	unsigned long offset;
	243
	244	offset = tb->tb_jmp_offset[n];
	245	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	246	offset = tb->tb_jmp_offset[n + 2];
	247	if (offset != 0xffff)
	248	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	249	}
	250
d4e8164f FB	251	#else
	252
	253	/* set the jump target */
5fafdf24	254	static inline void tb_set_jmp_target(TranslationBlock *tb,
d4e8164f FB	255	int n, unsigned long addr)
d4e8164f FB	256	{
95f7652d	257	tb->tb_next[n] = addr;
d4e8164f FB	258	}
	259
	260	#endif
	261
5fafdf24	262	static inline void tb_add_jump(TranslationBlock *tb, int n,
d4e8164f FB	263	TranslationBlock *tb_next)
d4e8164f FB	264	{
cf25629d FB	265	/* NOTE: this test is only needed for thread safety */
	266	if (!tb->jmp_next[n]) {
	267	/* patch the native jump address */
	268	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
3b46e624	269
cf25629d FB	270	/* add in TB jmp circular list */
	271	tb->jmp_next[n] = tb_next->jmp_first;
	272	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	273	}
d4e8164f FB	274	}
d4e8164f FB	275
a513fe19 FB	276	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	277
d4e8164f FB	278	#ifndef offsetof
	279	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	280	#endif
	281
d549f7d9 FB	282	#if defined(_WIN32)
	283	#define ASM_DATA_SECTION ".section \".data\"\n"
	284	#define ASM_PREVIOUS_SECTION ".section .text\n"
	285	#elif defined(__APPLE__)
	286	#define ASM_DATA_SECTION ".data\n"
	287	#define ASM_PREVIOUS_SECTION ".text\n"
d549f7d9 FB	288	#else
	289	#define ASM_DATA_SECTION ".section \".data\"\n"
	290	#define ASM_PREVIOUS_SECTION ".previous\n"
d549f7d9 FB	291	#endif
d549f7d9 FB	292
75913b72 FB	293	#define ASM_OP_LABEL_NAME(n, opname) \
	294	ASM_NAME(__op_label) #n "." ASM_NAME(opname)
	295
33417e70 FB	296	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	297	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	298	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	299
15a51156 AJ	300	#if defined(__hppa__)
	301
	302	typedef int spinlock_t[4];
	303
	304	#define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }
	305
	306	static inline void resetlock (spinlock_t *p)
	307	{
	308	(p)[0] = (p)[1] = (p)[2] = (p)[3] = 1;
	309	}
	310
	311	#else
	312
	313	typedef int spinlock_t;
	314
	315	#define SPIN_LOCK_UNLOCKED 0
	316
	317	static inline void resetlock (spinlock_t *p)
	318	{
	319	*p = SPIN_LOCK_UNLOCKED;
	320	}
	321
	322	#endif
	323
204a1b8d	324	#if defined(__powerpc__)
d4e8164f FB	325	static inline int testandset (int *p)
	326	{
	327	int ret;
	328	__asm__ __volatile__ (
02e1ec9b FB	329	"0: lwarx %0,0,%1\n"
	330	" xor. %0,%3,%0\n"
	331	" bne 1f\n"
	332	" stwcx. %2,0,%1\n"
	333	" bne- 0b\n"
d4e8164f FB	334	"1: "
	335	: "=&r" (ret)
	336	: "r" (p), "r" (1), "r" (0)
	337	: "cr0", "memory");
	338	return ret;
	339	}
204a1b8d	340	#elif defined(__i386__)
d4e8164f FB	341	static inline int testandset (int *p)
d4e8164f FB	342	{
4955a2cd	343	long int readval = 0;
3b46e624	344
4955a2cd FB	345	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	346	: "+m" (*p), "+a" (readval)
	347	: "r" (1)
	348	: "cc");
	349	return readval;
d4e8164f	350	}
204a1b8d	351	#elif defined(__x86_64__)
bc51c5c9 FB	352	static inline int testandset (int *p)
bc51c5c9 FB	353	{
4955a2cd	354	long int readval = 0;
3b46e624	355
4955a2cd FB	356	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	357	: "+m" (*p), "+a" (readval)
	358	: "r" (1)
	359	: "cc");
	360	return readval;
bc51c5c9	361	}
204a1b8d	362	#elif defined(__s390__)
d4e8164f FB	363	static inline int testandset (int *p)
	364	{
	365	int ret;
	366
	367	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	368	" jl 0b"
	369	: "=&d" (ret)
5fafdf24	370	: "r" (1), "a" (p), "0" (*p)
d4e8164f FB	371	: "cc", "memory" );
	372	return ret;
	373	}
204a1b8d	374	#elif defined(__alpha__)
2f87c607	375	static inline int testandset (int *p)
d4e8164f FB	376	{
	377	int ret;
	378	unsigned long one;
	379
	380	__asm__ __volatile__ ("0: mov 1,%2\n"
	381	" ldl_l %0,%1\n"
	382	" stl_c %2,%1\n"
	383	" beq %2,1f\n"
	384	".subsection 2\n"
	385	"1: br 0b\n"
	386	".previous"
	387	: "=r" (ret), "=m" (*p), "=r" (one)
	388	: "m" (*p));
	389	return ret;
	390	}
204a1b8d	391	#elif defined(__sparc__)
d4e8164f FB	392	static inline int testandset (int *p)
	393	{
	394	int ret;
	395
	396	__asm__ __volatile__("ldstub [%1], %0"
	397	: "=r" (ret)
	398	: "r" (p)
	399	: "memory");
	400
	401	return (ret ? 1 : 0);
	402	}
204a1b8d	403	#elif defined(__arm__)
a95c6790 FB	404	static inline int testandset (int *spinlock)
	405	{
	406	register unsigned int ret;
	407	__asm__ __volatile__("swp %0, %1, [%2]"
	408	: "=r"(ret)
	409	: "0"(1), "r"(spinlock));
3b46e624	410
a95c6790 FB	411	return ret;
a95c6790 FB	412	}
204a1b8d	413	#elif defined(__mc68000)
38e584a0 FB	414	static inline int testandset (int *p)
	415	{
	416	char ret;
	417	__asm__ __volatile__("tas %1; sne %0"
	418	: "=r" (ret)
	419	: "m" (p)
	420	: "cc","memory");
4955a2cd	421	return ret;
38e584a0	422	}
15a51156 AJ	423	#elif defined(__hppa__)
	424
	425	/* Because malloc only guarantees 8-byte alignment for malloc'd data,
	426	and GCC only guarantees 8-byte alignment for stack locals, we can't
	427	be assured of 16-byte alignment for atomic lock data even if we
	428	specify "__attribute ((aligned(16)))" in the type declaration. So,
	429	we use a struct containing an array of four ints for the atomic lock
	430	type and dynamically select the 16-byte aligned int from the array
	431	for the semaphore. */
	432	#define __PA_LDCW_ALIGNMENT 16
	433	static inline void ldcw_align (void p) {
	434	unsigned long a = (unsigned long)p;
	435	a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
	436	return (void *)a;
	437	}
	438
	439	static inline int testandset (spinlock_t *p)
	440	{
	441	unsigned int ret;
	442	p = ldcw_align(p);
	443	__asm__ __volatile__("ldcw 0(%1),%0"
	444	: "=r" (ret)
	445	: "r" (p)
	446	: "memory" );
	447	return !ret;
	448	}
	449
204a1b8d	450	#elif defined(__ia64)
38e584a0	451
b8076a74 FB	452	#include <ia64intrin.h>
	453
	454	static inline int testandset (int *p)
	455	{
	456	return __sync_lock_test_and_set (p, 1);
	457	}
204a1b8d	458	#elif defined(__mips__)
c4b89d18 TS	459	static inline int testandset (int *p)
	460	{
	461	int ret;
	462
	463	__asm__ __volatile__ (
	464	" .set push \n"
	465	" .set noat \n"
	466	" .set mips2 \n"
	467	"1: li $1, 1 \n"
	468	" ll %0, %1 \n"
	469	" sc $1, %1 \n"
976a0d0d	470	" beqz $1, 1b \n"
c4b89d18 TS	471	" .set pop "
	472	: "=r" (ret), "+R" (*p)
	473	:
	474	: "memory");
	475
	476	return ret;
	477	}
204a1b8d TS	478	#else
204a1b8d TS	479	#error unimplemented CPU support
c4b89d18 TS	480	#endif
c4b89d18 TS	481
aebcb60e	482	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	483	static inline void spin_lock(spinlock_t *lock)
	484	{
	485	while (testandset(lock));
	486	}
	487
	488	static inline void spin_unlock(spinlock_t *lock)
	489	{
15a51156	490	resetlock(lock);
d4e8164f FB	491	}
	492
	493	static inline int spin_trylock(spinlock_t *lock)
	494	{
	495	return !testandset(lock);
	496	}
3c1cf9fa FB	497	#else
	498	static inline void spin_lock(spinlock_t *lock)
	499	{
	500	}
	501
	502	static inline void spin_unlock(spinlock_t *lock)
	503	{
	504	}
	505
	506	static inline int spin_trylock(spinlock_t *lock)
	507	{
	508	return 1;
	509	}
	510	#endif
d4e8164f FB	511
	512	extern spinlock_t tb_lock;
	513
36bdbe54	514	extern int tb_invalidated_flag;
6e59c1db	515
e95c8d51	516	#if !defined(CONFIG_USER_ONLY)
6e59c1db	517
6ebbf390	518	void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
6e59c1db FB	519	void *retaddr);
6e59c1db FB	520
6ebbf390	521	#define ACCESS_TYPE (NB_MMU_MODES + 1)
6e59c1db FB	522	#define MEMSUFFIX _code
	523	#define env cpu_single_env
	524
	525	#define DATA_SIZE 1
	526	#include "softmmu_header.h"
	527
	528	#define DATA_SIZE 2
	529	#include "softmmu_header.h"
	530
	531	#define DATA_SIZE 4
	532	#include "softmmu_header.h"
	533
c27004ec FB	534	#define DATA_SIZE 8
	535	#include "softmmu_header.h"
	536
6e59c1db FB	537	#undef ACCESS_TYPE
	538	#undef MEMSUFFIX
	539	#undef env
	540
	541	#endif
4390df51 FB	542
4390df51 FB	543	#if defined(CONFIG_USER_ONLY)
4d7a0880	544	static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
4390df51 FB	545	{
	546	return addr;
	547	}
	548	#else
	549	/* NOTE: this function can trigger an exception */
1ccde1cb FB	550	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	551	is the offset relative to phys_ram_base */
4d7a0880	552	static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
4390df51	553	{
4d7a0880	554	int mmu_idx, page_index, pd;
4390df51	555
4d7a0880 BS	556	page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	557	mmu_idx = cpu_mmu_index(env1);
	558	if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
4390df51	559	(addr & TARGET_PAGE_MASK), 0)) {
c27004ec FB	560	ldub_code(addr);
c27004ec FB	561	}
4d7a0880	562	pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
2a4188a3	563	if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
647de6ca	564	#if defined(TARGET_SPARC) \|\| defined(TARGET_MIPS)
6c36d3fa BS	565	do_unassigned_access(addr, 0, 1, 0);
6c36d3fa BS	566	#else
4d7a0880	567	cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
6c36d3fa	568	#endif
4390df51	569	}
4d7a0880	570	return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
4390df51 FB	571	}
4390df51 FB	572	#endif
9df217a3	573
9df217a3	574	#ifdef USE_KQEMU
f32fc648 FB	575	#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG \| CODE_DIRTY_FLAG))
f32fc648 FB	576
da260249 FB	577	#define MSR_QPI_COMMBASE 0xfabe0010
da260249 FB	578
9df217a3 FB	579	int kqemu_init(CPUState *env);
	580	int kqemu_cpu_exec(CPUState *env);
	581	void kqemu_flush_page(CPUState *env, target_ulong addr);
	582	void kqemu_flush(CPUState *env, int global);
4b7df22f	583	void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
f32fc648	584	void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
da260249 FB	585	void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
da260249 FB	586	ram_addr_t phys_offset);
a332e112	587	void kqemu_cpu_interrupt(CPUState *env);
f32fc648	588	void kqemu_record_dump(void);
9df217a3	589
da260249 FB	590	extern uint32_t kqemu_comm_base;
da260249 FB	591
9df217a3 FB	592	static inline int kqemu_is_ok(CPUState *env)
	593	{
	594	return(env->kqemu_enabled &&
5fafdf24	595	(env->cr[0] & CR0_PE_MASK) &&
f32fc648	596	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
9df217a3	597	(env->eflags & IF_MASK) &&
f32fc648	598	!(env->eflags & VM_MASK) &&
5fafdf24	599	(env->kqemu_enabled == 2 \|\|
f32fc648 FB	600	((env->hflags & HF_CPL_MASK) == 3 &&
f32fc648 FB	601	(env->eflags & IOPL_MASK) != IOPL_MASK)));
9df217a3 FB	602	}
	603
	604	#endif