[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern target_ulong gen_opc_jump_pc[2];
extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);

#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
unsigned long code_gen_max_block_size(void);
void cpu_gen_init(void);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb,
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb,
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(CPUState *env);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
                      target_phys_addr_t paddr, int prot,
                      int mmu_idx, int is_softmmu);
static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
                               target_phys_addr_t paddr, int prot,
                               int mmu_idx, int is_softmmu)
{
    if (prot & PAGE_READ)
        prot |= PAGE_EXEC;
    return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
}

#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__ia64)
#define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)	/* range of addl */
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
/* XXX: make it dynamic on x86 */
#define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__) || defined(__x86_64__)
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    uint64_t flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next;
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2];
    target_ulong page_addr[2];

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    unsigned long tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2];
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
}

static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
	    (tmp & TB_JMP_ADDR_MASK));
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(target_ulong pc);
void tb_flush(CPUState *env);
void tb_link_phys(TranslationBlock *tb,
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__) || defined(__x86_64__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n,
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);

        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#endif

#define ASM_OP_LABEL_NAME(n, opname) \
    ASM_NAME(__op_label) #n "." ASM_NAME(opname)

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#if defined(__powerpc__)
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1\n"
                          "      xor. %0,%3,%0\n"
                          "      bne 1f\n"
                          "      stwcx. %2,0,%1\n"
                          "      bne- 0b\n"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#elif defined(__i386__)
static inline int testandset (int *p)
{
    long int readval = 0;

    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#elif defined(__x86_64__)
static inline int testandset (int *p)
{
    long int readval = 0;

    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#elif defined(__s390__)
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p)
			  : "cc", "memory" );
    return ret;
}
#elif defined(__alpha__)
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#elif defined(__sparc__)
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#elif defined(__arm__)
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));

    return ret;
}
#elif defined(__mc68000)
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret;
}
#elif defined(__ia64)

#include <ia64intrin.h>

static inline int testandset (int *p)
{
    return __sync_lock_test_and_set (p, 1);
}
#elif defined(__mips__)
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ (
	"	.set push		\n"
	"	.set noat		\n"
	"	.set mips2		\n"
	"1:	li	$1, 1		\n"
	"	ll	%0, %1		\n"
	"	sc	$1, %1		\n"
	"	beqz	$1, 1b		\n"
	"	.set pop		"
	: "=r" (ret), "+R" (*p)
	:
	: "memory");

    return ret;
}
#else
#error unimplemented CPU support
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
              void *retaddr);

#define ACCESS_TYPE (NB_MMU_MODES + 1)
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int mmu_idx, index, pd;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = cpu_mmu_index(env);
    if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
                         (addr & TARGET_PAGE_MASK), 0)) {
        ldub_code(addr);
    }
    pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
        do_unassigned_access(addr, 0, 1, 0);
#else
        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
#endif
    }
    return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
}
#endif

#ifdef USE_KQEMU
#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))

int kqemu_init(CPUState *env);
int kqemu_cpu_exec(CPUState *env);
void kqemu_flush_page(CPUState *env, target_ulong addr);
void kqemu_flush(CPUState *env, int global);
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
void kqemu_cpu_interrupt(CPUState *env);
void kqemu_record_dump(void);

static inline int kqemu_is_ok(CPUState *env)
{
    return(env->kqemu_enabled &&
           (env->cr[0] & CR0_PE_MASK) &&
           !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
           (env->eflags & IF_MASK) &&
           !(env->eflags & VM_MASK) &&
           (env->kqemu_enabled == 2 ||
            ((env->hflags & HF_CPL_MASK) == 3 &&
             (env->eflags & IOPL_MASK) != IOPL_MASK)));
}

#endif
Commit	Line	Data
d4e8164f FB	1	/*
d4e8164f FB	2	* internal execution defines for qemu
5fafdf24	3	*
d4e8164f FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
	24	/* is_jmp field values */
	25	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	26	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	27	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	28	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	29
	30	struct TranslationBlock;
	31
	32	/* XXX: make safe guess about sizes */
	33	#define MAX_OP_PER_INSTR 32
	34	#define OPC_BUF_SIZE 512
	35	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	36
	37	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	38
c27004ec FB	39	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
c27004ec FB	40	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
66e85a21	41	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46	42	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
c3278b7b	43	extern target_ulong gen_opc_jump_pc[2];
30d6cb84	44	extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
b346ff46	45
9886cc16 FB	46	typedef void (GenOpFunc)(void);
	47	typedef void (GenOpFunc1)(long);
	48	typedef void (GenOpFunc2)(long, long);
	49	typedef void (GenOpFunc3)(long, long, long);
3b46e624	50
b346ff46 FB	51	#if defined(TARGET_I386)
b346ff46 FB	52
33417e70	53	void optimize_flags_init(void);
d4e8164f	54
b346ff46 FB	55	#endif
	56
	57	extern FILE *logfile;
	58	extern int loglevel;
	59
4c3a88a2 FB	60	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	61	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
d07bde88	62	unsigned long code_gen_max_block_size(void);
57fec1fe	63	void cpu_gen_init(void);
4c3a88a2	64	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
d07bde88	65	int *gen_code_size_ptr);
5fafdf24	66	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	67	CPUState *env, unsigned long searched_pc,
	68	void *puc);
	69	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	70	int max_code_size, int *gen_code_size_ptr);
5fafdf24	71	int cpu_restore_state_copy(struct TranslationBlock *tb,
58fe2f10 FB	72	CPUState *env, unsigned long searched_pc,
58fe2f10 FB	73	void *puc);
2e12669a	74	void cpu_resume_from_signal(CPUState env1, void puc);
6a00d601	75	void cpu_exec_init(CPUState *env);
53a5960a	76	int page_unprotect(target_ulong address, unsigned long pc, void *puc);
5fafdf24	77	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
2e12669a	78	int is_cpu_write_access);
4390df51	79	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	80	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	81	void tlb_flush(CPUState *env, int flush_global);
5fafdf24 TS	82	int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
5fafdf24 TS	83	target_phys_addr_t paddr, int prot,
6ebbf390	84	int mmu_idx, int is_softmmu);
5fafdf24 TS	85	static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
5fafdf24 TS	86	target_phys_addr_t paddr, int prot,
6ebbf390	87	int mmu_idx, int is_softmmu)
84b7b8e7 FB	88	{
	89	if (prot & PAGE_READ)
	90	prot \|= PAGE_EXEC;
6ebbf390	91	return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
84b7b8e7	92	}
d4e8164f	93
d4e8164f FB	94	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
d4e8164f FB	95
4390df51 FB	96	#define CODE_GEN_PHYS_HASH_BITS 15
	97	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	98
d4e8164f	99	/* maximum total translate dcode allocated */
4390df51 FB	100
4390df51 FB	101	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	102	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	103	summary of the ranges:
	104
	105	i386 : signed 32 bits
	106	arm : signed 26 bits
	107	ppc : signed 24 bits
	108	sparc : signed 32 bits
	109	alpha : signed 23 bits
	110	*/
	111
	112	#if defined(__alpha__)
	113	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
b8076a74 FB	114	#elif defined(__ia64)
b8076a74 FB	115	#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
4390df51	116	#elif defined(__powerpc__)
c4c7e3e6	117	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51	118	#else
57fec1fe	119	/* XXX: make it dynamic on x86 */
c98baaac	120	#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
4390df51 FB	121	#endif
4390df51 FB	122
d4e8164f FB	123	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	124
4390df51 FB	125	/* estimated block size for TB allocation */
	126	/* XXX: use a per code average code fragment size and modulate it
	127	according to the host CPU */
	128	#if defined(CONFIG_SOFTMMU)
	129	#define CODE_GEN_AVG_BLOCK_SIZE 128
	130	#else
	131	#define CODE_GEN_AVG_BLOCK_SIZE 64
	132	#endif
	133
	134	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	135
57fec1fe	136	#if defined(__powerpc__) \|\| defined(__x86_64__)
4390df51 FB	137	#define USE_DIRECT_JUMP
4390df51 FB	138	#endif
67b915a5	139	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	140	#define USE_DIRECT_JUMP
	141	#endif
	142
	143	typedef struct TranslationBlock {
2e12669a FB	144	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	145	target_ulong cs_base; /* CS base for this block */
c068688b	146	uint64_t flags; /* flags defining in which context the code was generated */
d4e8164f FB	147	uint16_t size; /* size of target code for this block (1 <=
d4e8164f FB	148	size <= TARGET_PAGE_SIZE) */
58fe2f10	149	uint16_t cflags; /* compile flags */
bf088061 FB	150	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	151	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
	152	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	153	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	154
d4e8164f	155	uint8_t tc_ptr; / pointer to the translated code */
4390df51	156	/* next matching tb for physical address. */
5fafdf24	157	struct TranslationBlock *phys_hash_next;
4390df51 FB	158	/* first and second physical page containing code. The lower bit
4390df51 FB	159	of the pointer tells the index in page_next[] */
5fafdf24 TS	160	struct TranslationBlock *page_next[2];
5fafdf24 TS	161	target_ulong page_addr[2];
4390df51	162
d4e8164f FB	163	/* the following data are used to directly call another TB from
	164	the code of this one. */
	165	uint16_t tb_next_offset[2]; /* offset of original jump target */
	166	#ifdef USE_DIRECT_JUMP
4cbb86e1	167	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	168	#else
57fec1fe	169	unsigned long tb_next[2]; /* address of jump generated code */
d4e8164f FB	170	#endif
	171	/* list of TBs jumping to this one. This is a circular list using
	172	the two least significant bits of the pointers to tell what is
	173	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	174	jmp_first */
5fafdf24	175	struct TranslationBlock *jmp_next[2];
d4e8164f FB	176	struct TranslationBlock *jmp_first;
	177	} TranslationBlock;
	178
b362e5e0 PB	179	static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
	180	{
	181	target_ulong tmp;
	182	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	183	return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
	184	}
	185
8a40a180	186	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
d4e8164f	187	{
b362e5e0 PB	188	target_ulong tmp;
	189	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	190	return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) \|
	191	(tmp & TB_JMP_ADDR_MASK));
d4e8164f FB	192	}
d4e8164f FB	193
4390df51 FB	194	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	195	{
	196	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	197	}
	198
c27004ec	199	TranslationBlock *tb_alloc(target_ulong pc);
0124311e	200	void tb_flush(CPUState *env);
5fafdf24	201	void tb_link_phys(TranslationBlock *tb,
4390df51	202	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f	203
4390df51	204	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	205
	206	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	207	extern uint8_t *code_gen_ptr;
	208
4390df51 FB	209	#if defined(USE_DIRECT_JUMP)
	210
	211	#if defined(__powerpc__)
4cbb86e1	212	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	213	{
d4e8164f FB	214	uint32_t val, *ptr;
d4e8164f FB	215
d4e8164f FB	216	/* patch the branch destination */
4cbb86e1	217	ptr = (uint32_t *)jmp_addr;
d4e8164f	218	val = *ptr;
4cbb86e1	219	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	220	*ptr = val;
	221	/* flush icache */
	222	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	223	asm volatile ("sync" : : : "memory");
	224	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	225	asm volatile ("sync" : : : "memory");
	226	asm volatile ("isync" : : : "memory");
	227	}
57fec1fe	228	#elif defined(__i386__) \|\| defined(__x86_64__)
4390df51 FB	229	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	230	{
	231	/* patch the branch destination */
	232	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	233	/* no need to flush icache explicitely */
	234	}
	235	#endif
d4e8164f	236
5fafdf24	237	static inline void tb_set_jmp_target(TranslationBlock *tb,
4cbb86e1 FB	238	int n, unsigned long addr)
	239	{
	240	unsigned long offset;
	241
	242	offset = tb->tb_jmp_offset[n];
	243	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	244	offset = tb->tb_jmp_offset[n + 2];
	245	if (offset != 0xffff)
	246	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	247	}
	248
d4e8164f FB	249	#else
	250
	251	/* set the jump target */
5fafdf24	252	static inline void tb_set_jmp_target(TranslationBlock *tb,
d4e8164f FB	253	int n, unsigned long addr)
d4e8164f FB	254	{
95f7652d	255	tb->tb_next[n] = addr;
d4e8164f FB	256	}
	257
	258	#endif
	259
5fafdf24	260	static inline void tb_add_jump(TranslationBlock *tb, int n,
d4e8164f FB	261	TranslationBlock *tb_next)
d4e8164f FB	262	{
cf25629d FB	263	/* NOTE: this test is only needed for thread safety */
	264	if (!tb->jmp_next[n]) {
	265	/* patch the native jump address */
	266	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
3b46e624	267
cf25629d FB	268	/* add in TB jmp circular list */
	269	tb->jmp_next[n] = tb_next->jmp_first;
	270	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	271	}
d4e8164f FB	272	}
d4e8164f FB	273
a513fe19 FB	274	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	275
d4e8164f FB	276	#ifndef offsetof
	277	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	278	#endif
	279
d549f7d9 FB	280	#if defined(_WIN32)
	281	#define ASM_DATA_SECTION ".section \".data\"\n"
	282	#define ASM_PREVIOUS_SECTION ".section .text\n"
	283	#elif defined(__APPLE__)
	284	#define ASM_DATA_SECTION ".data\n"
	285	#define ASM_PREVIOUS_SECTION ".text\n"
d549f7d9 FB	286	#else
	287	#define ASM_DATA_SECTION ".section \".data\"\n"
	288	#define ASM_PREVIOUS_SECTION ".previous\n"
d549f7d9 FB	289	#endif
d549f7d9 FB	290
75913b72 FB	291	#define ASM_OP_LABEL_NAME(n, opname) \
	292	ASM_NAME(__op_label) #n "." ASM_NAME(opname)
	293
33417e70 FB	294	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	295	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	296	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	297
204a1b8d	298	#if defined(__powerpc__)
d4e8164f FB	299	static inline int testandset (int *p)
	300	{
	301	int ret;
	302	__asm__ __volatile__ (
02e1ec9b FB	303	"0: lwarx %0,0,%1\n"
	304	" xor. %0,%3,%0\n"
	305	" bne 1f\n"
	306	" stwcx. %2,0,%1\n"
	307	" bne- 0b\n"
d4e8164f FB	308	"1: "
	309	: "=&r" (ret)
	310	: "r" (p), "r" (1), "r" (0)
	311	: "cr0", "memory");
	312	return ret;
	313	}
204a1b8d	314	#elif defined(__i386__)
d4e8164f FB	315	static inline int testandset (int *p)
d4e8164f FB	316	{
4955a2cd	317	long int readval = 0;
3b46e624	318
4955a2cd FB	319	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	320	: "+m" (*p), "+a" (readval)
	321	: "r" (1)
	322	: "cc");
	323	return readval;
d4e8164f	324	}
204a1b8d	325	#elif defined(__x86_64__)
bc51c5c9 FB	326	static inline int testandset (int *p)
bc51c5c9 FB	327	{
4955a2cd	328	long int readval = 0;
3b46e624	329
4955a2cd FB	330	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	331	: "+m" (*p), "+a" (readval)
	332	: "r" (1)
	333	: "cc");
	334	return readval;
bc51c5c9	335	}
204a1b8d	336	#elif defined(__s390__)
d4e8164f FB	337	static inline int testandset (int *p)
	338	{
	339	int ret;
	340
	341	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	342	" jl 0b"
	343	: "=&d" (ret)
5fafdf24	344	: "r" (1), "a" (p), "0" (*p)
d4e8164f FB	345	: "cc", "memory" );
	346	return ret;
	347	}
204a1b8d	348	#elif defined(__alpha__)
2f87c607	349	static inline int testandset (int *p)
d4e8164f FB	350	{
	351	int ret;
	352	unsigned long one;
	353
	354	__asm__ __volatile__ ("0: mov 1,%2\n"
	355	" ldl_l %0,%1\n"
	356	" stl_c %2,%1\n"
	357	" beq %2,1f\n"
	358	".subsection 2\n"
	359	"1: br 0b\n"
	360	".previous"
	361	: "=r" (ret), "=m" (*p), "=r" (one)
	362	: "m" (*p));
	363	return ret;
	364	}
204a1b8d	365	#elif defined(__sparc__)
d4e8164f FB	366	static inline int testandset (int *p)
	367	{
	368	int ret;
	369
	370	__asm__ __volatile__("ldstub [%1], %0"
	371	: "=r" (ret)
	372	: "r" (p)
	373	: "memory");
	374
	375	return (ret ? 1 : 0);
	376	}
204a1b8d	377	#elif defined(__arm__)
a95c6790 FB	378	static inline int testandset (int *spinlock)
	379	{
	380	register unsigned int ret;
	381	__asm__ __volatile__("swp %0, %1, [%2]"
	382	: "=r"(ret)
	383	: "0"(1), "r"(spinlock));
3b46e624	384
a95c6790 FB	385	return ret;
a95c6790 FB	386	}
204a1b8d	387	#elif defined(__mc68000)
38e584a0 FB	388	static inline int testandset (int *p)
	389	{
	390	char ret;
	391	__asm__ __volatile__("tas %1; sne %0"
	392	: "=r" (ret)
	393	: "m" (p)
	394	: "cc","memory");
4955a2cd	395	return ret;
38e584a0	396	}
204a1b8d	397	#elif defined(__ia64)
38e584a0	398
b8076a74 FB	399	#include <ia64intrin.h>
	400
	401	static inline int testandset (int *p)
	402	{
	403	return __sync_lock_test_and_set (p, 1);
	404	}
204a1b8d	405	#elif defined(__mips__)
c4b89d18 TS	406	static inline int testandset (int *p)
	407	{
	408	int ret;
	409
	410	__asm__ __volatile__ (
	411	" .set push \n"
	412	" .set noat \n"
	413	" .set mips2 \n"
	414	"1: li $1, 1 \n"
	415	" ll %0, %1 \n"
	416	" sc $1, %1 \n"
976a0d0d	417	" beqz $1, 1b \n"
c4b89d18 TS	418	" .set pop "
	419	: "=r" (ret), "+R" (*p)
	420	:
	421	: "memory");
	422
	423	return ret;
	424	}
204a1b8d TS	425	#else
204a1b8d TS	426	#error unimplemented CPU support
c4b89d18 TS	427	#endif
c4b89d18 TS	428
d4e8164f FB	429	typedef int spinlock_t;
	430
	431	#define SPIN_LOCK_UNLOCKED 0
	432
aebcb60e	433	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	434	static inline void spin_lock(spinlock_t *lock)
	435	{
	436	while (testandset(lock));
	437	}
	438
	439	static inline void spin_unlock(spinlock_t *lock)
	440	{
	441	*lock = 0;
	442	}
	443
	444	static inline int spin_trylock(spinlock_t *lock)
	445	{
	446	return !testandset(lock);
	447	}
3c1cf9fa FB	448	#else
	449	static inline void spin_lock(spinlock_t *lock)
	450	{
	451	}
	452
	453	static inline void spin_unlock(spinlock_t *lock)
	454	{
	455	}
	456
	457	static inline int spin_trylock(spinlock_t *lock)
	458	{
	459	return 1;
	460	}
	461	#endif
d4e8164f FB	462
	463	extern spinlock_t tb_lock;
	464
36bdbe54	465	extern int tb_invalidated_flag;
6e59c1db	466
e95c8d51	467	#if !defined(CONFIG_USER_ONLY)
6e59c1db	468
6ebbf390	469	void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
6e59c1db FB	470	void *retaddr);
6e59c1db FB	471
6ebbf390	472	#define ACCESS_TYPE (NB_MMU_MODES + 1)
6e59c1db FB	473	#define MEMSUFFIX _code
	474	#define env cpu_single_env
	475
	476	#define DATA_SIZE 1
	477	#include "softmmu_header.h"
	478
	479	#define DATA_SIZE 2
	480	#include "softmmu_header.h"
	481
	482	#define DATA_SIZE 4
	483	#include "softmmu_header.h"
	484
c27004ec FB	485	#define DATA_SIZE 8
	486	#include "softmmu_header.h"
	487
6e59c1db FB	488	#undef ACCESS_TYPE
	489	#undef MEMSUFFIX
	490	#undef env
	491
	492	#endif
4390df51 FB	493
	494	#if defined(CONFIG_USER_ONLY)
	495	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	496	{
	497	return addr;
	498	}
	499	#else
	500	/* NOTE: this function can trigger an exception */
1ccde1cb FB	501	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	502	is the offset relative to phys_ram_base */
4390df51 FB	503	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
4390df51 FB	504	{
6ebbf390	505	int mmu_idx, index, pd;
4390df51 FB	506
4390df51 FB	507	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390 JM	508	mmu_idx = cpu_mmu_index(env);
6ebbf390 JM	509	if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
4390df51	510	(addr & TARGET_PAGE_MASK), 0)) {
c27004ec FB	511	ldub_code(addr);
c27004ec FB	512	}
6ebbf390	513	pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
2a4188a3	514	if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
647de6ca	515	#if defined(TARGET_SPARC) \|\| defined(TARGET_MIPS)
6c36d3fa BS	516	do_unassigned_access(addr, 0, 1, 0);
6c36d3fa BS	517	#else
36d23958	518	cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
6c36d3fa	519	#endif
4390df51	520	}
6ebbf390	521	return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
4390df51 FB	522	}
4390df51 FB	523	#endif
9df217a3	524
9df217a3	525	#ifdef USE_KQEMU
f32fc648 FB	526	#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG \| CODE_DIRTY_FLAG))
f32fc648 FB	527
9df217a3 FB	528	int kqemu_init(CPUState *env);
	529	int kqemu_cpu_exec(CPUState *env);
	530	void kqemu_flush_page(CPUState *env, target_ulong addr);
	531	void kqemu_flush(CPUState *env, int global);
4b7df22f	532	void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
f32fc648	533	void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
a332e112	534	void kqemu_cpu_interrupt(CPUState *env);
f32fc648	535	void kqemu_record_dump(void);
9df217a3 FB	536
	537	static inline int kqemu_is_ok(CPUState *env)
	538	{
	539	return(env->kqemu_enabled &&
5fafdf24	540	(env->cr[0] & CR0_PE_MASK) &&
f32fc648	541	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
9df217a3	542	(env->eflags & IF_MASK) &&
f32fc648	543	!(env->eflags & VM_MASK) &&
5fafdf24	544	(env->kqemu_enabled == 2 \|\|
f32fc648 FB	545	((env->hflags & HF_CPL_MASK) == 3 &&
f32fc648 FB	546	(env->eflags & IOPL_MASK) != IOPL_MASK)));
9df217a3 FB	547	}
	548
	549	#endif