[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

#ifndef glue
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s)	tostring(s)
#define tostring(s)	#s
#endif

#if __GNUC__ < 3
#define __builtin_expect(x, n) (x)
#endif

#ifdef __i386__
#define REGPARM(n) __attribute((regparm(n)))
#else
#define REGPARM(n)
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern long gen_labels[OPC_BUF_SIZE];
extern int nb_gen_labels;
extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern target_ulong gen_opc_jump_pc[2];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);
                    
#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb, 
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb, 
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(void);
int page_unprotect(unsigned long address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page(CPUState *env, target_ulong vaddr, 
                 target_phys_addr_t paddr, int prot, 
                 int is_user, int is_softmmu);

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__ia64)
#define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)	/* range of addl */
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
#define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__) 
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next; 
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2]; 
    target_ulong page_addr[2]; 

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2]; 
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
    return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(target_ulong pc);
void tb_flush(CPUState *env);
void tb_link_phys(TranslationBlock *tb, 
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n, 
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
        
        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#endif

#define ASM_OP_LABEL_NAME(n, opname) \
    ASM_NAME(__op_label) #n "." ASM_NAME(opname)

#if defined(__powerpc__)

/* we patch the jump instruction directly */
#define GOTO_TB(opname, tbparam, n)\
do {\
    asm volatile (ASM_DATA_SECTION\
		  ASM_OP_LABEL_NAME(n, opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "b " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
} while (0)

#elif defined(__i386__) && defined(USE_DIRECT_JUMP)

/* we patch the jump instruction directly */
#define GOTO_TB(opname, tbparam, n)\
do {\
    asm volatile (".section .data\n"\
		  ASM_OP_LABEL_NAME(n, opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "jmp " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define GOTO_TB(opname, tbparam, n)\
do {\
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
    static void __attribute__((unused)) *__op_label ## n \
        __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n: ;\
dummy_label ## n: ;\
} while (0)

#endif

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1\n"
                          "      xor. %0,%3,%0\n"
                          "      bne 1f\n"
                          "      stwcx. %2,0,%1\n"
                          "      bne- 0b\n"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    long int readval = 0;
    
    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#endif

#ifdef __x86_64__
static inline int testandset (int *p)
{
    long int readval = 0;
    
    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

#ifdef __arm__
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));
    
    return ret;
}
#endif

#ifdef __mc68000
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret;
}
#endif

#ifdef __ia64
#include <ia64intrin.h>

static inline int testandset (int *p)
{
    return __sync_lock_test_and_set (p, 1);
}
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(target_ulong addr, int is_write, int is_user, 
              void *retaddr);

#define ACCESS_TYPE 3
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int is_user, index, pd;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
#if defined(TARGET_I386)
    is_user = ((env->hflags & HF_CPL_MASK) == 3);
#elif defined (TARGET_PPC)
    is_user = msr_pr;
#elif defined (TARGET_MIPS)
    is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
#elif defined (TARGET_SPARC)
    is_user = (env->psrs == 0);
#else
#error "Unimplemented !"
#endif
    if (__builtin_expect(env->tlb_read[is_user][index].address != 
                         (addr & TARGET_PAGE_MASK), 0)) {
        ldub_code(addr);
    }
    pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM) {
        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
    }
    return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
}
#endif


#ifdef USE_KQEMU
int kqemu_init(CPUState *env);
int kqemu_cpu_exec(CPUState *env);
void kqemu_flush_page(CPUState *env, target_ulong addr);
void kqemu_flush(CPUState *env, int global);
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
void kqemu_cpu_interrupt(CPUState *env);

static inline int kqemu_is_ok(CPUState *env)
{
    return(env->kqemu_enabled &&
           (env->hflags & HF_CPL_MASK) == 3 &&
           (env->eflags & IOPL_MASK) != IOPL_MASK &&
           (env->cr[0] & CR0_PE_MASK) && 
           (env->eflags & IF_MASK) &&
           !(env->eflags & VM_MASK));
}

#endif
Commit	Line	Data
d4e8164f FB	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
33417e70 FB	24	#ifndef glue
	25	#define xglue(x, y) x ## y
	26	#define glue(x, y) xglue(x, y)
	27	#define stringify(s) tostring(s)
	28	#define tostring(s) #s
	29	#endif
	30
c98baaac	31	#if __GNUC__ < 3
33417e70 FB	32	#define __builtin_expect(x, n) (x)
	33	#endif
	34
e2222c39 FB	35	#ifdef __i386__
	36	#define REGPARM(n) __attribute((regparm(n)))
	37	#else
	38	#define REGPARM(n)
	39	#endif
	40
b346ff46 FB	41	/* is_jmp field values */
	42	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	43	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	44	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	45	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	46
	47	struct TranslationBlock;
	48
	49	/* XXX: make safe guess about sizes */
	50	#define MAX_OP_PER_INSTR 32
	51	#define OPC_BUF_SIZE 512
	52	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	53
	54	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	55
	56	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	57	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
c27004ec FB	58	extern long gen_labels[OPC_BUF_SIZE];
	59	extern int nb_gen_labels;
	60	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
	61	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
66e85a21	62	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46	63	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
c3278b7b	64	extern target_ulong gen_opc_jump_pc[2];
b346ff46	65
9886cc16 FB	66	typedef void (GenOpFunc)(void);
	67	typedef void (GenOpFunc1)(long);
	68	typedef void (GenOpFunc2)(long, long);
	69	typedef void (GenOpFunc3)(long, long, long);
	70
b346ff46 FB	71	#if defined(TARGET_I386)
b346ff46 FB	72
33417e70	73	void optimize_flags_init(void);
d4e8164f	74
b346ff46 FB	75	#endif
	76
	77	extern FILE *logfile;
	78	extern int loglevel;
	79
4c3a88a2 FB	80	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	81	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
b346ff46	82	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
4c3a88a2	83	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
b346ff46	84	int max_code_size, int *gen_code_size_ptr);
66e85a21	85	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	86	CPUState *env, unsigned long searched_pc,
	87	void *puc);
	88	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	89	int max_code_size, int *gen_code_size_ptr);
	90	int cpu_restore_state_copy(struct TranslationBlock *tb,
	91	CPUState *env, unsigned long searched_pc,
	92	void *puc);
2e12669a	93	void cpu_resume_from_signal(CPUState env1, void puc);
b346ff46	94	void cpu_exec_init(void);
2e12669a FB	95	int page_unprotect(unsigned long address, unsigned long pc, void *puc);
	96	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
	97	int is_cpu_write_access);
4390df51	98	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	99	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	100	void tlb_flush(CPUState *env, int flush_global);
2e12669a FB	101	int tlb_set_page(CPUState *env, target_ulong vaddr,
2e12669a FB	102	target_phys_addr_t paddr, int prot,
4390df51	103	int is_user, int is_softmmu);
d4e8164f FB	104
	105	#define CODE_GEN_MAX_SIZE 65536
	106	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	107
4390df51 FB	108	#define CODE_GEN_PHYS_HASH_BITS 15
	109	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	110
d4e8164f	111	/* maximum total translate dcode allocated */
4390df51 FB	112
4390df51 FB	113	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	114	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	115	summary of the ranges:
	116
	117	i386 : signed 32 bits
	118	arm : signed 26 bits
	119	ppc : signed 24 bits
	120	sparc : signed 32 bits
	121	alpha : signed 23 bits
	122	*/
	123
	124	#if defined(__alpha__)
	125	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
b8076a74 FB	126	#elif defined(__ia64)
b8076a74 FB	127	#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
4390df51	128	#elif defined(__powerpc__)
c4c7e3e6	129	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51	130	#else
c98baaac	131	#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
4390df51 FB	132	#endif
4390df51 FB	133
d4e8164f FB	134	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	135
4390df51 FB	136	/* estimated block size for TB allocation */
	137	/* XXX: use a per code average code fragment size and modulate it
	138	according to the host CPU */
	139	#if defined(CONFIG_SOFTMMU)
	140	#define CODE_GEN_AVG_BLOCK_SIZE 128
	141	#else
	142	#define CODE_GEN_AVG_BLOCK_SIZE 64
	143	#endif
	144
	145	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	146
	147	#if defined(__powerpc__)
	148	#define USE_DIRECT_JUMP
	149	#endif
67b915a5	150	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	151	#define USE_DIRECT_JUMP
	152	#endif
	153
	154	typedef struct TranslationBlock {
2e12669a FB	155	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	156	target_ulong cs_base; /* CS base for this block */
d4e8164f FB	157	unsigned int flags; /* flags defining in which context the code was generated */
	158	uint16_t size; /* size of target code for this block (1 <=
	159	size <= TARGET_PAGE_SIZE) */
58fe2f10	160	uint16_t cflags; /* compile flags */
bf088061 FB	161	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	162	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
	163	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	164	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	165
d4e8164f	166	uint8_t tc_ptr; / pointer to the translated code */
4390df51 FB	167	/* next matching tb for physical address. */
	168	struct TranslationBlock *phys_hash_next;
	169	/* first and second physical page containing code. The lower bit
	170	of the pointer tells the index in page_next[] */
	171	struct TranslationBlock *page_next[2];
	172	target_ulong page_addr[2];
	173
d4e8164f FB	174	/* the following data are used to directly call another TB from
	175	the code of this one. */
	176	uint16_t tb_next_offset[2]; /* offset of original jump target */
	177	#ifdef USE_DIRECT_JUMP
4cbb86e1	178	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	179	#else
95f7652d	180	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	181	#endif
	182	/* list of TBs jumping to this one. This is a circular list using
	183	the two least significant bits of the pointers to tell what is
	184	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	185	jmp_first */
	186	struct TranslationBlock *jmp_next[2];
	187	struct TranslationBlock *jmp_first;
	188	} TranslationBlock;
	189
8a40a180	190	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
d4e8164f	191	{
8a40a180	192	return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
d4e8164f FB	193	}
d4e8164f FB	194
4390df51 FB	195	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	196	{
	197	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	198	}
	199
c27004ec	200	TranslationBlock *tb_alloc(target_ulong pc);
0124311e	201	void tb_flush(CPUState *env);
4390df51 FB	202	void tb_link_phys(TranslationBlock *tb,
4390df51 FB	203	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f	204
4390df51	205	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	206
	207	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	208	extern uint8_t *code_gen_ptr;
	209
4390df51 FB	210	#if defined(USE_DIRECT_JUMP)
	211
	212	#if defined(__powerpc__)
4cbb86e1	213	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	214	{
d4e8164f FB	215	uint32_t val, *ptr;
d4e8164f FB	216
d4e8164f FB	217	/* patch the branch destination */
4cbb86e1	218	ptr = (uint32_t *)jmp_addr;
d4e8164f	219	val = *ptr;
4cbb86e1	220	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	221	*ptr = val;
	222	/* flush icache */
	223	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	224	asm volatile ("sync" : : : "memory");
	225	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	226	asm volatile ("sync" : : : "memory");
	227	asm volatile ("isync" : : : "memory");
	228	}
4390df51 FB	229	#elif defined(__i386__)
	230	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	231	{
	232	/* patch the branch destination */
	233	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	234	/* no need to flush icache explicitely */
	235	}
	236	#endif
d4e8164f	237
4cbb86e1 FB	238	static inline void tb_set_jmp_target(TranslationBlock *tb,
	239	int n, unsigned long addr)
	240	{
	241	unsigned long offset;
	242
	243	offset = tb->tb_jmp_offset[n];
	244	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	245	offset = tb->tb_jmp_offset[n + 2];
	246	if (offset != 0xffff)
	247	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	248	}
	249
d4e8164f FB	250	#else
	251
	252	/* set the jump target */
	253	static inline void tb_set_jmp_target(TranslationBlock *tb,
	254	int n, unsigned long addr)
	255	{
95f7652d	256	tb->tb_next[n] = addr;
d4e8164f FB	257	}
	258
	259	#endif
	260
	261	static inline void tb_add_jump(TranslationBlock *tb, int n,
	262	TranslationBlock *tb_next)
	263	{
cf25629d FB	264	/* NOTE: this test is only needed for thread safety */
	265	if (!tb->jmp_next[n]) {
	266	/* patch the native jump address */
	267	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	268
	269	/* add in TB jmp circular list */
	270	tb->jmp_next[n] = tb_next->jmp_first;
	271	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	272	}
d4e8164f FB	273	}
d4e8164f FB	274
a513fe19 FB	275	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	276
d4e8164f FB	277	#ifndef offsetof
	278	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	279	#endif
	280
d549f7d9 FB	281	#if defined(_WIN32)
	282	#define ASM_DATA_SECTION ".section \".data\"\n"
	283	#define ASM_PREVIOUS_SECTION ".section .text\n"
	284	#elif defined(__APPLE__)
	285	#define ASM_DATA_SECTION ".data\n"
	286	#define ASM_PREVIOUS_SECTION ".text\n"
d549f7d9 FB	287	#else
	288	#define ASM_DATA_SECTION ".section \".data\"\n"
	289	#define ASM_PREVIOUS_SECTION ".previous\n"
d549f7d9 FB	290	#endif
d549f7d9 FB	291
75913b72 FB	292	#define ASM_OP_LABEL_NAME(n, opname) \
	293	ASM_NAME(__op_label) #n "." ASM_NAME(opname)
	294
b346ff46 FB	295	#if defined(__powerpc__)
b346ff46 FB	296
4390df51	297	/* we patch the jump instruction directly */
ae063a68	298	#define GOTO_TB(opname, tbparam, n)\
b346ff46	299	do {\
d549f7d9	300	asm volatile (ASM_DATA_SECTION\
75913b72	301	ASM_OP_LABEL_NAME(n, opname) ":\n"\
9257a9e4	302	".long 1f\n"\
d549f7d9 FB	303	ASM_PREVIOUS_SECTION \
d549f7d9 FB	304	"b " ASM_NAME(__op_jmp) #n "\n"\
9257a9e4	305	"1:\n");\
4390df51 FB	306	} while (0)
	307
	308	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
	309
	310	/* we patch the jump instruction directly */
ae063a68	311	#define GOTO_TB(opname, tbparam, n)\
c27004ec FB	312	do {\
c27004ec FB	313	asm volatile (".section .data\n"\
75913b72	314	ASM_OP_LABEL_NAME(n, opname) ":\n"\
c27004ec FB	315	".long 1f\n"\
	316	ASM_PREVIOUS_SECTION \
	317	"jmp " ASM_NAME(__op_jmp) #n "\n"\
	318	"1:\n");\
	319	} while (0)
	320
b346ff46 FB	321	#else
	322
	323	/* jump to next block operations (more portable code, does not need
	324	cache flushing, but slower because of indirect jump) */
ae063a68	325	#define GOTO_TB(opname, tbparam, n)\
b346ff46	326	do {\
2f62b397	327	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
75913b72 FB	328	static void __attribute__((unused)) *__op_label ## n \
75913b72 FB	329	__asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
b346ff46	330	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
ae063a68 FB	331	label ## n: ;\
ae063a68 FB	332	dummy_label ## n: ;\
b346ff46 FB	333	} while (0)
b346ff46 FB	334
ae063a68 FB	335	#endif
ae063a68 FB	336
33417e70 FB	337	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	338	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	339	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	340
d4e8164f FB	341	#ifdef __powerpc__
	342	static inline int testandset (int *p)
	343	{
	344	int ret;
	345	__asm__ __volatile__ (
02e1ec9b FB	346	"0: lwarx %0,0,%1\n"
	347	" xor. %0,%3,%0\n"
	348	" bne 1f\n"
	349	" stwcx. %2,0,%1\n"
	350	" bne- 0b\n"
d4e8164f FB	351	"1: "
	352	: "=&r" (ret)
	353	: "r" (p), "r" (1), "r" (0)
	354	: "cr0", "memory");
	355	return ret;
	356	}
	357	#endif
	358
	359	#ifdef __i386__
	360	static inline int testandset (int *p)
	361	{
4955a2cd	362	long int readval = 0;
d4e8164f	363
4955a2cd FB	364	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	365	: "+m" (*p), "+a" (readval)
	366	: "r" (1)
	367	: "cc");
	368	return readval;
d4e8164f FB	369	}
	370	#endif
	371
bc51c5c9 FB	372	#ifdef __x86_64__
	373	static inline int testandset (int *p)
	374	{
4955a2cd	375	long int readval = 0;
bc51c5c9	376
4955a2cd FB	377	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	378	: "+m" (*p), "+a" (readval)
	379	: "r" (1)
	380	: "cc");
	381	return readval;
bc51c5c9 FB	382	}
	383	#endif
	384
d4e8164f FB	385	#ifdef __s390__
	386	static inline int testandset (int *p)
	387	{
	388	int ret;
	389
	390	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	391	" jl 0b"
	392	: "=&d" (ret)
	393	: "r" (1), "a" (p), "0" (*p)
	394	: "cc", "memory" );
	395	return ret;
	396	}
	397	#endif
	398
	399	#ifdef __alpha__
2f87c607	400	static inline int testandset (int *p)
d4e8164f FB	401	{
	402	int ret;
	403	unsigned long one;
	404
	405	__asm__ __volatile__ ("0: mov 1,%2\n"
	406	" ldl_l %0,%1\n"
	407	" stl_c %2,%1\n"
	408	" beq %2,1f\n"
	409	".subsection 2\n"
	410	"1: br 0b\n"
	411	".previous"
	412	: "=r" (ret), "=m" (*p), "=r" (one)
	413	: "m" (*p));
	414	return ret;
	415	}
	416	#endif
	417
	418	#ifdef __sparc__
	419	static inline int testandset (int *p)
	420	{
	421	int ret;
	422
	423	__asm__ __volatile__("ldstub [%1], %0"
	424	: "=r" (ret)
	425	: "r" (p)
	426	: "memory");
	427
	428	return (ret ? 1 : 0);
	429	}
	430	#endif
	431
a95c6790 FB	432	#ifdef __arm__
	433	static inline int testandset (int *spinlock)
	434	{
	435	register unsigned int ret;
	436	__asm__ __volatile__("swp %0, %1, [%2]"
	437	: "=r"(ret)
	438	: "0"(1), "r"(spinlock));
	439
	440	return ret;
	441	}
	442	#endif
	443
38e584a0 FB	444	#ifdef __mc68000
	445	static inline int testandset (int *p)
	446	{
	447	char ret;
	448	__asm__ __volatile__("tas %1; sne %0"
	449	: "=r" (ret)
	450	: "m" (p)
	451	: "cc","memory");
4955a2cd	452	return ret;
38e584a0 FB	453	}
	454	#endif
	455
b8076a74 FB	456	#ifdef __ia64
	457	#include <ia64intrin.h>
	458
	459	static inline int testandset (int *p)
	460	{
	461	return __sync_lock_test_and_set (p, 1);
	462	}
	463	#endif
	464
d4e8164f FB	465	typedef int spinlock_t;
	466
	467	#define SPIN_LOCK_UNLOCKED 0
	468
aebcb60e	469	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	470	static inline void spin_lock(spinlock_t *lock)
	471	{
	472	while (testandset(lock));
	473	}
	474
	475	static inline void spin_unlock(spinlock_t *lock)
	476	{
	477	*lock = 0;
	478	}
	479
	480	static inline int spin_trylock(spinlock_t *lock)
	481	{
	482	return !testandset(lock);
	483	}
3c1cf9fa FB	484	#else
	485	static inline void spin_lock(spinlock_t *lock)
	486	{
	487	}
	488
	489	static inline void spin_unlock(spinlock_t *lock)
	490	{
	491	}
	492
	493	static inline int spin_trylock(spinlock_t *lock)
	494	{
	495	return 1;
	496	}
	497	#endif
d4e8164f FB	498
	499	extern spinlock_t tb_lock;
	500
36bdbe54	501	extern int tb_invalidated_flag;
6e59c1db	502
e95c8d51	503	#if !defined(CONFIG_USER_ONLY)
6e59c1db	504
c27004ec	505	void tlb_fill(target_ulong addr, int is_write, int is_user,
6e59c1db FB	506	void *retaddr);
	507
	508	#define ACCESS_TYPE 3
	509	#define MEMSUFFIX _code
	510	#define env cpu_single_env
	511
	512	#define DATA_SIZE 1
	513	#include "softmmu_header.h"
	514
	515	#define DATA_SIZE 2
	516	#include "softmmu_header.h"
	517
	518	#define DATA_SIZE 4
	519	#include "softmmu_header.h"
	520
c27004ec FB	521	#define DATA_SIZE 8
	522	#include "softmmu_header.h"
	523
6e59c1db FB	524	#undef ACCESS_TYPE
	525	#undef MEMSUFFIX
	526	#undef env
	527
	528	#endif
4390df51 FB	529
	530	#if defined(CONFIG_USER_ONLY)
	531	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	532	{
	533	return addr;
	534	}
	535	#else
	536	/* NOTE: this function can trigger an exception */
1ccde1cb FB	537	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	538	is the offset relative to phys_ram_base */
4390df51 FB	539	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
4390df51 FB	540	{
c27004ec	541	int is_user, index, pd;
4390df51 FB	542
4390df51 FB	543	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
3f5dcc34	544	#if defined(TARGET_I386)
4390df51	545	is_user = ((env->hflags & HF_CPL_MASK) == 3);
3f5dcc34 FB	546	#elif defined (TARGET_PPC)
3f5dcc34 FB	547	is_user = msr_pr;
6af0bf9c FB	548	#elif defined (TARGET_MIPS)
6af0bf9c FB	549	is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
e95c8d51 FB	550	#elif defined (TARGET_SPARC)
e95c8d51 FB	551	is_user = (env->psrs == 0);
3f5dcc34 FB	552	#else
	553	#error "Unimplemented !"
	554	#endif
4390df51 FB	555	if (__builtin_expect(env->tlb_read[is_user][index].address !=
4390df51 FB	556	(addr & TARGET_PAGE_MASK), 0)) {
c27004ec FB	557	ldub_code(addr);
	558	}
	559	pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
	560	if (pd > IO_MEM_ROM) {
	561	cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
4390df51 FB	562	}
	563	return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
	564	}
	565	#endif
9df217a3 FB	566
	567
	568	#ifdef USE_KQEMU
9df217a3 FB	569	int kqemu_init(CPUState *env);
	570	int kqemu_cpu_exec(CPUState *env);
	571	void kqemu_flush_page(CPUState *env, target_ulong addr);
	572	void kqemu_flush(CPUState *env, int global);
4b7df22f	573	void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
a332e112	574	void kqemu_cpu_interrupt(CPUState *env);
9df217a3 FB	575
	576	static inline int kqemu_is_ok(CPUState *env)
	577	{
	578	return(env->kqemu_enabled &&
	579	(env->hflags & HF_CPL_MASK) == 3 &&
	580	(env->eflags & IOPL_MASK) != IOPL_MASK &&
	581	(env->cr[0] & CR0_PE_MASK) &&
	582	(env->eflags & IF_MASK) &&
de758150	583	!(env->eflags & VM_MASK));
9df217a3 FB	584	}
	585
	586	#endif