[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

#ifndef glue
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s)	tostring(s)
#define tostring(s)	#s
#endif

#if GCC_MAJOR < 3
#define __builtin_expect(x, n) (x)
#endif

#ifdef __i386__
#define REGPARM(n) __attribute((regparm(n)))
#else
#define REGPARM(n)
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);
                    
#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb, 
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb, 
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_exec_init(void);
int page_unprotect(unsigned long address);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, uint32_t addr);
void tlb_flush_page_write(CPUState *env, uint32_t addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot, 
                 int is_user, int is_softmmu);

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_HASH_BITS     15
#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
#define CODE_GEN_BUFFER_SIZE     (8 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__) 
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) 
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    unsigned long pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    unsigned long cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY  0x0001 /* block was generated in code copy mode */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    struct TranslationBlock *hash_next; /* next matching tb for virtual address */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next; 
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2]; 
    target_ulong page_addr[2]; 

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2]; 
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_HASH_SIZE - 1);
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(unsigned long pc);
void tb_flush(CPUState *env);
void tb_link(TranslationBlock *tb);
void tb_link_phys(TranslationBlock *tb, 
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

/* find a translation block in the translation cache. If not found,
   return NULL and the pointer to the last element of the list in pptb */
static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
                                        unsigned long pc, 
                                        unsigned long cs_base,
                                        unsigned int flags)
{
    TranslationBlock **ptb, *tb;
    unsigned int h;
 
    h = tb_hash_func(pc);
    ptb = &tb_hash[h];
    for(;;) {
        tb = *ptb;
        if (!tb)
            break;
        if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
            return tb;
        ptb = &tb->hash_next;
    }
    *pptb = ptb;
    return NULL;
}


#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n, 
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
        
        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(__powerpc__)

/* we patch the jump instruction directly */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    asm volatile (".section \".data\"\n"\
		  "__op_label" #n "." stringify(opname) ":\n"\
		  ".long 1f\n"\
		  ".previous\n"\
                  "b __op_jmp" #n "\n"\
		  "1:\n");\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
    EXIT_TB();\
} while (0)

#define JUMP_TB2(opname, tbparam, n)\
do {\
    asm volatile ("b __op_jmp" #n "\n");\
} while (0)

#elif defined(__i386__) && defined(USE_DIRECT_JUMP)

/* we patch the jump instruction directly */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    asm volatile (".section \".data\"\n"\
		  "__op_label" #n "." stringify(opname) ":\n"\
		  ".long 1f\n"\
		  ".previous\n"\
                  "jmp __op_jmp" #n "\n"\
		  "1:\n");\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
    EXIT_TB();\
} while (0)

#define JUMP_TB2(opname, tbparam, n)\
do {\
    asm volatile ("jmp __op_jmp" #n "\n");\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n:\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
dummy_label ## n:\
    EXIT_TB();\
} while (0)

/* second jump to same destination 'n' */
#define JUMP_TB2(opname, tbparam, n)\
do {\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
} while (0)

#endif

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1 ;"
                          "      xor. %0,%3,%0;"
                          "      bne 1f;"
                          "      stwcx. %2,0,%1;"
                          "      bne- 0b;"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    char ret;
    long int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

#ifdef __arm__
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));
    
    return ret;
}
#endif

#ifdef __mc68000
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret == 0;
}
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if (defined(TARGET_I386) || defined(TARGET_PPC)) && \
    !defined(CONFIG_USER_ONLY)

void tlb_fill(unsigned long addr, int is_write, int is_user, 
              void *retaddr);

#define ACCESS_TYPE 3
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
/* XXX: i386 target specific */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int is_user, index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
#if defined(TARGET_I386)
    is_user = ((env->hflags & HF_CPL_MASK) == 3);
#elif defined (TARGET_PPC)
    is_user = msr_pr;
#else
#error "Unimplemented !"
#endif
    if (__builtin_expect(env->tlb_read[is_user][index].address != 
                         (addr & TARGET_PAGE_MASK), 0)) {
        ldub_code((void *)addr);
    }
    return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
}
#endif
Commit	Line	Data
d4e8164f FB	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
33417e70 FB	24	#ifndef glue
	25	#define xglue(x, y) x ## y
	26	#define glue(x, y) xglue(x, y)
	27	#define stringify(s) tostring(s)
	28	#define tostring(s) #s
	29	#endif
	30
	31	#if GCC_MAJOR < 3
	32	#define __builtin_expect(x, n) (x)
	33	#endif
	34
e2222c39 FB	35	#ifdef __i386__
	36	#define REGPARM(n) __attribute((regparm(n)))
	37	#else
	38	#define REGPARM(n)
	39	#endif
	40
b346ff46 FB	41	/* is_jmp field values */
	42	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	43	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	44	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	45	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	46
	47	struct TranslationBlock;
	48
	49	/* XXX: make safe guess about sizes */
	50	#define MAX_OP_PER_INSTR 32
	51	#define OPC_BUF_SIZE 512
	52	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	53
	54	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	55
	56	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	57	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
	58	extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
66e85a21	59	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46 FB	60	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
b346ff46 FB	61
9886cc16 FB	62	typedef void (GenOpFunc)(void);
	63	typedef void (GenOpFunc1)(long);
	64	typedef void (GenOpFunc2)(long, long);
	65	typedef void (GenOpFunc3)(long, long, long);
	66
b346ff46 FB	67	#if defined(TARGET_I386)
b346ff46 FB	68
33417e70	69	void optimize_flags_init(void);
d4e8164f	70
b346ff46 FB	71	#endif
	72
	73	extern FILE *logfile;
	74	extern int loglevel;
	75
4c3a88a2 FB	76	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	77	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
b346ff46	78	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
4c3a88a2	79	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
b346ff46	80	int max_code_size, int *gen_code_size_ptr);
66e85a21	81	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	82	CPUState *env, unsigned long searched_pc,
	83	void *puc);
	84	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	85	int max_code_size, int *gen_code_size_ptr);
	86	int cpu_restore_state_copy(struct TranslationBlock *tb,
	87	CPUState *env, unsigned long searched_pc,
	88	void *puc);
b346ff46	89	void cpu_exec_init(void);
d4e8164f	90	int page_unprotect(unsigned long address);
4390df51	91	void tb_invalidate_page_range(target_ulong start, target_ulong end);
33417e70	92	void tlb_flush_page(CPUState *env, uint32_t addr);
6e59c1db	93	void tlb_flush_page_write(CPUState *env, uint32_t addr);
ee8b7021	94	void tlb_flush(CPUState *env, int flush_global);
4390df51 FB	95	int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
4390df51 FB	96	int is_user, int is_softmmu);
d4e8164f FB	97
	98	#define CODE_GEN_MAX_SIZE 65536
	99	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	100
	101	#define CODE_GEN_HASH_BITS 15
	102	#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
	103
4390df51 FB	104	#define CODE_GEN_PHYS_HASH_BITS 15
	105	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	106
d4e8164f	107	/* maximum total translate dcode allocated */
4390df51 FB	108
4390df51 FB	109	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	110	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	111	summary of the ranges:
	112
	113	i386 : signed 32 bits
	114	arm : signed 26 bits
	115	ppc : signed 24 bits
	116	sparc : signed 32 bits
	117	alpha : signed 23 bits
	118	*/
	119
	120	#if defined(__alpha__)
	121	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
	122	#elif defined(__powerpc__)
c4c7e3e6	123	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51 FB	124	#else
	125	#define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024)
	126	#endif
	127
d4e8164f FB	128	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	129
4390df51 FB	130	/* estimated block size for TB allocation */
	131	/* XXX: use a per code average code fragment size and modulate it
	132	according to the host CPU */
	133	#if defined(CONFIG_SOFTMMU)
	134	#define CODE_GEN_AVG_BLOCK_SIZE 128
	135	#else
	136	#define CODE_GEN_AVG_BLOCK_SIZE 64
	137	#endif
	138
	139	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	140
	141	#if defined(__powerpc__)
	142	#define USE_DIRECT_JUMP
	143	#endif
	144	#if defined(__i386__)
d4e8164f FB	145	#define USE_DIRECT_JUMP
	146	#endif
	147
	148	typedef struct TranslationBlock {
	149	unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
	150	unsigned long cs_base; /* CS base for this block */
	151	unsigned int flags; /* flags defining in which context the code was generated */
	152	uint16_t size; /* size of target code for this block (1 <=
	153	size <= TARGET_PAGE_SIZE) */
58fe2f10 FB	154	uint16_t cflags; /* compile flags */
	155	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	156
d4e8164f	157	uint8_t tc_ptr; / pointer to the translated code */
4390df51 FB	158	struct TranslationBlock hash_next; / next matching tb for virtual address */
	159	/* next matching tb for physical address. */
	160	struct TranslationBlock *phys_hash_next;
	161	/* first and second physical page containing code. The lower bit
	162	of the pointer tells the index in page_next[] */
	163	struct TranslationBlock *page_next[2];
	164	target_ulong page_addr[2];
	165
d4e8164f FB	166	/* the following data are used to directly call another TB from
	167	the code of this one. */
	168	uint16_t tb_next_offset[2]; /* offset of original jump target */
	169	#ifdef USE_DIRECT_JUMP
4cbb86e1	170	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	171	#else
95f7652d	172	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	173	#endif
	174	/* list of TBs jumping to this one. This is a circular list using
	175	the two least significant bits of the pointers to tell what is
	176	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	177	jmp_first */
	178	struct TranslationBlock *jmp_next[2];
	179	struct TranslationBlock *jmp_first;
	180	} TranslationBlock;
	181
	182	static inline unsigned int tb_hash_func(unsigned long pc)
	183	{
	184	return pc & (CODE_GEN_HASH_SIZE - 1);
	185	}
	186
4390df51 FB	187	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	188	{
	189	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	190	}
	191
d4e8164f	192	TranslationBlock *tb_alloc(unsigned long pc);
0124311e	193	void tb_flush(CPUState *env);
d4e8164f	194	void tb_link(TranslationBlock *tb);
4390df51 FB	195	void tb_link_phys(TranslationBlock *tb,
4390df51 FB	196	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f FB	197
d4e8164f FB	198	extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
4390df51	199	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	200
	201	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	202	extern uint8_t *code_gen_ptr;
	203
	204	/* find a translation block in the translation cache. If not found,
	205	return NULL and the pointer to the last element of the list in pptb */
	206	static inline TranslationBlock tb_find(TranslationBlock **pptb,
	207	unsigned long pc,
	208	unsigned long cs_base,
	209	unsigned int flags)
	210	{
	211	TranslationBlock *ptb, tb;
	212	unsigned int h;
	213
	214	h = tb_hash_func(pc);
	215	ptb = &tb_hash[h];
	216	for(;;) {
	217	tb = *ptb;
	218	if (!tb)
	219	break;
	220	if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
	221	return tb;
	222	ptb = &tb->hash_next;
	223	}
	224	*pptb = ptb;
	225	return NULL;
	226	}
	227
d4e8164f	228
4390df51 FB	229	#if defined(USE_DIRECT_JUMP)
	230
	231	#if defined(__powerpc__)
4cbb86e1	232	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	233	{
d4e8164f FB	234	uint32_t val, *ptr;
d4e8164f FB	235
d4e8164f FB	236	/* patch the branch destination */
4cbb86e1	237	ptr = (uint32_t *)jmp_addr;
d4e8164f	238	val = *ptr;
4cbb86e1	239	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	240	*ptr = val;
	241	/* flush icache */
	242	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	243	asm volatile ("sync" : : : "memory");
	244	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	245	asm volatile ("sync" : : : "memory");
	246	asm volatile ("isync" : : : "memory");
	247	}
4390df51 FB	248	#elif defined(__i386__)
	249	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	250	{
	251	/* patch the branch destination */
	252	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	253	/* no need to flush icache explicitely */
	254	}
	255	#endif
d4e8164f	256
4cbb86e1 FB	257	static inline void tb_set_jmp_target(TranslationBlock *tb,
	258	int n, unsigned long addr)
	259	{
	260	unsigned long offset;
	261
	262	offset = tb->tb_jmp_offset[n];
	263	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	264	offset = tb->tb_jmp_offset[n + 2];
	265	if (offset != 0xffff)
	266	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	267	}
	268
d4e8164f FB	269	#else
	270
	271	/* set the jump target */
	272	static inline void tb_set_jmp_target(TranslationBlock *tb,
	273	int n, unsigned long addr)
	274	{
95f7652d	275	tb->tb_next[n] = addr;
d4e8164f FB	276	}
	277
	278	#endif
	279
	280	static inline void tb_add_jump(TranslationBlock *tb, int n,
	281	TranslationBlock *tb_next)
	282	{
cf25629d FB	283	/* NOTE: this test is only needed for thread safety */
	284	if (!tb->jmp_next[n]) {
	285	/* patch the native jump address */
	286	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	287
	288	/* add in TB jmp circular list */
	289	tb->jmp_next[n] = tb_next->jmp_first;
	290	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	291	}
d4e8164f FB	292	}
d4e8164f FB	293
a513fe19 FB	294	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	295
d4e8164f FB	296	#ifndef offsetof
	297	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	298	#endif
	299
b346ff46 FB	300	#if defined(__powerpc__)
b346ff46 FB	301
4390df51	302	/* we patch the jump instruction directly */
9257a9e4	303	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46	304	do {\
9257a9e4 FB	305	asm volatile (".section \".data\"\n"\
	306	"__op_label" #n "." stringify(opname) ":\n"\
	307	".long 1f\n"\
	308	".previous\n"\
	309	"b __op_jmp" #n "\n"\
	310	"1:\n");\
b346ff46 FB	311	T0 = (long)(tbparam) + (n);\
b346ff46 FB	312	EIP = eip;\
31e8f3c8	313	EXIT_TB();\
b346ff46 FB	314	} while (0)
b346ff46 FB	315
4cbb86e1 FB	316	#define JUMP_TB2(opname, tbparam, n)\
4cbb86e1 FB	317	do {\
4390df51 FB	318	asm volatile ("b __op_jmp" #n "\n");\
	319	} while (0)
	320
	321	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
	322
	323	/* we patch the jump instruction directly */
	324	#define JUMP_TB(opname, tbparam, n, eip)\
	325	do {\
	326	asm volatile (".section \".data\"\n"\
	327	"__op_label" #n "." stringify(opname) ":\n"\
	328	".long 1f\n"\
	329	".previous\n"\
	330	"jmp __op_jmp" #n "\n"\
	331	"1:\n");\
	332	T0 = (long)(tbparam) + (n);\
	333	EIP = eip;\
	334	EXIT_TB();\
	335	} while (0)
	336
	337	#define JUMP_TB2(opname, tbparam, n)\
	338	do {\
	339	asm volatile ("jmp __op_jmp" #n "\n");\
4cbb86e1 FB	340	} while (0)
4cbb86e1 FB	341
b346ff46 FB	342	#else
	343
	344	/* jump to next block operations (more portable code, does not need
	345	cache flushing, but slower because of indirect jump) */
9257a9e4	346	#define JUMP_TB(opname, tbparam, n, eip)\
b346ff46 FB	347	do {\
b346ff46 FB	348	static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
2f62b397	349	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
b346ff46 FB	350	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
	351	label ## n:\
	352	T0 = (long)(tbparam) + (n);\
	353	EIP = eip;\
2f62b397	354	dummy_label ## n:\
9621339d	355	EXIT_TB();\
b346ff46 FB	356	} while (0)
b346ff46 FB	357
4cbb86e1 FB	358	/* second jump to same destination 'n' */
	359	#define JUMP_TB2(opname, tbparam, n)\
	360	do {\
4390df51	361	goto (void )(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
4cbb86e1 FB	362	} while (0)
4cbb86e1 FB	363
b346ff46 FB	364	#endif
b346ff46 FB	365
33417e70 FB	366	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
	367	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
	368
d4e8164f FB	369	#ifdef __powerpc__
	370	static inline int testandset (int *p)
	371	{
	372	int ret;
	373	__asm__ __volatile__ (
	374	"0: lwarx %0,0,%1 ;"
	375	" xor. %0,%3,%0;"
	376	" bne 1f;"
	377	" stwcx. %2,0,%1;"
	378	" bne- 0b;"
	379	"1: "
	380	: "=&r" (ret)
	381	: "r" (p), "r" (1), "r" (0)
	382	: "cr0", "memory");
	383	return ret;
	384	}
	385	#endif
	386
	387	#ifdef __i386__
	388	static inline int testandset (int *p)
	389	{
	390	char ret;
	391	long int readval;
	392
	393	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	394	: "=q" (ret), "=m" (*p), "=a" (readval)
	395	: "r" (1), "m" (*p), "a" (0)
	396	: "memory");
	397	return ret;
	398	}
	399	#endif
	400
	401	#ifdef __s390__
	402	static inline int testandset (int *p)
	403	{
	404	int ret;
	405
	406	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	407	" jl 0b"
	408	: "=&d" (ret)
	409	: "r" (1), "a" (p), "0" (*p)
	410	: "cc", "memory" );
	411	return ret;
	412	}
	413	#endif
	414
	415	#ifdef __alpha__
2f87c607	416	static inline int testandset (int *p)
d4e8164f FB	417	{
	418	int ret;
	419	unsigned long one;
	420
	421	__asm__ __volatile__ ("0: mov 1,%2\n"
	422	" ldl_l %0,%1\n"
	423	" stl_c %2,%1\n"
	424	" beq %2,1f\n"
	425	".subsection 2\n"
	426	"1: br 0b\n"
	427	".previous"
	428	: "=r" (ret), "=m" (*p), "=r" (one)
	429	: "m" (*p));
	430	return ret;
	431	}
	432	#endif
	433
	434	#ifdef __sparc__
	435	static inline int testandset (int *p)
	436	{
	437	int ret;
	438
	439	__asm__ __volatile__("ldstub [%1], %0"
	440	: "=r" (ret)
	441	: "r" (p)
	442	: "memory");
	443
	444	return (ret ? 1 : 0);
	445	}
	446	#endif
	447
a95c6790 FB	448	#ifdef __arm__
	449	static inline int testandset (int *spinlock)
	450	{
	451	register unsigned int ret;
	452	__asm__ __volatile__("swp %0, %1, [%2]"
	453	: "=r"(ret)
	454	: "0"(1), "r"(spinlock));
	455
	456	return ret;
	457	}
	458	#endif
	459
38e584a0 FB	460	#ifdef __mc68000
	461	static inline int testandset (int *p)
	462	{
	463	char ret;
	464	__asm__ __volatile__("tas %1; sne %0"
	465	: "=r" (ret)
	466	: "m" (p)
	467	: "cc","memory");
	468	return ret == 0;
	469	}
	470	#endif
	471
d4e8164f FB	472	typedef int spinlock_t;
	473
	474	#define SPIN_LOCK_UNLOCKED 0
	475
aebcb60e	476	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	477	static inline void spin_lock(spinlock_t *lock)
	478	{
	479	while (testandset(lock));
	480	}
	481
	482	static inline void spin_unlock(spinlock_t *lock)
	483	{
	484	*lock = 0;
	485	}
	486
	487	static inline int spin_trylock(spinlock_t *lock)
	488	{
	489	return !testandset(lock);
	490	}
3c1cf9fa FB	491	#else
	492	static inline void spin_lock(spinlock_t *lock)
	493	{
	494	}
	495
	496	static inline void spin_unlock(spinlock_t *lock)
	497	{
	498	}
	499
	500	static inline int spin_trylock(spinlock_t *lock)
	501	{
	502	return 1;
	503	}
	504	#endif
d4e8164f FB	505
	506	extern spinlock_t tb_lock;
	507
36bdbe54	508	extern int tb_invalidated_flag;
6e59c1db	509
9886cc16 FB	510	#if (defined(TARGET_I386) \|\| defined(TARGET_PPC)) && \
9886cc16 FB	511	!defined(CONFIG_USER_ONLY)
6e59c1db FB	512
	513	void tlb_fill(unsigned long addr, int is_write, int is_user,
	514	void *retaddr);
	515
	516	#define ACCESS_TYPE 3
	517	#define MEMSUFFIX _code
	518	#define env cpu_single_env
	519
	520	#define DATA_SIZE 1
	521	#include "softmmu_header.h"
	522
	523	#define DATA_SIZE 2
	524	#include "softmmu_header.h"
	525
	526	#define DATA_SIZE 4
	527	#include "softmmu_header.h"
	528
	529	#undef ACCESS_TYPE
	530	#undef MEMSUFFIX
	531	#undef env
	532
	533	#endif
4390df51 FB	534
	535	#if defined(CONFIG_USER_ONLY)
	536	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	537	{
	538	return addr;
	539	}
	540	#else
	541	/* NOTE: this function can trigger an exception */
1ccde1cb FB	542	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	543	is the offset relative to phys_ram_base */
4390df51 FB	544	/* XXX: i386 target specific */
	545	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	546	{
	547	int is_user, index;
	548
	549	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
3f5dcc34	550	#if defined(TARGET_I386)
4390df51	551	is_user = ((env->hflags & HF_CPL_MASK) == 3);
3f5dcc34 FB	552	#elif defined (TARGET_PPC)
	553	is_user = msr_pr;
	554	#else
	555	#error "Unimplemented !"
	556	#endif
4390df51 FB	557	if (__builtin_expect(env->tlb_read[is_user][index].address !=
	558	(addr & TARGET_PAGE_MASK), 0)) {
	559	ldub_code((void *)addr);
	560	}
	561	return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
	562	}
	563	#endif