[qemu.git] / exec-i386.c

/*
 *  i386 emulator main execution loop
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "exec-i386.h"
#include "disas.h"

//#define DEBUG_EXEC
//#define DEBUG_SIGNAL

/* main execution loop */

/* thread support */

spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void cpu_lock(void)
{
    spin_lock(&global_cpu_lock);
}

void cpu_unlock(void)
{
    spin_unlock(&global_cpu_lock);
}

/* exception support */
/* NOTE: not static to force relocation generation by GCC */
void raise_exception_err(int exception_index, int error_code)
{
    /* NOTE: the register at this point must be saved by hand because
       longjmp restore them */
#ifdef __sparc__
	/* We have to stay in the same register window as our caller,
	 * thus this trick.
	 */
	__asm__ __volatile__("restore\n\t"
			     "mov\t%o0, %i0");
#endif
#ifdef reg_EAX
    env->regs[R_EAX] = EAX;
#endif
#ifdef reg_ECX
    env->regs[R_ECX] = ECX;
#endif
#ifdef reg_EDX
    env->regs[R_EDX] = EDX;
#endif
#ifdef reg_EBX
    env->regs[R_EBX] = EBX;
#endif
#ifdef reg_ESP
    env->regs[R_ESP] = ESP;
#endif
#ifdef reg_EBP
    env->regs[R_EBP] = EBP;
#endif
#ifdef reg_ESI
    env->regs[R_ESI] = ESI;
#endif
#ifdef reg_EDI
    env->regs[R_EDI] = EDI;
#endif
    env->exception_index = exception_index;
    env->error_code = error_code;
    longjmp(env->jmp_env, 1);
}

/* short cut if error_code is 0 or not present */
void raise_exception(int exception_index)
{
    raise_exception_err(exception_index, 0);
}

int cpu_x86_exec(CPUX86State *env1)
{
    int saved_T0, saved_T1, saved_A0;
    CPUX86State *saved_env;
#ifdef reg_EAX
    int saved_EAX;
#endif
#ifdef reg_ECX
    int saved_ECX;
#endif
#ifdef reg_EDX
    int saved_EDX;
#endif
#ifdef reg_EBX
    int saved_EBX;
#endif
#ifdef reg_ESP
    int saved_ESP;
#endif
#ifdef reg_EBP
    int saved_EBP;
#endif
#ifdef reg_ESI
    int saved_ESI;
#endif
#ifdef reg_EDI
    int saved_EDI;
#endif
    int code_gen_size, ret, code_size;
    void (*gen_func)(void);
    TranslationBlock *tb, **ptb;
    uint8_t *tc_ptr, *cs_base, *pc;
    unsigned int flags;
    
    /* first we save global registers */
    saved_T0 = T0;
    saved_T1 = T1;
    saved_A0 = A0;
    saved_env = env;
    env = env1;
#ifdef reg_EAX
    saved_EAX = EAX;
    EAX = env->regs[R_EAX];
#endif
#ifdef reg_ECX
    saved_ECX = ECX;
    ECX = env->regs[R_ECX];
#endif
#ifdef reg_EDX
    saved_EDX = EDX;
    EDX = env->regs[R_EDX];
#endif
#ifdef reg_EBX
    saved_EBX = EBX;
    EBX = env->regs[R_EBX];
#endif
#ifdef reg_ESP
    saved_ESP = ESP;
    ESP = env->regs[R_ESP];
#endif
#ifdef reg_EBP
    saved_EBP = EBP;
    EBP = env->regs[R_EBP];
#endif
#ifdef reg_ESI
    saved_ESI = ESI;
    ESI = env->regs[R_ESI];
#endif
#ifdef reg_EDI
    saved_EDI = EDI;
    EDI = env->regs[R_EDI];
#endif
    
    /* put eflags in CPU temporary format */
    CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    DF = 1 - (2 * ((env->eflags >> 10) & 1));
    CC_OP = CC_OP_EFLAGS;
    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    env->interrupt_request = 0;

    /* prepare setjmp context for exception handling */
    if (setjmp(env->jmp_env) == 0) {
        T0 = 0; /* force lookup of first TB */
        for(;;) {
            if (env->interrupt_request) {
                raise_exception(EXCP_INTERRUPT);
            }
#ifdef DEBUG_EXEC
            if (loglevel) {
                /* XXX: save all volatile state in cpu state */
                /* restore flags in standard format */
                env->regs[R_EAX] = EAX;
                env->regs[R_EBX] = EBX;
                env->regs[R_ECX] = ECX;
                env->regs[R_EDX] = EDX;
                env->regs[R_ESI] = ESI;
                env->regs[R_EDI] = EDI;
                env->regs[R_EBP] = EBP;
                env->regs[R_ESP] = ESP;
                env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
                cpu_x86_dump_state(env, logfile, 0);
                env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
            }
#endif
            /* we compute the CPU state. We assume it will not
               change during the whole generated block. */
            flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
            flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
            flags |= (((unsigned long)env->seg_cache[R_DS].base | 
                       (unsigned long)env->seg_cache[R_ES].base |
                       (unsigned long)env->seg_cache[R_SS].base) != 0) << 
                GEN_FLAG_ADDSEG_SHIFT;
            if (!(env->eflags & VM_MASK)) {
                flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
            } else {
                /* NOTE: a dummy CPL is kept */
                flags |= (1 << GEN_FLAG_VM_SHIFT);
                flags |= (3 << GEN_FLAG_CPL_SHIFT);
            }
            flags |= (env->eflags & (IOPL_MASK | TF_MASK));
            cs_base = env->seg_cache[R_CS].base;
            pc = cs_base + env->eip;
            tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, 
                         flags);
            if (!tb) {
                spin_lock(&tb_lock);
                /* if no translated code available, then translate it now */
                tb = tb_alloc((unsigned long)pc);
                if (!tb) {
                    /* flush must be done */
                    tb_flush();
                    /* cannot fail at this point */
                    tb = tb_alloc((unsigned long)pc);
                    /* don't forget to invalidate previous TB info */
                    ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
                    T0 = 0;
                }
                tc_ptr = code_gen_ptr;
                tb->tc_ptr = tc_ptr;
                ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE, 
                                       &code_gen_size, pc, cs_base, flags,
                                       &code_size, tb);
                /* if invalid instruction, signal it */
                if (ret != 0) {
                    /* NOTE: the tb is allocated but not linked, so we
                       can leave it */
                    spin_unlock(&tb_lock);
                    raise_exception(EXCP06_ILLOP);
                }
                *ptb = tb;
                tb->size = code_size;
                tb->cs_base = (unsigned long)cs_base;
                tb->flags = flags;
                tb->hash_next = NULL;
                tb_link(tb);
                code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
                spin_unlock(&tb_lock);
            }
#ifdef DEBUG_EXEC
	    if (loglevel) {
		fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
			(long)tb->tc_ptr, (long)tb->pc,
			lookup_symbol((void *)tb->pc));
	    }
#endif
            /* see if we can patch the calling TB */
            if (T0 != 0 && !(env->eflags & TF_MASK)) {
                spin_lock(&tb_lock);
                tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
                spin_unlock(&tb_lock);
            }

            tc_ptr = tb->tc_ptr;

            /* execute the generated code */
            gen_func = (void *)tc_ptr;
#ifdef __sparc__
	    __asm__ __volatile__("call	%0\n\t"
				 " mov	%%o7,%%i0"
				 : /* no outputs */
				 : "r" (gen_func) 
				 : "i0", "i1", "i2", "i3", "i4", "i5");
#else
            gen_func();
#endif
        }
    }
    ret = env->exception_index;

    /* restore flags in standard format */
    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);

    /* restore global registers */
#ifdef reg_EAX
    EAX = saved_EAX;
#endif
#ifdef reg_ECX
    ECX = saved_ECX;
#endif
#ifdef reg_EDX
    EDX = saved_EDX;
#endif
#ifdef reg_EBX
    EBX = saved_EBX;
#endif
#ifdef reg_ESP
    ESP = saved_ESP;
#endif
#ifdef reg_EBP
    EBP = saved_EBP;
#endif
#ifdef reg_ESI
    ESI = saved_ESI;
#endif
#ifdef reg_EDI
    EDI = saved_EDI;
#endif
    T0 = saved_T0;
    T1 = saved_T1;
    A0 = saved_A0;
    env = saved_env;
    return ret;
}

void cpu_x86_interrupt(CPUX86State *s)
{
    s->interrupt_request = 1;
}


void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    load_seg(seg_reg, selector);
    env = saved_env;
}

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#include <sys/ucontext.h>

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception. 'is_write' is 1 if a
   write caused the exception and otherwise 0'. 'old_set' is the
   signal set which should be restored */
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
#if defined(DEBUG_SIGNAL)
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n", 
           pc, address, is_write, *(unsigned long *)old_set);
#endif
    /* XXX: locking issue */
    if (is_write && page_unprotect(address)) {
        return 1;
    }
    if (pc >= (unsigned long)code_gen_buffer &&
        pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) {
        /* the PC is inside the translated code. It means that we have
           a virtual CPU fault */
        /* we restore the process signal mask as the sigreturn should
           do it */
        sigprocmask(SIG_SETMASK, old_set, NULL);
        /* XXX: need to compute virtual pc position by retranslating
           code. The rest of the CPU state should be correct. */
        env->cr2 = address;
        raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
        /* never comes here */
        return 1;
    } else {
        return 0;
    }
}

#if defined(__i386__)

int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    
#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP    EIP
#define REG_ERR    ERR
#define REG_TRAPNO TRAPNO
#endif
    pc = uc->uc_mcontext.gregs[REG_EIP];
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? 
                             (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
                             &uc->uc_sigmask);
}

#elif defined(__powerpc)

int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc)
{
    struct ucontext *uc = puc;
    struct pt_regs *regs = uc->uc_mcontext.regs;
    unsigned long pc;
    int is_write;

    pc = regs->nip;
    is_write = 0;
#if 0
    /* ppc 4xx case */
    if (regs->dsisr & 0x00800000)
        is_write = 1;
#else
    if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
        is_write = 1;
#endif
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}

#else

#error CPU specific signal handler needed

#endif
Commit	Line	Data
7d13299d FB	1	/*
	2	* i386 emulator main execution loop
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
3ef693a0 FB	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
7d13299d	10	*
3ef693a0 FB	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
7d13299d	15	*
3ef693a0 FB	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d FB	19	*/
7d13299d FB	20	#include "exec-i386.h"
956034d7	21	#include "disas.h"
7d13299d	22
dc99065b	23	//#define DEBUG_EXEC
9de5e440	24	//#define DEBUG_SIGNAL
7d13299d FB	25
	26	/* main execution loop */
	27
1b6b029e FB	28	/* thread support */
1b6b029e FB	29
25eb4484	30	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
1b6b029e FB	31
	32	void cpu_lock(void)
	33	{
25eb4484	34	spin_lock(&global_cpu_lock);
1b6b029e FB	35	}
	36
	37	void cpu_unlock(void)
	38	{
25eb4484	39	spin_unlock(&global_cpu_lock);
1b6b029e FB	40	}
1b6b029e FB	41
9de5e440 FB	42	/* exception support */
9de5e440 FB	43	/* NOTE: not static to force relocation generation by GCC */
b56dad1c	44	void raise_exception_err(int exception_index, int error_code)
9de5e440 FB	45	{
	46	/* NOTE: the register at this point must be saved by hand because
	47	longjmp restore them */
ae228531 FB	48	#ifdef __sparc__
	49	/* We have to stay in the same register window as our caller,
	50	* thus this trick.
	51	*/
	52	__asm__ __volatile__("restore\n\t"
	53	"mov\t%o0, %i0");
	54	#endif
9de5e440 FB	55	#ifdef reg_EAX
	56	env->regs[R_EAX] = EAX;
	57	#endif
	58	#ifdef reg_ECX
	59	env->regs[R_ECX] = ECX;
	60	#endif
	61	#ifdef reg_EDX
	62	env->regs[R_EDX] = EDX;
	63	#endif
	64	#ifdef reg_EBX
	65	env->regs[R_EBX] = EBX;
	66	#endif
	67	#ifdef reg_ESP
	68	env->regs[R_ESP] = ESP;
	69	#endif
	70	#ifdef reg_EBP
	71	env->regs[R_EBP] = EBP;
	72	#endif
	73	#ifdef reg_ESI
	74	env->regs[R_ESI] = ESI;
	75	#endif
	76	#ifdef reg_EDI
	77	env->regs[R_EDI] = EDI;
	78	#endif
	79	env->exception_index = exception_index;
b56dad1c	80	env->error_code = error_code;
9de5e440 FB	81	longjmp(env->jmp_env, 1);
	82	}
	83
b56dad1c FB	84	/* short cut if error_code is 0 or not present */
	85	void raise_exception(int exception_index)
	86	{
	87	raise_exception_err(exception_index, 0);
	88	}
	89
7d13299d FB	90	int cpu_x86_exec(CPUX86State *env1)
	91	{
	92	int saved_T0, saved_T1, saved_A0;
	93	CPUX86State *saved_env;
04369ff2 FB	94	#ifdef reg_EAX
	95	int saved_EAX;
	96	#endif
	97	#ifdef reg_ECX
	98	int saved_ECX;
	99	#endif
	100	#ifdef reg_EDX
	101	int saved_EDX;
	102	#endif
	103	#ifdef reg_EBX
	104	int saved_EBX;
	105	#endif
	106	#ifdef reg_ESP
	107	int saved_ESP;
	108	#endif
	109	#ifdef reg_EBP
	110	int saved_EBP;
	111	#endif
	112	#ifdef reg_ESI
	113	int saved_ESI;
	114	#endif
	115	#ifdef reg_EDI
	116	int saved_EDI;
	117	#endif
fd6ce8f6	118	int code_gen_size, ret, code_size;
7d13299d	119	void (*gen_func)(void);
9de5e440	120	TranslationBlock tb, *ptb;
dab2ed99	121	uint8_t tc_ptr, cs_base, *pc;
6dbad63e	122	unsigned int flags;
d4e8164f	123
7d13299d FB	124	/* first we save global registers */
	125	saved_T0 = T0;
	126	saved_T1 = T1;
	127	saved_A0 = A0;
	128	saved_env = env;
	129	env = env1;
04369ff2 FB	130	#ifdef reg_EAX
	131	saved_EAX = EAX;
	132	EAX = env->regs[R_EAX];
	133	#endif
	134	#ifdef reg_ECX
	135	saved_ECX = ECX;
	136	ECX = env->regs[R_ECX];
	137	#endif
	138	#ifdef reg_EDX
	139	saved_EDX = EDX;
	140	EDX = env->regs[R_EDX];
	141	#endif
	142	#ifdef reg_EBX
	143	saved_EBX = EBX;
	144	EBX = env->regs[R_EBX];
	145	#endif
	146	#ifdef reg_ESP
	147	saved_ESP = ESP;
	148	ESP = env->regs[R_ESP];
	149	#endif
	150	#ifdef reg_EBP
	151	saved_EBP = EBP;
	152	EBP = env->regs[R_EBP];
	153	#endif
	154	#ifdef reg_ESI
	155	saved_ESI = ESI;
	156	ESI = env->regs[R_ESI];
	157	#endif
	158	#ifdef reg_EDI
	159	saved_EDI = EDI;
	160	EDI = env->regs[R_EDI];
	161	#endif
7d13299d	162
9de5e440	163	/* put eflags in CPU temporary format */
fc2b4c48 FB	164	CC_SRC = env->eflags & (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
fc2b4c48 FB	165	DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440	166	CC_OP = CC_OP_EFLAGS;
fc2b4c48	167	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
9de5e440	168	env->interrupt_request = 0;
9d27abd9	169
7d13299d FB	170	/* prepare setjmp context for exception handling */
7d13299d FB	171	if (setjmp(env->jmp_env) == 0) {
d4e8164f	172	T0 = 0; /* force lookup of first TB */
7d13299d	173	for(;;) {
9de5e440 FB	174	if (env->interrupt_request) {
	175	raise_exception(EXCP_INTERRUPT);
	176	}
7d13299d FB	177	#ifdef DEBUG_EXEC
7d13299d FB	178	if (loglevel) {
9d27abd9 FB	179	/* XXX: save all volatile state in cpu state */
	180	/* restore flags in standard format */
	181	env->regs[R_EAX] = EAX;
	182	env->regs[R_EBX] = EBX;
	183	env->regs[R_ECX] = ECX;
	184	env->regs[R_EDX] = EDX;
	185	env->regs[R_ESI] = ESI;
	186	env->regs[R_EDI] = EDI;
	187	env->regs[R_EBP] = EBP;
	188	env->regs[R_ESP] = ESP;
	189	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
	190	cpu_x86_dump_state(env, logfile, 0);
	191	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
7d13299d FB	192	}
7d13299d FB	193	#endif
6dbad63e FB	194	/* we compute the CPU state. We assume it will not
	195	change during the whole generated block. */
	196	flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
dab2ed99	197	flags \|= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
6dbad63e FB	198	flags \|= (((unsigned long)env->seg_cache[R_DS].base \|
	199	(unsigned long)env->seg_cache[R_ES].base \|
	200	(unsigned long)env->seg_cache[R_SS].base) != 0) <<
	201	GEN_FLAG_ADDSEG_SHIFT;
9d27abd9 FB	202	if (!(env->eflags & VM_MASK)) {
	203	flags \|= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
	204	} else {
	205	/* NOTE: a dummy CPL is kept */
	206	flags \|= (1 << GEN_FLAG_VM_SHIFT);
	207	flags \|= (3 << GEN_FLAG_CPL_SHIFT);
	208	}
cf25629d	209	flags \|= (env->eflags & (IOPL_MASK \| TF_MASK));
dab2ed99 FB	210	cs_base = env->seg_cache[R_CS].base;
dab2ed99 FB	211	pc = cs_base + env->eip;
9de5e440 FB	212	tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
	213	flags);
	214	if (!tb) {
cf25629d	215	spin_lock(&tb_lock);
7d13299d	216	/* if no translated code available, then translate it now */
d4e8164f FB	217	tb = tb_alloc((unsigned long)pc);
	218	if (!tb) {
	219	/* flush must be done */
	220	tb_flush();
	221	/* cannot fail at this point */
	222	tb = tb_alloc((unsigned long)pc);
	223	/* don't forget to invalidate previous TB info */
	224	ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
	225	T0 = 0;
	226	}
7d13299d	227	tc_ptr = code_gen_ptr;
d4e8164f	228	tb->tc_ptr = tc_ptr;
9de5e440	229	ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE,
fd6ce8f6	230	&code_gen_size, pc, cs_base, flags,
d4e8164f	231	&code_size, tb);
9de5e440 FB	232	/* if invalid instruction, signal it */
9de5e440 FB	233	if (ret != 0) {
d4e8164f FB	234	/* NOTE: the tb is allocated but not linked, so we
d4e8164f FB	235	can leave it */
25eb4484	236	spin_unlock(&tb_lock);
9de5e440 FB	237	raise_exception(EXCP06_ILLOP);
9de5e440 FB	238	}
9de5e440	239	*ptb = tb;
d4e8164f	240	tb->size = code_size;
9de5e440 FB	241	tb->cs_base = (unsigned long)cs_base;
9de5e440 FB	242	tb->flags = flags;
9de5e440	243	tb->hash_next = NULL;
d4e8164f	244	tb_link(tb);
7d13299d	245	code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
cf25629d	246	spin_unlock(&tb_lock);
7d13299d	247	}
9d27abd9	248	#ifdef DEBUG_EXEC
956034d7 FB	249	if (loglevel) {
	250	fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
	251	(long)tb->tc_ptr, (long)tb->pc,
	252	lookup_symbol((void *)tb->pc));
956034d7	253	}
9d27abd9	254	#endif
d4e8164f FB	255	/* see if we can patch the calling TB */
d4e8164f FB	256	if (T0 != 0 && !(env->eflags & TF_MASK)) {
cf25629d	257	spin_lock(&tb_lock);
d4e8164f	258	tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
cf25629d	259	spin_unlock(&tb_lock);
d4e8164f	260	}
cf25629d	261
9de5e440	262	tc_ptr = tb->tc_ptr;
d4e8164f FB	263
d4e8164f FB	264	/* execute the generated code */
7d13299d	265	gen_func = (void *)tc_ptr;
ae228531 FB	266	#ifdef __sparc__
	267	__asm__ __volatile__("call %0\n\t"
	268	" mov %%o7,%%i0"
	269	: /* no outputs */
d4e8164f	270	: "r" (gen_func)
ae228531 FB	271	: "i0", "i1", "i2", "i3", "i4", "i5");
ae228531 FB	272	#else
7d13299d	273	gen_func();
ae228531	274	#endif
7d13299d FB	275	}
	276	}
	277	ret = env->exception_index;
	278
9de5e440	279	/* restore flags in standard format */
fc2b4c48	280	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
9de5e440	281
7d13299d	282	/* restore global registers */
04369ff2 FB	283	#ifdef reg_EAX
	284	EAX = saved_EAX;
	285	#endif
	286	#ifdef reg_ECX
	287	ECX = saved_ECX;
	288	#endif
	289	#ifdef reg_EDX
	290	EDX = saved_EDX;
	291	#endif
	292	#ifdef reg_EBX
	293	EBX = saved_EBX;
	294	#endif
	295	#ifdef reg_ESP
	296	ESP = saved_ESP;
	297	#endif
	298	#ifdef reg_EBP
	299	EBP = saved_EBP;
	300	#endif
	301	#ifdef reg_ESI
	302	ESI = saved_ESI;
	303	#endif
	304	#ifdef reg_EDI
	305	EDI = saved_EDI;
	306	#endif
7d13299d FB	307	T0 = saved_T0;
	308	T1 = saved_T1;
	309	A0 = saved_A0;
	310	env = saved_env;
	311	return ret;
	312	}
6dbad63e	313
9de5e440 FB	314	void cpu_x86_interrupt(CPUX86State *s)
	315	{
	316	s->interrupt_request = 1;
	317	}
	318
	319
6dbad63e FB	320	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
	321	{
	322	CPUX86State *saved_env;
	323
	324	saved_env = env;
	325	env = s;
	326	load_seg(seg_reg, selector);
	327	env = saved_env;
	328	}
9de5e440 FB	329
	330	#undef EAX
	331	#undef ECX
	332	#undef EDX
	333	#undef EBX
	334	#undef ESP
	335	#undef EBP
	336	#undef ESI
	337	#undef EDI
	338	#undef EIP
	339	#include <signal.h>
	340	#include <sys/ucontext.h>
	341
b56dad1c	342	/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6 FB	343	the effective address of the memory exception. 'is_write' is 1 if a
	344	write caused the exception and otherwise 0'. 'old_set' is the
	345	signal set which should be restored */
2b413144 FB	346	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
2b413144 FB	347	int is_write, sigset_t *old_set)
9de5e440	348	{
fd6ce8f6 FB	349	#if defined(DEBUG_SIGNAL)
	350	printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
	351	pc, address, is_write, (unsigned long )old_set);
9de5e440	352	#endif
25eb4484	353	/* XXX: locking issue */
fd6ce8f6	354	if (is_write && page_unprotect(address)) {
fd6ce8f6 FB	355	return 1;
fd6ce8f6 FB	356	}
9de5e440 FB	357	if (pc >= (unsigned long)code_gen_buffer &&
	358	pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) {
	359	/* the PC is inside the translated code. It means that we have
	360	a virtual CPU fault */
	361	/* we restore the process signal mask as the sigreturn should
	362	do it */
	363	sigprocmask(SIG_SETMASK, old_set, NULL);
	364	/* XXX: need to compute virtual pc position by retranslating
	365	code. The rest of the CPU state should be correct. */
b56dad1c	366	env->cr2 = address;
fd6ce8f6	367	raise_exception_err(EXCP0E_PAGE, 4 \| (is_write << 1));
9de5e440 FB	368	/* never comes here */
	369	return 1;
	370	} else {
	371	return 0;
	372	}
	373	}
	374
2b413144 FB	375	#if defined(__i386__)
2b413144 FB	376
9de5e440 FB	377	int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
	378	void *puc)
	379	{
9de5e440 FB	380	struct ucontext *uc = puc;
9de5e440 FB	381	unsigned long pc;
9de5e440	382
d691f669 FB	383	#ifndef REG_EIP
d691f669 FB	384	/* for glibc 2.1 */
fd6ce8f6 FB	385	#define REG_EIP EIP
	386	#define REG_ERR ERR
	387	#define REG_TRAPNO TRAPNO
d691f669	388	#endif
fc2b4c48	389	pc = uc->uc_mcontext.gregs[REG_EIP];
fd6ce8f6 FB	390	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	391	uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
	392	(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
2b413144 FB	393	&uc->uc_sigmask);
	394	}
	395
25eb4484	396	#elif defined(__powerpc)
2b413144 FB	397
	398	int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
	399	void *puc)
	400	{
25eb4484 FB	401	struct ucontext *uc = puc;
	402	struct pt_regs *regs = uc->uc_mcontext.regs;
	403	unsigned long pc;
25eb4484 FB	404	int is_write;
	405
	406	pc = regs->nip;
25eb4484 FB	407	is_write = 0;
	408	#if 0
	409	/* ppc 4xx case */
	410	if (regs->dsisr & 0x00800000)
	411	is_write = 1;
	412	#else
	413	if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
	414	is_write = 1;
	415	#endif
	416	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
2b413144 FB	417	is_write, &uc->uc_sigmask);
	418	}
	419
9de5e440	420	#else
2b413144	421
25eb4484	422	#error CPU specific signal handler needed
2b413144	423
9de5e440	424	#endif