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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 FB |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
7d13299d FB |
19 | */ |
20 | #include "exec-i386.h" | |
956034d7 | 21 | #include "disas.h" |
7d13299d | 22 | |
dc99065b | 23 | //#define DEBUG_EXEC |
9de5e440 | 24 | //#define DEBUG_SIGNAL |
7d13299d FB |
25 | |
26 | /* main execution loop */ | |
27 | ||
1b6b029e FB |
28 | /* thread support */ |
29 | ||
25eb4484 | 30 | spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
1b6b029e FB |
31 | |
32 | void cpu_lock(void) | |
33 | { | |
25eb4484 | 34 | spin_lock(&global_cpu_lock); |
1b6b029e FB |
35 | } |
36 | ||
37 | void cpu_unlock(void) | |
38 | { | |
25eb4484 | 39 | spin_unlock(&global_cpu_lock); |
1b6b029e FB |
40 | } |
41 | ||
9de5e440 FB |
42 | /* exception support */ |
43 | /* NOTE: not static to force relocation generation by GCC */ | |
b56dad1c | 44 | void raise_exception_err(int exception_index, int error_code) |
9de5e440 FB |
45 | { |
46 | /* NOTE: the register at this point must be saved by hand because | |
47 | longjmp restore them */ | |
ae228531 FB |
48 | #ifdef __sparc__ |
49 | /* We have to stay in the same register window as our caller, | |
50 | * thus this trick. | |
51 | */ | |
52 | __asm__ __volatile__("restore\n\t" | |
53 | "mov\t%o0, %i0"); | |
54 | #endif | |
9de5e440 FB |
55 | #ifdef reg_EAX |
56 | env->regs[R_EAX] = EAX; | |
57 | #endif | |
58 | #ifdef reg_ECX | |
59 | env->regs[R_ECX] = ECX; | |
60 | #endif | |
61 | #ifdef reg_EDX | |
62 | env->regs[R_EDX] = EDX; | |
63 | #endif | |
64 | #ifdef reg_EBX | |
65 | env->regs[R_EBX] = EBX; | |
66 | #endif | |
67 | #ifdef reg_ESP | |
68 | env->regs[R_ESP] = ESP; | |
69 | #endif | |
70 | #ifdef reg_EBP | |
71 | env->regs[R_EBP] = EBP; | |
72 | #endif | |
73 | #ifdef reg_ESI | |
74 | env->regs[R_ESI] = ESI; | |
75 | #endif | |
76 | #ifdef reg_EDI | |
77 | env->regs[R_EDI] = EDI; | |
78 | #endif | |
79 | env->exception_index = exception_index; | |
b56dad1c | 80 | env->error_code = error_code; |
9de5e440 FB |
81 | longjmp(env->jmp_env, 1); |
82 | } | |
83 | ||
b56dad1c FB |
84 | /* short cut if error_code is 0 or not present */ |
85 | void raise_exception(int exception_index) | |
86 | { | |
87 | raise_exception_err(exception_index, 0); | |
88 | } | |
89 | ||
7d13299d FB |
90 | int cpu_x86_exec(CPUX86State *env1) |
91 | { | |
92 | int saved_T0, saved_T1, saved_A0; | |
93 | CPUX86State *saved_env; | |
04369ff2 FB |
94 | #ifdef reg_EAX |
95 | int saved_EAX; | |
96 | #endif | |
97 | #ifdef reg_ECX | |
98 | int saved_ECX; | |
99 | #endif | |
100 | #ifdef reg_EDX | |
101 | int saved_EDX; | |
102 | #endif | |
103 | #ifdef reg_EBX | |
104 | int saved_EBX; | |
105 | #endif | |
106 | #ifdef reg_ESP | |
107 | int saved_ESP; | |
108 | #endif | |
109 | #ifdef reg_EBP | |
110 | int saved_EBP; | |
111 | #endif | |
112 | #ifdef reg_ESI | |
113 | int saved_ESI; | |
114 | #endif | |
115 | #ifdef reg_EDI | |
116 | int saved_EDI; | |
117 | #endif | |
fd6ce8f6 | 118 | int code_gen_size, ret, code_size; |
7d13299d | 119 | void (*gen_func)(void); |
9de5e440 | 120 | TranslationBlock *tb, **ptb; |
dab2ed99 | 121 | uint8_t *tc_ptr, *cs_base, *pc; |
6dbad63e | 122 | unsigned int flags; |
d4e8164f | 123 | |
7d13299d FB |
124 | /* first we save global registers */ |
125 | saved_T0 = T0; | |
126 | saved_T1 = T1; | |
127 | saved_A0 = A0; | |
128 | saved_env = env; | |
129 | env = env1; | |
04369ff2 FB |
130 | #ifdef reg_EAX |
131 | saved_EAX = EAX; | |
132 | EAX = env->regs[R_EAX]; | |
133 | #endif | |
134 | #ifdef reg_ECX | |
135 | saved_ECX = ECX; | |
136 | ECX = env->regs[R_ECX]; | |
137 | #endif | |
138 | #ifdef reg_EDX | |
139 | saved_EDX = EDX; | |
140 | EDX = env->regs[R_EDX]; | |
141 | #endif | |
142 | #ifdef reg_EBX | |
143 | saved_EBX = EBX; | |
144 | EBX = env->regs[R_EBX]; | |
145 | #endif | |
146 | #ifdef reg_ESP | |
147 | saved_ESP = ESP; | |
148 | ESP = env->regs[R_ESP]; | |
149 | #endif | |
150 | #ifdef reg_EBP | |
151 | saved_EBP = EBP; | |
152 | EBP = env->regs[R_EBP]; | |
153 | #endif | |
154 | #ifdef reg_ESI | |
155 | saved_ESI = ESI; | |
156 | ESI = env->regs[R_ESI]; | |
157 | #endif | |
158 | #ifdef reg_EDI | |
159 | saved_EDI = EDI; | |
160 | EDI = env->regs[R_EDI]; | |
161 | #endif | |
7d13299d | 162 | |
9de5e440 | 163 | /* put eflags in CPU temporary format */ |
fc2b4c48 FB |
164 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
165 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
9de5e440 | 166 | CC_OP = CC_OP_EFLAGS; |
fc2b4c48 | 167 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
9de5e440 | 168 | env->interrupt_request = 0; |
9d27abd9 | 169 | |
7d13299d FB |
170 | /* prepare setjmp context for exception handling */ |
171 | if (setjmp(env->jmp_env) == 0) { | |
d4e8164f | 172 | T0 = 0; /* force lookup of first TB */ |
7d13299d | 173 | for(;;) { |
9de5e440 FB |
174 | if (env->interrupt_request) { |
175 | raise_exception(EXCP_INTERRUPT); | |
176 | } | |
7d13299d FB |
177 | #ifdef DEBUG_EXEC |
178 | if (loglevel) { | |
9d27abd9 FB |
179 | /* XXX: save all volatile state in cpu state */ |
180 | /* restore flags in standard format */ | |
181 | env->regs[R_EAX] = EAX; | |
182 | env->regs[R_EBX] = EBX; | |
183 | env->regs[R_ECX] = ECX; | |
184 | env->regs[R_EDX] = EDX; | |
185 | env->regs[R_ESI] = ESI; | |
186 | env->regs[R_EDI] = EDI; | |
187 | env->regs[R_EBP] = EBP; | |
188 | env->regs[R_ESP] = ESP; | |
189 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
190 | cpu_x86_dump_state(env, logfile, 0); | |
191 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
7d13299d FB |
192 | } |
193 | #endif | |
6dbad63e FB |
194 | /* we compute the CPU state. We assume it will not |
195 | change during the whole generated block. */ | |
196 | flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT; | |
dab2ed99 | 197 | flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT; |
6dbad63e FB |
198 | flags |= (((unsigned long)env->seg_cache[R_DS].base | |
199 | (unsigned long)env->seg_cache[R_ES].base | | |
200 | (unsigned long)env->seg_cache[R_SS].base) != 0) << | |
201 | GEN_FLAG_ADDSEG_SHIFT; | |
9d27abd9 FB |
202 | if (!(env->eflags & VM_MASK)) { |
203 | flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT; | |
204 | } else { | |
205 | /* NOTE: a dummy CPL is kept */ | |
206 | flags |= (1 << GEN_FLAG_VM_SHIFT); | |
207 | flags |= (3 << GEN_FLAG_CPL_SHIFT); | |
208 | } | |
b56dad1c | 209 | flags |= (env->eflags & IOPL_MASK) >> (12 - GEN_FLAG_IOPL_SHIFT); |
cabb4d61 | 210 | flags |= (env->eflags & TF_MASK) << (GEN_FLAG_TF_SHIFT - 8); |
dab2ed99 FB |
211 | cs_base = env->seg_cache[R_CS].base; |
212 | pc = cs_base + env->eip; | |
d4e8164f | 213 | spin_lock(&tb_lock); |
9de5e440 FB |
214 | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
215 | flags); | |
216 | if (!tb) { | |
7d13299d | 217 | /* if no translated code available, then translate it now */ |
d4e8164f FB |
218 | tb = tb_alloc((unsigned long)pc); |
219 | if (!tb) { | |
220 | /* flush must be done */ | |
221 | tb_flush(); | |
222 | /* cannot fail at this point */ | |
223 | tb = tb_alloc((unsigned long)pc); | |
224 | /* don't forget to invalidate previous TB info */ | |
225 | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; | |
226 | T0 = 0; | |
227 | } | |
7d13299d | 228 | tc_ptr = code_gen_ptr; |
d4e8164f | 229 | tb->tc_ptr = tc_ptr; |
9de5e440 | 230 | ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE, |
fd6ce8f6 | 231 | &code_gen_size, pc, cs_base, flags, |
d4e8164f | 232 | &code_size, tb); |
9de5e440 FB |
233 | /* if invalid instruction, signal it */ |
234 | if (ret != 0) { | |
d4e8164f FB |
235 | /* NOTE: the tb is allocated but not linked, so we |
236 | can leave it */ | |
25eb4484 | 237 | spin_unlock(&tb_lock); |
9de5e440 FB |
238 | raise_exception(EXCP06_ILLOP); |
239 | } | |
9de5e440 | 240 | *ptb = tb; |
d4e8164f | 241 | tb->size = code_size; |
9de5e440 FB |
242 | tb->cs_base = (unsigned long)cs_base; |
243 | tb->flags = flags; | |
9de5e440 | 244 | tb->hash_next = NULL; |
d4e8164f | 245 | tb_link(tb); |
7d13299d FB |
246 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
247 | } | |
9d27abd9 | 248 | #ifdef DEBUG_EXEC |
956034d7 FB |
249 | if (loglevel) { |
250 | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n", | |
251 | (long)tb->tc_ptr, (long)tb->pc, | |
252 | lookup_symbol((void *)tb->pc)); | |
956034d7 | 253 | } |
9d27abd9 | 254 | #endif |
d4e8164f FB |
255 | |
256 | /* see if we can patch the calling TB */ | |
257 | if (T0 != 0 && !(env->eflags & TF_MASK)) { | |
258 | tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); | |
259 | } | |
9de5e440 | 260 | tc_ptr = tb->tc_ptr; |
d4e8164f FB |
261 | spin_unlock(&tb_lock); |
262 | ||
263 | /* execute the generated code */ | |
7d13299d | 264 | gen_func = (void *)tc_ptr; |
ae228531 FB |
265 | #ifdef __sparc__ |
266 | __asm__ __volatile__("call %0\n\t" | |
267 | " mov %%o7,%%i0" | |
268 | : /* no outputs */ | |
d4e8164f | 269 | : "r" (gen_func) |
ae228531 FB |
270 | : "i0", "i1", "i2", "i3", "i4", "i5"); |
271 | #else | |
7d13299d | 272 | gen_func(); |
ae228531 | 273 | #endif |
7d13299d FB |
274 | } |
275 | } | |
276 | ret = env->exception_index; | |
277 | ||
9de5e440 | 278 | /* restore flags in standard format */ |
fc2b4c48 | 279 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
9de5e440 | 280 | |
7d13299d | 281 | /* restore global registers */ |
04369ff2 FB |
282 | #ifdef reg_EAX |
283 | EAX = saved_EAX; | |
284 | #endif | |
285 | #ifdef reg_ECX | |
286 | ECX = saved_ECX; | |
287 | #endif | |
288 | #ifdef reg_EDX | |
289 | EDX = saved_EDX; | |
290 | #endif | |
291 | #ifdef reg_EBX | |
292 | EBX = saved_EBX; | |
293 | #endif | |
294 | #ifdef reg_ESP | |
295 | ESP = saved_ESP; | |
296 | #endif | |
297 | #ifdef reg_EBP | |
298 | EBP = saved_EBP; | |
299 | #endif | |
300 | #ifdef reg_ESI | |
301 | ESI = saved_ESI; | |
302 | #endif | |
303 | #ifdef reg_EDI | |
304 | EDI = saved_EDI; | |
305 | #endif | |
7d13299d FB |
306 | T0 = saved_T0; |
307 | T1 = saved_T1; | |
308 | A0 = saved_A0; | |
309 | env = saved_env; | |
310 | return ret; | |
311 | } | |
6dbad63e | 312 | |
9de5e440 FB |
313 | void cpu_x86_interrupt(CPUX86State *s) |
314 | { | |
315 | s->interrupt_request = 1; | |
316 | } | |
317 | ||
318 | ||
6dbad63e FB |
319 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
320 | { | |
321 | CPUX86State *saved_env; | |
322 | ||
323 | saved_env = env; | |
324 | env = s; | |
325 | load_seg(seg_reg, selector); | |
326 | env = saved_env; | |
327 | } | |
9de5e440 FB |
328 | |
329 | #undef EAX | |
330 | #undef ECX | |
331 | #undef EDX | |
332 | #undef EBX | |
333 | #undef ESP | |
334 | #undef EBP | |
335 | #undef ESI | |
336 | #undef EDI | |
337 | #undef EIP | |
338 | #include <signal.h> | |
339 | #include <sys/ucontext.h> | |
340 | ||
b56dad1c | 341 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
fd6ce8f6 FB |
342 | the effective address of the memory exception. 'is_write' is 1 if a |
343 | write caused the exception and otherwise 0'. 'old_set' is the | |
344 | signal set which should be restored */ | |
2b413144 FB |
345 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
346 | int is_write, sigset_t *old_set) | |
9de5e440 | 347 | { |
fd6ce8f6 FB |
348 | #if defined(DEBUG_SIGNAL) |
349 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n", | |
350 | pc, address, is_write, *(unsigned long *)old_set); | |
9de5e440 | 351 | #endif |
25eb4484 | 352 | /* XXX: locking issue */ |
fd6ce8f6 | 353 | if (is_write && page_unprotect(address)) { |
fd6ce8f6 FB |
354 | return 1; |
355 | } | |
9de5e440 FB |
356 | if (pc >= (unsigned long)code_gen_buffer && |
357 | pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) { | |
358 | /* the PC is inside the translated code. It means that we have | |
359 | a virtual CPU fault */ | |
360 | /* we restore the process signal mask as the sigreturn should | |
361 | do it */ | |
362 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
363 | /* XXX: need to compute virtual pc position by retranslating | |
364 | code. The rest of the CPU state should be correct. */ | |
b56dad1c | 365 | env->cr2 = address; |
fd6ce8f6 | 366 | raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1)); |
9de5e440 FB |
367 | /* never comes here */ |
368 | return 1; | |
369 | } else { | |
370 | return 0; | |
371 | } | |
372 | } | |
373 | ||
2b413144 FB |
374 | #if defined(__i386__) |
375 | ||
9de5e440 FB |
376 | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
377 | void *puc) | |
378 | { | |
9de5e440 FB |
379 | struct ucontext *uc = puc; |
380 | unsigned long pc; | |
9de5e440 | 381 | |
d691f669 FB |
382 | #ifndef REG_EIP |
383 | /* for glibc 2.1 */ | |
fd6ce8f6 FB |
384 | #define REG_EIP EIP |
385 | #define REG_ERR ERR | |
386 | #define REG_TRAPNO TRAPNO | |
d691f669 | 387 | #endif |
fc2b4c48 | 388 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
fd6ce8f6 FB |
389 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
390 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? | |
391 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
2b413144 FB |
392 | &uc->uc_sigmask); |
393 | } | |
394 | ||
25eb4484 | 395 | #elif defined(__powerpc) |
2b413144 FB |
396 | |
397 | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, | |
398 | void *puc) | |
399 | { | |
25eb4484 FB |
400 | struct ucontext *uc = puc; |
401 | struct pt_regs *regs = uc->uc_mcontext.regs; | |
402 | unsigned long pc; | |
25eb4484 FB |
403 | int is_write; |
404 | ||
405 | pc = regs->nip; | |
25eb4484 FB |
406 | is_write = 0; |
407 | #if 0 | |
408 | /* ppc 4xx case */ | |
409 | if (regs->dsisr & 0x00800000) | |
410 | is_write = 1; | |
411 | #else | |
412 | if (regs->trap != 0x400 && (regs->dsisr & 0x02000000)) | |
413 | is_write = 1; | |
414 | #endif | |
415 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
2b413144 FB |
416 | is_write, &uc->uc_sigmask); |
417 | } | |
418 | ||
9de5e440 | 419 | #else |
2b413144 | 420 | |
25eb4484 | 421 | #error CPU specific signal handler needed |
2b413144 | 422 | |
9de5e440 | 423 | #endif |