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vga optimization (Glauber Costa)
[qemu.git] / exec.c
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54936004 1/*
fd6ce8f6 2 * virtual page mapping and translated block handling
5fafdf24 3 *
54936004
FB		 4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
67b915a5 20#include "config.h"
d5a8f07c 21#ifdef _WIN32
4fddf62a 22#define WIN32_LEAN_AND_MEAN
d5a8f07c
FB		 23#include <windows.h>
24#else
a98d49b1 25#include <sys/types.h>
d5a8f07c
FB		 26#include <sys/mman.h>
27#endif
54936004
FB		 28#include <stdlib.h>
29#include <stdio.h>
30#include <stdarg.h>
31#include <string.h>
32#include <errno.h>
33#include <unistd.h>
34#include <inttypes.h>
35
6180a181
FB		 36#include "cpu.h"
37#include "exec-all.h"
ca10f867 38#include "qemu-common.h"
b67d9a52 39#include "tcg.h"
b3c7724c 40#include "hw/hw.h"
74576198 41#include "osdep.h"
7ba1e619 42#include "kvm.h"
53a5960a
PB		 43#if defined(CONFIG_USER_ONLY)
44#include <qemu.h>
45#endif
54936004 46
fd6ce8f6 47//#define DEBUG_TB_INVALIDATE
66e85a21 48//#define DEBUG_FLUSH
9fa3e853 49//#define DEBUG_TLB
67d3b957 50//#define DEBUG_UNASSIGNED
fd6ce8f6
FB		 51
52/* make various TB consistency checks */
5fafdf24
TS		 53//#define DEBUG_TB_CHECK
54//#define DEBUG_TLB_CHECK
fd6ce8f6 55
1196be37 56//#define DEBUG_IOPORT
db7b5426 57//#define DEBUG_SUBPAGE
1196be37 58
99773bd4
PB		 59#if !defined(CONFIG_USER_ONLY)
60/* TB consistency checks only implemented for usermode emulation. */
61#undef DEBUG_TB_CHECK
62#endif
63
9fa3e853
FB		 64#define SMC_BITMAP_USE_THRESHOLD 10
65
66#define MMAP_AREA_START 0x00000000
67#define MMAP_AREA_END 0xa8000000
fd6ce8f6 68
108c49b8
FB		 69#if defined(TARGET_SPARC64)
70#define TARGET_PHYS_ADDR_SPACE_BITS 41
5dcb6b91
BS		 71#elif defined(TARGET_SPARC)
72#define TARGET_PHYS_ADDR_SPACE_BITS 36
bedb69ea
JM		 73#elif defined(TARGET_ALPHA)
74#define TARGET_PHYS_ADDR_SPACE_BITS 42
75#define TARGET_VIRT_ADDR_SPACE_BITS 42
108c49b8
FB		 76#elif defined(TARGET_PPC64)
77#define TARGET_PHYS_ADDR_SPACE_BITS 42
00f82b8a
AJ		 78#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
79#define TARGET_PHYS_ADDR_SPACE_BITS 42
80#elif defined(TARGET_I386) && !defined(USE_KQEMU)
81#define TARGET_PHYS_ADDR_SPACE_BITS 36
108c49b8
FB		 82#else
83/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
84#define TARGET_PHYS_ADDR_SPACE_BITS 32
85#endif
86
bdaf78e0 87static TranslationBlock *tbs;
26a5f13b 88int code_gen_max_blocks;
9fa3e853 89TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
bdaf78e0 90static int nb_tbs;
eb51d102
FB		 91/* any access to the tbs or the page table must use this lock */
92spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
fd6ce8f6 93
141ac468
BS		 94#if defined(__arm__) || defined(__sparc_v9__)
95/* The prologue must be reachable with a direct jump. ARM and Sparc64
96 have limited branch ranges (possibly also PPC) so place it in a
d03d860b
BS		 97 section close to code segment. */
98#define code_gen_section \
99 __attribute__((__section__(".gen_code"))) \
100 __attribute__((aligned (32)))
101#else
102#define code_gen_section \
103 __attribute__((aligned (32)))
104#endif
105
106uint8_t code_gen_prologue[1024] code_gen_section;
bdaf78e0
BS		 107static uint8_t *code_gen_buffer;
108static unsigned long code_gen_buffer_size;
26a5f13b 109/* threshold to flush the translated code buffer */
bdaf78e0 110static unsigned long code_gen_buffer_max_size;
fd6ce8f6
FB		 111uint8_t *code_gen_ptr;
112
e2eef170 113#if !defined(CONFIG_USER_ONLY)
00f82b8a 114ram_addr_t phys_ram_size;
9fa3e853
FB		 115int phys_ram_fd;
116uint8_t *phys_ram_base;
1ccde1cb 117uint8_t *phys_ram_dirty;
74576198 118static int in_migration;
e9a1ab19 119static ram_addr_t phys_ram_alloc_offset = 0;
e2eef170 120#endif
9fa3e853 121
6a00d601
FB		 122CPUState *first_cpu;
123/* current CPU in the current thread. It is only valid inside
124 cpu_exec() */
5fafdf24 125CPUState *cpu_single_env;
2e70f6ef 126/* 0 = Do not count executed instructions.
bf20dc07 127 1 = Precise instruction counting.
2e70f6ef
PB		 128 2 = Adaptive rate instruction counting. */
129int use_icount = 0;
130/* Current instruction counter. While executing translated code this may
131 include some instructions that have not yet been executed. */
132int64_t qemu_icount;
6a00d601 133
54936004 134typedef struct PageDesc {
92e873b9 135 /* list of TBs intersecting this ram page */
fd6ce8f6 136 TranslationBlock *first_tb;
9fa3e853
FB		 137 /* in order to optimize self modifying code, we count the number
138 of lookups we do to a given page to use a bitmap */
139 unsigned int code_write_count;
140 uint8_t *code_bitmap;
141#if defined(CONFIG_USER_ONLY)
142 unsigned long flags;
143#endif
54936004
FB		 144} PageDesc;
145
92e873b9 146typedef struct PhysPageDesc {
0f459d16 147 /* offset in host memory of the page + io_index in the low bits */
00f82b8a 148 ram_addr_t phys_offset;
92e873b9
FB		 149} PhysPageDesc;
150
54936004 151#define L2_BITS 10
bedb69ea
JM		 152#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
153/* XXX: this is a temporary hack for alpha target.
154 * In the future, this is to be replaced by a multi-level table
155 * to actually be able to handle the complete 64 bits address space.
156 */
157#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
158#else
03875444 159#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
bedb69ea 160#endif
54936004
FB		 161
162#define L1_SIZE (1 << L1_BITS)
163#define L2_SIZE (1 << L2_BITS)
164
83fb7adf
FB		 165unsigned long qemu_real_host_page_size;
166unsigned long qemu_host_page_bits;
167unsigned long qemu_host_page_size;
168unsigned long qemu_host_page_mask;
54936004 169
92e873b9 170/* XXX: for system emulation, it could just be an array */
54936004 171static PageDesc *l1_map[L1_SIZE];
bdaf78e0 172static PhysPageDesc **l1_phys_map;
54936004 173
e2eef170
PB		 174#if !defined(CONFIG_USER_ONLY)
175static void io_mem_init(void);
176
33417e70 177/* io memory support */
33417e70
FB		 178CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
179CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a 180void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70 181static int io_mem_nb;
6658ffb8
PB		 182static int io_mem_watch;
183#endif
33417e70 184
34865134 185/* log support */
d9b630fd 186static const char *logfilename = "/tmp/qemu.log";
34865134
FB		 187FILE *logfile;
188int loglevel;
e735b91c 189static int log_append = 0;
34865134 190
e3db7226
FB		 191/* statistics */
192static int tlb_flush_count;
193static int tb_flush_count;
194static int tb_phys_invalidate_count;
195
db7b5426
BS		 196#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
197typedef struct subpage_t {
198 target_phys_addr_t base;
3ee89922
BS		 199 CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
200 CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
201 void *opaque[TARGET_PAGE_SIZE][2][4];
db7b5426
BS		 202} subpage_t;
203
7cb69cae
FB		 204#ifdef _WIN32
205static void map_exec(void *addr, long size)
206{
207 DWORD old_protect;
208 VirtualProtect(addr, size,
209 PAGE_EXECUTE_READWRITE, &old_protect);
210
211}
212#else
213static void map_exec(void *addr, long size)
214{
4369415f 215 unsigned long start, end, page_size;
7cb69cae 216
4369415f 217 page_size = getpagesize();
7cb69cae 218 start = (unsigned long)addr;
4369415f 219 start &= ~(page_size - 1);
7cb69cae
FB		 220
221 end = (unsigned long)addr + size;
4369415f
FB		 222 end += page_size - 1;
223 end &= ~(page_size - 1);
7cb69cae
FB		 224
225 mprotect((void *)start, end - start,
226 PROT_READ | PROT_WRITE | PROT_EXEC);
227}
228#endif
229
b346ff46 230static void page_init(void)
54936004 231{
83fb7adf 232 /* NOTE: we can always suppose that qemu_host_page_size >=
54936004 233 TARGET_PAGE_SIZE */
c2b48b69
AL		 234#ifdef _WIN32
235 {
236 SYSTEM_INFO system_info;
237
238 GetSystemInfo(&system_info);
239 qemu_real_host_page_size = system_info.dwPageSize;
240 }
241#else
242 qemu_real_host_page_size = getpagesize();
243#endif
83fb7adf
FB		 244 if (qemu_host_page_size == 0)
245 qemu_host_page_size = qemu_real_host_page_size;
246 if (qemu_host_page_size < TARGET_PAGE_SIZE)
247 qemu_host_page_size = TARGET_PAGE_SIZE;
248 qemu_host_page_bits = 0;
249 while ((1 << qemu_host_page_bits) < qemu_host_page_size)
250 qemu_host_page_bits++;
251 qemu_host_page_mask = ~(qemu_host_page_size - 1);
108c49b8
FB		 252 l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
253 memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
50a9569b
AZ		 254
255#if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
256 {
257 long long startaddr, endaddr;
258 FILE *f;
259 int n;
260
c8a706fe 261 mmap_lock();
0776590d 262 last_brk = (unsigned long)sbrk(0);
50a9569b
AZ		 263 f = fopen("/proc/self/maps", "r");
264 if (f) {
265 do {
266 n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
267 if (n == 2) {
e0b8d65a
BS		 268 startaddr = MIN(startaddr,
269 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
270 endaddr = MIN(endaddr,
271 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
b5fc909e 272 page_set_flags(startaddr & TARGET_PAGE_MASK,
50a9569b
AZ		 273 TARGET_PAGE_ALIGN(endaddr),
274 PAGE_RESERVED);
275 }
276 } while (!feof(f));
277 fclose(f);
278 }
c8a706fe 279 mmap_unlock();
50a9569b
AZ		 280 }
281#endif
54936004
FB		 282}
283
434929bf 284static inline PageDesc **page_l1_map(target_ulong index)
54936004 285{
17e2377a
PB		 286#if TARGET_LONG_BITS > 32
287 /* Host memory outside guest VM. For 32-bit targets we have already
288 excluded high addresses. */
d8173e0f 289 if (index > ((target_ulong)L2_SIZE * L1_SIZE))
17e2377a
PB		 290 return NULL;
291#endif
434929bf
AL		 292 return &l1_map[index >> L2_BITS];
293}
294
295static inline PageDesc *page_find_alloc(target_ulong index)
296{
297 PageDesc **lp, *p;
298 lp = page_l1_map(index);
299 if (!lp)
300 return NULL;
301
54936004
FB		 302 p = *lp;
303 if (!p) {
304 /* allocate if not found */
17e2377a
PB		 305#if defined(CONFIG_USER_ONLY)
306 unsigned long addr;
307 size_t len = sizeof(PageDesc) * L2_SIZE;
308 /* Don't use qemu_malloc because it may recurse. */
309 p = mmap(0, len, PROT_READ | PROT_WRITE,
310 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
54936004 311 *lp = p;
17e2377a
PB		 312 addr = h2g(p);
313 if (addr == (target_ulong)addr) {
314 page_set_flags(addr & TARGET_PAGE_MASK,
315 TARGET_PAGE_ALIGN(addr + len),
316 PAGE_RESERVED);
317 }
318#else
319 p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
320 *lp = p;
321#endif
54936004
FB		 322 }
323 return p + (index & (L2_SIZE - 1));
324}
325
00f82b8a 326static inline PageDesc *page_find(target_ulong index)
54936004 327{
434929bf
AL		 328 PageDesc **lp, *p;
329 lp = page_l1_map(index);
330 if (!lp)
331 return NULL;
54936004 332
434929bf 333 p = *lp;
54936004
FB		 334 if (!p)
335 return 0;
fd6ce8f6
FB		 336 return p + (index & (L2_SIZE - 1));
337}
338
108c49b8 339static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
92e873b9 340{
108c49b8 341 void **lp, **p;
e3f4e2a4 342 PhysPageDesc *pd;
92e873b9 343
108c49b8
FB		 344 p = (void **)l1_phys_map;
345#if TARGET_PHYS_ADDR_SPACE_BITS > 32
346
347#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
348#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
349#endif
350 lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
92e873b9
FB		 351 p = *lp;
352 if (!p) {
353 /* allocate if not found */
108c49b8
FB		 354 if (!alloc)
355 return NULL;
356 p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
357 memset(p, 0, sizeof(void *) * L1_SIZE);
358 *lp = p;
359 }
360#endif
361 lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
e3f4e2a4
PB		 362 pd = *lp;
363 if (!pd) {
364 int i;
108c49b8
FB		 365 /* allocate if not found */
366 if (!alloc)
367 return NULL;
e3f4e2a4
PB		 368 pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
369 *lp = pd;
370 for (i = 0; i < L2_SIZE; i++)
371 pd[i].phys_offset = IO_MEM_UNASSIGNED;
92e873b9 372 }
e3f4e2a4 373 return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
92e873b9
FB		 374}
375
108c49b8 376static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
92e873b9 377{
108c49b8 378 return phys_page_find_alloc(index, 0);
92e873b9
FB		 379}
380
9fa3e853 381#if !defined(CONFIG_USER_ONLY)
6a00d601 382static void tlb_protect_code(ram_addr_t ram_addr);
5fafdf24 383static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
3a7d929e 384 target_ulong vaddr);
c8a706fe
PB		 385#define mmap_lock() do { } while(0)
386#define mmap_unlock() do { } while(0)
9fa3e853 387#endif
fd6ce8f6 388
4369415f
FB		 389#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
390
391#if defined(CONFIG_USER_ONLY)
392/* Currently it is not recommanded to allocate big chunks of data in
393 user mode. It will change when a dedicated libc will be used */
394#define USE_STATIC_CODE_GEN_BUFFER
395#endif
396
397#ifdef USE_STATIC_CODE_GEN_BUFFER
398static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
399#endif
400
8fcd3692 401static void code_gen_alloc(unsigned long tb_size)
26a5f13b 402{
4369415f
FB		 403#ifdef USE_STATIC_CODE_GEN_BUFFER
404 code_gen_buffer = static_code_gen_buffer;
405 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
406 map_exec(code_gen_buffer, code_gen_buffer_size);
407#else
26a5f13b
FB		 408 code_gen_buffer_size = tb_size;
409 if (code_gen_buffer_size == 0) {
4369415f
FB		 410#if defined(CONFIG_USER_ONLY)
411 /* in user mode, phys_ram_size is not meaningful */
412 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
413#else
26a5f13b 414 /* XXX: needs ajustments */
174a9a1f 415 code_gen_buffer_size = (unsigned long)(phys_ram_size / 4);
4369415f 416#endif
26a5f13b
FB		 417 }
418 if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
419 code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
420 /* The code gen buffer location may have constraints depending on
421 the host cpu and OS */
422#if defined(__linux__)
423 {
424 int flags;
141ac468
BS		 425 void *start = NULL;
426
26a5f13b
FB		 427 flags = MAP_PRIVATE | MAP_ANONYMOUS;
428#if defined(__x86_64__)
429 flags |= MAP_32BIT;
430 /* Cannot map more than that */
431 if (code_gen_buffer_size > (800 * 1024 * 1024))
432 code_gen_buffer_size = (800 * 1024 * 1024);
141ac468
BS		 433#elif defined(__sparc_v9__)
434 // Map the buffer below 2G, so we can use direct calls and branches
435 flags |= MAP_FIXED;
436 start = (void *) 0x60000000UL;
437 if (code_gen_buffer_size > (512 * 1024 * 1024))
438 code_gen_buffer_size = (512 * 1024 * 1024);
26a5f13b 439#endif
141ac468
BS		 440 code_gen_buffer = mmap(start, code_gen_buffer_size,
441 PROT_WRITE | PROT_READ | PROT_EXEC,
26a5f13b
FB		 442 flags, -1, 0);
443 if (code_gen_buffer == MAP_FAILED) {
444 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
445 exit(1);
446 }
447 }
06e67a82
AL		 448#elif defined(__FreeBSD__)
449 {
450 int flags;
451 void *addr = NULL;
452 flags = MAP_PRIVATE | MAP_ANONYMOUS;
453#if defined(__x86_64__)
454 /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
455 * 0x40000000 is free */
456 flags |= MAP_FIXED;
457 addr = (void *)0x40000000;
458 /* Cannot map more than that */
459 if (code_gen_buffer_size > (800 * 1024 * 1024))
460 code_gen_buffer_size = (800 * 1024 * 1024);
461#endif
462 code_gen_buffer = mmap(addr, code_gen_buffer_size,
463 PROT_WRITE | PROT_READ | PROT_EXEC,
464 flags, -1, 0);
465 if (code_gen_buffer == MAP_FAILED) {
466 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
467 exit(1);
468 }
469 }
26a5f13b
FB		 470#else
471 code_gen_buffer = qemu_malloc(code_gen_buffer_size);
472 if (!code_gen_buffer) {
473 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
474 exit(1);
475 }
476 map_exec(code_gen_buffer, code_gen_buffer_size);
477#endif
4369415f 478#endif /* !USE_STATIC_CODE_GEN_BUFFER */
26a5f13b
FB		 479 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
480 code_gen_buffer_max_size = code_gen_buffer_size -
481 code_gen_max_block_size();
482 code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
483 tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
484}
485
486/* Must be called before using the QEMU cpus. 'tb_size' is the size
487 (in bytes) allocated to the translation buffer. Zero means default
488 size. */
489void cpu_exec_init_all(unsigned long tb_size)
490{
26a5f13b
FB		 491 cpu_gen_init();
492 code_gen_alloc(tb_size);
493 code_gen_ptr = code_gen_buffer;
4369415f 494 page_init();
e2eef170 495#if !defined(CONFIG_USER_ONLY)
26a5f13b 496 io_mem_init();
e2eef170 497#endif
26a5f13b
FB		 498}
499
9656f324
PB		 500#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
501
502#define CPU_COMMON_SAVE_VERSION 1
503
504static void cpu_common_save(QEMUFile *f, void *opaque)
505{
506 CPUState *env = opaque;
507
508 qemu_put_be32s(f, &env->halted);
509 qemu_put_be32s(f, &env->interrupt_request);
510}
511
512static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
513{
514 CPUState *env = opaque;
515
516 if (version_id != CPU_COMMON_SAVE_VERSION)
517 return -EINVAL;
518
519 qemu_get_be32s(f, &env->halted);
75f482ae 520 qemu_get_be32s(f, &env->interrupt_request);
9656f324
PB		 521 tlb_flush(env, 1);
522
523 return 0;
524}
525#endif
526
6a00d601 527void cpu_exec_init(CPUState *env)
fd6ce8f6 528{
6a00d601
FB		 529 CPUState **penv;
530 int cpu_index;
531
6a00d601
FB		 532 env->next_cpu = NULL;
533 penv = &first_cpu;
534 cpu_index = 0;
535 while (*penv != NULL) {
536 penv = (CPUState **)&(*penv)->next_cpu;
537 cpu_index++;
538 }
539 env->cpu_index = cpu_index;
540 *penv = env;
b3c7724c 541#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
9656f324
PB		 542 register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
543 cpu_common_save, cpu_common_load, env);
b3c7724c
PB		 544 register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
545 cpu_save, cpu_load, env);
546#endif
fd6ce8f6
FB		 547}
548
9fa3e853
FB		 549static inline void invalidate_page_bitmap(PageDesc *p)
550{
551 if (p->code_bitmap) {
59817ccb 552 qemu_free(p->code_bitmap);
9fa3e853
FB		 553 p->code_bitmap = NULL;
554 }
555 p->code_write_count = 0;
556}
557
fd6ce8f6
FB		 558/* set to NULL all the 'first_tb' fields in all PageDescs */
559static void page_flush_tb(void)
560{
561 int i, j;
562 PageDesc *p;
563
564 for(i = 0; i < L1_SIZE; i++) {
565 p = l1_map[i];
566 if (p) {
9fa3e853
FB		 567 for(j = 0; j < L2_SIZE; j++) {
568 p->first_tb = NULL;
569 invalidate_page_bitmap(p);
570 p++;
571 }
fd6ce8f6
FB		 572 }
573 }
574}
575
576/* flush all the translation blocks */
d4e8164f 577/* XXX: tb_flush is currently not thread safe */
6a00d601 578void tb_flush(CPUState *env1)
fd6ce8f6 579{
6a00d601 580 CPUState *env;
0124311e 581#if defined(DEBUG_FLUSH)
ab3d1727
BS		 582 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
583 (unsigned long)(code_gen_ptr - code_gen_buffer),
584 nb_tbs, nb_tbs > 0 ?
585 ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
fd6ce8f6 586#endif
26a5f13b 587 if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
a208e54a
PB		 588 cpu_abort(env1, "Internal error: code buffer overflow\n");
589
fd6ce8f6 590 nb_tbs = 0;
3b46e624 591
6a00d601
FB		 592 for(env = first_cpu; env != NULL; env = env->next_cpu) {
593 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
594 }
9fa3e853 595
8a8a608f 596 memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
fd6ce8f6 597 page_flush_tb();
9fa3e853 598
fd6ce8f6 599 code_gen_ptr = code_gen_buffer;
d4e8164f
FB		 600 /* XXX: flush processor icache at this point if cache flush is
601 expensive */
e3db7226 602 tb_flush_count++;
fd6ce8f6
FB		 603}
604
605#ifdef DEBUG_TB_CHECK
606
bc98a7ef 607static void tb_invalidate_check(target_ulong address)
fd6ce8f6
FB		 608{
609 TranslationBlock *tb;
610 int i;
611 address &= TARGET_PAGE_MASK;
99773bd4
PB		 612 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
613 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
fd6ce8f6
FB		 614 if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
615 address >= tb->pc + tb->size)) {
616 printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
99773bd4 617 address, (long)tb->pc, tb->size);
fd6ce8f6
FB		 618 }
619 }
620 }
621}
622
623/* verify that all the pages have correct rights for code */
624static void tb_page_check(void)
625{
626 TranslationBlock *tb;
627 int i, flags1, flags2;
3b46e624 628
99773bd4
PB		 629 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
630 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
fd6ce8f6
FB		 631 flags1 = page_get_flags(tb->pc);
632 flags2 = page_get_flags(tb->pc + tb->size - 1);
633 if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
634 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
99773bd4 635 (long)tb->pc, tb->size, flags1, flags2);
fd6ce8f6
FB		 636 }
637 }
638 }
639}
640
bdaf78e0 641static void tb_jmp_check(TranslationBlock *tb)
d4e8164f
FB		 642{
643 TranslationBlock *tb1;
644 unsigned int n1;
645
646 /* suppress any remaining jumps to this TB */
647 tb1 = tb->jmp_first;
648 for(;;) {
649 n1 = (long)tb1 & 3;
650 tb1 = (TranslationBlock *)((long)tb1 & ~3);
651 if (n1 == 2)
652 break;
653 tb1 = tb1->jmp_next[n1];
654 }
655 /* check end of list */
656 if (tb1 != tb) {
657 printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
658 }
659}
660
fd6ce8f6
FB		 661#endif
662
663/* invalidate one TB */
664static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
665 int next_offset)
666{
667 TranslationBlock *tb1;
668 for(;;) {
669 tb1 = *ptb;
670 if (tb1 == tb) {
671 *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
672 break;
673 }
674 ptb = (TranslationBlock **)((char *)tb1 + next_offset);
675 }
676}
677
9fa3e853
FB		 678static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
679{
680 TranslationBlock *tb1;
681 unsigned int n1;
682
683 for(;;) {
684 tb1 = *ptb;
685 n1 = (long)tb1 & 3;
686 tb1 = (TranslationBlock *)((long)tb1 & ~3);
687 if (tb1 == tb) {
688 *ptb = tb1->page_next[n1];
689 break;
690 }
691 ptb = &tb1->page_next[n1];
692 }
693}
694
d4e8164f
FB		 695static inline void tb_jmp_remove(TranslationBlock *tb, int n)
696{
697 TranslationBlock *tb1, **ptb;
698 unsigned int n1;
699
700 ptb = &tb->jmp_next[n];
701 tb1 = *ptb;
702 if (tb1) {
703 /* find tb(n) in circular list */
704 for(;;) {
705 tb1 = *ptb;
706 n1 = (long)tb1 & 3;
707 tb1 = (TranslationBlock *)((long)tb1 & ~3);
708 if (n1 == n && tb1 == tb)
709 break;
710 if (n1 == 2) {
711 ptb = &tb1->jmp_first;
712 } else {
713 ptb = &tb1->jmp_next[n1];
714 }
715 }
716 /* now we can suppress tb(n) from the list */
717 *ptb = tb->jmp_next[n];
718
719 tb->jmp_next[n] = NULL;
720 }
721}
722
723/* reset the jump entry 'n' of a TB so that it is not chained to
724 another TB */
725static inline void tb_reset_jump(TranslationBlock *tb, int n)
726{
727 tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
728}
729
2e70f6ef 730void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
fd6ce8f6 731{
6a00d601 732 CPUState *env;
8a40a180 733 PageDesc *p;
d4e8164f 734 unsigned int h, n1;
00f82b8a 735 target_phys_addr_t phys_pc;
8a40a180 736 TranslationBlock *tb1, *tb2;
3b46e624 737
8a40a180
FB		 738 /* remove the TB from the hash list */
739 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
740 h = tb_phys_hash_func(phys_pc);
5fafdf24 741 tb_remove(&tb_phys_hash[h], tb,
8a40a180
FB		 742 offsetof(TranslationBlock, phys_hash_next));
743
744 /* remove the TB from the page list */
745 if (tb->page_addr[0] != page_addr) {
746 p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
747 tb_page_remove(&p->first_tb, tb);
748 invalidate_page_bitmap(p);
749 }
750 if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
751 p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
752 tb_page_remove(&p->first_tb, tb);
753 invalidate_page_bitmap(p);
754 }
755
36bdbe54 756 tb_invalidated_flag = 1;
59817ccb 757
fd6ce8f6 758 /* remove the TB from the hash list */
8a40a180 759 h = tb_jmp_cache_hash_func(tb->pc);
6a00d601
FB		 760 for(env = first_cpu; env != NULL; env = env->next_cpu) {
761 if (env->tb_jmp_cache[h] == tb)
762 env->tb_jmp_cache[h] = NULL;
763 }
d4e8164f
FB		 764
765 /* suppress this TB from the two jump lists */
766 tb_jmp_remove(tb, 0);
767 tb_jmp_remove(tb, 1);
768
769 /* suppress any remaining jumps to this TB */
770 tb1 = tb->jmp_first;
771 for(;;) {
772 n1 = (long)tb1 & 3;
773 if (n1 == 2)
774 break;
775 tb1 = (TranslationBlock *)((long)tb1 & ~3);
776 tb2 = tb1->jmp_next[n1];
777 tb_reset_jump(tb1, n1);
778 tb1->jmp_next[n1] = NULL;
779 tb1 = tb2;
780 }
781 tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
9fa3e853 782
e3db7226 783 tb_phys_invalidate_count++;
9fa3e853
FB		 784}
785
786static inline void set_bits(uint8_t *tab, int start, int len)
787{
788 int end, mask, end1;
789
790 end = start + len;
791 tab += start >> 3;
792 mask = 0xff << (start & 7);
793 if ((start & ~7) == (end & ~7)) {
794 if (start < end) {
795 mask &= ~(0xff << (end & 7));
796 *tab |= mask;
797 }
798 } else {
799 *tab++ |= mask;
800 start = (start + 8) & ~7;
801 end1 = end & ~7;
802 while (start < end1) {
803 *tab++ = 0xff;
804 start += 8;
805 }
806 if (start < end) {
807 mask = ~(0xff << (end & 7));
808 *tab |= mask;
809 }
810 }
811}
812
813static void build_page_bitmap(PageDesc *p)
814{
815 int n, tb_start, tb_end;
816 TranslationBlock *tb;
3b46e624 817
b2a7081a 818 p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
9fa3e853
FB		 819 if (!p->code_bitmap)
820 return;
9fa3e853
FB		 821
822 tb = p->first_tb;
823 while (tb != NULL) {
824 n = (long)tb & 3;
825 tb = (TranslationBlock *)((long)tb & ~3);
826 /* NOTE: this is subtle as a TB may span two physical pages */
827 if (n == 0) {
828 /* NOTE: tb_end may be after the end of the page, but
829 it is not a problem */
830 tb_start = tb->pc & ~TARGET_PAGE_MASK;
831 tb_end = tb_start + tb->size;
832 if (tb_end > TARGET_PAGE_SIZE)
833 tb_end = TARGET_PAGE_SIZE;
834 } else {
835 tb_start = 0;
836 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
837 }
838 set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
839 tb = tb->page_next[n];
840 }
841}
842
2e70f6ef
PB		 843TranslationBlock *tb_gen_code(CPUState *env,
844 target_ulong pc, target_ulong cs_base,
845 int flags, int cflags)
d720b93d
FB		 846{
847 TranslationBlock *tb;
848 uint8_t *tc_ptr;
849 target_ulong phys_pc, phys_page2, virt_page2;
850 int code_gen_size;
851
c27004ec
FB		 852 phys_pc = get_phys_addr_code(env, pc);
853 tb = tb_alloc(pc);
d720b93d
FB		 854 if (!tb) {
855 /* flush must be done */
856 tb_flush(env);
857 /* cannot fail at this point */
c27004ec 858 tb = tb_alloc(pc);
2e70f6ef
PB		 859 /* Don't forget to invalidate previous TB info. */
860 tb_invalidated_flag = 1;
d720b93d
FB		 861 }
862 tc_ptr = code_gen_ptr;
863 tb->tc_ptr = tc_ptr;
864 tb->cs_base = cs_base;
865 tb->flags = flags;
866 tb->cflags = cflags;
d07bde88 867 cpu_gen_code(env, tb, &code_gen_size);
d720b93d 868 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
3b46e624 869
d720b93d 870 /* check next page if needed */
c27004ec 871 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
d720b93d 872 phys_page2 = -1;
c27004ec 873 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
d720b93d
FB		 874 phys_page2 = get_phys_addr_code(env, virt_page2);
875 }
876 tb_link_phys(tb, phys_pc, phys_page2);
2e70f6ef 877 return tb;
d720b93d 878}
3b46e624 879
9fa3e853
FB		 880/* invalidate all TBs which intersect with the target physical page
881 starting in range [start;end[. NOTE: start and end must refer to
d720b93d
FB		 882 the same physical page. 'is_cpu_write_access' should be true if called
883 from a real cpu write access: the virtual CPU will exit the current
884 TB if code is modified inside this TB. */
00f82b8a 885void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
d720b93d
FB		 886 int is_cpu_write_access)
887{
6b917547 888 TranslationBlock *tb, *tb_next, *saved_tb;
d720b93d 889 CPUState *env = cpu_single_env;
9fa3e853 890 target_ulong tb_start, tb_end;
6b917547
AL		 891 PageDesc *p;
892 int n;
893#ifdef TARGET_HAS_PRECISE_SMC
894 int current_tb_not_found = is_cpu_write_access;
895 TranslationBlock *current_tb = NULL;
896 int current_tb_modified = 0;
897 target_ulong current_pc = 0;
898 target_ulong current_cs_base = 0;
899 int current_flags = 0;
900#endif /* TARGET_HAS_PRECISE_SMC */
9fa3e853
FB		 901
902 p = page_find(start >> TARGET_PAGE_BITS);
5fafdf24 903 if (!p)
9fa3e853 904 return;
5fafdf24 905 if (!p->code_bitmap &&
d720b93d
FB		 906 ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
907 is_cpu_write_access) {
9fa3e853
FB		 908 /* build code bitmap */
909 build_page_bitmap(p);
910 }
911
912 /* we remove all the TBs in the range [start, end[ */
913 /* XXX: see if in some cases it could be faster to invalidate all the code */
914 tb = p->first_tb;
915 while (tb != NULL) {
916 n = (long)tb & 3;
917 tb = (TranslationBlock *)((long)tb & ~3);
918 tb_next = tb->page_next[n];
919 /* NOTE: this is subtle as a TB may span two physical pages */
920 if (n == 0) {
921 /* NOTE: tb_end may be after the end of the page, but
922 it is not a problem */
923 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
924 tb_end = tb_start + tb->size;
925 } else {
926 tb_start = tb->page_addr[1];
927 tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
928 }
929 if (!(tb_end <= start || tb_start >= end)) {
d720b93d
FB		 930#ifdef TARGET_HAS_PRECISE_SMC
931 if (current_tb_not_found) {
932 current_tb_not_found = 0;
933 current_tb = NULL;
2e70f6ef 934 if (env->mem_io_pc) {
d720b93d 935 /* now we have a real cpu fault */
2e70f6ef 936 current_tb = tb_find_pc(env->mem_io_pc);
d720b93d
FB		 937 }
938 }
939 if (current_tb == tb &&
2e70f6ef 940 (current_tb->cflags & CF_COUNT_MASK) != 1) {
d720b93d
FB		 941 /* If we are modifying the current TB, we must stop
942 its execution. We could be more precise by checking
943 that the modification is after the current PC, but it
944 would require a specialized function to partially
945 restore the CPU state */
3b46e624 946
d720b93d 947 current_tb_modified = 1;
5fafdf24 948 cpu_restore_state(current_tb, env,
2e70f6ef 949 env->mem_io_pc, NULL);
6b917547
AL		 950 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
951 &current_flags);
d720b93d
FB		 952 }
953#endif /* TARGET_HAS_PRECISE_SMC */
6f5a9f7e
FB		 954 /* we need to do that to handle the case where a signal
955 occurs while doing tb_phys_invalidate() */
956 saved_tb = NULL;
957 if (env) {
958 saved_tb = env->current_tb;
959 env->current_tb = NULL;
960 }
9fa3e853 961 tb_phys_invalidate(tb, -1);
6f5a9f7e
FB		 962 if (env) {
963 env->current_tb = saved_tb;
964 if (env->interrupt_request && env->current_tb)
965 cpu_interrupt(env, env->interrupt_request);
966 }
9fa3e853
FB		 967 }
968 tb = tb_next;
969 }
970#if !defined(CONFIG_USER_ONLY)
971 /* if no code remaining, no need to continue to use slow writes */
972 if (!p->first_tb) {
973 invalidate_page_bitmap(p);
d720b93d 974 if (is_cpu_write_access) {
2e70f6ef 975 tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
d720b93d
FB		 976 }
977 }
978#endif
979#ifdef TARGET_HAS_PRECISE_SMC
980 if (current_tb_modified) {
981 /* we generate a block containing just the instruction
982 modifying the memory. It will ensure that it cannot modify
983 itself */
ea1c1802 984 env->current_tb = NULL;
2e70f6ef 985 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
d720b93d 986 cpu_resume_from_signal(env, NULL);
9fa3e853 987 }
fd6ce8f6 988#endif
9fa3e853 989}
fd6ce8f6 990
9fa3e853 991/* len must be <= 8 and start must be a multiple of len */
00f82b8a 992static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
9fa3e853
FB		 993{
994 PageDesc *p;
995 int offset, b;
59817ccb 996#if 0
a4193c8a
FB		 997 if (1) {
998 if (loglevel) {
5fafdf24 999 fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
2e70f6ef 1000 cpu_single_env->mem_io_vaddr, len,
5fafdf24 1001 cpu_single_env->eip,
a4193c8a
FB		 1002 cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
1003 }
59817ccb
FB		 1004 }
1005#endif
9fa3e853 1006 p = page_find(start >> TARGET_PAGE_BITS);
5fafdf24 1007 if (!p)
9fa3e853
FB		 1008 return;
1009 if (p->code_bitmap) {
1010 offset = start & ~TARGET_PAGE_MASK;
1011 b = p->code_bitmap[offset >> 3] >> (offset & 7);
1012 if (b & ((1 << len) - 1))
1013 goto do_invalidate;
1014 } else {
1015 do_invalidate:
d720b93d 1016 tb_invalidate_phys_page_range(start, start + len, 1);
9fa3e853
FB		 1017 }
1018}
1019
9fa3e853 1020#if !defined(CONFIG_SOFTMMU)
00f82b8a 1021static void tb_invalidate_phys_page(target_phys_addr_t addr,
d720b93d 1022 unsigned long pc, void *puc)
9fa3e853 1023{
6b917547 1024 TranslationBlock *tb;
9fa3e853 1025 PageDesc *p;
6b917547 1026 int n;
d720b93d 1027#ifdef TARGET_HAS_PRECISE_SMC
6b917547 1028 TranslationBlock *current_tb = NULL;
d720b93d 1029 CPUState *env = cpu_single_env;
6b917547
AL		 1030 int current_tb_modified = 0;
1031 target_ulong current_pc = 0;
1032 target_ulong current_cs_base = 0;
1033 int current_flags = 0;
d720b93d 1034#endif
9fa3e853
FB		 1035
1036 addr &= TARGET_PAGE_MASK;
1037 p = page_find(addr >> TARGET_PAGE_BITS);
5fafdf24 1038 if (!p)
9fa3e853
FB		 1039 return;
1040 tb = p->first_tb;
d720b93d
FB		 1041#ifdef TARGET_HAS_PRECISE_SMC
1042 if (tb && pc != 0) {
1043 current_tb = tb_find_pc(pc);
1044 }
1045#endif
9fa3e853
FB		 1046 while (tb != NULL) {
1047 n = (long)tb & 3;
1048 tb = (TranslationBlock *)((long)tb & ~3);
d720b93d
FB		 1049#ifdef TARGET_HAS_PRECISE_SMC
1050 if (current_tb == tb &&
2e70f6ef 1051 (current_tb->cflags & CF_COUNT_MASK) != 1) {
d720b93d
FB		 1052 /* If we are modifying the current TB, we must stop
1053 its execution. We could be more precise by checking
1054 that the modification is after the current PC, but it
1055 would require a specialized function to partially
1056 restore the CPU state */
3b46e624 1057
d720b93d
FB		 1058 current_tb_modified = 1;
1059 cpu_restore_state(current_tb, env, pc, puc);
6b917547
AL		 1060 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
1061 &current_flags);
d720b93d
FB		 1062 }
1063#endif /* TARGET_HAS_PRECISE_SMC */
9fa3e853
FB		 1064 tb_phys_invalidate(tb, addr);
1065 tb = tb->page_next[n];
1066 }
fd6ce8f6 1067 p->first_tb = NULL;
d720b93d
FB		 1068#ifdef TARGET_HAS_PRECISE_SMC
1069 if (current_tb_modified) {
1070 /* we generate a block containing just the instruction
1071 modifying the memory. It will ensure that it cannot modify
1072 itself */
ea1c1802 1073 env->current_tb = NULL;
2e70f6ef 1074 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
d720b93d
FB		 1075 cpu_resume_from_signal(env, puc);
1076 }
1077#endif
fd6ce8f6 1078}
9fa3e853 1079#endif
fd6ce8f6
FB		 1080
1081/* add the tb in the target page and protect it if necessary */
5fafdf24 1082static inline void tb_alloc_page(TranslationBlock *tb,
53a5960a 1083 unsigned int n, target_ulong page_addr)
fd6ce8f6
FB		 1084{
1085 PageDesc *p;
9fa3e853
FB		 1086 TranslationBlock *last_first_tb;
1087
1088 tb->page_addr[n] = page_addr;
3a7d929e 1089 p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
9fa3e853
FB		 1090 tb->page_next[n] = p->first_tb;
1091 last_first_tb = p->first_tb;
1092 p->first_tb = (TranslationBlock *)((long)tb | n);
1093 invalidate_page_bitmap(p);
fd6ce8f6 1094
107db443 1095#if defined(TARGET_HAS_SMC) || 1
d720b93d 1096
9fa3e853 1097#if defined(CONFIG_USER_ONLY)
fd6ce8f6 1098 if (p->flags & PAGE_WRITE) {
53a5960a
PB		 1099 target_ulong addr;
1100 PageDesc *p2;
9fa3e853
FB		 1101 int prot;
1102
fd6ce8f6
FB		 1103 /* force the host page as non writable (writes will have a
1104 page fault + mprotect overhead) */
53a5960a 1105 page_addr &= qemu_host_page_mask;
fd6ce8f6 1106 prot = 0;
53a5960a
PB		 1107 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1108 addr += TARGET_PAGE_SIZE) {
1109
1110 p2 = page_find (addr >> TARGET_PAGE_BITS);
1111 if (!p2)
1112 continue;
1113 prot |= p2->flags;
1114 p2->flags &= ~PAGE_WRITE;
1115 page_get_flags(addr);
1116 }
5fafdf24 1117 mprotect(g2h(page_addr), qemu_host_page_size,
fd6ce8f6
FB		 1118 (prot & PAGE_BITS) & ~PAGE_WRITE);
1119#ifdef DEBUG_TB_INVALIDATE
ab3d1727 1120 printf("protecting code page: 0x" TARGET_FMT_lx "\n",
53a5960a 1121 page_addr);
fd6ce8f6 1122#endif
fd6ce8f6 1123 }
9fa3e853
FB		 1124#else
1125 /* if some code is already present, then the pages are already
1126 protected. So we handle the case where only the first TB is
1127 allocated in a physical page */
1128 if (!last_first_tb) {
6a00d601 1129 tlb_protect_code(page_addr);
9fa3e853
FB		 1130 }
1131#endif
d720b93d
FB		 1132
1133#endif /* TARGET_HAS_SMC */
fd6ce8f6
FB		 1134}
1135
1136/* Allocate a new translation block. Flush the translation buffer if
1137 too many translation blocks or too much generated code. */
c27004ec 1138TranslationBlock *tb_alloc(target_ulong pc)
fd6ce8f6
FB		 1139{
1140 TranslationBlock *tb;
fd6ce8f6 1141
26a5f13b
FB		 1142 if (nb_tbs >= code_gen_max_blocks ||
1143 (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
d4e8164f 1144 return NULL;
fd6ce8f6
FB		 1145 tb = &tbs[nb_tbs++];
1146 tb->pc = pc;
b448f2f3 1147 tb->cflags = 0;
d4e8164f
FB		 1148 return tb;
1149}
1150
2e70f6ef
PB		 1151void tb_free(TranslationBlock *tb)
1152{
bf20dc07 1153 /* In practice this is mostly used for single use temporary TB
2e70f6ef
PB		 1154 Ignore the hard cases and just back up if this TB happens to
1155 be the last one generated. */
1156 if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
1157 code_gen_ptr = tb->tc_ptr;
1158 nb_tbs--;
1159 }
1160}
1161
9fa3e853
FB		 1162/* add a new TB and link it to the physical page tables. phys_page2 is
1163 (-1) to indicate that only one page contains the TB. */
5fafdf24 1164void tb_link_phys(TranslationBlock *tb,
9fa3e853 1165 target_ulong phys_pc, target_ulong phys_page2)
d4e8164f 1166{
9fa3e853
FB		 1167 unsigned int h;
1168 TranslationBlock **ptb;
1169
c8a706fe
PB		 1170 /* Grab the mmap lock to stop another thread invalidating this TB
1171 before we are done. */
1172 mmap_lock();
9fa3e853
FB		 1173 /* add in the physical hash table */
1174 h = tb_phys_hash_func(phys_pc);
1175 ptb = &tb_phys_hash[h];
1176 tb->phys_hash_next = *ptb;
1177 *ptb = tb;
fd6ce8f6
FB		 1178
1179 /* add in the page list */
9fa3e853
FB		 1180 tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
1181 if (phys_page2 != -1)
1182 tb_alloc_page(tb, 1, phys_page2);
1183 else
1184 tb->page_addr[1] = -1;
9fa3e853 1185
d4e8164f
FB		 1186 tb->jmp_first = (TranslationBlock *)((long)tb | 2);
1187 tb->jmp_next[0] = NULL;
1188 tb->jmp_next[1] = NULL;
1189
1190 /* init original jump addresses */
1191 if (tb->tb_next_offset[0] != 0xffff)
1192 tb_reset_jump(tb, 0);
1193 if (tb->tb_next_offset[1] != 0xffff)
1194 tb_reset_jump(tb, 1);
8a40a180
FB		 1195
1196#ifdef DEBUG_TB_CHECK
1197 tb_page_check();
1198#endif
c8a706fe 1199 mmap_unlock();
fd6ce8f6
FB		 1200}
1201
9fa3e853
FB		 1202/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1203 tb[1].tc_ptr. Return NULL if not found */
1204TranslationBlock *tb_find_pc(unsigned long tc_ptr)
fd6ce8f6 1205{
9fa3e853
FB		 1206 int m_min, m_max, m;
1207 unsigned long v;
1208 TranslationBlock *tb;
a513fe19
FB		 1209
1210 if (nb_tbs <= 0)
1211 return NULL;
1212 if (tc_ptr < (unsigned long)code_gen_buffer ||
1213 tc_ptr >= (unsigned long)code_gen_ptr)
1214 return NULL;
1215 /* binary search (cf Knuth) */
1216 m_min = 0;
1217 m_max = nb_tbs - 1;
1218 while (m_min <= m_max) {
1219 m = (m_min + m_max) >> 1;
1220 tb = &tbs[m];
1221 v = (unsigned long)tb->tc_ptr;
1222 if (v == tc_ptr)
1223 return tb;
1224 else if (tc_ptr < v) {
1225 m_max = m - 1;
1226 } else {
1227 m_min = m + 1;
1228 }
5fafdf24 1229 }
a513fe19
FB		 1230 return &tbs[m_max];
1231}
7501267e 1232
ea041c0e
FB		 1233static void tb_reset_jump_recursive(TranslationBlock *tb);
1234
1235static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1236{
1237 TranslationBlock *tb1, *tb_next, **ptb;
1238 unsigned int n1;
1239
1240 tb1 = tb->jmp_next[n];
1241 if (tb1 != NULL) {
1242 /* find head of list */
1243 for(;;) {
1244 n1 = (long)tb1 & 3;
1245 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1246 if (n1 == 2)
1247 break;
1248 tb1 = tb1->jmp_next[n1];
1249 }
1250 /* we are now sure now that tb jumps to tb1 */
1251 tb_next = tb1;
1252
1253 /* remove tb from the jmp_first list */
1254 ptb = &tb_next->jmp_first;
1255 for(;;) {
1256 tb1 = *ptb;
1257 n1 = (long)tb1 & 3;
1258 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1259 if (n1 == n && tb1 == tb)
1260 break;
1261 ptb = &tb1->jmp_next[n1];
1262 }
1263 *ptb = tb->jmp_next[n];
1264 tb->jmp_next[n] = NULL;
3b46e624 1265
ea041c0e
FB		 1266 /* suppress the jump to next tb in generated code */
1267 tb_reset_jump(tb, n);
1268
0124311e 1269 /* suppress jumps in the tb on which we could have jumped */
ea041c0e
FB		 1270 tb_reset_jump_recursive(tb_next);
1271 }
1272}
1273
1274static void tb_reset_jump_recursive(TranslationBlock *tb)
1275{
1276 tb_reset_jump_recursive2(tb, 0);
1277 tb_reset_jump_recursive2(tb, 1);
1278}
1279
1fddef4b 1280#if defined(TARGET_HAS_ICE)
d720b93d
FB		 1281static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1282{
9b3c35e0
JM		 1283 target_phys_addr_t addr;
1284 target_ulong pd;
c2f07f81
PB		 1285 ram_addr_t ram_addr;
1286 PhysPageDesc *p;
d720b93d 1287
c2f07f81
PB		 1288 addr = cpu_get_phys_page_debug(env, pc);
1289 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1290 if (!p) {
1291 pd = IO_MEM_UNASSIGNED;
1292 } else {
1293 pd = p->phys_offset;
1294 }
1295 ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
706cd4b5 1296 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
d720b93d 1297}
c27004ec 1298#endif
d720b93d 1299
6658ffb8 1300/* Add a watchpoint. */
a1d1bb31
AL		 1301int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1302 int flags, CPUWatchpoint **watchpoint)
6658ffb8 1303{
b4051334 1304 target_ulong len_mask = ~(len - 1);
2dc9f411 1305 CPUWatchpoint *wp, *prev_wp;
6658ffb8 1306
b4051334
AL		 1307 /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
1308 if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
1309 fprintf(stderr, "qemu: tried to set invalid watchpoint at "
1310 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
1311 return -EINVAL;
1312 }
a1d1bb31
AL		 1313 wp = qemu_malloc(sizeof(*wp));
1314 if (!wp)
426cd5d6 1315 return -ENOMEM;
a1d1bb31
AL		 1316
1317 wp->vaddr = addr;
b4051334 1318 wp->len_mask = len_mask;
a1d1bb31
AL		 1319 wp->flags = flags;
1320
2dc9f411
AL		 1321 /* keep all GDB-injected watchpoints in front */
1322 if (!(flags & BP_GDB) && env->watchpoints) {
1323 prev_wp = env->watchpoints;
1324 while (prev_wp->next != NULL && (prev_wp->next->flags & BP_GDB))
1325 prev_wp = prev_wp->next;
1326 } else {
1327 prev_wp = NULL;
1328 }
1329
1330 /* Insert new watchpoint */
1331 if (prev_wp) {
1332 wp->next = prev_wp->next;
1333 prev_wp->next = wp;
1334 } else {
1335 wp->next = env->watchpoints;
1336 env->watchpoints = wp;
1337 }
a1d1bb31
AL		 1338 if (wp->next)
1339 wp->next->prev = wp;
2dc9f411 1340 wp->prev = prev_wp;
6658ffb8 1341
6658ffb8 1342 tlb_flush_page(env, addr);
a1d1bb31
AL		 1343
1344 if (watchpoint)
1345 *watchpoint = wp;
1346 return 0;
6658ffb8
PB		 1347}
1348
a1d1bb31
AL		 1349/* Remove a specific watchpoint. */
1350int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
1351 int flags)
6658ffb8 1352{
b4051334 1353 target_ulong len_mask = ~(len - 1);
a1d1bb31 1354 CPUWatchpoint *wp;
6658ffb8 1355
a1d1bb31 1356 for (wp = env->watchpoints; wp != NULL; wp = wp->next) {
b4051334 1357 if (addr == wp->vaddr && len_mask == wp->len_mask
6e140f28 1358 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
a1d1bb31 1359 cpu_watchpoint_remove_by_ref(env, wp);
6658ffb8
PB		 1360 return 0;
1361 }
1362 }
a1d1bb31 1363 return -ENOENT;
6658ffb8
PB		 1364}
1365
a1d1bb31
AL		 1366/* Remove a specific watchpoint by reference. */
1367void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
1368{
1369 if (watchpoint->next)
1370 watchpoint->next->prev = watchpoint->prev;
1371 if (watchpoint->prev)
1372 watchpoint->prev->next = watchpoint->next;
1373 else
1374 env->watchpoints = watchpoint->next;
7d03f82f 1375
a1d1bb31
AL		 1376 tlb_flush_page(env, watchpoint->vaddr);
1377
1378 qemu_free(watchpoint);
1379}
1380
1381/* Remove all matching watchpoints. */
1382void cpu_watchpoint_remove_all(CPUState *env, int mask)
1383{
1384 CPUWatchpoint *wp;
1385
1386 for (wp = env->watchpoints; wp != NULL; wp = wp->next)
1387 if (wp->flags & mask)
1388 cpu_watchpoint_remove_by_ref(env, wp);
7d03f82f
EI		 1389}
1390
a1d1bb31
AL		 1391/* Add a breakpoint. */
1392int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
1393 CPUBreakpoint **breakpoint)
4c3a88a2 1394{
1fddef4b 1395#if defined(TARGET_HAS_ICE)
2dc9f411 1396 CPUBreakpoint *bp, *prev_bp;
3b46e624 1397
a1d1bb31
AL		 1398 bp = qemu_malloc(sizeof(*bp));
1399 if (!bp)
426cd5d6 1400 return -ENOMEM;
4c3a88a2 1401
a1d1bb31
AL		 1402 bp->pc = pc;
1403 bp->flags = flags;
1404
2dc9f411
AL		 1405 /* keep all GDB-injected breakpoints in front */
1406 if (!(flags & BP_GDB) && env->breakpoints) {
1407 prev_bp = env->breakpoints;
1408 while (prev_bp->next != NULL && (prev_bp->next->flags & BP_GDB))
1409 prev_bp = prev_bp->next;
1410 } else {
1411 prev_bp = NULL;
1412 }
1413
1414 /* Insert new breakpoint */
1415 if (prev_bp) {
1416 bp->next = prev_bp->next;
1417 prev_bp->next = bp;
1418 } else {
1419 bp->next = env->breakpoints;
1420 env->breakpoints = bp;
1421 }
a1d1bb31
AL		 1422 if (bp->next)
1423 bp->next->prev = bp;
2dc9f411 1424 bp->prev = prev_bp;
3b46e624 1425
d720b93d 1426 breakpoint_invalidate(env, pc);
a1d1bb31
AL		 1427
1428 if (breakpoint)
1429 *breakpoint = bp;
4c3a88a2
FB		 1430 return 0;
1431#else
a1d1bb31 1432 return -ENOSYS;
4c3a88a2
FB		 1433#endif
1434}
1435
a1d1bb31
AL		 1436/* Remove a specific breakpoint. */
1437int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
1438{
7d03f82f 1439#if defined(TARGET_HAS_ICE)
a1d1bb31
AL		 1440 CPUBreakpoint *bp;
1441
1442 for (bp = env->breakpoints; bp != NULL; bp = bp->next) {
1443 if (bp->pc == pc && bp->flags == flags) {
1444 cpu_breakpoint_remove_by_ref(env, bp);
1445 return 0;
1446 }
7d03f82f 1447 }
a1d1bb31
AL		 1448 return -ENOENT;
1449#else
1450 return -ENOSYS;
7d03f82f
EI		 1451#endif
1452}
1453
a1d1bb31
AL		 1454/* Remove a specific breakpoint by reference. */
1455void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
4c3a88a2 1456{
1fddef4b 1457#if defined(TARGET_HAS_ICE)
a1d1bb31
AL		 1458 if (breakpoint->next)
1459 breakpoint->next->prev = breakpoint->prev;
1460 if (breakpoint->prev)
1461 breakpoint->prev->next = breakpoint->next;
1462 else
1463 env->breakpoints = breakpoint->next;
d720b93d 1464
a1d1bb31
AL		 1465 breakpoint_invalidate(env, breakpoint->pc);
1466
1467 qemu_free(breakpoint);
1468#endif
1469}
1470
1471/* Remove all matching breakpoints. */
1472void cpu_breakpoint_remove_all(CPUState *env, int mask)
1473{
1474#if defined(TARGET_HAS_ICE)
1475 CPUBreakpoint *bp;
1476
1477 for (bp = env->breakpoints; bp != NULL; bp = bp->next)
1478 if (bp->flags & mask)
1479 cpu_breakpoint_remove_by_ref(env, bp);
4c3a88a2
FB		 1480#endif
1481}
1482
c33a346e
FB		 1483/* enable or disable single step mode. EXCP_DEBUG is returned by the
1484 CPU loop after each instruction */
1485void cpu_single_step(CPUState *env, int enabled)
1486{
1fddef4b 1487#if defined(TARGET_HAS_ICE)
c33a346e
FB		 1488 if (env->singlestep_enabled != enabled) {
1489 env->singlestep_enabled = enabled;
1490 /* must flush all the translated code to avoid inconsistancies */
9fa3e853 1491 /* XXX: only flush what is necessary */
0124311e 1492 tb_flush(env);
c33a346e
FB		 1493 }
1494#endif
1495}
1496
34865134
FB		 1497/* enable or disable low levels log */
1498void cpu_set_log(int log_flags)
1499{
1500 loglevel = log_flags;
1501 if (loglevel && !logfile) {
11fcfab4 1502 logfile = fopen(logfilename, log_append ? "a" : "w");
34865134
FB		 1503 if (!logfile) {
1504 perror(logfilename);
1505 _exit(1);
1506 }
9fa3e853
FB		 1507#if !defined(CONFIG_SOFTMMU)
1508 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1509 {
b55266b5 1510 static char logfile_buf[4096];
9fa3e853
FB		 1511 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1512 }
1513#else
34865134 1514 setvbuf(logfile, NULL, _IOLBF, 0);
9fa3e853 1515#endif
e735b91c
PB		 1516 log_append = 1;
1517 }
1518 if (!loglevel && logfile) {
1519 fclose(logfile);
1520 logfile = NULL;
34865134
FB		 1521 }
1522}
1523
1524void cpu_set_log_filename(const char *filename)
1525{
1526 logfilename = strdup(filename);
e735b91c
PB		 1527 if (logfile) {
1528 fclose(logfile);
1529 logfile = NULL;
1530 }
1531 cpu_set_log(loglevel);
34865134 1532}
c33a346e 1533
0124311e 1534/* mask must never be zero, except for A20 change call */
68a79315 1535void cpu_interrupt(CPUState *env, int mask)
ea041c0e 1536{
d5975363 1537#if !defined(USE_NPTL)
ea041c0e 1538 TranslationBlock *tb;
15a51156 1539 static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
d5975363 1540#endif
2e70f6ef 1541 int old_mask;
59817ccb 1542
2e70f6ef 1543 old_mask = env->interrupt_request;
d5975363 1544 /* FIXME: This is probably not threadsafe. A different thread could
bf20dc07 1545 be in the middle of a read-modify-write operation. */
68a79315 1546 env->interrupt_request |= mask;
d5975363
PB		 1547#if defined(USE_NPTL)
1548 /* FIXME: TB unchaining isn't SMP safe. For now just ignore the
1549 problem and hope the cpu will stop of its own accord. For userspace
1550 emulation this often isn't actually as bad as it sounds. Often
1551 signals are used primarily to interrupt blocking syscalls. */
1552#else
2e70f6ef 1553 if (use_icount) {
266910c4 1554 env->icount_decr.u16.high = 0xffff;
2e70f6ef
PB		 1555#ifndef CONFIG_USER_ONLY
1556 /* CPU_INTERRUPT_EXIT isn't a real interrupt. It just means
1557 an async event happened and we need to process it. */
1558 if (!can_do_io(env)
1559 && (mask & ~(old_mask | CPU_INTERRUPT_EXIT)) != 0) {
1560 cpu_abort(env, "Raised interrupt while not in I/O function");
1561 }
1562#endif
1563 } else {
1564 tb = env->current_tb;
1565 /* if the cpu is currently executing code, we must unlink it and
1566 all the potentially executing TB */
1567 if (tb && !testandset(&interrupt_lock)) {
1568 env->current_tb = NULL;
1569 tb_reset_jump_recursive(tb);
1570 resetlock(&interrupt_lock);
1571 }
ea041c0e 1572 }
d5975363 1573#endif
ea041c0e
FB		 1574}
1575
b54ad049
FB		 1576void cpu_reset_interrupt(CPUState *env, int mask)
1577{
1578 env->interrupt_request &= ~mask;
1579}
1580
c7cd6a37 1581const CPULogItem cpu_log_items[] = {
5fafdf24 1582 { CPU_LOG_TB_OUT_ASM, "out_asm",
f193c797
FB		 1583 "show generated host assembly code for each compiled TB" },
1584 { CPU_LOG_TB_IN_ASM, "in_asm",
1585 "show target assembly code for each compiled TB" },
5fafdf24 1586 { CPU_LOG_TB_OP, "op",
57fec1fe 1587 "show micro ops for each compiled TB" },
f193c797 1588 { CPU_LOG_TB_OP_OPT, "op_opt",
e01a1157
BS		 1589 "show micro ops "
1590#ifdef TARGET_I386
1591 "before eflags optimization and "
f193c797 1592#endif
e01a1157 1593 "after liveness analysis" },
f193c797
FB		 1594 { CPU_LOG_INT, "int",
1595 "show interrupts/exceptions in short format" },
1596 { CPU_LOG_EXEC, "exec",
1597 "show trace before each executed TB (lots of logs)" },
9fddaa0c 1598 { CPU_LOG_TB_CPU, "cpu",
e91c8a77 1599 "show CPU state before block translation" },
f193c797
FB		 1600#ifdef TARGET_I386
1601 { CPU_LOG_PCALL, "pcall",
1602 "show protected mode far calls/returns/exceptions" },
1603#endif
8e3a9fd2 1604#ifdef DEBUG_IOPORT
fd872598
FB		 1605 { CPU_LOG_IOPORT, "ioport",
1606 "show all i/o ports accesses" },
8e3a9fd2 1607#endif
f193c797
FB		 1608 { 0, NULL, NULL },
1609};
1610
1611static int cmp1(const char *s1, int n, const char *s2)
1612{
1613 if (strlen(s2) != n)
1614 return 0;
1615 return memcmp(s1, s2, n) == 0;
1616}
3b46e624 1617
f193c797
FB		 1618/* takes a comma separated list of log masks. Return 0 if error. */
1619int cpu_str_to_log_mask(const char *str)
1620{
c7cd6a37 1621 const CPULogItem *item;
f193c797
FB		 1622 int mask;
1623 const char *p, *p1;
1624
1625 p = str;
1626 mask = 0;
1627 for(;;) {
1628 p1 = strchr(p, ',');
1629 if (!p1)
1630 p1 = p + strlen(p);
8e3a9fd2
FB		 1631 if(cmp1(p,p1-p,"all")) {
1632 for(item = cpu_log_items; item->mask != 0; item++) {
1633 mask |= item->mask;
1634 }
1635 } else {
f193c797
FB		 1636 for(item = cpu_log_items; item->mask != 0; item++) {
1637 if (cmp1(p, p1 - p, item->name))
1638 goto found;
1639 }
1640 return 0;
8e3a9fd2 1641 }
f193c797
FB		 1642 found:
1643 mask |= item->mask;
1644 if (*p1 != ',')
1645 break;
1646 p = p1 + 1;
1647 }
1648 return mask;
1649}
ea041c0e 1650
7501267e
FB		 1651void cpu_abort(CPUState *env, const char *fmt, ...)
1652{
1653 va_list ap;
493ae1f0 1654 va_list ap2;
7501267e
FB		 1655
1656 va_start(ap, fmt);
493ae1f0 1657 va_copy(ap2, ap);
7501267e
FB		 1658 fprintf(stderr, "qemu: fatal: ");
1659 vfprintf(stderr, fmt, ap);
1660 fprintf(stderr, "\n");
1661#ifdef TARGET_I386
7fe48483
FB		 1662 cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1663#else
1664 cpu_dump_state(env, stderr, fprintf, 0);
7501267e 1665#endif
924edcae 1666 if (logfile) {
f9373291 1667 fprintf(logfile, "qemu: fatal: ");
493ae1f0 1668 vfprintf(logfile, fmt, ap2);
f9373291
JM		 1669 fprintf(logfile, "\n");
1670#ifdef TARGET_I386
1671 cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1672#else
1673 cpu_dump_state(env, logfile, fprintf, 0);
1674#endif
924edcae
AZ		 1675 fflush(logfile);
1676 fclose(logfile);
1677 }
493ae1f0 1678 va_end(ap2);
f9373291 1679 va_end(ap);
7501267e
FB		 1680 abort();
1681}
1682
c5be9f08
TS		 1683CPUState *cpu_copy(CPUState *env)
1684{
01ba9816 1685 CPUState *new_env = cpu_init(env->cpu_model_str);
c5be9f08
TS		 1686 /* preserve chaining and index */
1687 CPUState *next_cpu = new_env->next_cpu;
1688 int cpu_index = new_env->cpu_index;
1689 memcpy(new_env, env, sizeof(CPUState));
1690 new_env->next_cpu = next_cpu;
1691 new_env->cpu_index = cpu_index;
1692 return new_env;
1693}
1694
0124311e
FB		 1695#if !defined(CONFIG_USER_ONLY)
1696
5c751e99
EI		 1697static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1698{
1699 unsigned int i;
1700
1701 /* Discard jump cache entries for any tb which might potentially
1702 overlap the flushed page. */
1703 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1704 memset (&env->tb_jmp_cache[i], 0,
1705 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1706
1707 i = tb_jmp_cache_hash_page(addr);
1708 memset (&env->tb_jmp_cache[i], 0,
1709 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1710}
1711
ee8b7021
FB		 1712/* NOTE: if flush_global is true, also flush global entries (not
1713 implemented yet) */
1714void tlb_flush(CPUState *env, int flush_global)
33417e70 1715{
33417e70 1716 int i;
0124311e 1717
9fa3e853
FB		 1718#if defined(DEBUG_TLB)
1719 printf("tlb_flush:\n");
1720#endif
0124311e
FB		 1721 /* must reset current TB so that interrupts cannot modify the
1722 links while we are modifying them */
1723 env->current_tb = NULL;
1724
33417e70 1725 for(i = 0; i < CPU_TLB_SIZE; i++) {
84b7b8e7
FB		 1726 env->tlb_table[0][i].addr_read = -1;
1727 env->tlb_table[0][i].addr_write = -1;
1728 env->tlb_table[0][i].addr_code = -1;
1729 env->tlb_table[1][i].addr_read = -1;
1730 env->tlb_table[1][i].addr_write = -1;
1731 env->tlb_table[1][i].addr_code = -1;
6fa4cea9
JM		 1732#if (NB_MMU_MODES >= 3)
1733 env->tlb_table[2][i].addr_read = -1;
1734 env->tlb_table[2][i].addr_write = -1;
1735 env->tlb_table[2][i].addr_code = -1;
1736#if (NB_MMU_MODES == 4)
1737 env->tlb_table[3][i].addr_read = -1;
1738 env->tlb_table[3][i].addr_write = -1;
1739 env->tlb_table[3][i].addr_code = -1;
1740#endif
1741#endif
33417e70 1742 }
9fa3e853 1743
8a40a180 1744 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
9fa3e853 1745
0a962c02
FB		 1746#ifdef USE_KQEMU
1747 if (env->kqemu_enabled) {
1748 kqemu_flush(env, flush_global);
1749 }
9fa3e853 1750#endif
e3db7226 1751 tlb_flush_count++;
33417e70
FB		 1752}
1753
274da6b2 1754static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
61382a50 1755{
5fafdf24 1756 if (addr == (tlb_entry->addr_read &
84b7b8e7 1757 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
5fafdf24 1758 addr == (tlb_entry->addr_write &
84b7b8e7 1759 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
5fafdf24 1760 addr == (tlb_entry->addr_code &
84b7b8e7
FB		 1761 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1762 tlb_entry->addr_read = -1;
1763 tlb_entry->addr_write = -1;
1764 tlb_entry->addr_code = -1;
1765 }
61382a50
FB		 1766}
1767
2e12669a 1768void tlb_flush_page(CPUState *env, target_ulong addr)
33417e70 1769{
8a40a180 1770 int i;
0124311e 1771
9fa3e853 1772#if defined(DEBUG_TLB)
108c49b8 1773 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
9fa3e853 1774#endif
0124311e
FB		 1775 /* must reset current TB so that interrupts cannot modify the
1776 links while we are modifying them */
1777 env->current_tb = NULL;
61382a50
FB		 1778
1779 addr &= TARGET_PAGE_MASK;
1780 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
84b7b8e7
FB		 1781 tlb_flush_entry(&env->tlb_table[0][i], addr);
1782 tlb_flush_entry(&env->tlb_table[1][i], addr);
6fa4cea9
JM		 1783#if (NB_MMU_MODES >= 3)
1784 tlb_flush_entry(&env->tlb_table[2][i], addr);
1785#if (NB_MMU_MODES == 4)
1786 tlb_flush_entry(&env->tlb_table[3][i], addr);
1787#endif
1788#endif
0124311e 1789
5c751e99 1790 tlb_flush_jmp_cache(env, addr);
9fa3e853 1791
0a962c02
FB		 1792#ifdef USE_KQEMU
1793 if (env->kqemu_enabled) {
1794 kqemu_flush_page(env, addr);
1795 }
1796#endif
9fa3e853
FB		 1797}
1798
9fa3e853
FB		 1799/* update the TLBs so that writes to code in the virtual page 'addr'
1800 can be detected */
6a00d601 1801static void tlb_protect_code(ram_addr_t ram_addr)
9fa3e853 1802{
5fafdf24 1803 cpu_physical_memory_reset_dirty(ram_addr,
6a00d601
FB		 1804 ram_addr + TARGET_PAGE_SIZE,
1805 CODE_DIRTY_FLAG);
9fa3e853
FB		 1806}
1807
9fa3e853 1808/* update the TLB so that writes in physical page 'phys_addr' are no longer
3a7d929e 1809 tested for self modifying code */
5fafdf24 1810static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
3a7d929e 1811 target_ulong vaddr)
9fa3e853 1812{
3a7d929e 1813 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
1ccde1cb
FB		 1814}
1815
5fafdf24 1816static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
1ccde1cb
FB		 1817 unsigned long start, unsigned long length)
1818{
1819 unsigned long addr;
84b7b8e7
FB		 1820 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1821 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
1ccde1cb 1822 if ((addr - start) < length) {
0f459d16 1823 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
1ccde1cb
FB		 1824 }
1825 }
1826}
1827
3a7d929e 1828void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
0a962c02 1829 int dirty_flags)
1ccde1cb
FB		 1830{
1831 CPUState *env;
4f2ac237 1832 unsigned long length, start1;
0a962c02
FB		 1833 int i, mask, len;
1834 uint8_t *p;
1ccde1cb
FB		 1835
1836 start &= TARGET_PAGE_MASK;
1837 end = TARGET_PAGE_ALIGN(end);
1838
1839 length = end - start;
1840 if (length == 0)
1841 return;
0a962c02 1842 len = length >> TARGET_PAGE_BITS;
3a7d929e 1843#ifdef USE_KQEMU
6a00d601
FB		 1844 /* XXX: should not depend on cpu context */
1845 env = first_cpu;
3a7d929e 1846 if (env->kqemu_enabled) {
f23db169
FB		 1847 ram_addr_t addr;
1848 addr = start;
1849 for(i = 0; i < len; i++) {
1850 kqemu_set_notdirty(env, addr);
1851 addr += TARGET_PAGE_SIZE;
1852 }
3a7d929e
FB		 1853 }
1854#endif
f23db169
FB		 1855 mask = ~dirty_flags;
1856 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
1857 for(i = 0; i < len; i++)
1858 p[i] &= mask;
1859
1ccde1cb
FB		 1860 /* we modify the TLB cache so that the dirty bit will be set again
1861 when accessing the range */
59817ccb 1862 start1 = start + (unsigned long)phys_ram_base;
6a00d601
FB		 1863 for(env = first_cpu; env != NULL; env = env->next_cpu) {
1864 for(i = 0; i < CPU_TLB_SIZE; i++)
84b7b8e7 1865 tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
6a00d601 1866 for(i = 0; i < CPU_TLB_SIZE; i++)
84b7b8e7 1867 tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
6fa4cea9
JM		 1868#if (NB_MMU_MODES >= 3)
1869 for(i = 0; i < CPU_TLB_SIZE; i++)
1870 tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
1871#if (NB_MMU_MODES == 4)
1872 for(i = 0; i < CPU_TLB_SIZE; i++)
1873 tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
1874#endif
1875#endif
6a00d601 1876 }
1ccde1cb
FB		 1877}
1878
74576198
AL		 1879int cpu_physical_memory_set_dirty_tracking(int enable)
1880{
1881 in_migration = enable;
1882 return 0;
1883}
1884
1885int cpu_physical_memory_get_dirty_tracking(void)
1886{
1887 return in_migration;
1888}
1889
2bec46dc
AL		 1890void cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, target_phys_addr_t end_addr)
1891{
1892 if (kvm_enabled())
1893 kvm_physical_sync_dirty_bitmap(start_addr, end_addr);
1894}
1895
3a7d929e
FB		 1896static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
1897{
1898 ram_addr_t ram_addr;
1899
84b7b8e7 1900 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
5fafdf24 1901 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
3a7d929e
FB		 1902 tlb_entry->addend - (unsigned long)phys_ram_base;
1903 if (!cpu_physical_memory_is_dirty(ram_addr)) {
0f459d16 1904 tlb_entry->addr_write |= TLB_NOTDIRTY;
3a7d929e
FB		 1905 }
1906 }
1907}
1908
1909/* update the TLB according to the current state of the dirty bits */
1910void cpu_tlb_update_dirty(CPUState *env)
1911{
1912 int i;
1913 for(i = 0; i < CPU_TLB_SIZE; i++)
84b7b8e7 1914 tlb_update_dirty(&env->tlb_table[0][i]);
3a7d929e 1915 for(i = 0; i < CPU_TLB_SIZE; i++)
84b7b8e7 1916 tlb_update_dirty(&env->tlb_table[1][i]);
6fa4cea9
JM		 1917#if (NB_MMU_MODES >= 3)
1918 for(i = 0; i < CPU_TLB_SIZE; i++)
1919 tlb_update_dirty(&env->tlb_table[2][i]);
1920#if (NB_MMU_MODES == 4)
1921 for(i = 0; i < CPU_TLB_SIZE; i++)
1922 tlb_update_dirty(&env->tlb_table[3][i]);
1923#endif
1924#endif
3a7d929e
FB		 1925}
1926
0f459d16 1927static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
1ccde1cb 1928{
0f459d16
PB		 1929 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
1930 tlb_entry->addr_write = vaddr;
1ccde1cb
FB		 1931}
1932
0f459d16
PB		 1933/* update the TLB corresponding to virtual page vaddr
1934 so that it is no longer dirty */
1935static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
1ccde1cb 1936{
1ccde1cb
FB		 1937 int i;
1938
0f459d16 1939 vaddr &= TARGET_PAGE_MASK;
1ccde1cb 1940 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
0f459d16
PB		 1941 tlb_set_dirty1(&env->tlb_table[0][i], vaddr);
1942 tlb_set_dirty1(&env->tlb_table[1][i], vaddr);
6fa4cea9 1943#if (NB_MMU_MODES >= 3)
0f459d16 1944 tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
6fa4cea9 1945#if (NB_MMU_MODES == 4)
0f459d16 1946 tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
6fa4cea9
JM		 1947#endif
1948#endif
9fa3e853
FB		 1949}
1950
59817ccb
FB		 1951/* add a new TLB entry. At most one entry for a given virtual address
1952 is permitted. Return 0 if OK or 2 if the page could not be mapped
1953 (can only happen in non SOFTMMU mode for I/O pages or pages
1954 conflicting with the host address space). */
5fafdf24
TS		 1955int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
1956 target_phys_addr_t paddr, int prot,
6ebbf390 1957 int mmu_idx, int is_softmmu)
9fa3e853 1958{
92e873b9 1959 PhysPageDesc *p;
4f2ac237 1960 unsigned long pd;
9fa3e853 1961 unsigned int index;
4f2ac237 1962 target_ulong address;
0f459d16 1963 target_ulong code_address;
108c49b8 1964 target_phys_addr_t addend;
9fa3e853 1965 int ret;
84b7b8e7 1966 CPUTLBEntry *te;
a1d1bb31 1967 CPUWatchpoint *wp;
0f459d16 1968 target_phys_addr_t iotlb;
9fa3e853 1969
92e873b9 1970 p = phys_page_find(paddr >> TARGET_PAGE_BITS);
9fa3e853
FB		 1971 if (!p) {
1972 pd = IO_MEM_UNASSIGNED;
9fa3e853
FB		 1973 } else {
1974 pd = p->phys_offset;
9fa3e853
FB		 1975 }
1976#if defined(DEBUG_TLB)
6ebbf390
JM		 1977 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
1978 vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
9fa3e853
FB		 1979#endif
1980
1981 ret = 0;
0f459d16
PB		 1982 address = vaddr;
1983 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
1984 /* IO memory case (romd handled later) */
1985 address |= TLB_MMIO;
1986 }
1987 addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
1988 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
1989 /* Normal RAM. */
1990 iotlb = pd & TARGET_PAGE_MASK;
1991 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
1992 iotlb |= IO_MEM_NOTDIRTY;
1993 else
1994 iotlb |= IO_MEM_ROM;
1995 } else {
1996 /* IO handlers are currently passed a phsical address.
1997 It would be nice to pass an offset from the base address
1998 of that region. This would avoid having to special case RAM,
1999 and avoid full address decoding in every device.
2000 We can't use the high bits of pd for this because
2001 IO_MEM_ROMD uses these as a ram address. */
2002 iotlb = (pd & ~TARGET_PAGE_MASK) + paddr;
2003 }
2004
2005 code_address = address;
2006 /* Make accesses to pages with watchpoints go via the
2007 watchpoint trap routines. */
a1d1bb31
AL		 2008 for (wp = env->watchpoints; wp != NULL; wp = wp->next) {
2009 if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
0f459d16
PB		 2010 iotlb = io_mem_watch + paddr;
2011 /* TODO: The memory case can be optimized by not trapping
2012 reads of pages with a write breakpoint. */
2013 address |= TLB_MMIO;
6658ffb8 2014 }
0f459d16 2015 }
d79acba4 2016
0f459d16
PB		 2017 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2018 env->iotlb[mmu_idx][index] = iotlb - vaddr;
2019 te = &env->tlb_table[mmu_idx][index];
2020 te->addend = addend - vaddr;
2021 if (prot & PAGE_READ) {
2022 te->addr_read = address;
2023 } else {
2024 te->addr_read = -1;
2025 }
5c751e99 2026
0f459d16
PB		 2027 if (prot & PAGE_EXEC) {
2028 te->addr_code = code_address;
2029 } else {
2030 te->addr_code = -1;
2031 }
2032 if (prot & PAGE_WRITE) {
2033 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
2034 (pd & IO_MEM_ROMD)) {
2035 /* Write access calls the I/O callback. */
2036 te->addr_write = address | TLB_MMIO;
2037 } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
2038 !cpu_physical_memory_is_dirty(pd)) {
2039 te->addr_write = address | TLB_NOTDIRTY;
9fa3e853 2040 } else {
0f459d16 2041 te->addr_write = address;
9fa3e853 2042 }
0f459d16
PB		 2043 } else {
2044 te->addr_write = -1;
9fa3e853 2045 }
9fa3e853
FB		 2046 return ret;
2047}
2048
0124311e
FB		 2049#else
2050
ee8b7021 2051void tlb_flush(CPUState *env, int flush_global)
0124311e
FB		 2052{
2053}
2054
2e12669a 2055void tlb_flush_page(CPUState *env, target_ulong addr)
0124311e
FB		 2056{
2057}
2058
5fafdf24
TS		 2059int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
2060 target_phys_addr_t paddr, int prot,
6ebbf390 2061 int mmu_idx, int is_softmmu)
9fa3e853
FB		 2062{
2063 return 0;
2064}
0124311e 2065
9fa3e853
FB		 2066/* dump memory mappings */
2067void page_dump(FILE *f)
33417e70 2068{
9fa3e853
FB		 2069 unsigned long start, end;
2070 int i, j, prot, prot1;
2071 PageDesc *p;
33417e70 2072
9fa3e853
FB		 2073 fprintf(f, "%-8s %-8s %-8s %s\n",
2074 "start", "end", "size", "prot");
2075 start = -1;
2076 end = -1;
2077 prot = 0;
2078 for(i = 0; i <= L1_SIZE; i++) {
2079 if (i < L1_SIZE)
2080 p = l1_map[i];
2081 else
2082 p = NULL;
2083 for(j = 0;j < L2_SIZE; j++) {
2084 if (!p)
2085 prot1 = 0;
2086 else
2087 prot1 = p[j].flags;
2088 if (prot1 != prot) {
2089 end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
2090 if (start != -1) {
2091 fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
5fafdf24 2092 start, end, end - start,
9fa3e853
FB		 2093 prot & PAGE_READ ? 'r' : '-',
2094 prot & PAGE_WRITE ? 'w' : '-',
2095 prot & PAGE_EXEC ? 'x' : '-');
2096 }
2097 if (prot1 != 0)
2098 start = end;
2099 else
2100 start = -1;
2101 prot = prot1;
2102 }
2103 if (!p)
2104 break;
2105 }
33417e70 2106 }
33417e70
FB		 2107}
2108
53a5960a 2109int page_get_flags(target_ulong address)
33417e70 2110{
9fa3e853
FB		 2111 PageDesc *p;
2112
2113 p = page_find(address >> TARGET_PAGE_BITS);
33417e70 2114 if (!p)
9fa3e853
FB		 2115 return 0;
2116 return p->flags;
2117}
2118
2119/* modify the flags of a page and invalidate the code if
2120 necessary. The flag PAGE_WRITE_ORG is positionned automatically
2121 depending on PAGE_WRITE */
53a5960a 2122void page_set_flags(target_ulong start, target_ulong end, int flags)
9fa3e853
FB		 2123{
2124 PageDesc *p;
53a5960a 2125 target_ulong addr;
9fa3e853 2126
c8a706fe 2127 /* mmap_lock should already be held. */
9fa3e853
FB		 2128 start = start & TARGET_PAGE_MASK;
2129 end = TARGET_PAGE_ALIGN(end);
2130 if (flags & PAGE_WRITE)
2131 flags |= PAGE_WRITE_ORG;
9fa3e853
FB		 2132 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2133 p = page_find_alloc(addr >> TARGET_PAGE_BITS);
17e2377a
PB		 2134 /* We may be called for host regions that are outside guest
2135 address space. */
2136 if (!p)
2137 return;
9fa3e853
FB		 2138 /* if the write protection is set, then we invalidate the code
2139 inside */
5fafdf24 2140 if (!(p->flags & PAGE_WRITE) &&
9fa3e853
FB		 2141 (flags & PAGE_WRITE) &&
2142 p->first_tb) {
d720b93d 2143 tb_invalidate_phys_page(addr, 0, NULL);
9fa3e853
FB		 2144 }
2145 p->flags = flags;
2146 }
33417e70
FB		 2147}
2148
3d97b40b
TS		 2149int page_check_range(target_ulong start, target_ulong len, int flags)
2150{
2151 PageDesc *p;
2152 target_ulong end;
2153 target_ulong addr;
2154
55f280c9
AZ		 2155 if (start + len < start)
2156 /* we've wrapped around */
2157 return -1;
2158
3d97b40b
TS		 2159 end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
2160 start = start & TARGET_PAGE_MASK;
2161
3d97b40b
TS		 2162 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2163 p = page_find(addr >> TARGET_PAGE_BITS);
2164 if( !p )
2165 return -1;
2166 if( !(p->flags & PAGE_VALID) )
2167 return -1;
2168
dae3270c 2169 if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
3d97b40b 2170 return -1;
dae3270c
FB		 2171 if (flags & PAGE_WRITE) {
2172 if (!(p->flags & PAGE_WRITE_ORG))
2173 return -1;
2174 /* unprotect the page if it was put read-only because it
2175 contains translated code */
2176 if (!(p->flags & PAGE_WRITE)) {
2177 if (!page_unprotect(addr, 0, NULL))
2178 return -1;
2179 }
2180 return 0;
2181 }
3d97b40b
TS		 2182 }
2183 return 0;
2184}
2185
9fa3e853
FB		 2186/* called from signal handler: invalidate the code and unprotect the
2187 page. Return TRUE if the fault was succesfully handled. */
53a5960a 2188int page_unprotect(target_ulong address, unsigned long pc, void *puc)
9fa3e853
FB		 2189{
2190 unsigned int page_index, prot, pindex;
2191 PageDesc *p, *p1;
53a5960a 2192 target_ulong host_start, host_end, addr;
9fa3e853 2193
c8a706fe
PB		 2194 /* Technically this isn't safe inside a signal handler. However we
2195 know this only ever happens in a synchronous SEGV handler, so in
2196 practice it seems to be ok. */
2197 mmap_lock();
2198
83fb7adf 2199 host_start = address & qemu_host_page_mask;
9fa3e853
FB		 2200 page_index = host_start >> TARGET_PAGE_BITS;
2201 p1 = page_find(page_index);
c8a706fe
PB		 2202 if (!p1) {
2203 mmap_unlock();
9fa3e853 2204 return 0;
c8a706fe 2205 }
83fb7adf 2206 host_end = host_start + qemu_host_page_size;
9fa3e853
FB		 2207 p = p1;
2208 prot = 0;
2209 for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
2210 prot |= p->flags;
2211 p++;
2212 }
2213 /* if the page was really writable, then we change its
2214 protection back to writable */
2215 if (prot & PAGE_WRITE_ORG) {
2216 pindex = (address - host_start) >> TARGET_PAGE_BITS;
2217 if (!(p1[pindex].flags & PAGE_WRITE)) {
5fafdf24 2218 mprotect((void *)g2h(host_start), qemu_host_page_size,
9fa3e853
FB		 2219 (prot & PAGE_BITS) | PAGE_WRITE);
2220 p1[pindex].flags |= PAGE_WRITE;
2221 /* and since the content will be modified, we must invalidate
2222 the corresponding translated code. */
d720b93d 2223 tb_invalidate_phys_page(address, pc, puc);
9fa3e853
FB		 2224#ifdef DEBUG_TB_CHECK
2225 tb_invalidate_check(address);
2226#endif
c8a706fe 2227 mmap_unlock();
9fa3e853
FB		 2228 return 1;
2229 }
2230 }
c8a706fe 2231 mmap_unlock();
9fa3e853
FB		 2232 return 0;
2233}
2234
6a00d601
FB		 2235static inline void tlb_set_dirty(CPUState *env,
2236 unsigned long addr, target_ulong vaddr)
1ccde1cb
FB		 2237{
2238}
9fa3e853
FB		 2239#endif /* defined(CONFIG_USER_ONLY) */
2240
e2eef170 2241#if !defined(CONFIG_USER_ONLY)
db7b5426 2242static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
00f82b8a
AJ		 2243 ram_addr_t memory);
2244static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2245 ram_addr_t orig_memory);
db7b5426
BS		 2246#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2247 need_subpage) \
2248 do { \
2249 if (addr > start_addr) \
2250 start_addr2 = 0; \
2251 else { \
2252 start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
2253 if (start_addr2 > 0) \
2254 need_subpage = 1; \
2255 } \
2256 \
49e9fba2 2257 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
db7b5426
BS		 2258 end_addr2 = TARGET_PAGE_SIZE - 1; \
2259 else { \
2260 end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2261 if (end_addr2 < TARGET_PAGE_SIZE - 1) \
2262 need_subpage = 1; \
2263 } \
2264 } while (0)
2265
33417e70
FB		 2266/* register physical memory. 'size' must be a multiple of the target
2267 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
2268 io memory page */
5fafdf24 2269void cpu_register_physical_memory(target_phys_addr_t start_addr,
00f82b8a
AJ		 2270 ram_addr_t size,
2271 ram_addr_t phys_offset)
33417e70 2272{
108c49b8 2273 target_phys_addr_t addr, end_addr;
92e873b9 2274 PhysPageDesc *p;
9d42037b 2275 CPUState *env;
00f82b8a 2276 ram_addr_t orig_size = size;
db7b5426 2277 void *subpage;
33417e70 2278
da260249
FB		 2279#ifdef USE_KQEMU
2280 /* XXX: should not depend on cpu context */
2281 env = first_cpu;
2282 if (env->kqemu_enabled) {
2283 kqemu_set_phys_mem(start_addr, size, phys_offset);
2284 }
2285#endif
7ba1e619
AL		 2286 if (kvm_enabled())
2287 kvm_set_phys_mem(start_addr, size, phys_offset);
2288
5fd386f6 2289 size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
49e9fba2
BS		 2290 end_addr = start_addr + (target_phys_addr_t)size;
2291 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
db7b5426
BS		 2292 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2293 if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
00f82b8a 2294 ram_addr_t orig_memory = p->phys_offset;
db7b5426
BS		 2295 target_phys_addr_t start_addr2, end_addr2;
2296 int need_subpage = 0;
2297
2298 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2299 need_subpage);
4254fab8 2300 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
db7b5426
BS		 2301 if (!(orig_memory & IO_MEM_SUBPAGE)) {
2302 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2303 &p->phys_offset, orig_memory);
2304 } else {
2305 subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2306 >> IO_MEM_SHIFT];
2307 }
2308 subpage_register(subpage, start_addr2, end_addr2, phys_offset);
2309 } else {
2310 p->phys_offset = phys_offset;
2311 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2312 (phys_offset & IO_MEM_ROMD))
2313 phys_offset += TARGET_PAGE_SIZE;
2314 }
2315 } else {
2316 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2317 p->phys_offset = phys_offset;
2318 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2319 (phys_offset & IO_MEM_ROMD))
2320 phys_offset += TARGET_PAGE_SIZE;
2321 else {
2322 target_phys_addr_t start_addr2, end_addr2;
2323 int need_subpage = 0;
2324
2325 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2326 end_addr2, need_subpage);
2327
4254fab8 2328 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
db7b5426
BS		 2329 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2330 &p->phys_offset, IO_MEM_UNASSIGNED);
2331 subpage_register(subpage, start_addr2, end_addr2,
2332 phys_offset);
2333 }
2334 }
2335 }
33417e70 2336 }
3b46e624 2337
9d42037b
FB		 2338 /* since each CPU stores ram addresses in its TLB cache, we must
2339 reset the modified entries */
2340 /* XXX: slow ! */
2341 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2342 tlb_flush(env, 1);
2343 }
33417e70
FB		 2344}
2345
ba863458 2346/* XXX: temporary until new memory mapping API */
00f82b8a 2347ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
ba863458
FB		 2348{
2349 PhysPageDesc *p;
2350
2351 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2352 if (!p)
2353 return IO_MEM_UNASSIGNED;
2354 return p->phys_offset;
2355}
2356
e9a1ab19 2357/* XXX: better than nothing */
00f82b8a 2358ram_addr_t qemu_ram_alloc(ram_addr_t size)
e9a1ab19
FB		 2359{
2360 ram_addr_t addr;
7fb4fdcf 2361 if ((phys_ram_alloc_offset + size) > phys_ram_size) {
012a7045 2362 fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n",
ed441467 2363 (uint64_t)size, (uint64_t)phys_ram_size);
e9a1ab19
FB		 2364 abort();
2365 }
2366 addr = phys_ram_alloc_offset;
2367 phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
2368 return addr;
2369}
2370
2371void qemu_ram_free(ram_addr_t addr)
2372{
2373}
2374
a4193c8a 2375static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
33417e70 2376{
67d3b957 2377#ifdef DEBUG_UNASSIGNED
ab3d1727 2378 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
b4f0a316 2379#endif
e18231a3
BS		 2380#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2381 do_unassigned_access(addr, 0, 0, 0, 1);
2382#endif
2383 return 0;
2384}
2385
2386static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
2387{
2388#ifdef DEBUG_UNASSIGNED
2389 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2390#endif
2391#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2392 do_unassigned_access(addr, 0, 0, 0, 2);
2393#endif
2394 return 0;
2395}
2396
2397static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
2398{
2399#ifdef DEBUG_UNASSIGNED
2400 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2401#endif
2402#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2403 do_unassigned_access(addr, 0, 0, 0, 4);
67d3b957 2404#endif
33417e70
FB		 2405 return 0;
2406}
2407
a4193c8a 2408static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
33417e70 2409{
67d3b957 2410#ifdef DEBUG_UNASSIGNED
ab3d1727 2411 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
67d3b957 2412#endif
e18231a3
BS		 2413#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2414 do_unassigned_access(addr, 1, 0, 0, 1);
2415#endif
2416}
2417
2418static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2419{
2420#ifdef DEBUG_UNASSIGNED
2421 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2422#endif
2423#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2424 do_unassigned_access(addr, 1, 0, 0, 2);
2425#endif
2426}
2427
2428static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2429{
2430#ifdef DEBUG_UNASSIGNED
2431 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2432#endif
2433#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2434 do_unassigned_access(addr, 1, 0, 0, 4);
b4f0a316 2435#endif
33417e70
FB		 2436}
2437
2438static CPUReadMemoryFunc *unassigned_mem_read[3] = {
2439 unassigned_mem_readb,
e18231a3
BS		 2440 unassigned_mem_readw,
2441 unassigned_mem_readl,
33417e70
FB		 2442};
2443
2444static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
2445 unassigned_mem_writeb,
e18231a3
BS		 2446 unassigned_mem_writew,
2447 unassigned_mem_writel,
33417e70
FB		 2448};
2449
0f459d16
PB		 2450static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
2451 uint32_t val)
9fa3e853 2452{
3a7d929e 2453 int dirty_flags;
3a7d929e
FB		 2454 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2455 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
9fa3e853 2456#if !defined(CONFIG_USER_ONLY)
3a7d929e
FB		 2457 tb_invalidate_phys_page_fast(ram_addr, 1);
2458 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
9fa3e853 2459#endif
3a7d929e 2460 }
0f459d16 2461 stb_p(phys_ram_base + ram_addr, val);
f32fc648
FB		 2462#ifdef USE_KQEMU
2463 if (cpu_single_env->kqemu_enabled &&
2464 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2465 kqemu_modify_page(cpu_single_env, ram_addr);
2466#endif
f23db169
FB		 2467 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2468 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2469 /* we remove the notdirty callback only if the code has been
2470 flushed */
2471 if (dirty_flags == 0xff)
2e70f6ef 2472 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
9fa3e853
FB		 2473}
2474
0f459d16
PB		 2475static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
2476 uint32_t val)
9fa3e853 2477{
3a7d929e 2478 int dirty_flags;
3a7d929e
FB		 2479 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2480 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
9fa3e853 2481#if !defined(CONFIG_USER_ONLY)
3a7d929e
FB		 2482 tb_invalidate_phys_page_fast(ram_addr, 2);
2483 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
9fa3e853 2484#endif
3a7d929e 2485 }
0f459d16 2486 stw_p(phys_ram_base + ram_addr, val);
f32fc648
FB		 2487#ifdef USE_KQEMU
2488 if (cpu_single_env->kqemu_enabled &&
2489 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2490 kqemu_modify_page(cpu_single_env, ram_addr);
2491#endif
f23db169
FB		 2492 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2493 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2494 /* we remove the notdirty callback only if the code has been
2495 flushed */
2496 if (dirty_flags == 0xff)
2e70f6ef 2497 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
9fa3e853
FB		 2498}
2499
0f459d16
PB		 2500static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
2501 uint32_t val)
9fa3e853 2502{
3a7d929e 2503 int dirty_flags;
3a7d929e
FB		 2504 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2505 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
9fa3e853 2506#if !defined(CONFIG_USER_ONLY)
3a7d929e
FB		 2507 tb_invalidate_phys_page_fast(ram_addr, 4);
2508 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
9fa3e853 2509#endif
3a7d929e 2510 }
0f459d16 2511 stl_p(phys_ram_base + ram_addr, val);
f32fc648
FB		 2512#ifdef USE_KQEMU
2513 if (cpu_single_env->kqemu_enabled &&
2514 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2515 kqemu_modify_page(cpu_single_env, ram_addr);
2516#endif
f23db169
FB		 2517 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2518 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2519 /* we remove the notdirty callback only if the code has been
2520 flushed */
2521 if (dirty_flags == 0xff)
2e70f6ef 2522 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
9fa3e853
FB		 2523}
2524
3a7d929e 2525static CPUReadMemoryFunc *error_mem_read[3] = {
9fa3e853
FB		 2526 NULL, /* never used */
2527 NULL, /* never used */
2528 NULL, /* never used */
2529};
2530
1ccde1cb
FB		 2531static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
2532 notdirty_mem_writeb,
2533 notdirty_mem_writew,
2534 notdirty_mem_writel,
2535};
2536
0f459d16 2537/* Generate a debug exception if a watchpoint has been hit. */
b4051334 2538static void check_watchpoint(int offset, int len_mask, int flags)
0f459d16
PB		 2539{
2540 CPUState *env = cpu_single_env;
06d55cc1
AL		 2541 target_ulong pc, cs_base;
2542 TranslationBlock *tb;
0f459d16 2543 target_ulong vaddr;
a1d1bb31 2544 CPUWatchpoint *wp;
06d55cc1 2545 int cpu_flags;
0f459d16 2546
06d55cc1
AL		 2547 if (env->watchpoint_hit) {
2548 /* We re-entered the check after replacing the TB. Now raise
2549 * the debug interrupt so that is will trigger after the
2550 * current instruction. */
2551 cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
2552 return;
2553 }
2e70f6ef 2554 vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
a1d1bb31 2555 for (wp = env->watchpoints; wp != NULL; wp = wp->next) {
b4051334
AL		 2556 if ((vaddr == (wp->vaddr & len_mask) ||
2557 (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
6e140f28
AL		 2558 wp->flags |= BP_WATCHPOINT_HIT;
2559 if (!env->watchpoint_hit) {
2560 env->watchpoint_hit = wp;
2561 tb = tb_find_pc(env->mem_io_pc);
2562 if (!tb) {
2563 cpu_abort(env, "check_watchpoint: could not find TB for "
2564 "pc=%p", (void *)env->mem_io_pc);
2565 }
2566 cpu_restore_state(tb, env, env->mem_io_pc, NULL);
2567 tb_phys_invalidate(tb, -1);
2568 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2569 env->exception_index = EXCP_DEBUG;
2570 } else {
2571 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2572 tb_gen_code(env, pc, cs_base, cpu_flags, 1);
2573 }
2574 cpu_resume_from_signal(env, NULL);
06d55cc1 2575 }
6e140f28
AL		 2576 } else {
2577 wp->flags &= ~BP_WATCHPOINT_HIT;
0f459d16
PB		 2578 }
2579 }
2580}
2581
6658ffb8
PB		 2582/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2583 so these check for a hit then pass through to the normal out-of-line
2584 phys routines. */
2585static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2586{
b4051334 2587 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
6658ffb8
PB		 2588 return ldub_phys(addr);
2589}
2590
2591static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2592{
b4051334 2593 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
6658ffb8
PB		 2594 return lduw_phys(addr);
2595}
2596
2597static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2598{
b4051334 2599 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
6658ffb8
PB		 2600 return ldl_phys(addr);
2601}
2602
6658ffb8
PB		 2603static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2604 uint32_t val)
2605{
b4051334 2606 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
6658ffb8
PB		 2607 stb_phys(addr, val);
2608}
2609
2610static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2611 uint32_t val)
2612{
b4051334 2613 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
6658ffb8
PB		 2614 stw_phys(addr, val);
2615}
2616
2617static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2618 uint32_t val)
2619{
b4051334 2620 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
6658ffb8
PB		 2621 stl_phys(addr, val);
2622}
2623
2624static CPUReadMemoryFunc *watch_mem_read[3] = {
2625 watch_mem_readb,
2626 watch_mem_readw,
2627 watch_mem_readl,
2628};
2629
2630static CPUWriteMemoryFunc *watch_mem_write[3] = {
2631 watch_mem_writeb,
2632 watch_mem_writew,
2633 watch_mem_writel,
2634};
6658ffb8 2635
db7b5426
BS		 2636static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
2637 unsigned int len)
2638{
db7b5426
BS		 2639 uint32_t ret;
2640 unsigned int idx;
2641
2642 idx = SUBPAGE_IDX(addr - mmio->base);
2643#if defined(DEBUG_SUBPAGE)
2644 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
2645 mmio, len, addr, idx);
2646#endif
3ee89922 2647 ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr);
db7b5426
BS		 2648
2649 return ret;
2650}
2651
2652static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
2653 uint32_t value, unsigned int len)
2654{
db7b5426
BS		 2655 unsigned int idx;
2656
2657 idx = SUBPAGE_IDX(addr - mmio->base);
2658#if defined(DEBUG_SUBPAGE)
2659 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
2660 mmio, len, addr, idx, value);
2661#endif
3ee89922 2662 (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value);
db7b5426
BS		 2663}
2664
2665static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
2666{
2667#if defined(DEBUG_SUBPAGE)
2668 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2669#endif
2670
2671 return subpage_readlen(opaque, addr, 0);
2672}
2673
2674static void subpage_writeb (void *opaque, target_phys_addr_t addr,
2675 uint32_t value)
2676{
2677#if defined(DEBUG_SUBPAGE)
2678 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2679#endif
2680 subpage_writelen(opaque, addr, value, 0);
2681}
2682
2683static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
2684{
2685#if defined(DEBUG_SUBPAGE)
2686 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2687#endif
2688
2689 return subpage_readlen(opaque, addr, 1);
2690}
2691
2692static void subpage_writew (void *opaque, target_phys_addr_t addr,
2693 uint32_t value)
2694{
2695#if defined(DEBUG_SUBPAGE)
2696 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2697#endif
2698 subpage_writelen(opaque, addr, value, 1);
2699}
2700
2701static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
2702{
2703#if defined(DEBUG_SUBPAGE)
2704 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2705#endif
2706
2707 return subpage_readlen(opaque, addr, 2);
2708}
2709
2710static void subpage_writel (void *opaque,
2711 target_phys_addr_t addr, uint32_t value)
2712{
2713#if defined(DEBUG_SUBPAGE)
2714 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2715#endif
2716 subpage_writelen(opaque, addr, value, 2);
2717}
2718
2719static CPUReadMemoryFunc *subpage_read[] = {
2720 &subpage_readb,
2721 &subpage_readw,
2722 &subpage_readl,
2723};
2724
2725static CPUWriteMemoryFunc *subpage_write[] = {
2726 &subpage_writeb,
2727 &subpage_writew,
2728 &subpage_writel,
2729};
2730
2731static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
00f82b8a 2732 ram_addr_t memory)
db7b5426
BS		 2733{
2734 int idx, eidx;
4254fab8 2735 unsigned int i;
db7b5426
BS		 2736
2737 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2738 return -1;
2739 idx = SUBPAGE_IDX(start);
2740 eidx = SUBPAGE_IDX(end);
2741#if defined(DEBUG_SUBPAGE)
2742 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
2743 mmio, start, end, idx, eidx, memory);
2744#endif
2745 memory >>= IO_MEM_SHIFT;
2746 for (; idx <= eidx; idx++) {
4254fab8 2747 for (i = 0; i < 4; i++) {
3ee89922
BS		 2748 if (io_mem_read[memory][i]) {
2749 mmio->mem_read[idx][i] = &io_mem_read[memory][i];
2750 mmio->opaque[idx][0][i] = io_mem_opaque[memory];
2751 }
2752 if (io_mem_write[memory][i]) {
2753 mmio->mem_write[idx][i] = &io_mem_write[memory][i];
2754 mmio->opaque[idx][1][i] = io_mem_opaque[memory];
2755 }
4254fab8 2756 }
db7b5426
BS		 2757 }
2758
2759 return 0;
2760}
2761
00f82b8a
AJ		 2762static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2763 ram_addr_t orig_memory)
db7b5426
BS		 2764{
2765 subpage_t *mmio;
2766 int subpage_memory;
2767
2768 mmio = qemu_mallocz(sizeof(subpage_t));
2769 if (mmio != NULL) {
2770 mmio->base = base;
2771 subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
2772#if defined(DEBUG_SUBPAGE)
2773 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
2774 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
2775#endif
2776 *phys = subpage_memory | IO_MEM_SUBPAGE;
2777 subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory);
2778 }
2779
2780 return mmio;
2781}
2782
33417e70
FB		 2783static void io_mem_init(void)
2784{
3a7d929e 2785 cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
a4193c8a 2786 cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
3a7d929e 2787 cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
1ccde1cb
FB		 2788 io_mem_nb = 5;
2789
0f459d16 2790 io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
6658ffb8 2791 watch_mem_write, NULL);
1ccde1cb 2792 /* alloc dirty bits array */
0a962c02 2793 phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
3a7d929e 2794 memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
33417e70
FB		 2795}
2796
2797/* mem_read and mem_write are arrays of functions containing the
2798 function to access byte (index 0), word (index 1) and dword (index
3ee89922
BS		 2799 2). Functions can be omitted with a NULL function pointer. The
2800 registered functions may be modified dynamically later.
2801 If io_index is non zero, the corresponding io zone is
4254fab8
BS		 2802 modified. If it is zero, a new io zone is allocated. The return
2803 value can be used with cpu_register_physical_memory(). (-1) is
2804 returned if error. */
33417e70
FB		 2805int cpu_register_io_memory(int io_index,
2806 CPUReadMemoryFunc **mem_read,
a4193c8a
FB		 2807 CPUWriteMemoryFunc **mem_write,
2808 void *opaque)
33417e70 2809{
4254fab8 2810 int i, subwidth = 0;
33417e70
FB		 2811
2812 if (io_index <= 0) {
b5ff1b31 2813 if (io_mem_nb >= IO_MEM_NB_ENTRIES)
33417e70
FB		 2814 return -1;
2815 io_index = io_mem_nb++;
2816 } else {
2817 if (io_index >= IO_MEM_NB_ENTRIES)
2818 return -1;
2819 }
b5ff1b31 2820
33417e70 2821 for(i = 0;i < 3; i++) {
4254fab8
BS		 2822 if (!mem_read[i] || !mem_write[i])
2823 subwidth = IO_MEM_SUBWIDTH;
33417e70
FB		 2824 io_mem_read[io_index][i] = mem_read[i];
2825 io_mem_write[io_index][i] = mem_write[i];
2826 }
a4193c8a 2827 io_mem_opaque[io_index] = opaque;
4254fab8 2828 return (io_index << IO_MEM_SHIFT) | subwidth;
33417e70 2829}
61382a50 2830
8926b517
FB		 2831CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
2832{
2833 return io_mem_write[io_index >> IO_MEM_SHIFT];
2834}
2835
2836CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
2837{
2838 return io_mem_read[io_index >> IO_MEM_SHIFT];
2839}
2840
e2eef170
PB		 2841#endif /* !defined(CONFIG_USER_ONLY) */
2842
13eb76e0
FB		 2843/* physical memory access (slow version, mainly for debug) */
2844#if defined(CONFIG_USER_ONLY)
5fafdf24 2845void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
13eb76e0
FB		 2846 int len, int is_write)
2847{
2848 int l, flags;
2849 target_ulong page;
53a5960a 2850 void * p;
13eb76e0
FB		 2851
2852 while (len > 0) {
2853 page = addr & TARGET_PAGE_MASK;
2854 l = (page + TARGET_PAGE_SIZE) - addr;
2855 if (l > len)
2856 l = len;
2857 flags = page_get_flags(page);
2858 if (!(flags & PAGE_VALID))
2859 return;
2860 if (is_write) {
2861 if (!(flags & PAGE_WRITE))
2862 return;
579a97f7 2863 /* XXX: this code should not depend on lock_user */
72fb7daa 2864 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
579a97f7
FB		 2865 /* FIXME - should this return an error rather than just fail? */
2866 return;
72fb7daa
AJ		 2867 memcpy(p, buf, l);
2868 unlock_user(p, addr, l);
13eb76e0
FB		 2869 } else {
2870 if (!(flags & PAGE_READ))
2871 return;
579a97f7 2872 /* XXX: this code should not depend on lock_user */
72fb7daa 2873 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
579a97f7
FB		 2874 /* FIXME - should this return an error rather than just fail? */
2875 return;
72fb7daa 2876 memcpy(buf, p, l);
5b257578 2877 unlock_user(p, addr, 0);
13eb76e0
FB		 2878 }
2879 len -= l;
2880 buf += l;
2881 addr += l;
2882 }
2883}
8df1cd07 2884
13eb76e0 2885#else
5fafdf24 2886void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
13eb76e0
FB		 2887 int len, int is_write)
2888{
2889 int l, io_index;
2890 uint8_t *ptr;
2891 uint32_t val;
2e12669a
FB		 2892 target_phys_addr_t page;
2893 unsigned long pd;
92e873b9 2894 PhysPageDesc *p;
3b46e624 2895
13eb76e0
FB		 2896 while (len > 0) {
2897 page = addr & TARGET_PAGE_MASK;
2898 l = (page + TARGET_PAGE_SIZE) - addr;
2899 if (l > len)
2900 l = len;
92e873b9 2901 p = phys_page_find(page >> TARGET_PAGE_BITS);
13eb76e0
FB		 2902 if (!p) {
2903 pd = IO_MEM_UNASSIGNED;
2904 } else {
2905 pd = p->phys_offset;
2906 }
3b46e624 2907
13eb76e0 2908 if (is_write) {
3a7d929e 2909 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
13eb76e0 2910 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
6a00d601
FB		 2911 /* XXX: could force cpu_single_env to NULL to avoid
2912 potential bugs */
13eb76e0 2913 if (l >= 4 && ((addr & 3) == 0)) {
1c213d19 2914 /* 32 bit write access */
c27004ec 2915 val = ldl_p(buf);
a4193c8a 2916 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
13eb76e0
FB		 2917 l = 4;
2918 } else if (l >= 2 && ((addr & 1) == 0)) {
1c213d19 2919 /* 16 bit write access */
c27004ec 2920 val = lduw_p(buf);
a4193c8a 2921 io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
13eb76e0
FB		 2922 l = 2;
2923 } else {
1c213d19 2924 /* 8 bit write access */
c27004ec 2925 val = ldub_p(buf);
a4193c8a 2926 io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
13eb76e0
FB		 2927 l = 1;
2928 }
2929 } else {
b448f2f3
FB		 2930 unsigned long addr1;
2931 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
13eb76e0 2932 /* RAM case */
b448f2f3 2933 ptr = phys_ram_base + addr1;
13eb76e0 2934 memcpy(ptr, buf, l);
3a7d929e
FB		 2935 if (!cpu_physical_memory_is_dirty(addr1)) {
2936 /* invalidate code */
2937 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
2938 /* set dirty bit */
5fafdf24 2939 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
f23db169 2940 (0xff & ~CODE_DIRTY_FLAG);
3a7d929e 2941 }
13eb76e0
FB		 2942 }
2943 } else {
5fafdf24 2944 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
2a4188a3 2945 !(pd & IO_MEM_ROMD)) {
13eb76e0
FB		 2946 /* I/O case */
2947 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2948 if (l >= 4 && ((addr & 3) == 0)) {
2949 /* 32 bit read access */
a4193c8a 2950 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
c27004ec 2951 stl_p(buf, val);
13eb76e0
FB		 2952 l = 4;
2953 } else if (l >= 2 && ((addr & 1) == 0)) {
2954 /* 16 bit read access */
a4193c8a 2955 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
c27004ec 2956 stw_p(buf, val);
13eb76e0
FB		 2957 l = 2;
2958 } else {
1c213d19 2959 /* 8 bit read access */
a4193c8a 2960 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
c27004ec 2961 stb_p(buf, val);
13eb76e0
FB		 2962 l = 1;
2963 }
2964 } else {
2965 /* RAM case */
5fafdf24 2966 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
13eb76e0
FB		 2967 (addr & ~TARGET_PAGE_MASK);
2968 memcpy(buf, ptr, l);
2969 }
2970 }
2971 len -= l;
2972 buf += l;
2973 addr += l;
2974 }
2975}
8df1cd07 2976
d0ecd2aa 2977/* used for ROM loading : can write in RAM and ROM */
5fafdf24 2978void cpu_physical_memory_write_rom(target_phys_addr_t addr,
d0ecd2aa
FB		 2979 const uint8_t *buf, int len)
2980{
2981 int l;
2982 uint8_t *ptr;
2983 target_phys_addr_t page;
2984 unsigned long pd;
2985 PhysPageDesc *p;
3b46e624 2986
d0ecd2aa
FB		 2987 while (len > 0) {
2988 page = addr & TARGET_PAGE_MASK;
2989 l = (page + TARGET_PAGE_SIZE) - addr;
2990 if (l > len)
2991 l = len;
2992 p = phys_page_find(page >> TARGET_PAGE_BITS);
2993 if (!p) {
2994 pd = IO_MEM_UNASSIGNED;
2995 } else {
2996 pd = p->phys_offset;
2997 }
3b46e624 2998
d0ecd2aa 2999 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
2a4188a3
FB		 3000 (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
3001 !(pd & IO_MEM_ROMD)) {
d0ecd2aa
FB		 3002 /* do nothing */
3003 } else {
3004 unsigned long addr1;
3005 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3006 /* ROM/RAM case */
3007 ptr = phys_ram_base + addr1;
3008 memcpy(ptr, buf, l);
3009 }
3010 len -= l;
3011 buf += l;
3012 addr += l;
3013 }
3014}
3015
3016
8df1cd07
FB		 3017/* warning: addr must be aligned */
3018uint32_t ldl_phys(target_phys_addr_t addr)
3019{
3020 int io_index;
3021 uint8_t *ptr;
3022 uint32_t val;
3023 unsigned long pd;
3024 PhysPageDesc *p;
3025
3026 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3027 if (!p) {
3028 pd = IO_MEM_UNASSIGNED;
3029 } else {
3030 pd = p->phys_offset;
3031 }
3b46e624 3032
5fafdf24 3033 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
2a4188a3 3034 !(pd & IO_MEM_ROMD)) {
8df1cd07
FB		 3035 /* I/O case */
3036 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3037 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3038 } else {
3039 /* RAM case */
5fafdf24 3040 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
8df1cd07
FB		 3041 (addr & ~TARGET_PAGE_MASK);
3042 val = ldl_p(ptr);
3043 }
3044 return val;
3045}
3046
84b7b8e7
FB		 3047/* warning: addr must be aligned */
3048uint64_t ldq_phys(target_phys_addr_t addr)
3049{
3050 int io_index;
3051 uint8_t *ptr;
3052 uint64_t val;
3053 unsigned long pd;
3054 PhysPageDesc *p;
3055
3056 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3057 if (!p) {
3058 pd = IO_MEM_UNASSIGNED;
3059 } else {
3060 pd = p->phys_offset;
3061 }
3b46e624 3062
2a4188a3
FB		 3063 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3064 !(pd & IO_MEM_ROMD)) {
84b7b8e7
FB		 3065 /* I/O case */
3066 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3067#ifdef TARGET_WORDS_BIGENDIAN
3068 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3069 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3070#else
3071 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3072 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3073#endif
3074 } else {
3075 /* RAM case */
5fafdf24 3076 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
84b7b8e7
FB		 3077 (addr & ~TARGET_PAGE_MASK);
3078 val = ldq_p(ptr);
3079 }
3080 return val;
3081}
3082
aab33094
FB		 3083/* XXX: optimize */
3084uint32_t ldub_phys(target_phys_addr_t addr)
3085{
3086 uint8_t val;
3087 cpu_physical_memory_read(addr, &val, 1);
3088 return val;
3089}
3090
3091/* XXX: optimize */
3092uint32_t lduw_phys(target_phys_addr_t addr)
3093{
3094 uint16_t val;
3095 cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
3096 return tswap16(val);
3097}
3098
8df1cd07
FB		 3099/* warning: addr must be aligned. The ram page is not masked as dirty
3100 and the code inside is not invalidated. It is useful if the dirty
3101 bits are used to track modified PTEs */
3102void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
3103{
3104 int io_index;
3105 uint8_t *ptr;
3106 unsigned long pd;
3107 PhysPageDesc *p;
3108
3109 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3110 if (!p) {
3111 pd = IO_MEM_UNASSIGNED;
3112 } else {
3113 pd = p->phys_offset;
3114 }
3b46e624 3115
3a7d929e 3116 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
8df1cd07
FB		 3117 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3118 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3119 } else {
74576198
AL		 3120 unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3121 ptr = phys_ram_base + addr1;
8df1cd07 3122 stl_p(ptr, val);
74576198
AL		 3123
3124 if (unlikely(in_migration)) {
3125 if (!cpu_physical_memory_is_dirty(addr1)) {
3126 /* invalidate code */
3127 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3128 /* set dirty bit */
3129 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3130 (0xff & ~CODE_DIRTY_FLAG);
3131 }
3132 }
8df1cd07
FB		 3133 }
3134}
3135
bc98a7ef
JM		 3136void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
3137{
3138 int io_index;
3139 uint8_t *ptr;
3140 unsigned long pd;
3141 PhysPageDesc *p;
3142
3143 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3144 if (!p) {
3145 pd = IO_MEM_UNASSIGNED;
3146 } else {
3147 pd = p->phys_offset;
3148 }
3b46e624 3149
bc98a7ef
JM		 3150 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3151 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3152#ifdef TARGET_WORDS_BIGENDIAN
3153 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3154 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3155#else
3156 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3157 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3158#endif
3159 } else {
5fafdf24 3160 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bc98a7ef
JM		 3161 (addr & ~TARGET_PAGE_MASK);
3162 stq_p(ptr, val);
3163 }
3164}
3165
8df1cd07 3166/* warning: addr must be aligned */
8df1cd07
FB		 3167void stl_phys(target_phys_addr_t addr, uint32_t val)
3168{
3169 int io_index;
3170 uint8_t *ptr;
3171 unsigned long pd;
3172 PhysPageDesc *p;
3173
3174 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3175 if (!p) {
3176 pd = IO_MEM_UNASSIGNED;
3177 } else {
3178 pd = p->phys_offset;
3179 }
3b46e624 3180
3a7d929e 3181 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
8df1cd07
FB		 3182 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3183 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3184 } else {
3185 unsigned long addr1;
3186 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3187 /* RAM case */
3188 ptr = phys_ram_base + addr1;
3189 stl_p(ptr, val);
3a7d929e
FB		 3190 if (!cpu_physical_memory_is_dirty(addr1)) {
3191 /* invalidate code */
3192 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3193 /* set dirty bit */
f23db169
FB		 3194 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3195 (0xff & ~CODE_DIRTY_FLAG);
3a7d929e 3196 }
8df1cd07
FB		 3197 }
3198}
3199
aab33094
FB		 3200/* XXX: optimize */
3201void stb_phys(target_phys_addr_t addr, uint32_t val)
3202{
3203 uint8_t v = val;
3204 cpu_physical_memory_write(addr, &v, 1);
3205}
3206
3207/* XXX: optimize */
3208void stw_phys(target_phys_addr_t addr, uint32_t val)
3209{
3210 uint16_t v = tswap16(val);
3211 cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
3212}
3213
3214/* XXX: optimize */
3215void stq_phys(target_phys_addr_t addr, uint64_t val)
3216{
3217 val = tswap64(val);
3218 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3219}
3220
13eb76e0
FB		 3221#endif
3222
3223/* virtual memory access for debug */
5fafdf24 3224int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
b448f2f3 3225 uint8_t *buf, int len, int is_write)
13eb76e0
FB		 3226{
3227 int l;
9b3c35e0
JM		 3228 target_phys_addr_t phys_addr;
3229 target_ulong page;
13eb76e0
FB		 3230
3231 while (len > 0) {
3232 page = addr & TARGET_PAGE_MASK;
3233 phys_addr = cpu_get_phys_page_debug(env, page);
3234 /* if no physical page mapped, return an error */
3235 if (phys_addr == -1)
3236 return -1;
3237 l = (page + TARGET_PAGE_SIZE) - addr;
3238 if (l > len)
3239 l = len;
5fafdf24 3240 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
b448f2f3 3241 buf, l, is_write);
13eb76e0
FB		 3242 len -= l;
3243 buf += l;
3244 addr += l;
3245 }
3246 return 0;
3247}
3248
2e70f6ef
PB		 3249/* in deterministic execution mode, instructions doing device I/Os
3250 must be at the end of the TB */
3251void cpu_io_recompile(CPUState *env, void *retaddr)
3252{
3253 TranslationBlock *tb;
3254 uint32_t n, cflags;
3255 target_ulong pc, cs_base;
3256 uint64_t flags;
3257
3258 tb = tb_find_pc((unsigned long)retaddr);
3259 if (!tb) {
3260 cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
3261 retaddr);
3262 }
3263 n = env->icount_decr.u16.low + tb->icount;
3264 cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
3265 /* Calculate how many instructions had been executed before the fault
bf20dc07 3266 occurred. */
2e70f6ef
PB		 3267 n = n - env->icount_decr.u16.low;
3268 /* Generate a new TB ending on the I/O insn. */
3269 n++;
3270 /* On MIPS and SH, delay slot instructions can only be restarted if
3271 they were already the first instruction in the TB. If this is not
bf20dc07 3272 the first instruction in a TB then re-execute the preceding
2e70f6ef
PB		 3273 branch. */
3274#if defined(TARGET_MIPS)
3275 if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
3276 env->active_tc.PC -= 4;
3277 env->icount_decr.u16.low++;
3278 env->hflags &= ~MIPS_HFLAG_BMASK;
3279 }
3280#elif defined(TARGET_SH4)
3281 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
3282 && n > 1) {
3283 env->pc -= 2;
3284 env->icount_decr.u16.low++;
3285 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
3286 }
3287#endif
3288 /* This should never happen. */
3289 if (n > CF_COUNT_MASK)
3290 cpu_abort(env, "TB too big during recompile");
3291
3292 cflags = n | CF_LAST_IO;
3293 pc = tb->pc;
3294 cs_base = tb->cs_base;
3295 flags = tb->flags;
3296 tb_phys_invalidate(tb, -1);
3297 /* FIXME: In theory this could raise an exception. In practice
3298 we have already translated the block once so it's probably ok. */
3299 tb_gen_code(env, pc, cs_base, flags, cflags);
bf20dc07 3300 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
2e70f6ef
PB		 3301 the first in the TB) then we end up generating a whole new TB and
3302 repeating the fault, which is horribly inefficient.
3303 Better would be to execute just this insn uncached, or generate a
3304 second new TB. */
3305 cpu_resume_from_signal(env, NULL);
3306}
3307
e3db7226
FB		 3308void dump_exec_info(FILE *f,
3309 int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3310{
3311 int i, target_code_size, max_target_code_size;
3312 int direct_jmp_count, direct_jmp2_count, cross_page;
3313 TranslationBlock *tb;
3b46e624 3314
e3db7226
FB		 3315 target_code_size = 0;
3316 max_target_code_size = 0;
3317 cross_page = 0;
3318 direct_jmp_count = 0;
3319 direct_jmp2_count = 0;
3320 for(i = 0; i < nb_tbs; i++) {
3321 tb = &tbs[i];
3322 target_code_size += tb->size;
3323 if (tb->size > max_target_code_size)
3324 max_target_code_size = tb->size;
3325 if (tb->page_addr[1] != -1)
3326 cross_page++;
3327 if (tb->tb_next_offset[0] != 0xffff) {
3328 direct_jmp_count++;
3329 if (tb->tb_next_offset[1] != 0xffff) {
3330 direct_jmp2_count++;
3331 }
3332 }
3333 }
3334 /* XXX: avoid using doubles ? */
57fec1fe 3335 cpu_fprintf(f, "Translation buffer state:\n");
26a5f13b
FB		 3336 cpu_fprintf(f, "gen code size %ld/%ld\n",
3337 code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
3338 cpu_fprintf(f, "TB count %d/%d\n",
3339 nb_tbs, code_gen_max_blocks);
5fafdf24 3340 cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
e3db7226
FB		 3341 nb_tbs ? target_code_size / nb_tbs : 0,
3342 max_target_code_size);
5fafdf24 3343 cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
e3db7226
FB		 3344 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
3345 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
5fafdf24
TS		 3346 cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
3347 cross_page,
e3db7226
FB		 3348 nb_tbs ? (cross_page * 100) / nb_tbs : 0);
3349 cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
5fafdf24 3350 direct_jmp_count,
e3db7226
FB		 3351 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
3352 direct_jmp2_count,
3353 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
57fec1fe 3354 cpu_fprintf(f, "\nStatistics:\n");
e3db7226
FB		 3355 cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
3356 cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
3357 cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
b67d9a52 3358 tcg_dump_info(f, cpu_fprintf);
e3db7226
FB		 3359}
3360
5fafdf24 3361#if !defined(CONFIG_USER_ONLY)
61382a50
FB		 3362
3363#define MMUSUFFIX _cmmu
3364#define GETPC() NULL
3365#define env cpu_single_env
b769d8fe 3366#define SOFTMMU_CODE_ACCESS
61382a50
FB		 3367
3368#define SHIFT 0
3369#include "softmmu_template.h"
3370
3371#define SHIFT 1
3372#include "softmmu_template.h"
3373
3374#define SHIFT 2
3375#include "softmmu_template.h"
3376
3377#define SHIFT 3
3378#include "softmmu_template.h"
3379
3380#undef env
3381
3382#endif
Qemu copy for testing