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Commit | Line | Data |
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54936004 | 1 | /* |
5b6dd868 | 2 | * Virtual page mapping |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 | 26 | |
055403b2 | 27 | #include "qemu-common.h" |
6180a181 | 28 | #include "cpu.h" |
b67d9a52 | 29 | #include "tcg.h" |
b3c7724c | 30 | #include "hw/hw.h" |
cc9e98cb | 31 | #include "hw/qdev.h" |
1de7afc9 | 32 | #include "qemu/osdep.h" |
9c17d615 | 33 | #include "sysemu/kvm.h" |
2ff3de68 | 34 | #include "sysemu/sysemu.h" |
0d09e41a | 35 | #include "hw/xen/xen.h" |
1de7afc9 PB |
36 | #include "qemu/timer.h" |
37 | #include "qemu/config-file.h" | |
022c62cb | 38 | #include "exec/memory.h" |
9c17d615 | 39 | #include "sysemu/dma.h" |
022c62cb | 40 | #include "exec/address-spaces.h" |
53a5960a PB |
41 | #if defined(CONFIG_USER_ONLY) |
42 | #include <qemu.h> | |
432d268c | 43 | #else /* !CONFIG_USER_ONLY */ |
9c17d615 | 44 | #include "sysemu/xen-mapcache.h" |
6506e4f9 | 45 | #include "trace.h" |
53a5960a | 46 | #endif |
0d6d3c87 | 47 | #include "exec/cpu-all.h" |
54936004 | 48 | |
022c62cb | 49 | #include "exec/cputlb.h" |
5b6dd868 | 50 | #include "translate-all.h" |
0cac1b66 | 51 | |
022c62cb | 52 | #include "exec/memory-internal.h" |
582b55a9 | 53 | #include "qemu/cache-utils.h" |
67d95c15 | 54 | |
b35ba30f MT |
55 | #include "qemu/range.h" |
56 | ||
db7b5426 | 57 | //#define DEBUG_SUBPAGE |
1196be37 | 58 | |
e2eef170 | 59 | #if !defined(CONFIG_USER_ONLY) |
74576198 | 60 | static int in_migration; |
94a6b54f | 61 | |
a3161038 | 62 | RAMList ram_list = { .blocks = QTAILQ_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
63 | |
64 | static MemoryRegion *system_memory; | |
309cb471 | 65 | static MemoryRegion *system_io; |
62152b8a | 66 | |
f6790af6 AK |
67 | AddressSpace address_space_io; |
68 | AddressSpace address_space_memory; | |
2673a5da | 69 | |
0844e007 | 70 | MemoryRegion io_mem_rom, io_mem_notdirty; |
acc9d80b | 71 | static MemoryRegion io_mem_unassigned; |
0e0df1e2 | 72 | |
e2eef170 | 73 | #endif |
9fa3e853 | 74 | |
bdc44640 | 75 | struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); |
6a00d601 FB |
76 | /* current CPU in the current thread. It is only valid inside |
77 | cpu_exec() */ | |
4917cf44 | 78 | DEFINE_TLS(CPUState *, current_cpu); |
2e70f6ef | 79 | /* 0 = Do not count executed instructions. |
bf20dc07 | 80 | 1 = Precise instruction counting. |
2e70f6ef | 81 | 2 = Adaptive rate instruction counting. */ |
5708fc66 | 82 | int use_icount; |
6a00d601 | 83 | |
e2eef170 | 84 | #if !defined(CONFIG_USER_ONLY) |
4346ae3e | 85 | |
1db8abb1 PB |
86 | typedef struct PhysPageEntry PhysPageEntry; |
87 | ||
88 | struct PhysPageEntry { | |
9736e55b | 89 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ |
8b795765 | 90 | uint32_t skip : 6; |
9736e55b | 91 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ |
8b795765 | 92 | uint32_t ptr : 26; |
1db8abb1 PB |
93 | }; |
94 | ||
8b795765 MT |
95 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
96 | ||
03f49957 | 97 | /* Size of the L2 (and L3, etc) page tables. */ |
57271d63 | 98 | #define ADDR_SPACE_BITS 64 |
03f49957 | 99 | |
026736ce | 100 | #define P_L2_BITS 9 |
03f49957 PB |
101 | #define P_L2_SIZE (1 << P_L2_BITS) |
102 | ||
103 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
104 | ||
105 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
0475d94f | 106 | |
53cb28cb MA |
107 | typedef struct PhysPageMap { |
108 | unsigned sections_nb; | |
109 | unsigned sections_nb_alloc; | |
110 | unsigned nodes_nb; | |
111 | unsigned nodes_nb_alloc; | |
112 | Node *nodes; | |
113 | MemoryRegionSection *sections; | |
114 | } PhysPageMap; | |
115 | ||
1db8abb1 PB |
116 | struct AddressSpaceDispatch { |
117 | /* This is a multi-level map on the physical address space. | |
118 | * The bottom level has pointers to MemoryRegionSections. | |
119 | */ | |
120 | PhysPageEntry phys_map; | |
53cb28cb | 121 | PhysPageMap map; |
acc9d80b | 122 | AddressSpace *as; |
1db8abb1 PB |
123 | }; |
124 | ||
90260c6c JK |
125 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
126 | typedef struct subpage_t { | |
127 | MemoryRegion iomem; | |
acc9d80b | 128 | AddressSpace *as; |
90260c6c JK |
129 | hwaddr base; |
130 | uint16_t sub_section[TARGET_PAGE_SIZE]; | |
131 | } subpage_t; | |
132 | ||
b41aac4f LPF |
133 | #define PHYS_SECTION_UNASSIGNED 0 |
134 | #define PHYS_SECTION_NOTDIRTY 1 | |
135 | #define PHYS_SECTION_ROM 2 | |
136 | #define PHYS_SECTION_WATCH 3 | |
5312bd8b | 137 | |
e2eef170 | 138 | static void io_mem_init(void); |
62152b8a | 139 | static void memory_map_init(void); |
e2eef170 | 140 | |
1ec9b909 | 141 | static MemoryRegion io_mem_watch; |
6658ffb8 | 142 | #endif |
fd6ce8f6 | 143 | |
6d9a1304 | 144 | #if !defined(CONFIG_USER_ONLY) |
d6f2ea22 | 145 | |
53cb28cb | 146 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
d6f2ea22 | 147 | { |
53cb28cb MA |
148 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { |
149 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc * 2, 16); | |
150 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); | |
151 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); | |
d6f2ea22 | 152 | } |
f7bf5461 AK |
153 | } |
154 | ||
53cb28cb | 155 | static uint32_t phys_map_node_alloc(PhysPageMap *map) |
f7bf5461 AK |
156 | { |
157 | unsigned i; | |
8b795765 | 158 | uint32_t ret; |
f7bf5461 | 159 | |
53cb28cb | 160 | ret = map->nodes_nb++; |
f7bf5461 | 161 | assert(ret != PHYS_MAP_NODE_NIL); |
53cb28cb | 162 | assert(ret != map->nodes_nb_alloc); |
03f49957 | 163 | for (i = 0; i < P_L2_SIZE; ++i) { |
53cb28cb MA |
164 | map->nodes[ret][i].skip = 1; |
165 | map->nodes[ret][i].ptr = PHYS_MAP_NODE_NIL; | |
d6f2ea22 | 166 | } |
f7bf5461 | 167 | return ret; |
d6f2ea22 AK |
168 | } |
169 | ||
53cb28cb MA |
170 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
171 | hwaddr *index, hwaddr *nb, uint16_t leaf, | |
2999097b | 172 | int level) |
f7bf5461 AK |
173 | { |
174 | PhysPageEntry *p; | |
175 | int i; | |
03f49957 | 176 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); |
108c49b8 | 177 | |
9736e55b | 178 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { |
53cb28cb MA |
179 | lp->ptr = phys_map_node_alloc(map); |
180 | p = map->nodes[lp->ptr]; | |
f7bf5461 | 181 | if (level == 0) { |
03f49957 | 182 | for (i = 0; i < P_L2_SIZE; i++) { |
9736e55b | 183 | p[i].skip = 0; |
b41aac4f | 184 | p[i].ptr = PHYS_SECTION_UNASSIGNED; |
4346ae3e | 185 | } |
67c4d23c | 186 | } |
f7bf5461 | 187 | } else { |
53cb28cb | 188 | p = map->nodes[lp->ptr]; |
92e873b9 | 189 | } |
03f49957 | 190 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
f7bf5461 | 191 | |
03f49957 | 192 | while (*nb && lp < &p[P_L2_SIZE]) { |
07f07b31 | 193 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
9736e55b | 194 | lp->skip = 0; |
c19e8800 | 195 | lp->ptr = leaf; |
07f07b31 AK |
196 | *index += step; |
197 | *nb -= step; | |
2999097b | 198 | } else { |
53cb28cb | 199 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); |
2999097b AK |
200 | } |
201 | ++lp; | |
f7bf5461 AK |
202 | } |
203 | } | |
204 | ||
ac1970fb | 205 | static void phys_page_set(AddressSpaceDispatch *d, |
a8170e5e | 206 | hwaddr index, hwaddr nb, |
2999097b | 207 | uint16_t leaf) |
f7bf5461 | 208 | { |
2999097b | 209 | /* Wildly overreserve - it doesn't matter much. */ |
53cb28cb | 210 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); |
5cd2c5b6 | 211 | |
53cb28cb | 212 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
213 | } |
214 | ||
b35ba30f MT |
215 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, |
216 | * and update our entry so we can skip it and go directly to the destination. | |
217 | */ | |
218 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes, unsigned long *compacted) | |
219 | { | |
220 | unsigned valid_ptr = P_L2_SIZE; | |
221 | int valid = 0; | |
222 | PhysPageEntry *p; | |
223 | int i; | |
224 | ||
225 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
226 | return; | |
227 | } | |
228 | ||
229 | p = nodes[lp->ptr]; | |
230 | for (i = 0; i < P_L2_SIZE; i++) { | |
231 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
232 | continue; | |
233 | } | |
234 | ||
235 | valid_ptr = i; | |
236 | valid++; | |
237 | if (p[i].skip) { | |
238 | phys_page_compact(&p[i], nodes, compacted); | |
239 | } | |
240 | } | |
241 | ||
242 | /* We can only compress if there's only one child. */ | |
243 | if (valid != 1) { | |
244 | return; | |
245 | } | |
246 | ||
247 | assert(valid_ptr < P_L2_SIZE); | |
248 | ||
249 | /* Don't compress if it won't fit in the # of bits we have. */ | |
250 | if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { | |
251 | return; | |
252 | } | |
253 | ||
254 | lp->ptr = p[valid_ptr].ptr; | |
255 | if (!p[valid_ptr].skip) { | |
256 | /* If our only child is a leaf, make this a leaf. */ | |
257 | /* By design, we should have made this node a leaf to begin with so we | |
258 | * should never reach here. | |
259 | * But since it's so simple to handle this, let's do it just in case we | |
260 | * change this rule. | |
261 | */ | |
262 | lp->skip = 0; | |
263 | } else { | |
264 | lp->skip += p[valid_ptr].skip; | |
265 | } | |
266 | } | |
267 | ||
268 | static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb) | |
269 | { | |
270 | DECLARE_BITMAP(compacted, nodes_nb); | |
271 | ||
272 | if (d->phys_map.skip) { | |
53cb28cb | 273 | phys_page_compact(&d->phys_map, d->map.nodes, compacted); |
b35ba30f MT |
274 | } |
275 | } | |
276 | ||
97115a8d | 277 | static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr addr, |
9affd6fc | 278 | Node *nodes, MemoryRegionSection *sections) |
92e873b9 | 279 | { |
31ab2b4a | 280 | PhysPageEntry *p; |
97115a8d | 281 | hwaddr index = addr >> TARGET_PAGE_BITS; |
31ab2b4a | 282 | int i; |
f1f6e3b8 | 283 | |
9736e55b | 284 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
c19e8800 | 285 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
9affd6fc | 286 | return §ions[PHYS_SECTION_UNASSIGNED]; |
31ab2b4a | 287 | } |
9affd6fc | 288 | p = nodes[lp.ptr]; |
03f49957 | 289 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
5312bd8b | 290 | } |
b35ba30f MT |
291 | |
292 | if (sections[lp.ptr].size.hi || | |
293 | range_covers_byte(sections[lp.ptr].offset_within_address_space, | |
294 | sections[lp.ptr].size.lo, addr)) { | |
295 | return §ions[lp.ptr]; | |
296 | } else { | |
297 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
298 | } | |
f3705d53 AK |
299 | } |
300 | ||
e5548617 BS |
301 | bool memory_region_is_unassigned(MemoryRegion *mr) |
302 | { | |
2a8e7499 | 303 | return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device |
5b6dd868 | 304 | && mr != &io_mem_watch; |
fd6ce8f6 | 305 | } |
149f54b5 | 306 | |
c7086b4a | 307 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, |
90260c6c JK |
308 | hwaddr addr, |
309 | bool resolve_subpage) | |
9f029603 | 310 | { |
90260c6c JK |
311 | MemoryRegionSection *section; |
312 | subpage_t *subpage; | |
313 | ||
53cb28cb | 314 | section = phys_page_find(d->phys_map, addr, d->map.nodes, d->map.sections); |
90260c6c JK |
315 | if (resolve_subpage && section->mr->subpage) { |
316 | subpage = container_of(section->mr, subpage_t, iomem); | |
53cb28cb | 317 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
90260c6c JK |
318 | } |
319 | return section; | |
9f029603 JK |
320 | } |
321 | ||
90260c6c | 322 | static MemoryRegionSection * |
c7086b4a | 323 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
90260c6c | 324 | hwaddr *plen, bool resolve_subpage) |
149f54b5 PB |
325 | { |
326 | MemoryRegionSection *section; | |
327 | Int128 diff; | |
328 | ||
c7086b4a | 329 | section = address_space_lookup_region(d, addr, resolve_subpage); |
149f54b5 PB |
330 | /* Compute offset within MemoryRegionSection */ |
331 | addr -= section->offset_within_address_space; | |
332 | ||
333 | /* Compute offset within MemoryRegion */ | |
334 | *xlat = addr + section->offset_within_region; | |
335 | ||
336 | diff = int128_sub(section->mr->size, int128_make64(addr)); | |
3752a036 | 337 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
149f54b5 PB |
338 | return section; |
339 | } | |
90260c6c | 340 | |
5c8a00ce PB |
341 | MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr, |
342 | hwaddr *xlat, hwaddr *plen, | |
343 | bool is_write) | |
90260c6c | 344 | { |
30951157 AK |
345 | IOMMUTLBEntry iotlb; |
346 | MemoryRegionSection *section; | |
347 | MemoryRegion *mr; | |
348 | hwaddr len = *plen; | |
349 | ||
350 | for (;;) { | |
c7086b4a | 351 | section = address_space_translate_internal(as->dispatch, addr, &addr, plen, true); |
30951157 AK |
352 | mr = section->mr; |
353 | ||
354 | if (!mr->iommu_ops) { | |
355 | break; | |
356 | } | |
357 | ||
358 | iotlb = mr->iommu_ops->translate(mr, addr); | |
359 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
360 | | (addr & iotlb.addr_mask)); | |
361 | len = MIN(len, (addr | iotlb.addr_mask) - addr + 1); | |
362 | if (!(iotlb.perm & (1 << is_write))) { | |
363 | mr = &io_mem_unassigned; | |
364 | break; | |
365 | } | |
366 | ||
367 | as = iotlb.target_as; | |
368 | } | |
369 | ||
370 | *plen = len; | |
371 | *xlat = addr; | |
372 | return mr; | |
90260c6c JK |
373 | } |
374 | ||
375 | MemoryRegionSection * | |
376 | address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat, | |
377 | hwaddr *plen) | |
378 | { | |
30951157 | 379 | MemoryRegionSection *section; |
c7086b4a | 380 | section = address_space_translate_internal(as->dispatch, addr, xlat, plen, false); |
30951157 AK |
381 | |
382 | assert(!section->mr->iommu_ops); | |
383 | return section; | |
90260c6c | 384 | } |
5b6dd868 | 385 | #endif |
fd6ce8f6 | 386 | |
5b6dd868 | 387 | void cpu_exec_init_all(void) |
fdbb84d1 | 388 | { |
5b6dd868 | 389 | #if !defined(CONFIG_USER_ONLY) |
b2a8658e | 390 | qemu_mutex_init(&ram_list.mutex); |
5b6dd868 BS |
391 | memory_map_init(); |
392 | io_mem_init(); | |
fdbb84d1 | 393 | #endif |
5b6dd868 | 394 | } |
fdbb84d1 | 395 | |
b170fce3 | 396 | #if !defined(CONFIG_USER_ONLY) |
5b6dd868 BS |
397 | |
398 | static int cpu_common_post_load(void *opaque, int version_id) | |
fd6ce8f6 | 399 | { |
259186a7 | 400 | CPUState *cpu = opaque; |
a513fe19 | 401 | |
5b6dd868 BS |
402 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
403 | version_id is increased. */ | |
259186a7 AF |
404 | cpu->interrupt_request &= ~0x01; |
405 | tlb_flush(cpu->env_ptr, 1); | |
5b6dd868 BS |
406 | |
407 | return 0; | |
a513fe19 | 408 | } |
7501267e | 409 | |
1a1562f5 | 410 | const VMStateDescription vmstate_cpu_common = { |
5b6dd868 BS |
411 | .name = "cpu_common", |
412 | .version_id = 1, | |
413 | .minimum_version_id = 1, | |
414 | .minimum_version_id_old = 1, | |
415 | .post_load = cpu_common_post_load, | |
416 | .fields = (VMStateField []) { | |
259186a7 AF |
417 | VMSTATE_UINT32(halted, CPUState), |
418 | VMSTATE_UINT32(interrupt_request, CPUState), | |
5b6dd868 BS |
419 | VMSTATE_END_OF_LIST() |
420 | } | |
421 | }; | |
1a1562f5 | 422 | |
5b6dd868 | 423 | #endif |
ea041c0e | 424 | |
38d8f5c8 | 425 | CPUState *qemu_get_cpu(int index) |
ea041c0e | 426 | { |
bdc44640 | 427 | CPUState *cpu; |
ea041c0e | 428 | |
bdc44640 | 429 | CPU_FOREACH(cpu) { |
55e5c285 | 430 | if (cpu->cpu_index == index) { |
bdc44640 | 431 | return cpu; |
55e5c285 | 432 | } |
ea041c0e | 433 | } |
5b6dd868 | 434 | |
bdc44640 | 435 | return NULL; |
ea041c0e FB |
436 | } |
437 | ||
5b6dd868 | 438 | void cpu_exec_init(CPUArchState *env) |
ea041c0e | 439 | { |
5b6dd868 | 440 | CPUState *cpu = ENV_GET_CPU(env); |
b170fce3 | 441 | CPUClass *cc = CPU_GET_CLASS(cpu); |
bdc44640 | 442 | CPUState *some_cpu; |
5b6dd868 BS |
443 | int cpu_index; |
444 | ||
445 | #if defined(CONFIG_USER_ONLY) | |
446 | cpu_list_lock(); | |
447 | #endif | |
5b6dd868 | 448 | cpu_index = 0; |
bdc44640 | 449 | CPU_FOREACH(some_cpu) { |
5b6dd868 BS |
450 | cpu_index++; |
451 | } | |
55e5c285 | 452 | cpu->cpu_index = cpu_index; |
1b1ed8dc | 453 | cpu->numa_node = 0; |
5b6dd868 BS |
454 | QTAILQ_INIT(&env->breakpoints); |
455 | QTAILQ_INIT(&env->watchpoints); | |
456 | #ifndef CONFIG_USER_ONLY | |
457 | cpu->thread_id = qemu_get_thread_id(); | |
458 | #endif | |
bdc44640 | 459 | QTAILQ_INSERT_TAIL(&cpus, cpu, node); |
5b6dd868 BS |
460 | #if defined(CONFIG_USER_ONLY) |
461 | cpu_list_unlock(); | |
462 | #endif | |
e0d47944 AF |
463 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { |
464 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, cpu); | |
465 | } | |
5b6dd868 | 466 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
5b6dd868 BS |
467 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, |
468 | cpu_save, cpu_load, env); | |
b170fce3 | 469 | assert(cc->vmsd == NULL); |
e0d47944 | 470 | assert(qdev_get_vmsd(DEVICE(cpu)) == NULL); |
5b6dd868 | 471 | #endif |
b170fce3 AF |
472 | if (cc->vmsd != NULL) { |
473 | vmstate_register(NULL, cpu_index, cc->vmsd, cpu); | |
474 | } | |
ea041c0e FB |
475 | } |
476 | ||
1fddef4b | 477 | #if defined(TARGET_HAS_ICE) |
94df27fd | 478 | #if defined(CONFIG_USER_ONLY) |
00b941e5 | 479 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
94df27fd PB |
480 | { |
481 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
482 | } | |
483 | #else | |
00b941e5 | 484 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
1e7855a5 | 485 | { |
e8262a1b MF |
486 | hwaddr phys = cpu_get_phys_page_debug(cpu, pc); |
487 | if (phys != -1) { | |
488 | tb_invalidate_phys_addr(phys | (pc & ~TARGET_PAGE_MASK)); | |
489 | } | |
1e7855a5 | 490 | } |
c27004ec | 491 | #endif |
94df27fd | 492 | #endif /* TARGET_HAS_ICE */ |
d720b93d | 493 | |
c527ee8f | 494 | #if defined(CONFIG_USER_ONLY) |
9349b4f9 | 495 | void cpu_watchpoint_remove_all(CPUArchState *env, int mask) |
c527ee8f PB |
496 | |
497 | { | |
498 | } | |
499 | ||
9349b4f9 | 500 | int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, |
c527ee8f PB |
501 | int flags, CPUWatchpoint **watchpoint) |
502 | { | |
503 | return -ENOSYS; | |
504 | } | |
505 | #else | |
6658ffb8 | 506 | /* Add a watchpoint. */ |
9349b4f9 | 507 | int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, |
a1d1bb31 | 508 | int flags, CPUWatchpoint **watchpoint) |
6658ffb8 | 509 | { |
b4051334 | 510 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 511 | CPUWatchpoint *wp; |
6658ffb8 | 512 | |
b4051334 | 513 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
0dc23828 MF |
514 | if ((len & (len - 1)) || (addr & ~len_mask) || |
515 | len == 0 || len > TARGET_PAGE_SIZE) { | |
b4051334 AL |
516 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " |
517 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
518 | return -EINVAL; | |
519 | } | |
7267c094 | 520 | wp = g_malloc(sizeof(*wp)); |
a1d1bb31 AL |
521 | |
522 | wp->vaddr = addr; | |
b4051334 | 523 | wp->len_mask = len_mask; |
a1d1bb31 AL |
524 | wp->flags = flags; |
525 | ||
2dc9f411 | 526 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 527 | if (flags & BP_GDB) |
72cf2d4f | 528 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 529 | else |
72cf2d4f | 530 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 531 | |
6658ffb8 | 532 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
533 | |
534 | if (watchpoint) | |
535 | *watchpoint = wp; | |
536 | return 0; | |
6658ffb8 PB |
537 | } |
538 | ||
a1d1bb31 | 539 | /* Remove a specific watchpoint. */ |
9349b4f9 | 540 | int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len, |
a1d1bb31 | 541 | int flags) |
6658ffb8 | 542 | { |
b4051334 | 543 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 544 | CPUWatchpoint *wp; |
6658ffb8 | 545 | |
72cf2d4f | 546 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 547 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 548 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 549 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
550 | return 0; |
551 | } | |
552 | } | |
a1d1bb31 | 553 | return -ENOENT; |
6658ffb8 PB |
554 | } |
555 | ||
a1d1bb31 | 556 | /* Remove a specific watchpoint by reference. */ |
9349b4f9 | 557 | void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) |
a1d1bb31 | 558 | { |
72cf2d4f | 559 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 560 | |
a1d1bb31 AL |
561 | tlb_flush_page(env, watchpoint->vaddr); |
562 | ||
7267c094 | 563 | g_free(watchpoint); |
a1d1bb31 AL |
564 | } |
565 | ||
566 | /* Remove all matching watchpoints. */ | |
9349b4f9 | 567 | void cpu_watchpoint_remove_all(CPUArchState *env, int mask) |
a1d1bb31 | 568 | { |
c0ce998e | 569 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 570 | |
72cf2d4f | 571 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
572 | if (wp->flags & mask) |
573 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 574 | } |
7d03f82f | 575 | } |
c527ee8f | 576 | #endif |
7d03f82f | 577 | |
a1d1bb31 | 578 | /* Add a breakpoint. */ |
9349b4f9 | 579 | int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, |
a1d1bb31 | 580 | CPUBreakpoint **breakpoint) |
4c3a88a2 | 581 | { |
1fddef4b | 582 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 583 | CPUBreakpoint *bp; |
3b46e624 | 584 | |
7267c094 | 585 | bp = g_malloc(sizeof(*bp)); |
4c3a88a2 | 586 | |
a1d1bb31 AL |
587 | bp->pc = pc; |
588 | bp->flags = flags; | |
589 | ||
2dc9f411 | 590 | /* keep all GDB-injected breakpoints in front */ |
00b941e5 | 591 | if (flags & BP_GDB) { |
72cf2d4f | 592 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
00b941e5 | 593 | } else { |
72cf2d4f | 594 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
00b941e5 | 595 | } |
3b46e624 | 596 | |
00b941e5 | 597 | breakpoint_invalidate(ENV_GET_CPU(env), pc); |
a1d1bb31 | 598 | |
00b941e5 | 599 | if (breakpoint) { |
a1d1bb31 | 600 | *breakpoint = bp; |
00b941e5 | 601 | } |
4c3a88a2 FB |
602 | return 0; |
603 | #else | |
a1d1bb31 | 604 | return -ENOSYS; |
4c3a88a2 FB |
605 | #endif |
606 | } | |
607 | ||
a1d1bb31 | 608 | /* Remove a specific breakpoint. */ |
9349b4f9 | 609 | int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) |
a1d1bb31 | 610 | { |
7d03f82f | 611 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
612 | CPUBreakpoint *bp; |
613 | ||
72cf2d4f | 614 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
615 | if (bp->pc == pc && bp->flags == flags) { |
616 | cpu_breakpoint_remove_by_ref(env, bp); | |
617 | return 0; | |
618 | } | |
7d03f82f | 619 | } |
a1d1bb31 AL |
620 | return -ENOENT; |
621 | #else | |
622 | return -ENOSYS; | |
7d03f82f EI |
623 | #endif |
624 | } | |
625 | ||
a1d1bb31 | 626 | /* Remove a specific breakpoint by reference. */ |
9349b4f9 | 627 | void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) |
4c3a88a2 | 628 | { |
1fddef4b | 629 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 630 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 631 | |
00b941e5 | 632 | breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc); |
a1d1bb31 | 633 | |
7267c094 | 634 | g_free(breakpoint); |
a1d1bb31 AL |
635 | #endif |
636 | } | |
637 | ||
638 | /* Remove all matching breakpoints. */ | |
9349b4f9 | 639 | void cpu_breakpoint_remove_all(CPUArchState *env, int mask) |
a1d1bb31 AL |
640 | { |
641 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 642 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 643 | |
72cf2d4f | 644 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
645 | if (bp->flags & mask) |
646 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 647 | } |
4c3a88a2 FB |
648 | #endif |
649 | } | |
650 | ||
c33a346e FB |
651 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
652 | CPU loop after each instruction */ | |
3825b28f | 653 | void cpu_single_step(CPUState *cpu, int enabled) |
c33a346e | 654 | { |
1fddef4b | 655 | #if defined(TARGET_HAS_ICE) |
ed2803da AF |
656 | if (cpu->singlestep_enabled != enabled) { |
657 | cpu->singlestep_enabled = enabled; | |
658 | if (kvm_enabled()) { | |
38e478ec | 659 | kvm_update_guest_debug(cpu, 0); |
ed2803da | 660 | } else { |
ccbb4d44 | 661 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 | 662 | /* XXX: only flush what is necessary */ |
38e478ec | 663 | CPUArchState *env = cpu->env_ptr; |
e22a25c9 AL |
664 | tb_flush(env); |
665 | } | |
c33a346e FB |
666 | } |
667 | #endif | |
668 | } | |
669 | ||
9349b4f9 | 670 | void cpu_abort(CPUArchState *env, const char *fmt, ...) |
7501267e | 671 | { |
878096ee | 672 | CPUState *cpu = ENV_GET_CPU(env); |
7501267e | 673 | va_list ap; |
493ae1f0 | 674 | va_list ap2; |
7501267e FB |
675 | |
676 | va_start(ap, fmt); | |
493ae1f0 | 677 | va_copy(ap2, ap); |
7501267e FB |
678 | fprintf(stderr, "qemu: fatal: "); |
679 | vfprintf(stderr, fmt, ap); | |
680 | fprintf(stderr, "\n"); | |
878096ee | 681 | cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
93fcfe39 AL |
682 | if (qemu_log_enabled()) { |
683 | qemu_log("qemu: fatal: "); | |
684 | qemu_log_vprintf(fmt, ap2); | |
685 | qemu_log("\n"); | |
a0762859 | 686 | log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
31b1a7b4 | 687 | qemu_log_flush(); |
93fcfe39 | 688 | qemu_log_close(); |
924edcae | 689 | } |
493ae1f0 | 690 | va_end(ap2); |
f9373291 | 691 | va_end(ap); |
fd052bf6 RV |
692 | #if defined(CONFIG_USER_ONLY) |
693 | { | |
694 | struct sigaction act; | |
695 | sigfillset(&act.sa_mask); | |
696 | act.sa_handler = SIG_DFL; | |
697 | sigaction(SIGABRT, &act, NULL); | |
698 | } | |
699 | #endif | |
7501267e FB |
700 | abort(); |
701 | } | |
702 | ||
0124311e | 703 | #if !defined(CONFIG_USER_ONLY) |
041603fe PB |
704 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
705 | { | |
706 | RAMBlock *block; | |
707 | ||
708 | /* The list is protected by the iothread lock here. */ | |
709 | block = ram_list.mru_block; | |
710 | if (block && addr - block->offset < block->length) { | |
711 | goto found; | |
712 | } | |
713 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { | |
714 | if (addr - block->offset < block->length) { | |
715 | goto found; | |
716 | } | |
717 | } | |
718 | ||
719 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
720 | abort(); | |
721 | ||
722 | found: | |
723 | ram_list.mru_block = block; | |
724 | return block; | |
725 | } | |
726 | ||
d24981d3 JQ |
727 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t end, |
728 | uintptr_t length) | |
729 | { | |
041603fe PB |
730 | RAMBlock *block; |
731 | ram_addr_t start1; | |
d24981d3 | 732 | |
041603fe PB |
733 | block = qemu_get_ram_block(start); |
734 | assert(block == qemu_get_ram_block(end - 1)); | |
735 | start1 = (uintptr_t)block->host + (start - block->offset); | |
736 | cpu_tlb_reset_dirty_all(start1, length); | |
d24981d3 JQ |
737 | } |
738 | ||
5579c7f3 | 739 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 740 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
52159192 | 741 | unsigned client) |
1ccde1cb | 742 | { |
d24981d3 | 743 | uintptr_t length; |
1ccde1cb FB |
744 | |
745 | start &= TARGET_PAGE_MASK; | |
746 | end = TARGET_PAGE_ALIGN(end); | |
747 | ||
748 | length = end - start; | |
749 | if (length == 0) | |
750 | return; | |
52159192 | 751 | cpu_physical_memory_mask_dirty_range(start, length, client); |
f23db169 | 752 | |
d24981d3 JQ |
753 | if (tcg_enabled()) { |
754 | tlb_reset_dirty_range_all(start, end, length); | |
5579c7f3 | 755 | } |
1ccde1cb FB |
756 | } |
757 | ||
8b9c99d9 | 758 | static int cpu_physical_memory_set_dirty_tracking(int enable) |
74576198 | 759 | { |
f6f3fbca | 760 | int ret = 0; |
74576198 | 761 | in_migration = enable; |
f6f3fbca | 762 | return ret; |
74576198 AL |
763 | } |
764 | ||
a8170e5e | 765 | hwaddr memory_region_section_get_iotlb(CPUArchState *env, |
149f54b5 PB |
766 | MemoryRegionSection *section, |
767 | target_ulong vaddr, | |
768 | hwaddr paddr, hwaddr xlat, | |
769 | int prot, | |
770 | target_ulong *address) | |
e5548617 | 771 | { |
a8170e5e | 772 | hwaddr iotlb; |
e5548617 BS |
773 | CPUWatchpoint *wp; |
774 | ||
cc5bea60 | 775 | if (memory_region_is_ram(section->mr)) { |
e5548617 BS |
776 | /* Normal RAM. */ |
777 | iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK) | |
149f54b5 | 778 | + xlat; |
e5548617 | 779 | if (!section->readonly) { |
b41aac4f | 780 | iotlb |= PHYS_SECTION_NOTDIRTY; |
e5548617 | 781 | } else { |
b41aac4f | 782 | iotlb |= PHYS_SECTION_ROM; |
e5548617 BS |
783 | } |
784 | } else { | |
53cb28cb | 785 | iotlb = section - address_space_memory.dispatch->map.sections; |
149f54b5 | 786 | iotlb += xlat; |
e5548617 BS |
787 | } |
788 | ||
789 | /* Make accesses to pages with watchpoints go via the | |
790 | watchpoint trap routines. */ | |
791 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { | |
792 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { | |
793 | /* Avoid trapping reads of pages with a write breakpoint. */ | |
794 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
b41aac4f | 795 | iotlb = PHYS_SECTION_WATCH + paddr; |
e5548617 BS |
796 | *address |= TLB_MMIO; |
797 | break; | |
798 | } | |
799 | } | |
800 | } | |
801 | ||
802 | return iotlb; | |
803 | } | |
9fa3e853 FB |
804 | #endif /* defined(CONFIG_USER_ONLY) */ |
805 | ||
e2eef170 | 806 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 807 | |
c227f099 | 808 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 809 | uint16_t section); |
acc9d80b | 810 | static subpage_t *subpage_init(AddressSpace *as, hwaddr base); |
54688b1e | 811 | |
575ddeb4 | 812 | static void *(*phys_mem_alloc)(size_t size) = qemu_anon_ram_alloc; |
91138037 MA |
813 | |
814 | /* | |
815 | * Set a custom physical guest memory alloator. | |
816 | * Accelerators with unusual needs may need this. Hopefully, we can | |
817 | * get rid of it eventually. | |
818 | */ | |
575ddeb4 | 819 | void phys_mem_set_alloc(void *(*alloc)(size_t)) |
91138037 MA |
820 | { |
821 | phys_mem_alloc = alloc; | |
822 | } | |
823 | ||
53cb28cb MA |
824 | static uint16_t phys_section_add(PhysPageMap *map, |
825 | MemoryRegionSection *section) | |
5312bd8b | 826 | { |
68f3f65b PB |
827 | /* The physical section number is ORed with a page-aligned |
828 | * pointer to produce the iotlb entries. Thus it should | |
829 | * never overflow into the page-aligned value. | |
830 | */ | |
53cb28cb | 831 | assert(map->sections_nb < TARGET_PAGE_SIZE); |
68f3f65b | 832 | |
53cb28cb MA |
833 | if (map->sections_nb == map->sections_nb_alloc) { |
834 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
835 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
836 | map->sections_nb_alloc); | |
5312bd8b | 837 | } |
53cb28cb | 838 | map->sections[map->sections_nb] = *section; |
dfde4e6e | 839 | memory_region_ref(section->mr); |
53cb28cb | 840 | return map->sections_nb++; |
5312bd8b AK |
841 | } |
842 | ||
058bc4b5 PB |
843 | static void phys_section_destroy(MemoryRegion *mr) |
844 | { | |
dfde4e6e PB |
845 | memory_region_unref(mr); |
846 | ||
058bc4b5 PB |
847 | if (mr->subpage) { |
848 | subpage_t *subpage = container_of(mr, subpage_t, iomem); | |
849 | memory_region_destroy(&subpage->iomem); | |
850 | g_free(subpage); | |
851 | } | |
852 | } | |
853 | ||
6092666e | 854 | static void phys_sections_free(PhysPageMap *map) |
5312bd8b | 855 | { |
9affd6fc PB |
856 | while (map->sections_nb > 0) { |
857 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
058bc4b5 PB |
858 | phys_section_destroy(section->mr); |
859 | } | |
9affd6fc PB |
860 | g_free(map->sections); |
861 | g_free(map->nodes); | |
5312bd8b AK |
862 | } |
863 | ||
ac1970fb | 864 | static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section) |
0f0cb164 AK |
865 | { |
866 | subpage_t *subpage; | |
a8170e5e | 867 | hwaddr base = section->offset_within_address_space |
0f0cb164 | 868 | & TARGET_PAGE_MASK; |
97115a8d | 869 | MemoryRegionSection *existing = phys_page_find(d->phys_map, base, |
53cb28cb | 870 | d->map.nodes, d->map.sections); |
0f0cb164 AK |
871 | MemoryRegionSection subsection = { |
872 | .offset_within_address_space = base, | |
052e87b0 | 873 | .size = int128_make64(TARGET_PAGE_SIZE), |
0f0cb164 | 874 | }; |
a8170e5e | 875 | hwaddr start, end; |
0f0cb164 | 876 | |
f3705d53 | 877 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
0f0cb164 | 878 | |
f3705d53 | 879 | if (!(existing->mr->subpage)) { |
acc9d80b | 880 | subpage = subpage_init(d->as, base); |
0f0cb164 | 881 | subsection.mr = &subpage->iomem; |
ac1970fb | 882 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
53cb28cb | 883 | phys_section_add(&d->map, &subsection)); |
0f0cb164 | 884 | } else { |
f3705d53 | 885 | subpage = container_of(existing->mr, subpage_t, iomem); |
0f0cb164 AK |
886 | } |
887 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
052e87b0 | 888 | end = start + int128_get64(section->size) - 1; |
53cb28cb MA |
889 | subpage_register(subpage, start, end, |
890 | phys_section_add(&d->map, section)); | |
0f0cb164 AK |
891 | } |
892 | ||
893 | ||
052e87b0 PB |
894 | static void register_multipage(AddressSpaceDispatch *d, |
895 | MemoryRegionSection *section) | |
33417e70 | 896 | { |
a8170e5e | 897 | hwaddr start_addr = section->offset_within_address_space; |
53cb28cb | 898 | uint16_t section_index = phys_section_add(&d->map, section); |
052e87b0 PB |
899 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
900 | TARGET_PAGE_BITS)); | |
dd81124b | 901 | |
733d5ef5 PB |
902 | assert(num_pages); |
903 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
33417e70 FB |
904 | } |
905 | ||
ac1970fb | 906 | static void mem_add(MemoryListener *listener, MemoryRegionSection *section) |
0f0cb164 | 907 | { |
89ae337a | 908 | AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
00752703 | 909 | AddressSpaceDispatch *d = as->next_dispatch; |
99b9cc06 | 910 | MemoryRegionSection now = *section, remain = *section; |
052e87b0 | 911 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
0f0cb164 | 912 | |
733d5ef5 PB |
913 | if (now.offset_within_address_space & ~TARGET_PAGE_MASK) { |
914 | uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) | |
915 | - now.offset_within_address_space; | |
916 | ||
052e87b0 | 917 | now.size = int128_min(int128_make64(left), now.size); |
ac1970fb | 918 | register_subpage(d, &now); |
733d5ef5 | 919 | } else { |
052e87b0 | 920 | now.size = int128_zero(); |
733d5ef5 | 921 | } |
052e87b0 PB |
922 | while (int128_ne(remain.size, now.size)) { |
923 | remain.size = int128_sub(remain.size, now.size); | |
924 | remain.offset_within_address_space += int128_get64(now.size); | |
925 | remain.offset_within_region += int128_get64(now.size); | |
69b67646 | 926 | now = remain; |
052e87b0 | 927 | if (int128_lt(remain.size, page_size)) { |
733d5ef5 | 928 | register_subpage(d, &now); |
88266249 | 929 | } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { |
052e87b0 | 930 | now.size = page_size; |
ac1970fb | 931 | register_subpage(d, &now); |
69b67646 | 932 | } else { |
052e87b0 | 933 | now.size = int128_and(now.size, int128_neg(page_size)); |
ac1970fb | 934 | register_multipage(d, &now); |
69b67646 | 935 | } |
0f0cb164 AK |
936 | } |
937 | } | |
938 | ||
62a2744c SY |
939 | void qemu_flush_coalesced_mmio_buffer(void) |
940 | { | |
941 | if (kvm_enabled()) | |
942 | kvm_flush_coalesced_mmio_buffer(); | |
943 | } | |
944 | ||
b2a8658e UD |
945 | void qemu_mutex_lock_ramlist(void) |
946 | { | |
947 | qemu_mutex_lock(&ram_list.mutex); | |
948 | } | |
949 | ||
950 | void qemu_mutex_unlock_ramlist(void) | |
951 | { | |
952 | qemu_mutex_unlock(&ram_list.mutex); | |
953 | } | |
954 | ||
e1e84ba0 | 955 | #ifdef __linux__ |
c902760f MT |
956 | |
957 | #include <sys/vfs.h> | |
958 | ||
959 | #define HUGETLBFS_MAGIC 0x958458f6 | |
960 | ||
961 | static long gethugepagesize(const char *path) | |
962 | { | |
963 | struct statfs fs; | |
964 | int ret; | |
965 | ||
966 | do { | |
9742bf26 | 967 | ret = statfs(path, &fs); |
c902760f MT |
968 | } while (ret != 0 && errno == EINTR); |
969 | ||
970 | if (ret != 0) { | |
9742bf26 YT |
971 | perror(path); |
972 | return 0; | |
c902760f MT |
973 | } |
974 | ||
975 | if (fs.f_type != HUGETLBFS_MAGIC) | |
9742bf26 | 976 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
c902760f MT |
977 | |
978 | return fs.f_bsize; | |
979 | } | |
980 | ||
ef36fa14 MT |
981 | static sigjmp_buf sigjump; |
982 | ||
983 | static void sigbus_handler(int signal) | |
984 | { | |
985 | siglongjmp(sigjump, 1); | |
986 | } | |
987 | ||
04b16653 AW |
988 | static void *file_ram_alloc(RAMBlock *block, |
989 | ram_addr_t memory, | |
990 | const char *path) | |
c902760f MT |
991 | { |
992 | char *filename; | |
8ca761f6 PF |
993 | char *sanitized_name; |
994 | char *c; | |
c902760f MT |
995 | void *area; |
996 | int fd; | |
c902760f MT |
997 | unsigned long hpagesize; |
998 | ||
999 | hpagesize = gethugepagesize(path); | |
1000 | if (!hpagesize) { | |
9742bf26 | 1001 | return NULL; |
c902760f MT |
1002 | } |
1003 | ||
1004 | if (memory < hpagesize) { | |
1005 | return NULL; | |
1006 | } | |
1007 | ||
1008 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
1009 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); | |
1010 | return NULL; | |
1011 | } | |
1012 | ||
8ca761f6 PF |
1013 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ |
1014 | sanitized_name = g_strdup(block->mr->name); | |
1015 | for (c = sanitized_name; *c != '\0'; c++) { | |
1016 | if (*c == '/') | |
1017 | *c = '_'; | |
1018 | } | |
1019 | ||
1020 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, | |
1021 | sanitized_name); | |
1022 | g_free(sanitized_name); | |
c902760f MT |
1023 | |
1024 | fd = mkstemp(filename); | |
1025 | if (fd < 0) { | |
9742bf26 | 1026 | perror("unable to create backing store for hugepages"); |
e4ada482 | 1027 | g_free(filename); |
9742bf26 | 1028 | return NULL; |
c902760f MT |
1029 | } |
1030 | unlink(filename); | |
e4ada482 | 1031 | g_free(filename); |
c902760f MT |
1032 | |
1033 | memory = (memory+hpagesize-1) & ~(hpagesize-1); | |
1034 | ||
1035 | /* | |
1036 | * ftruncate is not supported by hugetlbfs in older | |
1037 | * hosts, so don't bother bailing out on errors. | |
1038 | * If anything goes wrong with it under other filesystems, | |
1039 | * mmap will fail. | |
1040 | */ | |
1041 | if (ftruncate(fd, memory)) | |
9742bf26 | 1042 | perror("ftruncate"); |
c902760f | 1043 | |
c902760f | 1044 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); |
c902760f | 1045 | if (area == MAP_FAILED) { |
9742bf26 YT |
1046 | perror("file_ram_alloc: can't mmap RAM pages"); |
1047 | close(fd); | |
1048 | return (NULL); | |
c902760f | 1049 | } |
ef36fa14 MT |
1050 | |
1051 | if (mem_prealloc) { | |
1052 | int ret, i; | |
1053 | struct sigaction act, oldact; | |
1054 | sigset_t set, oldset; | |
1055 | ||
1056 | memset(&act, 0, sizeof(act)); | |
1057 | act.sa_handler = &sigbus_handler; | |
1058 | act.sa_flags = 0; | |
1059 | ||
1060 | ret = sigaction(SIGBUS, &act, &oldact); | |
1061 | if (ret) { | |
1062 | perror("file_ram_alloc: failed to install signal handler"); | |
1063 | exit(1); | |
1064 | } | |
1065 | ||
1066 | /* unblock SIGBUS */ | |
1067 | sigemptyset(&set); | |
1068 | sigaddset(&set, SIGBUS); | |
1069 | pthread_sigmask(SIG_UNBLOCK, &set, &oldset); | |
1070 | ||
1071 | if (sigsetjmp(sigjump, 1)) { | |
1072 | fprintf(stderr, "file_ram_alloc: failed to preallocate pages\n"); | |
1073 | exit(1); | |
1074 | } | |
1075 | ||
1076 | /* MAP_POPULATE silently ignores failures */ | |
1077 | for (i = 0; i < (memory/hpagesize)-1; i++) { | |
1078 | memset(area + (hpagesize*i), 0, 1); | |
1079 | } | |
1080 | ||
1081 | ret = sigaction(SIGBUS, &oldact, NULL); | |
1082 | if (ret) { | |
1083 | perror("file_ram_alloc: failed to reinstall signal handler"); | |
1084 | exit(1); | |
1085 | } | |
1086 | ||
1087 | pthread_sigmask(SIG_SETMASK, &oldset, NULL); | |
1088 | } | |
1089 | ||
04b16653 | 1090 | block->fd = fd; |
c902760f MT |
1091 | return area; |
1092 | } | |
e1e84ba0 MA |
1093 | #else |
1094 | static void *file_ram_alloc(RAMBlock *block, | |
1095 | ram_addr_t memory, | |
1096 | const char *path) | |
1097 | { | |
1098 | fprintf(stderr, "-mem-path not supported on this host\n"); | |
1099 | exit(1); | |
1100 | } | |
c902760f MT |
1101 | #endif |
1102 | ||
d17b5288 | 1103 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
1104 | { |
1105 | RAMBlock *block, *next_block; | |
3e837b2c | 1106 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 | 1107 | |
49cd9ac6 SH |
1108 | assert(size != 0); /* it would hand out same offset multiple times */ |
1109 | ||
a3161038 | 1110 | if (QTAILQ_EMPTY(&ram_list.blocks)) |
04b16653 AW |
1111 | return 0; |
1112 | ||
a3161038 | 1113 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
f15fbc4b | 1114 | ram_addr_t end, next = RAM_ADDR_MAX; |
04b16653 AW |
1115 | |
1116 | end = block->offset + block->length; | |
1117 | ||
a3161038 | 1118 | QTAILQ_FOREACH(next_block, &ram_list.blocks, next) { |
04b16653 AW |
1119 | if (next_block->offset >= end) { |
1120 | next = MIN(next, next_block->offset); | |
1121 | } | |
1122 | } | |
1123 | if (next - end >= size && next - end < mingap) { | |
3e837b2c | 1124 | offset = end; |
04b16653 AW |
1125 | mingap = next - end; |
1126 | } | |
1127 | } | |
3e837b2c AW |
1128 | |
1129 | if (offset == RAM_ADDR_MAX) { | |
1130 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1131 | (uint64_t)size); | |
1132 | abort(); | |
1133 | } | |
1134 | ||
04b16653 AW |
1135 | return offset; |
1136 | } | |
1137 | ||
652d7ec2 | 1138 | ram_addr_t last_ram_offset(void) |
d17b5288 AW |
1139 | { |
1140 | RAMBlock *block; | |
1141 | ram_addr_t last = 0; | |
1142 | ||
a3161038 | 1143 | QTAILQ_FOREACH(block, &ram_list.blocks, next) |
d17b5288 AW |
1144 | last = MAX(last, block->offset + block->length); |
1145 | ||
1146 | return last; | |
1147 | } | |
1148 | ||
ddb97f1d JB |
1149 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
1150 | { | |
1151 | int ret; | |
ddb97f1d JB |
1152 | |
1153 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
2ff3de68 MA |
1154 | if (!qemu_opt_get_bool(qemu_get_machine_opts(), |
1155 | "dump-guest-core", true)) { | |
ddb97f1d JB |
1156 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
1157 | if (ret) { | |
1158 | perror("qemu_madvise"); | |
1159 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1160 | "but dump_guest_core=off specified\n"); | |
1161 | } | |
1162 | } | |
1163 | } | |
1164 | ||
c5705a77 | 1165 | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev) |
84b89d78 CM |
1166 | { |
1167 | RAMBlock *new_block, *block; | |
1168 | ||
c5705a77 | 1169 | new_block = NULL; |
a3161038 | 1170 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
c5705a77 AK |
1171 | if (block->offset == addr) { |
1172 | new_block = block; | |
1173 | break; | |
1174 | } | |
1175 | } | |
1176 | assert(new_block); | |
1177 | assert(!new_block->idstr[0]); | |
84b89d78 | 1178 | |
09e5ab63 AL |
1179 | if (dev) { |
1180 | char *id = qdev_get_dev_path(dev); | |
84b89d78 CM |
1181 | if (id) { |
1182 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 1183 | g_free(id); |
84b89d78 CM |
1184 | } |
1185 | } | |
1186 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
1187 | ||
b2a8658e UD |
1188 | /* This assumes the iothread lock is taken here too. */ |
1189 | qemu_mutex_lock_ramlist(); | |
a3161038 | 1190 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
c5705a77 | 1191 | if (block != new_block && !strcmp(block->idstr, new_block->idstr)) { |
84b89d78 CM |
1192 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
1193 | new_block->idstr); | |
1194 | abort(); | |
1195 | } | |
1196 | } | |
b2a8658e | 1197 | qemu_mutex_unlock_ramlist(); |
c5705a77 AK |
1198 | } |
1199 | ||
8490fc78 LC |
1200 | static int memory_try_enable_merging(void *addr, size_t len) |
1201 | { | |
2ff3de68 | 1202 | if (!qemu_opt_get_bool(qemu_get_machine_opts(), "mem-merge", true)) { |
8490fc78 LC |
1203 | /* disabled by the user */ |
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
1208 | } | |
1209 | ||
c5705a77 AK |
1210 | ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
1211 | MemoryRegion *mr) | |
1212 | { | |
abb26d63 | 1213 | RAMBlock *block, *new_block; |
c5705a77 AK |
1214 | |
1215 | size = TARGET_PAGE_ALIGN(size); | |
1216 | new_block = g_malloc0(sizeof(*new_block)); | |
3435f395 | 1217 | new_block->fd = -1; |
84b89d78 | 1218 | |
b2a8658e UD |
1219 | /* This assumes the iothread lock is taken here too. */ |
1220 | qemu_mutex_lock_ramlist(); | |
7c637366 | 1221 | new_block->mr = mr; |
432d268c | 1222 | new_block->offset = find_ram_offset(size); |
6977dfe6 YT |
1223 | if (host) { |
1224 | new_block->host = host; | |
cd19cfa2 | 1225 | new_block->flags |= RAM_PREALLOC_MASK; |
dfeaf2ab MA |
1226 | } else if (xen_enabled()) { |
1227 | if (mem_path) { | |
1228 | fprintf(stderr, "-mem-path not supported with Xen\n"); | |
1229 | exit(1); | |
1230 | } | |
1231 | xen_ram_alloc(new_block->offset, size, mr); | |
6977dfe6 YT |
1232 | } else { |
1233 | if (mem_path) { | |
e1e84ba0 MA |
1234 | if (phys_mem_alloc != qemu_anon_ram_alloc) { |
1235 | /* | |
1236 | * file_ram_alloc() needs to allocate just like | |
1237 | * phys_mem_alloc, but we haven't bothered to provide | |
1238 | * a hook there. | |
1239 | */ | |
1240 | fprintf(stderr, | |
1241 | "-mem-path not supported with this accelerator\n"); | |
1242 | exit(1); | |
1243 | } | |
6977dfe6 | 1244 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
0628c182 MA |
1245 | } |
1246 | if (!new_block->host) { | |
91138037 | 1247 | new_block->host = phys_mem_alloc(size); |
39228250 MA |
1248 | if (!new_block->host) { |
1249 | fprintf(stderr, "Cannot set up guest memory '%s': %s\n", | |
1250 | new_block->mr->name, strerror(errno)); | |
1251 | exit(1); | |
1252 | } | |
8490fc78 | 1253 | memory_try_enable_merging(new_block->host, size); |
6977dfe6 | 1254 | } |
c902760f | 1255 | } |
94a6b54f PB |
1256 | new_block->length = size; |
1257 | ||
abb26d63 PB |
1258 | /* Keep the list sorted from biggest to smallest block. */ |
1259 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { | |
1260 | if (block->length < new_block->length) { | |
1261 | break; | |
1262 | } | |
1263 | } | |
1264 | if (block) { | |
1265 | QTAILQ_INSERT_BEFORE(block, new_block, next); | |
1266 | } else { | |
1267 | QTAILQ_INSERT_TAIL(&ram_list.blocks, new_block, next); | |
1268 | } | |
0d6d3c87 | 1269 | ram_list.mru_block = NULL; |
94a6b54f | 1270 | |
f798b07f | 1271 | ram_list.version++; |
b2a8658e | 1272 | qemu_mutex_unlock_ramlist(); |
f798b07f | 1273 | |
7267c094 | 1274 | ram_list.phys_dirty = g_realloc(ram_list.phys_dirty, |
04b16653 | 1275 | last_ram_offset() >> TARGET_PAGE_BITS); |
5fda043f IM |
1276 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
1277 | 0, size >> TARGET_PAGE_BITS); | |
75218e7f | 1278 | cpu_physical_memory_set_dirty_range(new_block->offset, size); |
94a6b54f | 1279 | |
ddb97f1d | 1280 | qemu_ram_setup_dump(new_block->host, size); |
ad0b5321 | 1281 | qemu_madvise(new_block->host, size, QEMU_MADV_HUGEPAGE); |
3e469dbf | 1282 | qemu_madvise(new_block->host, size, QEMU_MADV_DONTFORK); |
ddb97f1d | 1283 | |
6f0437e8 JK |
1284 | if (kvm_enabled()) |
1285 | kvm_setup_guest_memory(new_block->host, size); | |
1286 | ||
94a6b54f PB |
1287 | return new_block->offset; |
1288 | } | |
e9a1ab19 | 1289 | |
c5705a77 | 1290 | ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr) |
6977dfe6 | 1291 | { |
c5705a77 | 1292 | return qemu_ram_alloc_from_ptr(size, NULL, mr); |
6977dfe6 YT |
1293 | } |
1294 | ||
1f2e98b6 AW |
1295 | void qemu_ram_free_from_ptr(ram_addr_t addr) |
1296 | { | |
1297 | RAMBlock *block; | |
1298 | ||
b2a8658e UD |
1299 | /* This assumes the iothread lock is taken here too. */ |
1300 | qemu_mutex_lock_ramlist(); | |
a3161038 | 1301 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
1f2e98b6 | 1302 | if (addr == block->offset) { |
a3161038 | 1303 | QTAILQ_REMOVE(&ram_list.blocks, block, next); |
0d6d3c87 | 1304 | ram_list.mru_block = NULL; |
f798b07f | 1305 | ram_list.version++; |
7267c094 | 1306 | g_free(block); |
b2a8658e | 1307 | break; |
1f2e98b6 AW |
1308 | } |
1309 | } | |
b2a8658e | 1310 | qemu_mutex_unlock_ramlist(); |
1f2e98b6 AW |
1311 | } |
1312 | ||
c227f099 | 1313 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 1314 | { |
04b16653 AW |
1315 | RAMBlock *block; |
1316 | ||
b2a8658e UD |
1317 | /* This assumes the iothread lock is taken here too. */ |
1318 | qemu_mutex_lock_ramlist(); | |
a3161038 | 1319 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
04b16653 | 1320 | if (addr == block->offset) { |
a3161038 | 1321 | QTAILQ_REMOVE(&ram_list.blocks, block, next); |
0d6d3c87 | 1322 | ram_list.mru_block = NULL; |
f798b07f | 1323 | ram_list.version++; |
cd19cfa2 HY |
1324 | if (block->flags & RAM_PREALLOC_MASK) { |
1325 | ; | |
dfeaf2ab MA |
1326 | } else if (xen_enabled()) { |
1327 | xen_invalidate_map_cache_entry(block->host); | |
089f3f76 | 1328 | #ifndef _WIN32 |
3435f395 MA |
1329 | } else if (block->fd >= 0) { |
1330 | munmap(block->host, block->length); | |
1331 | close(block->fd); | |
089f3f76 | 1332 | #endif |
04b16653 | 1333 | } else { |
dfeaf2ab | 1334 | qemu_anon_ram_free(block->host, block->length); |
04b16653 | 1335 | } |
7267c094 | 1336 | g_free(block); |
b2a8658e | 1337 | break; |
04b16653 AW |
1338 | } |
1339 | } | |
b2a8658e | 1340 | qemu_mutex_unlock_ramlist(); |
04b16653 | 1341 | |
e9a1ab19 FB |
1342 | } |
1343 | ||
cd19cfa2 HY |
1344 | #ifndef _WIN32 |
1345 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
1346 | { | |
1347 | RAMBlock *block; | |
1348 | ram_addr_t offset; | |
1349 | int flags; | |
1350 | void *area, *vaddr; | |
1351 | ||
a3161038 | 1352 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
cd19cfa2 HY |
1353 | offset = addr - block->offset; |
1354 | if (offset < block->length) { | |
1355 | vaddr = block->host + offset; | |
1356 | if (block->flags & RAM_PREALLOC_MASK) { | |
1357 | ; | |
dfeaf2ab MA |
1358 | } else if (xen_enabled()) { |
1359 | abort(); | |
cd19cfa2 HY |
1360 | } else { |
1361 | flags = MAP_FIXED; | |
1362 | munmap(vaddr, length); | |
3435f395 | 1363 | if (block->fd >= 0) { |
cd19cfa2 | 1364 | #ifdef MAP_POPULATE |
3435f395 MA |
1365 | flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : |
1366 | MAP_PRIVATE; | |
fd28aa13 | 1367 | #else |
3435f395 | 1368 | flags |= MAP_PRIVATE; |
cd19cfa2 | 1369 | #endif |
3435f395 MA |
1370 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
1371 | flags, block->fd, offset); | |
cd19cfa2 | 1372 | } else { |
2eb9fbaa MA |
1373 | /* |
1374 | * Remap needs to match alloc. Accelerators that | |
1375 | * set phys_mem_alloc never remap. If they did, | |
1376 | * we'd need a remap hook here. | |
1377 | */ | |
1378 | assert(phys_mem_alloc == qemu_anon_ram_alloc); | |
1379 | ||
cd19cfa2 HY |
1380 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
1381 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
1382 | flags, -1, 0); | |
cd19cfa2 HY |
1383 | } |
1384 | if (area != vaddr) { | |
f15fbc4b AP |
1385 | fprintf(stderr, "Could not remap addr: " |
1386 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", | |
cd19cfa2 HY |
1387 | length, addr); |
1388 | exit(1); | |
1389 | } | |
8490fc78 | 1390 | memory_try_enable_merging(vaddr, length); |
ddb97f1d | 1391 | qemu_ram_setup_dump(vaddr, length); |
cd19cfa2 HY |
1392 | } |
1393 | return; | |
1394 | } | |
1395 | } | |
1396 | } | |
1397 | #endif /* !_WIN32 */ | |
1398 | ||
1b5ec234 PB |
1399 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
1400 | With the exception of the softmmu code in this file, this should | |
1401 | only be used for local memory (e.g. video ram) that the device owns, | |
1402 | and knows it isn't going to access beyond the end of the block. | |
1403 | ||
1404 | It should not be used for general purpose DMA. | |
1405 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
1406 | */ | |
1407 | void *qemu_get_ram_ptr(ram_addr_t addr) | |
1408 | { | |
1409 | RAMBlock *block = qemu_get_ram_block(addr); | |
1410 | ||
0d6d3c87 PB |
1411 | if (xen_enabled()) { |
1412 | /* We need to check if the requested address is in the RAM | |
1413 | * because we don't want to map the entire memory in QEMU. | |
1414 | * In that case just map until the end of the page. | |
1415 | */ | |
1416 | if (block->offset == 0) { | |
1417 | return xen_map_cache(addr, 0, 0); | |
1418 | } else if (block->host == NULL) { | |
1419 | block->host = | |
1420 | xen_map_cache(block->offset, block->length, 1); | |
1421 | } | |
1422 | } | |
1423 | return block->host + (addr - block->offset); | |
dc828ca1 PB |
1424 | } |
1425 | ||
38bee5dc SS |
1426 | /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr |
1427 | * but takes a size argument */ | |
cb85f7ab | 1428 | static void *qemu_ram_ptr_length(ram_addr_t addr, hwaddr *size) |
38bee5dc | 1429 | { |
8ab934f9 SS |
1430 | if (*size == 0) { |
1431 | return NULL; | |
1432 | } | |
868bb33f | 1433 | if (xen_enabled()) { |
e41d7c69 | 1434 | return xen_map_cache(addr, *size, 1); |
868bb33f | 1435 | } else { |
38bee5dc SS |
1436 | RAMBlock *block; |
1437 | ||
a3161038 | 1438 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
38bee5dc SS |
1439 | if (addr - block->offset < block->length) { |
1440 | if (addr - block->offset + *size > block->length) | |
1441 | *size = block->length - addr + block->offset; | |
1442 | return block->host + (addr - block->offset); | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1447 | abort(); | |
38bee5dc SS |
1448 | } |
1449 | } | |
1450 | ||
7443b437 PB |
1451 | /* Some of the softmmu routines need to translate from a host pointer |
1452 | (typically a TLB entry) back to a ram offset. */ | |
1b5ec234 | 1453 | MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
5579c7f3 | 1454 | { |
94a6b54f PB |
1455 | RAMBlock *block; |
1456 | uint8_t *host = ptr; | |
1457 | ||
868bb33f | 1458 | if (xen_enabled()) { |
e41d7c69 | 1459 | *ram_addr = xen_ram_addr_from_mapcache(ptr); |
1b5ec234 | 1460 | return qemu_get_ram_block(*ram_addr)->mr; |
712c2b41 SS |
1461 | } |
1462 | ||
23887b79 PB |
1463 | block = ram_list.mru_block; |
1464 | if (block && block->host && host - block->host < block->length) { | |
1465 | goto found; | |
1466 | } | |
1467 | ||
a3161038 | 1468 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
432d268c JN |
1469 | /* This case append when the block is not mapped. */ |
1470 | if (block->host == NULL) { | |
1471 | continue; | |
1472 | } | |
f471a17e | 1473 | if (host - block->host < block->length) { |
23887b79 | 1474 | goto found; |
f471a17e | 1475 | } |
94a6b54f | 1476 | } |
432d268c | 1477 | |
1b5ec234 | 1478 | return NULL; |
23887b79 PB |
1479 | |
1480 | found: | |
1481 | *ram_addr = block->offset + (host - block->host); | |
1b5ec234 | 1482 | return block->mr; |
e890261f | 1483 | } |
f471a17e | 1484 | |
a8170e5e | 1485 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, |
0e0df1e2 | 1486 | uint64_t val, unsigned size) |
9fa3e853 | 1487 | { |
52159192 | 1488 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { |
0e0df1e2 | 1489 | tb_invalidate_phys_page_fast(ram_addr, size); |
3a7d929e | 1490 | } |
0e0df1e2 AK |
1491 | switch (size) { |
1492 | case 1: | |
1493 | stb_p(qemu_get_ram_ptr(ram_addr), val); | |
1494 | break; | |
1495 | case 2: | |
1496 | stw_p(qemu_get_ram_ptr(ram_addr), val); | |
1497 | break; | |
1498 | case 4: | |
1499 | stl_p(qemu_get_ram_ptr(ram_addr), val); | |
1500 | break; | |
1501 | default: | |
1502 | abort(); | |
3a7d929e | 1503 | } |
52159192 JQ |
1504 | cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_MIGRATION); |
1505 | cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_VGA); | |
f23db169 FB |
1506 | /* we remove the notdirty callback only if the code has been |
1507 | flushed */ | |
06567942 | 1508 | if (cpu_physical_memory_is_dirty(ram_addr)) { |
4917cf44 AF |
1509 | CPUArchState *env = current_cpu->env_ptr; |
1510 | tlb_set_dirty(env, env->mem_io_vaddr); | |
1511 | } | |
9fa3e853 FB |
1512 | } |
1513 | ||
b018ddf6 PB |
1514 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, |
1515 | unsigned size, bool is_write) | |
1516 | { | |
1517 | return is_write; | |
1518 | } | |
1519 | ||
0e0df1e2 | 1520 | static const MemoryRegionOps notdirty_mem_ops = { |
0e0df1e2 | 1521 | .write = notdirty_mem_write, |
b018ddf6 | 1522 | .valid.accepts = notdirty_mem_accepts, |
0e0df1e2 | 1523 | .endianness = DEVICE_NATIVE_ENDIAN, |
1ccde1cb FB |
1524 | }; |
1525 | ||
0f459d16 | 1526 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 1527 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 | 1528 | { |
4917cf44 | 1529 | CPUArchState *env = current_cpu->env_ptr; |
06d55cc1 | 1530 | target_ulong pc, cs_base; |
0f459d16 | 1531 | target_ulong vaddr; |
a1d1bb31 | 1532 | CPUWatchpoint *wp; |
06d55cc1 | 1533 | int cpu_flags; |
0f459d16 | 1534 | |
06d55cc1 AL |
1535 | if (env->watchpoint_hit) { |
1536 | /* We re-entered the check after replacing the TB. Now raise | |
1537 | * the debug interrupt so that is will trigger after the | |
1538 | * current instruction. */ | |
c3affe56 | 1539 | cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_DEBUG); |
06d55cc1 AL |
1540 | return; |
1541 | } | |
2e70f6ef | 1542 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 1543 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
1544 | if ((vaddr == (wp->vaddr & len_mask) || |
1545 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
1546 | wp->flags |= BP_WATCHPOINT_HIT; |
1547 | if (!env->watchpoint_hit) { | |
1548 | env->watchpoint_hit = wp; | |
5a316526 | 1549 | tb_check_watchpoint(env); |
6e140f28 AL |
1550 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
1551 | env->exception_index = EXCP_DEBUG; | |
488d6577 | 1552 | cpu_loop_exit(env); |
6e140f28 AL |
1553 | } else { |
1554 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
1555 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
488d6577 | 1556 | cpu_resume_from_signal(env, NULL); |
6e140f28 | 1557 | } |
06d55cc1 | 1558 | } |
6e140f28 AL |
1559 | } else { |
1560 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
1561 | } |
1562 | } | |
1563 | } | |
1564 | ||
6658ffb8 PB |
1565 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
1566 | so these check for a hit then pass through to the normal out-of-line | |
1567 | phys routines. */ | |
a8170e5e | 1568 | static uint64_t watch_mem_read(void *opaque, hwaddr addr, |
1ec9b909 | 1569 | unsigned size) |
6658ffb8 | 1570 | { |
1ec9b909 AK |
1571 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ); |
1572 | switch (size) { | |
1573 | case 1: return ldub_phys(addr); | |
1574 | case 2: return lduw_phys(addr); | |
1575 | case 4: return ldl_phys(addr); | |
1576 | default: abort(); | |
1577 | } | |
6658ffb8 PB |
1578 | } |
1579 | ||
a8170e5e | 1580 | static void watch_mem_write(void *opaque, hwaddr addr, |
1ec9b909 | 1581 | uint64_t val, unsigned size) |
6658ffb8 | 1582 | { |
1ec9b909 AK |
1583 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE); |
1584 | switch (size) { | |
67364150 MF |
1585 | case 1: |
1586 | stb_phys(addr, val); | |
1587 | break; | |
1588 | case 2: | |
1589 | stw_phys(addr, val); | |
1590 | break; | |
1591 | case 4: | |
1592 | stl_phys(addr, val); | |
1593 | break; | |
1ec9b909 AK |
1594 | default: abort(); |
1595 | } | |
6658ffb8 PB |
1596 | } |
1597 | ||
1ec9b909 AK |
1598 | static const MemoryRegionOps watch_mem_ops = { |
1599 | .read = watch_mem_read, | |
1600 | .write = watch_mem_write, | |
1601 | .endianness = DEVICE_NATIVE_ENDIAN, | |
6658ffb8 | 1602 | }; |
6658ffb8 | 1603 | |
a8170e5e | 1604 | static uint64_t subpage_read(void *opaque, hwaddr addr, |
70c68e44 | 1605 | unsigned len) |
db7b5426 | 1606 | { |
acc9d80b JK |
1607 | subpage_t *subpage = opaque; |
1608 | uint8_t buf[4]; | |
791af8c8 | 1609 | |
db7b5426 | 1610 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 1611 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, |
acc9d80b | 1612 | subpage, len, addr); |
db7b5426 | 1613 | #endif |
acc9d80b JK |
1614 | address_space_read(subpage->as, addr + subpage->base, buf, len); |
1615 | switch (len) { | |
1616 | case 1: | |
1617 | return ldub_p(buf); | |
1618 | case 2: | |
1619 | return lduw_p(buf); | |
1620 | case 4: | |
1621 | return ldl_p(buf); | |
1622 | default: | |
1623 | abort(); | |
1624 | } | |
db7b5426 BS |
1625 | } |
1626 | ||
a8170e5e | 1627 | static void subpage_write(void *opaque, hwaddr addr, |
70c68e44 | 1628 | uint64_t value, unsigned len) |
db7b5426 | 1629 | { |
acc9d80b JK |
1630 | subpage_t *subpage = opaque; |
1631 | uint8_t buf[4]; | |
1632 | ||
db7b5426 | 1633 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 1634 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx |
acc9d80b JK |
1635 | " value %"PRIx64"\n", |
1636 | __func__, subpage, len, addr, value); | |
db7b5426 | 1637 | #endif |
acc9d80b JK |
1638 | switch (len) { |
1639 | case 1: | |
1640 | stb_p(buf, value); | |
1641 | break; | |
1642 | case 2: | |
1643 | stw_p(buf, value); | |
1644 | break; | |
1645 | case 4: | |
1646 | stl_p(buf, value); | |
1647 | break; | |
1648 | default: | |
1649 | abort(); | |
1650 | } | |
1651 | address_space_write(subpage->as, addr + subpage->base, buf, len); | |
db7b5426 BS |
1652 | } |
1653 | ||
c353e4cc | 1654 | static bool subpage_accepts(void *opaque, hwaddr addr, |
016e9d62 | 1655 | unsigned len, bool is_write) |
c353e4cc | 1656 | { |
acc9d80b | 1657 | subpage_t *subpage = opaque; |
c353e4cc | 1658 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 1659 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", |
acc9d80b | 1660 | __func__, subpage, is_write ? 'w' : 'r', len, addr); |
c353e4cc PB |
1661 | #endif |
1662 | ||
acc9d80b | 1663 | return address_space_access_valid(subpage->as, addr + subpage->base, |
016e9d62 | 1664 | len, is_write); |
c353e4cc PB |
1665 | } |
1666 | ||
70c68e44 AK |
1667 | static const MemoryRegionOps subpage_ops = { |
1668 | .read = subpage_read, | |
1669 | .write = subpage_write, | |
c353e4cc | 1670 | .valid.accepts = subpage_accepts, |
70c68e44 | 1671 | .endianness = DEVICE_NATIVE_ENDIAN, |
db7b5426 BS |
1672 | }; |
1673 | ||
c227f099 | 1674 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 1675 | uint16_t section) |
db7b5426 BS |
1676 | { |
1677 | int idx, eidx; | |
1678 | ||
1679 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
1680 | return -1; | |
1681 | idx = SUBPAGE_IDX(start); | |
1682 | eidx = SUBPAGE_IDX(end); | |
1683 | #if defined(DEBUG_SUBPAGE) | |
016e9d62 AK |
1684 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", |
1685 | __func__, mmio, start, end, idx, eidx, section); | |
db7b5426 | 1686 | #endif |
db7b5426 | 1687 | for (; idx <= eidx; idx++) { |
5312bd8b | 1688 | mmio->sub_section[idx] = section; |
db7b5426 BS |
1689 | } |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
acc9d80b | 1694 | static subpage_t *subpage_init(AddressSpace *as, hwaddr base) |
db7b5426 | 1695 | { |
c227f099 | 1696 | subpage_t *mmio; |
db7b5426 | 1697 | |
7267c094 | 1698 | mmio = g_malloc0(sizeof(subpage_t)); |
1eec614b | 1699 | |
acc9d80b | 1700 | mmio->as = as; |
1eec614b | 1701 | mmio->base = base; |
2c9b15ca | 1702 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
70c68e44 | 1703 | "subpage", TARGET_PAGE_SIZE); |
b3b00c78 | 1704 | mmio->iomem.subpage = true; |
db7b5426 | 1705 | #if defined(DEBUG_SUBPAGE) |
016e9d62 AK |
1706 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, |
1707 | mmio, base, TARGET_PAGE_SIZE); | |
db7b5426 | 1708 | #endif |
b41aac4f | 1709 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); |
db7b5426 BS |
1710 | |
1711 | return mmio; | |
1712 | } | |
1713 | ||
53cb28cb | 1714 | static uint16_t dummy_section(PhysPageMap *map, MemoryRegion *mr) |
5312bd8b AK |
1715 | { |
1716 | MemoryRegionSection section = { | |
1717 | .mr = mr, | |
1718 | .offset_within_address_space = 0, | |
1719 | .offset_within_region = 0, | |
052e87b0 | 1720 | .size = int128_2_64(), |
5312bd8b AK |
1721 | }; |
1722 | ||
53cb28cb | 1723 | return phys_section_add(map, §ion); |
5312bd8b AK |
1724 | } |
1725 | ||
a8170e5e | 1726 | MemoryRegion *iotlb_to_region(hwaddr index) |
aa102231 | 1727 | { |
53cb28cb MA |
1728 | return address_space_memory.dispatch->map.sections[ |
1729 | index & ~TARGET_PAGE_MASK].mr; | |
aa102231 AK |
1730 | } |
1731 | ||
e9179ce1 AK |
1732 | static void io_mem_init(void) |
1733 | { | |
2c9b15ca PB |
1734 | memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, "rom", UINT64_MAX); |
1735 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, | |
0e0df1e2 | 1736 | "unassigned", UINT64_MAX); |
2c9b15ca | 1737 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, |
0e0df1e2 | 1738 | "notdirty", UINT64_MAX); |
2c9b15ca | 1739 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, |
1ec9b909 | 1740 | "watch", UINT64_MAX); |
e9179ce1 AK |
1741 | } |
1742 | ||
ac1970fb | 1743 | static void mem_begin(MemoryListener *listener) |
00752703 PB |
1744 | { |
1745 | AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); | |
53cb28cb MA |
1746 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); |
1747 | uint16_t n; | |
1748 | ||
1749 | n = dummy_section(&d->map, &io_mem_unassigned); | |
1750 | assert(n == PHYS_SECTION_UNASSIGNED); | |
1751 | n = dummy_section(&d->map, &io_mem_notdirty); | |
1752 | assert(n == PHYS_SECTION_NOTDIRTY); | |
1753 | n = dummy_section(&d->map, &io_mem_rom); | |
1754 | assert(n == PHYS_SECTION_ROM); | |
1755 | n = dummy_section(&d->map, &io_mem_watch); | |
1756 | assert(n == PHYS_SECTION_WATCH); | |
00752703 | 1757 | |
9736e55b | 1758 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; |
00752703 PB |
1759 | d->as = as; |
1760 | as->next_dispatch = d; | |
1761 | } | |
1762 | ||
1763 | static void mem_commit(MemoryListener *listener) | |
ac1970fb | 1764 | { |
89ae337a | 1765 | AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
0475d94f PB |
1766 | AddressSpaceDispatch *cur = as->dispatch; |
1767 | AddressSpaceDispatch *next = as->next_dispatch; | |
1768 | ||
53cb28cb | 1769 | phys_page_compact_all(next, next->map.nodes_nb); |
b35ba30f | 1770 | |
0475d94f | 1771 | as->dispatch = next; |
b41aac4f | 1772 | |
53cb28cb MA |
1773 | if (cur) { |
1774 | phys_sections_free(&cur->map); | |
1775 | g_free(cur); | |
1776 | } | |
9affd6fc PB |
1777 | } |
1778 | ||
1d71148e | 1779 | static void tcg_commit(MemoryListener *listener) |
50c1e149 | 1780 | { |
182735ef | 1781 | CPUState *cpu; |
117712c3 AK |
1782 | |
1783 | /* since each CPU stores ram addresses in its TLB cache, we must | |
1784 | reset the modified entries */ | |
1785 | /* XXX: slow ! */ | |
bdc44640 | 1786 | CPU_FOREACH(cpu) { |
182735ef AF |
1787 | CPUArchState *env = cpu->env_ptr; |
1788 | ||
117712c3 AK |
1789 | tlb_flush(env, 1); |
1790 | } | |
50c1e149 AK |
1791 | } |
1792 | ||
93632747 AK |
1793 | static void core_log_global_start(MemoryListener *listener) |
1794 | { | |
1795 | cpu_physical_memory_set_dirty_tracking(1); | |
1796 | } | |
1797 | ||
1798 | static void core_log_global_stop(MemoryListener *listener) | |
1799 | { | |
1800 | cpu_physical_memory_set_dirty_tracking(0); | |
1801 | } | |
1802 | ||
93632747 | 1803 | static MemoryListener core_memory_listener = { |
93632747 AK |
1804 | .log_global_start = core_log_global_start, |
1805 | .log_global_stop = core_log_global_stop, | |
ac1970fb | 1806 | .priority = 1, |
93632747 AK |
1807 | }; |
1808 | ||
1d71148e AK |
1809 | static MemoryListener tcg_memory_listener = { |
1810 | .commit = tcg_commit, | |
1811 | }; | |
1812 | ||
ac1970fb AK |
1813 | void address_space_init_dispatch(AddressSpace *as) |
1814 | { | |
00752703 | 1815 | as->dispatch = NULL; |
89ae337a | 1816 | as->dispatch_listener = (MemoryListener) { |
ac1970fb | 1817 | .begin = mem_begin, |
00752703 | 1818 | .commit = mem_commit, |
ac1970fb AK |
1819 | .region_add = mem_add, |
1820 | .region_nop = mem_add, | |
1821 | .priority = 0, | |
1822 | }; | |
89ae337a | 1823 | memory_listener_register(&as->dispatch_listener, as); |
ac1970fb AK |
1824 | } |
1825 | ||
83f3c251 AK |
1826 | void address_space_destroy_dispatch(AddressSpace *as) |
1827 | { | |
1828 | AddressSpaceDispatch *d = as->dispatch; | |
1829 | ||
89ae337a | 1830 | memory_listener_unregister(&as->dispatch_listener); |
83f3c251 AK |
1831 | g_free(d); |
1832 | as->dispatch = NULL; | |
1833 | } | |
1834 | ||
62152b8a AK |
1835 | static void memory_map_init(void) |
1836 | { | |
7267c094 | 1837 | system_memory = g_malloc(sizeof(*system_memory)); |
03f49957 | 1838 | |
57271d63 | 1839 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
7dca8043 | 1840 | address_space_init(&address_space_memory, system_memory, "memory"); |
309cb471 | 1841 | |
7267c094 | 1842 | system_io = g_malloc(sizeof(*system_io)); |
3bb28b72 JK |
1843 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
1844 | 65536); | |
7dca8043 | 1845 | address_space_init(&address_space_io, system_io, "I/O"); |
93632747 | 1846 | |
f6790af6 | 1847 | memory_listener_register(&core_memory_listener, &address_space_memory); |
2641689a LG |
1848 | if (tcg_enabled()) { |
1849 | memory_listener_register(&tcg_memory_listener, &address_space_memory); | |
1850 | } | |
62152b8a AK |
1851 | } |
1852 | ||
1853 | MemoryRegion *get_system_memory(void) | |
1854 | { | |
1855 | return system_memory; | |
1856 | } | |
1857 | ||
309cb471 AK |
1858 | MemoryRegion *get_system_io(void) |
1859 | { | |
1860 | return system_io; | |
1861 | } | |
1862 | ||
e2eef170 PB |
1863 | #endif /* !defined(CONFIG_USER_ONLY) */ |
1864 | ||
13eb76e0 FB |
1865 | /* physical memory access (slow version, mainly for debug) */ |
1866 | #if defined(CONFIG_USER_ONLY) | |
f17ec444 | 1867 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
a68fe89c | 1868 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
1869 | { |
1870 | int l, flags; | |
1871 | target_ulong page; | |
53a5960a | 1872 | void * p; |
13eb76e0 FB |
1873 | |
1874 | while (len > 0) { | |
1875 | page = addr & TARGET_PAGE_MASK; | |
1876 | l = (page + TARGET_PAGE_SIZE) - addr; | |
1877 | if (l > len) | |
1878 | l = len; | |
1879 | flags = page_get_flags(page); | |
1880 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 1881 | return -1; |
13eb76e0 FB |
1882 | if (is_write) { |
1883 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 1884 | return -1; |
579a97f7 | 1885 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 1886 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 1887 | return -1; |
72fb7daa AJ |
1888 | memcpy(p, buf, l); |
1889 | unlock_user(p, addr, l); | |
13eb76e0 FB |
1890 | } else { |
1891 | if (!(flags & PAGE_READ)) | |
a68fe89c | 1892 | return -1; |
579a97f7 | 1893 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 1894 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 1895 | return -1; |
72fb7daa | 1896 | memcpy(buf, p, l); |
5b257578 | 1897 | unlock_user(p, addr, 0); |
13eb76e0 FB |
1898 | } |
1899 | len -= l; | |
1900 | buf += l; | |
1901 | addr += l; | |
1902 | } | |
a68fe89c | 1903 | return 0; |
13eb76e0 | 1904 | } |
8df1cd07 | 1905 | |
13eb76e0 | 1906 | #else |
51d7a9eb | 1907 | |
a8170e5e AK |
1908 | static void invalidate_and_set_dirty(hwaddr addr, |
1909 | hwaddr length) | |
51d7a9eb AP |
1910 | { |
1911 | if (!cpu_physical_memory_is_dirty(addr)) { | |
1912 | /* invalidate code */ | |
1913 | tb_invalidate_phys_page_range(addr, addr + length, 0); | |
1914 | /* set dirty bit */ | |
52159192 JQ |
1915 | cpu_physical_memory_set_dirty_flag(addr, DIRTY_MEMORY_VGA); |
1916 | cpu_physical_memory_set_dirty_flag(addr, DIRTY_MEMORY_MIGRATION); | |
51d7a9eb | 1917 | } |
e226939d | 1918 | xen_modified_memory(addr, length); |
51d7a9eb AP |
1919 | } |
1920 | ||
2bbfa05d PB |
1921 | static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write) |
1922 | { | |
1923 | if (memory_region_is_ram(mr)) { | |
1924 | return !(is_write && mr->readonly); | |
1925 | } | |
1926 | if (memory_region_is_romd(mr)) { | |
1927 | return !is_write; | |
1928 | } | |
1929 | ||
1930 | return false; | |
1931 | } | |
1932 | ||
23326164 | 1933 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
82f2563f | 1934 | { |
e1622f4b | 1935 | unsigned access_size_max = mr->ops->valid.max_access_size; |
23326164 RH |
1936 | |
1937 | /* Regions are assumed to support 1-4 byte accesses unless | |
1938 | otherwise specified. */ | |
23326164 RH |
1939 | if (access_size_max == 0) { |
1940 | access_size_max = 4; | |
1941 | } | |
1942 | ||
1943 | /* Bound the maximum access by the alignment of the address. */ | |
1944 | if (!mr->ops->impl.unaligned) { | |
1945 | unsigned align_size_max = addr & -addr; | |
1946 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
1947 | access_size_max = align_size_max; | |
1948 | } | |
82f2563f | 1949 | } |
23326164 RH |
1950 | |
1951 | /* Don't attempt accesses larger than the maximum. */ | |
1952 | if (l > access_size_max) { | |
1953 | l = access_size_max; | |
82f2563f | 1954 | } |
098178f2 PB |
1955 | if (l & (l - 1)) { |
1956 | l = 1 << (qemu_fls(l) - 1); | |
1957 | } | |
23326164 RH |
1958 | |
1959 | return l; | |
82f2563f PB |
1960 | } |
1961 | ||
fd8aaa76 | 1962 | bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, |
ac1970fb | 1963 | int len, bool is_write) |
13eb76e0 | 1964 | { |
149f54b5 | 1965 | hwaddr l; |
13eb76e0 | 1966 | uint8_t *ptr; |
791af8c8 | 1967 | uint64_t val; |
149f54b5 | 1968 | hwaddr addr1; |
5c8a00ce | 1969 | MemoryRegion *mr; |
fd8aaa76 | 1970 | bool error = false; |
3b46e624 | 1971 | |
13eb76e0 | 1972 | while (len > 0) { |
149f54b5 | 1973 | l = len; |
5c8a00ce | 1974 | mr = address_space_translate(as, addr, &addr1, &l, is_write); |
3b46e624 | 1975 | |
13eb76e0 | 1976 | if (is_write) { |
5c8a00ce PB |
1977 | if (!memory_access_is_direct(mr, is_write)) { |
1978 | l = memory_access_size(mr, l, addr1); | |
4917cf44 | 1979 | /* XXX: could force current_cpu to NULL to avoid |
6a00d601 | 1980 | potential bugs */ |
23326164 RH |
1981 | switch (l) { |
1982 | case 8: | |
1983 | /* 64 bit write access */ | |
1984 | val = ldq_p(buf); | |
1985 | error |= io_mem_write(mr, addr1, val, 8); | |
1986 | break; | |
1987 | case 4: | |
1c213d19 | 1988 | /* 32 bit write access */ |
c27004ec | 1989 | val = ldl_p(buf); |
5c8a00ce | 1990 | error |= io_mem_write(mr, addr1, val, 4); |
23326164 RH |
1991 | break; |
1992 | case 2: | |
1c213d19 | 1993 | /* 16 bit write access */ |
c27004ec | 1994 | val = lduw_p(buf); |
5c8a00ce | 1995 | error |= io_mem_write(mr, addr1, val, 2); |
23326164 RH |
1996 | break; |
1997 | case 1: | |
1c213d19 | 1998 | /* 8 bit write access */ |
c27004ec | 1999 | val = ldub_p(buf); |
5c8a00ce | 2000 | error |= io_mem_write(mr, addr1, val, 1); |
23326164 RH |
2001 | break; |
2002 | default: | |
2003 | abort(); | |
13eb76e0 | 2004 | } |
2bbfa05d | 2005 | } else { |
5c8a00ce | 2006 | addr1 += memory_region_get_ram_addr(mr); |
13eb76e0 | 2007 | /* RAM case */ |
5579c7f3 | 2008 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 2009 | memcpy(ptr, buf, l); |
51d7a9eb | 2010 | invalidate_and_set_dirty(addr1, l); |
13eb76e0 FB |
2011 | } |
2012 | } else { | |
5c8a00ce | 2013 | if (!memory_access_is_direct(mr, is_write)) { |
13eb76e0 | 2014 | /* I/O case */ |
5c8a00ce | 2015 | l = memory_access_size(mr, l, addr1); |
23326164 RH |
2016 | switch (l) { |
2017 | case 8: | |
2018 | /* 64 bit read access */ | |
2019 | error |= io_mem_read(mr, addr1, &val, 8); | |
2020 | stq_p(buf, val); | |
2021 | break; | |
2022 | case 4: | |
13eb76e0 | 2023 | /* 32 bit read access */ |
5c8a00ce | 2024 | error |= io_mem_read(mr, addr1, &val, 4); |
c27004ec | 2025 | stl_p(buf, val); |
23326164 RH |
2026 | break; |
2027 | case 2: | |
13eb76e0 | 2028 | /* 16 bit read access */ |
5c8a00ce | 2029 | error |= io_mem_read(mr, addr1, &val, 2); |
c27004ec | 2030 | stw_p(buf, val); |
23326164 RH |
2031 | break; |
2032 | case 1: | |
1c213d19 | 2033 | /* 8 bit read access */ |
5c8a00ce | 2034 | error |= io_mem_read(mr, addr1, &val, 1); |
c27004ec | 2035 | stb_p(buf, val); |
23326164 RH |
2036 | break; |
2037 | default: | |
2038 | abort(); | |
13eb76e0 FB |
2039 | } |
2040 | } else { | |
2041 | /* RAM case */ | |
5c8a00ce | 2042 | ptr = qemu_get_ram_ptr(mr->ram_addr + addr1); |
f3705d53 | 2043 | memcpy(buf, ptr, l); |
13eb76e0 FB |
2044 | } |
2045 | } | |
2046 | len -= l; | |
2047 | buf += l; | |
2048 | addr += l; | |
2049 | } | |
fd8aaa76 PB |
2050 | |
2051 | return error; | |
13eb76e0 | 2052 | } |
8df1cd07 | 2053 | |
fd8aaa76 | 2054 | bool address_space_write(AddressSpace *as, hwaddr addr, |
ac1970fb AK |
2055 | const uint8_t *buf, int len) |
2056 | { | |
fd8aaa76 | 2057 | return address_space_rw(as, addr, (uint8_t *)buf, len, true); |
ac1970fb AK |
2058 | } |
2059 | ||
fd8aaa76 | 2060 | bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len) |
ac1970fb | 2061 | { |
fd8aaa76 | 2062 | return address_space_rw(as, addr, buf, len, false); |
ac1970fb AK |
2063 | } |
2064 | ||
2065 | ||
a8170e5e | 2066 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
ac1970fb AK |
2067 | int len, int is_write) |
2068 | { | |
fd8aaa76 | 2069 | address_space_rw(&address_space_memory, addr, buf, len, is_write); |
ac1970fb AK |
2070 | } |
2071 | ||
582b55a9 AG |
2072 | enum write_rom_type { |
2073 | WRITE_DATA, | |
2074 | FLUSH_CACHE, | |
2075 | }; | |
2076 | ||
2077 | static inline void cpu_physical_memory_write_rom_internal( | |
2078 | hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) | |
d0ecd2aa | 2079 | { |
149f54b5 | 2080 | hwaddr l; |
d0ecd2aa | 2081 | uint8_t *ptr; |
149f54b5 | 2082 | hwaddr addr1; |
5c8a00ce | 2083 | MemoryRegion *mr; |
3b46e624 | 2084 | |
d0ecd2aa | 2085 | while (len > 0) { |
149f54b5 | 2086 | l = len; |
5c8a00ce PB |
2087 | mr = address_space_translate(&address_space_memory, |
2088 | addr, &addr1, &l, true); | |
3b46e624 | 2089 | |
5c8a00ce PB |
2090 | if (!(memory_region_is_ram(mr) || |
2091 | memory_region_is_romd(mr))) { | |
d0ecd2aa FB |
2092 | /* do nothing */ |
2093 | } else { | |
5c8a00ce | 2094 | addr1 += memory_region_get_ram_addr(mr); |
d0ecd2aa | 2095 | /* ROM/RAM case */ |
5579c7f3 | 2096 | ptr = qemu_get_ram_ptr(addr1); |
582b55a9 AG |
2097 | switch (type) { |
2098 | case WRITE_DATA: | |
2099 | memcpy(ptr, buf, l); | |
2100 | invalidate_and_set_dirty(addr1, l); | |
2101 | break; | |
2102 | case FLUSH_CACHE: | |
2103 | flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); | |
2104 | break; | |
2105 | } | |
d0ecd2aa FB |
2106 | } |
2107 | len -= l; | |
2108 | buf += l; | |
2109 | addr += l; | |
2110 | } | |
2111 | } | |
2112 | ||
582b55a9 AG |
2113 | /* used for ROM loading : can write in RAM and ROM */ |
2114 | void cpu_physical_memory_write_rom(hwaddr addr, | |
2115 | const uint8_t *buf, int len) | |
2116 | { | |
2117 | cpu_physical_memory_write_rom_internal(addr, buf, len, WRITE_DATA); | |
2118 | } | |
2119 | ||
2120 | void cpu_flush_icache_range(hwaddr start, int len) | |
2121 | { | |
2122 | /* | |
2123 | * This function should do the same thing as an icache flush that was | |
2124 | * triggered from within the guest. For TCG we are always cache coherent, | |
2125 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
2126 | * the host's instruction cache at least. | |
2127 | */ | |
2128 | if (tcg_enabled()) { | |
2129 | return; | |
2130 | } | |
2131 | ||
2132 | cpu_physical_memory_write_rom_internal(start, NULL, len, FLUSH_CACHE); | |
2133 | } | |
2134 | ||
6d16c2f8 | 2135 | typedef struct { |
d3e71559 | 2136 | MemoryRegion *mr; |
6d16c2f8 | 2137 | void *buffer; |
a8170e5e AK |
2138 | hwaddr addr; |
2139 | hwaddr len; | |
6d16c2f8 AL |
2140 | } BounceBuffer; |
2141 | ||
2142 | static BounceBuffer bounce; | |
2143 | ||
ba223c29 AL |
2144 | typedef struct MapClient { |
2145 | void *opaque; | |
2146 | void (*callback)(void *opaque); | |
72cf2d4f | 2147 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
2148 | } MapClient; |
2149 | ||
72cf2d4f BS |
2150 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
2151 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
2152 | |
2153 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
2154 | { | |
7267c094 | 2155 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 AL |
2156 | |
2157 | client->opaque = opaque; | |
2158 | client->callback = callback; | |
72cf2d4f | 2159 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
2160 | return client; |
2161 | } | |
2162 | ||
8b9c99d9 | 2163 | static void cpu_unregister_map_client(void *_client) |
ba223c29 AL |
2164 | { |
2165 | MapClient *client = (MapClient *)_client; | |
2166 | ||
72cf2d4f | 2167 | QLIST_REMOVE(client, link); |
7267c094 | 2168 | g_free(client); |
ba223c29 AL |
2169 | } |
2170 | ||
2171 | static void cpu_notify_map_clients(void) | |
2172 | { | |
2173 | MapClient *client; | |
2174 | ||
72cf2d4f BS |
2175 | while (!QLIST_EMPTY(&map_client_list)) { |
2176 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 2177 | client->callback(client->opaque); |
34d5e948 | 2178 | cpu_unregister_map_client(client); |
ba223c29 AL |
2179 | } |
2180 | } | |
2181 | ||
51644ab7 PB |
2182 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write) |
2183 | { | |
5c8a00ce | 2184 | MemoryRegion *mr; |
51644ab7 PB |
2185 | hwaddr l, xlat; |
2186 | ||
2187 | while (len > 0) { | |
2188 | l = len; | |
5c8a00ce PB |
2189 | mr = address_space_translate(as, addr, &xlat, &l, is_write); |
2190 | if (!memory_access_is_direct(mr, is_write)) { | |
2191 | l = memory_access_size(mr, l, addr); | |
2192 | if (!memory_region_access_valid(mr, xlat, l, is_write)) { | |
51644ab7 PB |
2193 | return false; |
2194 | } | |
2195 | } | |
2196 | ||
2197 | len -= l; | |
2198 | addr += l; | |
2199 | } | |
2200 | return true; | |
2201 | } | |
2202 | ||
6d16c2f8 AL |
2203 | /* Map a physical memory region into a host virtual address. |
2204 | * May map a subset of the requested range, given by and returned in *plen. | |
2205 | * May return NULL if resources needed to perform the mapping are exhausted. | |
2206 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
2207 | * Use cpu_register_map_client() to know when retrying the map operation is |
2208 | * likely to succeed. | |
6d16c2f8 | 2209 | */ |
ac1970fb | 2210 | void *address_space_map(AddressSpace *as, |
a8170e5e AK |
2211 | hwaddr addr, |
2212 | hwaddr *plen, | |
ac1970fb | 2213 | bool is_write) |
6d16c2f8 | 2214 | { |
a8170e5e | 2215 | hwaddr len = *plen; |
e3127ae0 PB |
2216 | hwaddr done = 0; |
2217 | hwaddr l, xlat, base; | |
2218 | MemoryRegion *mr, *this_mr; | |
2219 | ram_addr_t raddr; | |
6d16c2f8 | 2220 | |
e3127ae0 PB |
2221 | if (len == 0) { |
2222 | return NULL; | |
2223 | } | |
38bee5dc | 2224 | |
e3127ae0 PB |
2225 | l = len; |
2226 | mr = address_space_translate(as, addr, &xlat, &l, is_write); | |
2227 | if (!memory_access_is_direct(mr, is_write)) { | |
2228 | if (bounce.buffer) { | |
2229 | return NULL; | |
6d16c2f8 | 2230 | } |
e85d9db5 KW |
2231 | /* Avoid unbounded allocations */ |
2232 | l = MIN(l, TARGET_PAGE_SIZE); | |
2233 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
e3127ae0 PB |
2234 | bounce.addr = addr; |
2235 | bounce.len = l; | |
d3e71559 PB |
2236 | |
2237 | memory_region_ref(mr); | |
2238 | bounce.mr = mr; | |
e3127ae0 PB |
2239 | if (!is_write) { |
2240 | address_space_read(as, addr, bounce.buffer, l); | |
8ab934f9 | 2241 | } |
6d16c2f8 | 2242 | |
e3127ae0 PB |
2243 | *plen = l; |
2244 | return bounce.buffer; | |
2245 | } | |
2246 | ||
2247 | base = xlat; | |
2248 | raddr = memory_region_get_ram_addr(mr); | |
2249 | ||
2250 | for (;;) { | |
6d16c2f8 AL |
2251 | len -= l; |
2252 | addr += l; | |
e3127ae0 PB |
2253 | done += l; |
2254 | if (len == 0) { | |
2255 | break; | |
2256 | } | |
2257 | ||
2258 | l = len; | |
2259 | this_mr = address_space_translate(as, addr, &xlat, &l, is_write); | |
2260 | if (this_mr != mr || xlat != base + done) { | |
2261 | break; | |
2262 | } | |
6d16c2f8 | 2263 | } |
e3127ae0 | 2264 | |
d3e71559 | 2265 | memory_region_ref(mr); |
e3127ae0 PB |
2266 | *plen = done; |
2267 | return qemu_ram_ptr_length(raddr + base, plen); | |
6d16c2f8 AL |
2268 | } |
2269 | ||
ac1970fb | 2270 | /* Unmaps a memory region previously mapped by address_space_map(). |
6d16c2f8 AL |
2271 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
2272 | * the amount of memory that was actually read or written by the caller. | |
2273 | */ | |
a8170e5e AK |
2274 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
2275 | int is_write, hwaddr access_len) | |
6d16c2f8 AL |
2276 | { |
2277 | if (buffer != bounce.buffer) { | |
d3e71559 PB |
2278 | MemoryRegion *mr; |
2279 | ram_addr_t addr1; | |
2280 | ||
2281 | mr = qemu_ram_addr_from_host(buffer, &addr1); | |
2282 | assert(mr != NULL); | |
6d16c2f8 | 2283 | if (is_write) { |
6d16c2f8 AL |
2284 | while (access_len) { |
2285 | unsigned l; | |
2286 | l = TARGET_PAGE_SIZE; | |
2287 | if (l > access_len) | |
2288 | l = access_len; | |
51d7a9eb | 2289 | invalidate_and_set_dirty(addr1, l); |
6d16c2f8 AL |
2290 | addr1 += l; |
2291 | access_len -= l; | |
2292 | } | |
2293 | } | |
868bb33f | 2294 | if (xen_enabled()) { |
e41d7c69 | 2295 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 2296 | } |
d3e71559 | 2297 | memory_region_unref(mr); |
6d16c2f8 AL |
2298 | return; |
2299 | } | |
2300 | if (is_write) { | |
ac1970fb | 2301 | address_space_write(as, bounce.addr, bounce.buffer, access_len); |
6d16c2f8 | 2302 | } |
f8a83245 | 2303 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 2304 | bounce.buffer = NULL; |
d3e71559 | 2305 | memory_region_unref(bounce.mr); |
ba223c29 | 2306 | cpu_notify_map_clients(); |
6d16c2f8 | 2307 | } |
d0ecd2aa | 2308 | |
a8170e5e AK |
2309 | void *cpu_physical_memory_map(hwaddr addr, |
2310 | hwaddr *plen, | |
ac1970fb AK |
2311 | int is_write) |
2312 | { | |
2313 | return address_space_map(&address_space_memory, addr, plen, is_write); | |
2314 | } | |
2315 | ||
a8170e5e AK |
2316 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
2317 | int is_write, hwaddr access_len) | |
ac1970fb AK |
2318 | { |
2319 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
2320 | } | |
2321 | ||
8df1cd07 | 2322 | /* warning: addr must be aligned */ |
a8170e5e | 2323 | static inline uint32_t ldl_phys_internal(hwaddr addr, |
1e78bcc1 | 2324 | enum device_endian endian) |
8df1cd07 | 2325 | { |
8df1cd07 | 2326 | uint8_t *ptr; |
791af8c8 | 2327 | uint64_t val; |
5c8a00ce | 2328 | MemoryRegion *mr; |
149f54b5 PB |
2329 | hwaddr l = 4; |
2330 | hwaddr addr1; | |
8df1cd07 | 2331 | |
5c8a00ce PB |
2332 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2333 | false); | |
2334 | if (l < 4 || !memory_access_is_direct(mr, false)) { | |
8df1cd07 | 2335 | /* I/O case */ |
5c8a00ce | 2336 | io_mem_read(mr, addr1, &val, 4); |
1e78bcc1 AG |
2337 | #if defined(TARGET_WORDS_BIGENDIAN) |
2338 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2339 | val = bswap32(val); | |
2340 | } | |
2341 | #else | |
2342 | if (endian == DEVICE_BIG_ENDIAN) { | |
2343 | val = bswap32(val); | |
2344 | } | |
2345 | #endif | |
8df1cd07 FB |
2346 | } else { |
2347 | /* RAM case */ | |
5c8a00ce | 2348 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
06ef3525 | 2349 | & TARGET_PAGE_MASK) |
149f54b5 | 2350 | + addr1); |
1e78bcc1 AG |
2351 | switch (endian) { |
2352 | case DEVICE_LITTLE_ENDIAN: | |
2353 | val = ldl_le_p(ptr); | |
2354 | break; | |
2355 | case DEVICE_BIG_ENDIAN: | |
2356 | val = ldl_be_p(ptr); | |
2357 | break; | |
2358 | default: | |
2359 | val = ldl_p(ptr); | |
2360 | break; | |
2361 | } | |
8df1cd07 FB |
2362 | } |
2363 | return val; | |
2364 | } | |
2365 | ||
a8170e5e | 2366 | uint32_t ldl_phys(hwaddr addr) |
1e78bcc1 AG |
2367 | { |
2368 | return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN); | |
2369 | } | |
2370 | ||
a8170e5e | 2371 | uint32_t ldl_le_phys(hwaddr addr) |
1e78bcc1 AG |
2372 | { |
2373 | return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN); | |
2374 | } | |
2375 | ||
a8170e5e | 2376 | uint32_t ldl_be_phys(hwaddr addr) |
1e78bcc1 AG |
2377 | { |
2378 | return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN); | |
2379 | } | |
2380 | ||
84b7b8e7 | 2381 | /* warning: addr must be aligned */ |
a8170e5e | 2382 | static inline uint64_t ldq_phys_internal(hwaddr addr, |
1e78bcc1 | 2383 | enum device_endian endian) |
84b7b8e7 | 2384 | { |
84b7b8e7 FB |
2385 | uint8_t *ptr; |
2386 | uint64_t val; | |
5c8a00ce | 2387 | MemoryRegion *mr; |
149f54b5 PB |
2388 | hwaddr l = 8; |
2389 | hwaddr addr1; | |
84b7b8e7 | 2390 | |
5c8a00ce PB |
2391 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2392 | false); | |
2393 | if (l < 8 || !memory_access_is_direct(mr, false)) { | |
84b7b8e7 | 2394 | /* I/O case */ |
5c8a00ce | 2395 | io_mem_read(mr, addr1, &val, 8); |
968a5627 PB |
2396 | #if defined(TARGET_WORDS_BIGENDIAN) |
2397 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2398 | val = bswap64(val); | |
2399 | } | |
2400 | #else | |
2401 | if (endian == DEVICE_BIG_ENDIAN) { | |
2402 | val = bswap64(val); | |
2403 | } | |
84b7b8e7 FB |
2404 | #endif |
2405 | } else { | |
2406 | /* RAM case */ | |
5c8a00ce | 2407 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
06ef3525 | 2408 | & TARGET_PAGE_MASK) |
149f54b5 | 2409 | + addr1); |
1e78bcc1 AG |
2410 | switch (endian) { |
2411 | case DEVICE_LITTLE_ENDIAN: | |
2412 | val = ldq_le_p(ptr); | |
2413 | break; | |
2414 | case DEVICE_BIG_ENDIAN: | |
2415 | val = ldq_be_p(ptr); | |
2416 | break; | |
2417 | default: | |
2418 | val = ldq_p(ptr); | |
2419 | break; | |
2420 | } | |
84b7b8e7 FB |
2421 | } |
2422 | return val; | |
2423 | } | |
2424 | ||
a8170e5e | 2425 | uint64_t ldq_phys(hwaddr addr) |
1e78bcc1 AG |
2426 | { |
2427 | return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN); | |
2428 | } | |
2429 | ||
a8170e5e | 2430 | uint64_t ldq_le_phys(hwaddr addr) |
1e78bcc1 AG |
2431 | { |
2432 | return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN); | |
2433 | } | |
2434 | ||
a8170e5e | 2435 | uint64_t ldq_be_phys(hwaddr addr) |
1e78bcc1 AG |
2436 | { |
2437 | return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN); | |
2438 | } | |
2439 | ||
aab33094 | 2440 | /* XXX: optimize */ |
a8170e5e | 2441 | uint32_t ldub_phys(hwaddr addr) |
aab33094 FB |
2442 | { |
2443 | uint8_t val; | |
2444 | cpu_physical_memory_read(addr, &val, 1); | |
2445 | return val; | |
2446 | } | |
2447 | ||
733f0b02 | 2448 | /* warning: addr must be aligned */ |
a8170e5e | 2449 | static inline uint32_t lduw_phys_internal(hwaddr addr, |
1e78bcc1 | 2450 | enum device_endian endian) |
aab33094 | 2451 | { |
733f0b02 MT |
2452 | uint8_t *ptr; |
2453 | uint64_t val; | |
5c8a00ce | 2454 | MemoryRegion *mr; |
149f54b5 PB |
2455 | hwaddr l = 2; |
2456 | hwaddr addr1; | |
733f0b02 | 2457 | |
5c8a00ce PB |
2458 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2459 | false); | |
2460 | if (l < 2 || !memory_access_is_direct(mr, false)) { | |
733f0b02 | 2461 | /* I/O case */ |
5c8a00ce | 2462 | io_mem_read(mr, addr1, &val, 2); |
1e78bcc1 AG |
2463 | #if defined(TARGET_WORDS_BIGENDIAN) |
2464 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2465 | val = bswap16(val); | |
2466 | } | |
2467 | #else | |
2468 | if (endian == DEVICE_BIG_ENDIAN) { | |
2469 | val = bswap16(val); | |
2470 | } | |
2471 | #endif | |
733f0b02 MT |
2472 | } else { |
2473 | /* RAM case */ | |
5c8a00ce | 2474 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
06ef3525 | 2475 | & TARGET_PAGE_MASK) |
149f54b5 | 2476 | + addr1); |
1e78bcc1 AG |
2477 | switch (endian) { |
2478 | case DEVICE_LITTLE_ENDIAN: | |
2479 | val = lduw_le_p(ptr); | |
2480 | break; | |
2481 | case DEVICE_BIG_ENDIAN: | |
2482 | val = lduw_be_p(ptr); | |
2483 | break; | |
2484 | default: | |
2485 | val = lduw_p(ptr); | |
2486 | break; | |
2487 | } | |
733f0b02 MT |
2488 | } |
2489 | return val; | |
aab33094 FB |
2490 | } |
2491 | ||
a8170e5e | 2492 | uint32_t lduw_phys(hwaddr addr) |
1e78bcc1 AG |
2493 | { |
2494 | return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN); | |
2495 | } | |
2496 | ||
a8170e5e | 2497 | uint32_t lduw_le_phys(hwaddr addr) |
1e78bcc1 AG |
2498 | { |
2499 | return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN); | |
2500 | } | |
2501 | ||
a8170e5e | 2502 | uint32_t lduw_be_phys(hwaddr addr) |
1e78bcc1 AG |
2503 | { |
2504 | return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN); | |
2505 | } | |
2506 | ||
8df1cd07 FB |
2507 | /* warning: addr must be aligned. The ram page is not masked as dirty |
2508 | and the code inside is not invalidated. It is useful if the dirty | |
2509 | bits are used to track modified PTEs */ | |
a8170e5e | 2510 | void stl_phys_notdirty(hwaddr addr, uint32_t val) |
8df1cd07 | 2511 | { |
8df1cd07 | 2512 | uint8_t *ptr; |
5c8a00ce | 2513 | MemoryRegion *mr; |
149f54b5 PB |
2514 | hwaddr l = 4; |
2515 | hwaddr addr1; | |
8df1cd07 | 2516 | |
5c8a00ce PB |
2517 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2518 | true); | |
2519 | if (l < 4 || !memory_access_is_direct(mr, true)) { | |
2520 | io_mem_write(mr, addr1, val, 4); | |
8df1cd07 | 2521 | } else { |
5c8a00ce | 2522 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
5579c7f3 | 2523 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 2524 | stl_p(ptr, val); |
74576198 AL |
2525 | |
2526 | if (unlikely(in_migration)) { | |
2527 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
2528 | /* invalidate code */ | |
2529 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
2530 | /* set dirty bit */ | |
52159192 JQ |
2531 | cpu_physical_memory_set_dirty_flag(addr1, |
2532 | DIRTY_MEMORY_MIGRATION); | |
2533 | cpu_physical_memory_set_dirty_flag(addr1, DIRTY_MEMORY_VGA); | |
74576198 AL |
2534 | } |
2535 | } | |
8df1cd07 FB |
2536 | } |
2537 | } | |
2538 | ||
2539 | /* warning: addr must be aligned */ | |
a8170e5e | 2540 | static inline void stl_phys_internal(hwaddr addr, uint32_t val, |
1e78bcc1 | 2541 | enum device_endian endian) |
8df1cd07 | 2542 | { |
8df1cd07 | 2543 | uint8_t *ptr; |
5c8a00ce | 2544 | MemoryRegion *mr; |
149f54b5 PB |
2545 | hwaddr l = 4; |
2546 | hwaddr addr1; | |
8df1cd07 | 2547 | |
5c8a00ce PB |
2548 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2549 | true); | |
2550 | if (l < 4 || !memory_access_is_direct(mr, true)) { | |
1e78bcc1 AG |
2551 | #if defined(TARGET_WORDS_BIGENDIAN) |
2552 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2553 | val = bswap32(val); | |
2554 | } | |
2555 | #else | |
2556 | if (endian == DEVICE_BIG_ENDIAN) { | |
2557 | val = bswap32(val); | |
2558 | } | |
2559 | #endif | |
5c8a00ce | 2560 | io_mem_write(mr, addr1, val, 4); |
8df1cd07 | 2561 | } else { |
8df1cd07 | 2562 | /* RAM case */ |
5c8a00ce | 2563 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
5579c7f3 | 2564 | ptr = qemu_get_ram_ptr(addr1); |
1e78bcc1 AG |
2565 | switch (endian) { |
2566 | case DEVICE_LITTLE_ENDIAN: | |
2567 | stl_le_p(ptr, val); | |
2568 | break; | |
2569 | case DEVICE_BIG_ENDIAN: | |
2570 | stl_be_p(ptr, val); | |
2571 | break; | |
2572 | default: | |
2573 | stl_p(ptr, val); | |
2574 | break; | |
2575 | } | |
51d7a9eb | 2576 | invalidate_and_set_dirty(addr1, 4); |
8df1cd07 FB |
2577 | } |
2578 | } | |
2579 | ||
a8170e5e | 2580 | void stl_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2581 | { |
2582 | stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); | |
2583 | } | |
2584 | ||
a8170e5e | 2585 | void stl_le_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2586 | { |
2587 | stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); | |
2588 | } | |
2589 | ||
a8170e5e | 2590 | void stl_be_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2591 | { |
2592 | stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN); | |
2593 | } | |
2594 | ||
aab33094 | 2595 | /* XXX: optimize */ |
a8170e5e | 2596 | void stb_phys(hwaddr addr, uint32_t val) |
aab33094 FB |
2597 | { |
2598 | uint8_t v = val; | |
2599 | cpu_physical_memory_write(addr, &v, 1); | |
2600 | } | |
2601 | ||
733f0b02 | 2602 | /* warning: addr must be aligned */ |
a8170e5e | 2603 | static inline void stw_phys_internal(hwaddr addr, uint32_t val, |
1e78bcc1 | 2604 | enum device_endian endian) |
aab33094 | 2605 | { |
733f0b02 | 2606 | uint8_t *ptr; |
5c8a00ce | 2607 | MemoryRegion *mr; |
149f54b5 PB |
2608 | hwaddr l = 2; |
2609 | hwaddr addr1; | |
733f0b02 | 2610 | |
5c8a00ce PB |
2611 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2612 | true); | |
2613 | if (l < 2 || !memory_access_is_direct(mr, true)) { | |
1e78bcc1 AG |
2614 | #if defined(TARGET_WORDS_BIGENDIAN) |
2615 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2616 | val = bswap16(val); | |
2617 | } | |
2618 | #else | |
2619 | if (endian == DEVICE_BIG_ENDIAN) { | |
2620 | val = bswap16(val); | |
2621 | } | |
2622 | #endif | |
5c8a00ce | 2623 | io_mem_write(mr, addr1, val, 2); |
733f0b02 | 2624 | } else { |
733f0b02 | 2625 | /* RAM case */ |
5c8a00ce | 2626 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
733f0b02 | 2627 | ptr = qemu_get_ram_ptr(addr1); |
1e78bcc1 AG |
2628 | switch (endian) { |
2629 | case DEVICE_LITTLE_ENDIAN: | |
2630 | stw_le_p(ptr, val); | |
2631 | break; | |
2632 | case DEVICE_BIG_ENDIAN: | |
2633 | stw_be_p(ptr, val); | |
2634 | break; | |
2635 | default: | |
2636 | stw_p(ptr, val); | |
2637 | break; | |
2638 | } | |
51d7a9eb | 2639 | invalidate_and_set_dirty(addr1, 2); |
733f0b02 | 2640 | } |
aab33094 FB |
2641 | } |
2642 | ||
a8170e5e | 2643 | void stw_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2644 | { |
2645 | stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); | |
2646 | } | |
2647 | ||
a8170e5e | 2648 | void stw_le_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2649 | { |
2650 | stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); | |
2651 | } | |
2652 | ||
a8170e5e | 2653 | void stw_be_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2654 | { |
2655 | stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN); | |
2656 | } | |
2657 | ||
aab33094 | 2658 | /* XXX: optimize */ |
a8170e5e | 2659 | void stq_phys(hwaddr addr, uint64_t val) |
aab33094 FB |
2660 | { |
2661 | val = tswap64(val); | |
71d2b725 | 2662 | cpu_physical_memory_write(addr, &val, 8); |
aab33094 FB |
2663 | } |
2664 | ||
a8170e5e | 2665 | void stq_le_phys(hwaddr addr, uint64_t val) |
1e78bcc1 AG |
2666 | { |
2667 | val = cpu_to_le64(val); | |
2668 | cpu_physical_memory_write(addr, &val, 8); | |
2669 | } | |
2670 | ||
a8170e5e | 2671 | void stq_be_phys(hwaddr addr, uint64_t val) |
1e78bcc1 AG |
2672 | { |
2673 | val = cpu_to_be64(val); | |
2674 | cpu_physical_memory_write(addr, &val, 8); | |
2675 | } | |
2676 | ||
5e2972fd | 2677 | /* virtual memory access for debug (includes writing to ROM) */ |
f17ec444 | 2678 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
b448f2f3 | 2679 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
2680 | { |
2681 | int l; | |
a8170e5e | 2682 | hwaddr phys_addr; |
9b3c35e0 | 2683 | target_ulong page; |
13eb76e0 FB |
2684 | |
2685 | while (len > 0) { | |
2686 | page = addr & TARGET_PAGE_MASK; | |
f17ec444 | 2687 | phys_addr = cpu_get_phys_page_debug(cpu, page); |
13eb76e0 FB |
2688 | /* if no physical page mapped, return an error */ |
2689 | if (phys_addr == -1) | |
2690 | return -1; | |
2691 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2692 | if (l > len) | |
2693 | l = len; | |
5e2972fd | 2694 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
5e2972fd AL |
2695 | if (is_write) |
2696 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
2697 | else | |
5e2972fd | 2698 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
13eb76e0 FB |
2699 | len -= l; |
2700 | buf += l; | |
2701 | addr += l; | |
2702 | } | |
2703 | return 0; | |
2704 | } | |
a68fe89c | 2705 | #endif |
13eb76e0 | 2706 | |
8e4a424b BS |
2707 | #if !defined(CONFIG_USER_ONLY) |
2708 | ||
2709 | /* | |
2710 | * A helper function for the _utterly broken_ virtio device model to find out if | |
2711 | * it's running on a big endian machine. Don't do this at home kids! | |
2712 | */ | |
2713 | bool virtio_is_big_endian(void); | |
2714 | bool virtio_is_big_endian(void) | |
2715 | { | |
2716 | #if defined(TARGET_WORDS_BIGENDIAN) | |
2717 | return true; | |
2718 | #else | |
2719 | return false; | |
2720 | #endif | |
2721 | } | |
2722 | ||
2723 | #endif | |
2724 | ||
76f35538 | 2725 | #ifndef CONFIG_USER_ONLY |
a8170e5e | 2726 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
76f35538 | 2727 | { |
5c8a00ce | 2728 | MemoryRegion*mr; |
149f54b5 | 2729 | hwaddr l = 1; |
76f35538 | 2730 | |
5c8a00ce PB |
2731 | mr = address_space_translate(&address_space_memory, |
2732 | phys_addr, &phys_addr, &l, false); | |
76f35538 | 2733 | |
5c8a00ce PB |
2734 | return !(memory_region_is_ram(mr) || |
2735 | memory_region_is_romd(mr)); | |
76f35538 | 2736 | } |
bd2fa51f MH |
2737 | |
2738 | void qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) | |
2739 | { | |
2740 | RAMBlock *block; | |
2741 | ||
2742 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { | |
2743 | func(block->host, block->offset, block->length, opaque); | |
2744 | } | |
2745 | } | |
ec3f8c99 | 2746 | #endif |