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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
fad6cb1a | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
54936004 | 19 | */ |
67b915a5 | 20 | #include "config.h" |
d5a8f07c FB |
21 | #ifdef _WIN32 |
22 | #include <windows.h> | |
23 | #else | |
a98d49b1 | 24 | #include <sys/types.h> |
d5a8f07c FB |
25 | #include <sys/mman.h> |
26 | #endif | |
54936004 FB |
27 | #include <stdlib.h> |
28 | #include <stdio.h> | |
29 | #include <stdarg.h> | |
30 | #include <string.h> | |
31 | #include <errno.h> | |
32 | #include <unistd.h> | |
33 | #include <inttypes.h> | |
34 | ||
6180a181 FB |
35 | #include "cpu.h" |
36 | #include "exec-all.h" | |
ca10f867 | 37 | #include "qemu-common.h" |
b67d9a52 | 38 | #include "tcg.h" |
b3c7724c | 39 | #include "hw/hw.h" |
74576198 | 40 | #include "osdep.h" |
7ba1e619 | 41 | #include "kvm.h" |
53a5960a PB |
42 | #if defined(CONFIG_USER_ONLY) |
43 | #include <qemu.h> | |
44 | #endif | |
54936004 | 45 | |
fd6ce8f6 | 46 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 47 | //#define DEBUG_FLUSH |
9fa3e853 | 48 | //#define DEBUG_TLB |
67d3b957 | 49 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
50 | |
51 | /* make various TB consistency checks */ | |
5fafdf24 TS |
52 | //#define DEBUG_TB_CHECK |
53 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 54 | |
1196be37 | 55 | //#define DEBUG_IOPORT |
db7b5426 | 56 | //#define DEBUG_SUBPAGE |
1196be37 | 57 | |
99773bd4 PB |
58 | #if !defined(CONFIG_USER_ONLY) |
59 | /* TB consistency checks only implemented for usermode emulation. */ | |
60 | #undef DEBUG_TB_CHECK | |
61 | #endif | |
62 | ||
9fa3e853 FB |
63 | #define SMC_BITMAP_USE_THRESHOLD 10 |
64 | ||
108c49b8 FB |
65 | #if defined(TARGET_SPARC64) |
66 | #define TARGET_PHYS_ADDR_SPACE_BITS 41 | |
5dcb6b91 BS |
67 | #elif defined(TARGET_SPARC) |
68 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
bedb69ea JM |
69 | #elif defined(TARGET_ALPHA) |
70 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
71 | #define TARGET_VIRT_ADDR_SPACE_BITS 42 | |
108c49b8 FB |
72 | #elif defined(TARGET_PPC64) |
73 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
640f42e4 | 74 | #elif defined(TARGET_X86_64) && !defined(CONFIG_KQEMU) |
00f82b8a | 75 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 |
640f42e4 | 76 | #elif defined(TARGET_I386) && !defined(CONFIG_KQEMU) |
00f82b8a | 77 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
108c49b8 FB |
78 | #else |
79 | /* Note: for compatibility with kqemu, we use 32 bits for x86_64 */ | |
80 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
81 | #endif | |
82 | ||
bdaf78e0 | 83 | static TranslationBlock *tbs; |
26a5f13b | 84 | int code_gen_max_blocks; |
9fa3e853 | 85 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 86 | static int nb_tbs; |
eb51d102 FB |
87 | /* any access to the tbs or the page table must use this lock */ |
88 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; | |
fd6ce8f6 | 89 | |
141ac468 BS |
90 | #if defined(__arm__) || defined(__sparc_v9__) |
91 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
92 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
93 | section close to code segment. */ |
94 | #define code_gen_section \ | |
95 | __attribute__((__section__(".gen_code"))) \ | |
96 | __attribute__((aligned (32))) | |
97 | #else | |
98 | #define code_gen_section \ | |
99 | __attribute__((aligned (32))) | |
100 | #endif | |
101 | ||
102 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
103 | static uint8_t *code_gen_buffer; |
104 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 105 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 106 | static unsigned long code_gen_buffer_max_size; |
fd6ce8f6 FB |
107 | uint8_t *code_gen_ptr; |
108 | ||
e2eef170 | 109 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 110 | int phys_ram_fd; |
1ccde1cb | 111 | uint8_t *phys_ram_dirty; |
74576198 | 112 | static int in_migration; |
94a6b54f PB |
113 | |
114 | typedef struct RAMBlock { | |
115 | uint8_t *host; | |
116 | ram_addr_t offset; | |
117 | ram_addr_t length; | |
118 | struct RAMBlock *next; | |
119 | } RAMBlock; | |
120 | ||
121 | static RAMBlock *ram_blocks; | |
122 | /* TODO: When we implement (and use) ram deallocation (e.g. for hotplug) | |
ccbb4d44 | 123 | then we can no longer assume contiguous ram offsets, and external uses |
94a6b54f PB |
124 | of this variable will break. */ |
125 | ram_addr_t last_ram_offset; | |
e2eef170 | 126 | #endif |
9fa3e853 | 127 | |
6a00d601 FB |
128 | CPUState *first_cpu; |
129 | /* current CPU in the current thread. It is only valid inside | |
130 | cpu_exec() */ | |
5fafdf24 | 131 | CPUState *cpu_single_env; |
2e70f6ef | 132 | /* 0 = Do not count executed instructions. |
bf20dc07 | 133 | 1 = Precise instruction counting. |
2e70f6ef PB |
134 | 2 = Adaptive rate instruction counting. */ |
135 | int use_icount = 0; | |
136 | /* Current instruction counter. While executing translated code this may | |
137 | include some instructions that have not yet been executed. */ | |
138 | int64_t qemu_icount; | |
6a00d601 | 139 | |
54936004 | 140 | typedef struct PageDesc { |
92e873b9 | 141 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 142 | TranslationBlock *first_tb; |
9fa3e853 FB |
143 | /* in order to optimize self modifying code, we count the number |
144 | of lookups we do to a given page to use a bitmap */ | |
145 | unsigned int code_write_count; | |
146 | uint8_t *code_bitmap; | |
147 | #if defined(CONFIG_USER_ONLY) | |
148 | unsigned long flags; | |
149 | #endif | |
54936004 FB |
150 | } PageDesc; |
151 | ||
92e873b9 | 152 | typedef struct PhysPageDesc { |
0f459d16 | 153 | /* offset in host memory of the page + io_index in the low bits */ |
00f82b8a | 154 | ram_addr_t phys_offset; |
8da3ff18 | 155 | ram_addr_t region_offset; |
92e873b9 FB |
156 | } PhysPageDesc; |
157 | ||
54936004 | 158 | #define L2_BITS 10 |
bedb69ea JM |
159 | #if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS) |
160 | /* XXX: this is a temporary hack for alpha target. | |
161 | * In the future, this is to be replaced by a multi-level table | |
162 | * to actually be able to handle the complete 64 bits address space. | |
163 | */ | |
164 | #define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS) | |
165 | #else | |
03875444 | 166 | #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS) |
bedb69ea | 167 | #endif |
54936004 FB |
168 | |
169 | #define L1_SIZE (1 << L1_BITS) | |
170 | #define L2_SIZE (1 << L2_BITS) | |
171 | ||
83fb7adf FB |
172 | unsigned long qemu_real_host_page_size; |
173 | unsigned long qemu_host_page_bits; | |
174 | unsigned long qemu_host_page_size; | |
175 | unsigned long qemu_host_page_mask; | |
54936004 | 176 | |
92e873b9 | 177 | /* XXX: for system emulation, it could just be an array */ |
54936004 | 178 | static PageDesc *l1_map[L1_SIZE]; |
bdaf78e0 | 179 | static PhysPageDesc **l1_phys_map; |
54936004 | 180 | |
e2eef170 PB |
181 | #if !defined(CONFIG_USER_ONLY) |
182 | static void io_mem_init(void); | |
183 | ||
33417e70 | 184 | /* io memory support */ |
33417e70 FB |
185 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
186 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 187 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
511d2b14 | 188 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
6658ffb8 PB |
189 | static int io_mem_watch; |
190 | #endif | |
33417e70 | 191 | |
34865134 | 192 | /* log support */ |
d9b630fd | 193 | static const char *logfilename = "/tmp/qemu.log"; |
34865134 FB |
194 | FILE *logfile; |
195 | int loglevel; | |
e735b91c | 196 | static int log_append = 0; |
34865134 | 197 | |
e3db7226 FB |
198 | /* statistics */ |
199 | static int tlb_flush_count; | |
200 | static int tb_flush_count; | |
201 | static int tb_phys_invalidate_count; | |
202 | ||
db7b5426 BS |
203 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
204 | typedef struct subpage_t { | |
205 | target_phys_addr_t base; | |
3ee89922 BS |
206 | CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4]; |
207 | CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4]; | |
208 | void *opaque[TARGET_PAGE_SIZE][2][4]; | |
8da3ff18 | 209 | ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4]; |
db7b5426 BS |
210 | } subpage_t; |
211 | ||
7cb69cae FB |
212 | #ifdef _WIN32 |
213 | static void map_exec(void *addr, long size) | |
214 | { | |
215 | DWORD old_protect; | |
216 | VirtualProtect(addr, size, | |
217 | PAGE_EXECUTE_READWRITE, &old_protect); | |
218 | ||
219 | } | |
220 | #else | |
221 | static void map_exec(void *addr, long size) | |
222 | { | |
4369415f | 223 | unsigned long start, end, page_size; |
7cb69cae | 224 | |
4369415f | 225 | page_size = getpagesize(); |
7cb69cae | 226 | start = (unsigned long)addr; |
4369415f | 227 | start &= ~(page_size - 1); |
7cb69cae FB |
228 | |
229 | end = (unsigned long)addr + size; | |
4369415f FB |
230 | end += page_size - 1; |
231 | end &= ~(page_size - 1); | |
7cb69cae FB |
232 | |
233 | mprotect((void *)start, end - start, | |
234 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
235 | } | |
236 | #endif | |
237 | ||
b346ff46 | 238 | static void page_init(void) |
54936004 | 239 | { |
83fb7adf | 240 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 241 | TARGET_PAGE_SIZE */ |
c2b48b69 AL |
242 | #ifdef _WIN32 |
243 | { | |
244 | SYSTEM_INFO system_info; | |
245 | ||
246 | GetSystemInfo(&system_info); | |
247 | qemu_real_host_page_size = system_info.dwPageSize; | |
248 | } | |
249 | #else | |
250 | qemu_real_host_page_size = getpagesize(); | |
251 | #endif | |
83fb7adf FB |
252 | if (qemu_host_page_size == 0) |
253 | qemu_host_page_size = qemu_real_host_page_size; | |
254 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
255 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
256 | qemu_host_page_bits = 0; | |
257 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
258 | qemu_host_page_bits++; | |
259 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
108c49b8 FB |
260 | l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *)); |
261 | memset(l1_phys_map, 0, L1_SIZE * sizeof(void *)); | |
50a9569b AZ |
262 | |
263 | #if !defined(_WIN32) && defined(CONFIG_USER_ONLY) | |
264 | { | |
265 | long long startaddr, endaddr; | |
266 | FILE *f; | |
267 | int n; | |
268 | ||
c8a706fe | 269 | mmap_lock(); |
0776590d | 270 | last_brk = (unsigned long)sbrk(0); |
50a9569b AZ |
271 | f = fopen("/proc/self/maps", "r"); |
272 | if (f) { | |
273 | do { | |
274 | n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr); | |
275 | if (n == 2) { | |
e0b8d65a BS |
276 | startaddr = MIN(startaddr, |
277 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
278 | endaddr = MIN(endaddr, | |
279 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
b5fc909e | 280 | page_set_flags(startaddr & TARGET_PAGE_MASK, |
50a9569b AZ |
281 | TARGET_PAGE_ALIGN(endaddr), |
282 | PAGE_RESERVED); | |
283 | } | |
284 | } while (!feof(f)); | |
285 | fclose(f); | |
286 | } | |
c8a706fe | 287 | mmap_unlock(); |
50a9569b AZ |
288 | } |
289 | #endif | |
54936004 FB |
290 | } |
291 | ||
434929bf | 292 | static inline PageDesc **page_l1_map(target_ulong index) |
54936004 | 293 | { |
17e2377a PB |
294 | #if TARGET_LONG_BITS > 32 |
295 | /* Host memory outside guest VM. For 32-bit targets we have already | |
296 | excluded high addresses. */ | |
d8173e0f | 297 | if (index > ((target_ulong)L2_SIZE * L1_SIZE)) |
17e2377a PB |
298 | return NULL; |
299 | #endif | |
434929bf AL |
300 | return &l1_map[index >> L2_BITS]; |
301 | } | |
302 | ||
303 | static inline PageDesc *page_find_alloc(target_ulong index) | |
304 | { | |
305 | PageDesc **lp, *p; | |
306 | lp = page_l1_map(index); | |
307 | if (!lp) | |
308 | return NULL; | |
309 | ||
54936004 FB |
310 | p = *lp; |
311 | if (!p) { | |
312 | /* allocate if not found */ | |
17e2377a | 313 | #if defined(CONFIG_USER_ONLY) |
17e2377a PB |
314 | size_t len = sizeof(PageDesc) * L2_SIZE; |
315 | /* Don't use qemu_malloc because it may recurse. */ | |
316 | p = mmap(0, len, PROT_READ | PROT_WRITE, | |
317 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); | |
54936004 | 318 | *lp = p; |
fb1c2cd7 AJ |
319 | if (h2g_valid(p)) { |
320 | unsigned long addr = h2g(p); | |
17e2377a PB |
321 | page_set_flags(addr & TARGET_PAGE_MASK, |
322 | TARGET_PAGE_ALIGN(addr + len), | |
323 | PAGE_RESERVED); | |
324 | } | |
325 | #else | |
326 | p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE); | |
327 | *lp = p; | |
328 | #endif | |
54936004 FB |
329 | } |
330 | return p + (index & (L2_SIZE - 1)); | |
331 | } | |
332 | ||
00f82b8a | 333 | static inline PageDesc *page_find(target_ulong index) |
54936004 | 334 | { |
434929bf AL |
335 | PageDesc **lp, *p; |
336 | lp = page_l1_map(index); | |
337 | if (!lp) | |
338 | return NULL; | |
54936004 | 339 | |
434929bf | 340 | p = *lp; |
54936004 FB |
341 | if (!p) |
342 | return 0; | |
fd6ce8f6 FB |
343 | return p + (index & (L2_SIZE - 1)); |
344 | } | |
345 | ||
108c49b8 | 346 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 347 | { |
108c49b8 | 348 | void **lp, **p; |
e3f4e2a4 | 349 | PhysPageDesc *pd; |
92e873b9 | 350 | |
108c49b8 FB |
351 | p = (void **)l1_phys_map; |
352 | #if TARGET_PHYS_ADDR_SPACE_BITS > 32 | |
353 | ||
354 | #if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS) | |
355 | #error unsupported TARGET_PHYS_ADDR_SPACE_BITS | |
356 | #endif | |
357 | lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1)); | |
92e873b9 FB |
358 | p = *lp; |
359 | if (!p) { | |
360 | /* allocate if not found */ | |
108c49b8 FB |
361 | if (!alloc) |
362 | return NULL; | |
363 | p = qemu_vmalloc(sizeof(void *) * L1_SIZE); | |
364 | memset(p, 0, sizeof(void *) * L1_SIZE); | |
365 | *lp = p; | |
366 | } | |
367 | #endif | |
368 | lp = p + ((index >> L2_BITS) & (L1_SIZE - 1)); | |
e3f4e2a4 PB |
369 | pd = *lp; |
370 | if (!pd) { | |
371 | int i; | |
108c49b8 FB |
372 | /* allocate if not found */ |
373 | if (!alloc) | |
374 | return NULL; | |
e3f4e2a4 PB |
375 | pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE); |
376 | *lp = pd; | |
67c4d23c | 377 | for (i = 0; i < L2_SIZE; i++) { |
e3f4e2a4 | 378 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
67c4d23c PB |
379 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; |
380 | } | |
92e873b9 | 381 | } |
e3f4e2a4 | 382 | return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1)); |
92e873b9 FB |
383 | } |
384 | ||
108c49b8 | 385 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 386 | { |
108c49b8 | 387 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
388 | } |
389 | ||
9fa3e853 | 390 | #if !defined(CONFIG_USER_ONLY) |
6a00d601 | 391 | static void tlb_protect_code(ram_addr_t ram_addr); |
5fafdf24 | 392 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 393 | target_ulong vaddr); |
c8a706fe PB |
394 | #define mmap_lock() do { } while(0) |
395 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 396 | #endif |
fd6ce8f6 | 397 | |
4369415f FB |
398 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
399 | ||
400 | #if defined(CONFIG_USER_ONLY) | |
ccbb4d44 | 401 | /* Currently it is not recommended to allocate big chunks of data in |
4369415f FB |
402 | user mode. It will change when a dedicated libc will be used */ |
403 | #define USE_STATIC_CODE_GEN_BUFFER | |
404 | #endif | |
405 | ||
406 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
407 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]; | |
408 | #endif | |
409 | ||
8fcd3692 | 410 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 411 | { |
4369415f FB |
412 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
413 | code_gen_buffer = static_code_gen_buffer; | |
414 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
415 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
416 | #else | |
26a5f13b FB |
417 | code_gen_buffer_size = tb_size; |
418 | if (code_gen_buffer_size == 0) { | |
4369415f FB |
419 | #if defined(CONFIG_USER_ONLY) |
420 | /* in user mode, phys_ram_size is not meaningful */ | |
421 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
422 | #else | |
ccbb4d44 | 423 | /* XXX: needs adjustments */ |
94a6b54f | 424 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
4369415f | 425 | #endif |
26a5f13b FB |
426 | } |
427 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
428 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
429 | /* The code gen buffer location may have constraints depending on | |
430 | the host cpu and OS */ | |
431 | #if defined(__linux__) | |
432 | { | |
433 | int flags; | |
141ac468 BS |
434 | void *start = NULL; |
435 | ||
26a5f13b FB |
436 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
437 | #if defined(__x86_64__) | |
438 | flags |= MAP_32BIT; | |
439 | /* Cannot map more than that */ | |
440 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
441 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
442 | #elif defined(__sparc_v9__) |
443 | // Map the buffer below 2G, so we can use direct calls and branches | |
444 | flags |= MAP_FIXED; | |
445 | start = (void *) 0x60000000UL; | |
446 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
447 | code_gen_buffer_size = (512 * 1024 * 1024); | |
1cb0661e | 448 | #elif defined(__arm__) |
63d41246 | 449 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
1cb0661e AZ |
450 | flags |= MAP_FIXED; |
451 | start = (void *) 0x01000000UL; | |
452 | if (code_gen_buffer_size > 16 * 1024 * 1024) | |
453 | code_gen_buffer_size = 16 * 1024 * 1024; | |
26a5f13b | 454 | #endif |
141ac468 BS |
455 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
456 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
457 | flags, -1, 0); |
458 | if (code_gen_buffer == MAP_FAILED) { | |
459 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
460 | exit(1); | |
461 | } | |
462 | } | |
c5e97233 | 463 | #elif defined(__FreeBSD__) || defined(__DragonFly__) |
06e67a82 AL |
464 | { |
465 | int flags; | |
466 | void *addr = NULL; | |
467 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
468 | #if defined(__x86_64__) | |
469 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
470 | * 0x40000000 is free */ | |
471 | flags |= MAP_FIXED; | |
472 | addr = (void *)0x40000000; | |
473 | /* Cannot map more than that */ | |
474 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
475 | code_gen_buffer_size = (800 * 1024 * 1024); | |
476 | #endif | |
477 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
478 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
479 | flags, -1, 0); | |
480 | if (code_gen_buffer == MAP_FAILED) { | |
481 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
482 | exit(1); | |
483 | } | |
484 | } | |
26a5f13b FB |
485 | #else |
486 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
26a5f13b FB |
487 | map_exec(code_gen_buffer, code_gen_buffer_size); |
488 | #endif | |
4369415f | 489 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b FB |
490 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
491 | code_gen_buffer_max_size = code_gen_buffer_size - | |
492 | code_gen_max_block_size(); | |
493 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; | |
494 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
495 | } | |
496 | ||
497 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
498 | (in bytes) allocated to the translation buffer. Zero means default | |
499 | size. */ | |
500 | void cpu_exec_init_all(unsigned long tb_size) | |
501 | { | |
26a5f13b FB |
502 | cpu_gen_init(); |
503 | code_gen_alloc(tb_size); | |
504 | code_gen_ptr = code_gen_buffer; | |
4369415f | 505 | page_init(); |
e2eef170 | 506 | #if !defined(CONFIG_USER_ONLY) |
26a5f13b | 507 | io_mem_init(); |
e2eef170 | 508 | #endif |
26a5f13b FB |
509 | } |
510 | ||
9656f324 PB |
511 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
512 | ||
513 | #define CPU_COMMON_SAVE_VERSION 1 | |
514 | ||
515 | static void cpu_common_save(QEMUFile *f, void *opaque) | |
516 | { | |
517 | CPUState *env = opaque; | |
518 | ||
b0a46a33 JK |
519 | cpu_synchronize_state(env, 0); |
520 | ||
9656f324 PB |
521 | qemu_put_be32s(f, &env->halted); |
522 | qemu_put_be32s(f, &env->interrupt_request); | |
523 | } | |
524 | ||
525 | static int cpu_common_load(QEMUFile *f, void *opaque, int version_id) | |
526 | { | |
527 | CPUState *env = opaque; | |
528 | ||
529 | if (version_id != CPU_COMMON_SAVE_VERSION) | |
530 | return -EINVAL; | |
531 | ||
532 | qemu_get_be32s(f, &env->halted); | |
75f482ae | 533 | qemu_get_be32s(f, &env->interrupt_request); |
3098dba0 AJ |
534 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
535 | version_id is increased. */ | |
536 | env->interrupt_request &= ~0x01; | |
9656f324 | 537 | tlb_flush(env, 1); |
b0a46a33 | 538 | cpu_synchronize_state(env, 1); |
9656f324 PB |
539 | |
540 | return 0; | |
541 | } | |
542 | #endif | |
543 | ||
950f1472 GC |
544 | CPUState *qemu_get_cpu(int cpu) |
545 | { | |
546 | CPUState *env = first_cpu; | |
547 | ||
548 | while (env) { | |
549 | if (env->cpu_index == cpu) | |
550 | break; | |
551 | env = env->next_cpu; | |
552 | } | |
553 | ||
554 | return env; | |
555 | } | |
556 | ||
6a00d601 | 557 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 558 | { |
6a00d601 FB |
559 | CPUState **penv; |
560 | int cpu_index; | |
561 | ||
c2764719 PB |
562 | #if defined(CONFIG_USER_ONLY) |
563 | cpu_list_lock(); | |
564 | #endif | |
6a00d601 FB |
565 | env->next_cpu = NULL; |
566 | penv = &first_cpu; | |
567 | cpu_index = 0; | |
568 | while (*penv != NULL) { | |
1e9fa730 | 569 | penv = &(*penv)->next_cpu; |
6a00d601 FB |
570 | cpu_index++; |
571 | } | |
572 | env->cpu_index = cpu_index; | |
268a362c | 573 | env->numa_node = 0; |
c0ce998e AL |
574 | TAILQ_INIT(&env->breakpoints); |
575 | TAILQ_INIT(&env->watchpoints); | |
6a00d601 | 576 | *penv = env; |
c2764719 PB |
577 | #if defined(CONFIG_USER_ONLY) |
578 | cpu_list_unlock(); | |
579 | #endif | |
b3c7724c | 580 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
9656f324 PB |
581 | register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION, |
582 | cpu_common_save, cpu_common_load, env); | |
b3c7724c PB |
583 | register_savevm("cpu", cpu_index, CPU_SAVE_VERSION, |
584 | cpu_save, cpu_load, env); | |
585 | #endif | |
fd6ce8f6 FB |
586 | } |
587 | ||
9fa3e853 FB |
588 | static inline void invalidate_page_bitmap(PageDesc *p) |
589 | { | |
590 | if (p->code_bitmap) { | |
59817ccb | 591 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
592 | p->code_bitmap = NULL; |
593 | } | |
594 | p->code_write_count = 0; | |
595 | } | |
596 | ||
fd6ce8f6 FB |
597 | /* set to NULL all the 'first_tb' fields in all PageDescs */ |
598 | static void page_flush_tb(void) | |
599 | { | |
600 | int i, j; | |
601 | PageDesc *p; | |
602 | ||
603 | for(i = 0; i < L1_SIZE; i++) { | |
604 | p = l1_map[i]; | |
605 | if (p) { | |
9fa3e853 FB |
606 | for(j = 0; j < L2_SIZE; j++) { |
607 | p->first_tb = NULL; | |
608 | invalidate_page_bitmap(p); | |
609 | p++; | |
610 | } | |
fd6ce8f6 FB |
611 | } |
612 | } | |
613 | } | |
614 | ||
615 | /* flush all the translation blocks */ | |
d4e8164f | 616 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 617 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 618 | { |
6a00d601 | 619 | CPUState *env; |
0124311e | 620 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
621 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
622 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
623 | nb_tbs, nb_tbs > 0 ? | |
624 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 625 | #endif |
26a5f13b | 626 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
627 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
628 | ||
fd6ce8f6 | 629 | nb_tbs = 0; |
3b46e624 | 630 | |
6a00d601 FB |
631 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
632 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
633 | } | |
9fa3e853 | 634 | |
8a8a608f | 635 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 636 | page_flush_tb(); |
9fa3e853 | 637 | |
fd6ce8f6 | 638 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
639 | /* XXX: flush processor icache at this point if cache flush is |
640 | expensive */ | |
e3db7226 | 641 | tb_flush_count++; |
fd6ce8f6 FB |
642 | } |
643 | ||
644 | #ifdef DEBUG_TB_CHECK | |
645 | ||
bc98a7ef | 646 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
647 | { |
648 | TranslationBlock *tb; | |
649 | int i; | |
650 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
651 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
652 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
653 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
654 | address >= tb->pc + tb->size)) { | |
655 | printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n", | |
99773bd4 | 656 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
657 | } |
658 | } | |
659 | } | |
660 | } | |
661 | ||
662 | /* verify that all the pages have correct rights for code */ | |
663 | static void tb_page_check(void) | |
664 | { | |
665 | TranslationBlock *tb; | |
666 | int i, flags1, flags2; | |
3b46e624 | 667 | |
99773bd4 PB |
668 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
669 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
670 | flags1 = page_get_flags(tb->pc); |
671 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
672 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
673 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 674 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
675 | } |
676 | } | |
677 | } | |
678 | } | |
679 | ||
bdaf78e0 | 680 | static void tb_jmp_check(TranslationBlock *tb) |
d4e8164f FB |
681 | { |
682 | TranslationBlock *tb1; | |
683 | unsigned int n1; | |
684 | ||
685 | /* suppress any remaining jumps to this TB */ | |
686 | tb1 = tb->jmp_first; | |
687 | for(;;) { | |
688 | n1 = (long)tb1 & 3; | |
689 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
690 | if (n1 == 2) | |
691 | break; | |
692 | tb1 = tb1->jmp_next[n1]; | |
693 | } | |
694 | /* check end of list */ | |
695 | if (tb1 != tb) { | |
696 | printf("ERROR: jmp_list from 0x%08lx\n", (long)tb); | |
697 | } | |
698 | } | |
699 | ||
fd6ce8f6 FB |
700 | #endif |
701 | ||
702 | /* invalidate one TB */ | |
703 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
704 | int next_offset) | |
705 | { | |
706 | TranslationBlock *tb1; | |
707 | for(;;) { | |
708 | tb1 = *ptb; | |
709 | if (tb1 == tb) { | |
710 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
711 | break; | |
712 | } | |
713 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
714 | } | |
715 | } | |
716 | ||
9fa3e853 FB |
717 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
718 | { | |
719 | TranslationBlock *tb1; | |
720 | unsigned int n1; | |
721 | ||
722 | for(;;) { | |
723 | tb1 = *ptb; | |
724 | n1 = (long)tb1 & 3; | |
725 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
726 | if (tb1 == tb) { | |
727 | *ptb = tb1->page_next[n1]; | |
728 | break; | |
729 | } | |
730 | ptb = &tb1->page_next[n1]; | |
731 | } | |
732 | } | |
733 | ||
d4e8164f FB |
734 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
735 | { | |
736 | TranslationBlock *tb1, **ptb; | |
737 | unsigned int n1; | |
738 | ||
739 | ptb = &tb->jmp_next[n]; | |
740 | tb1 = *ptb; | |
741 | if (tb1) { | |
742 | /* find tb(n) in circular list */ | |
743 | for(;;) { | |
744 | tb1 = *ptb; | |
745 | n1 = (long)tb1 & 3; | |
746 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
747 | if (n1 == n && tb1 == tb) | |
748 | break; | |
749 | if (n1 == 2) { | |
750 | ptb = &tb1->jmp_first; | |
751 | } else { | |
752 | ptb = &tb1->jmp_next[n1]; | |
753 | } | |
754 | } | |
755 | /* now we can suppress tb(n) from the list */ | |
756 | *ptb = tb->jmp_next[n]; | |
757 | ||
758 | tb->jmp_next[n] = NULL; | |
759 | } | |
760 | } | |
761 | ||
762 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
763 | another TB */ | |
764 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
765 | { | |
766 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
767 | } | |
768 | ||
2e70f6ef | 769 | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr) |
fd6ce8f6 | 770 | { |
6a00d601 | 771 | CPUState *env; |
8a40a180 | 772 | PageDesc *p; |
d4e8164f | 773 | unsigned int h, n1; |
00f82b8a | 774 | target_phys_addr_t phys_pc; |
8a40a180 | 775 | TranslationBlock *tb1, *tb2; |
3b46e624 | 776 | |
8a40a180 FB |
777 | /* remove the TB from the hash list */ |
778 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
779 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 780 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
781 | offsetof(TranslationBlock, phys_hash_next)); |
782 | ||
783 | /* remove the TB from the page list */ | |
784 | if (tb->page_addr[0] != page_addr) { | |
785 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
786 | tb_page_remove(&p->first_tb, tb); | |
787 | invalidate_page_bitmap(p); | |
788 | } | |
789 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
790 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
791 | tb_page_remove(&p->first_tb, tb); | |
792 | invalidate_page_bitmap(p); | |
793 | } | |
794 | ||
36bdbe54 | 795 | tb_invalidated_flag = 1; |
59817ccb | 796 | |
fd6ce8f6 | 797 | /* remove the TB from the hash list */ |
8a40a180 | 798 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
799 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
800 | if (env->tb_jmp_cache[h] == tb) | |
801 | env->tb_jmp_cache[h] = NULL; | |
802 | } | |
d4e8164f FB |
803 | |
804 | /* suppress this TB from the two jump lists */ | |
805 | tb_jmp_remove(tb, 0); | |
806 | tb_jmp_remove(tb, 1); | |
807 | ||
808 | /* suppress any remaining jumps to this TB */ | |
809 | tb1 = tb->jmp_first; | |
810 | for(;;) { | |
811 | n1 = (long)tb1 & 3; | |
812 | if (n1 == 2) | |
813 | break; | |
814 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
815 | tb2 = tb1->jmp_next[n1]; | |
816 | tb_reset_jump(tb1, n1); | |
817 | tb1->jmp_next[n1] = NULL; | |
818 | tb1 = tb2; | |
819 | } | |
820 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 821 | |
e3db7226 | 822 | tb_phys_invalidate_count++; |
9fa3e853 FB |
823 | } |
824 | ||
825 | static inline void set_bits(uint8_t *tab, int start, int len) | |
826 | { | |
827 | int end, mask, end1; | |
828 | ||
829 | end = start + len; | |
830 | tab += start >> 3; | |
831 | mask = 0xff << (start & 7); | |
832 | if ((start & ~7) == (end & ~7)) { | |
833 | if (start < end) { | |
834 | mask &= ~(0xff << (end & 7)); | |
835 | *tab |= mask; | |
836 | } | |
837 | } else { | |
838 | *tab++ |= mask; | |
839 | start = (start + 8) & ~7; | |
840 | end1 = end & ~7; | |
841 | while (start < end1) { | |
842 | *tab++ = 0xff; | |
843 | start += 8; | |
844 | } | |
845 | if (start < end) { | |
846 | mask = ~(0xff << (end & 7)); | |
847 | *tab |= mask; | |
848 | } | |
849 | } | |
850 | } | |
851 | ||
852 | static void build_page_bitmap(PageDesc *p) | |
853 | { | |
854 | int n, tb_start, tb_end; | |
855 | TranslationBlock *tb; | |
3b46e624 | 856 | |
b2a7081a | 857 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
858 | |
859 | tb = p->first_tb; | |
860 | while (tb != NULL) { | |
861 | n = (long)tb & 3; | |
862 | tb = (TranslationBlock *)((long)tb & ~3); | |
863 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
864 | if (n == 0) { | |
865 | /* NOTE: tb_end may be after the end of the page, but | |
866 | it is not a problem */ | |
867 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
868 | tb_end = tb_start + tb->size; | |
869 | if (tb_end > TARGET_PAGE_SIZE) | |
870 | tb_end = TARGET_PAGE_SIZE; | |
871 | } else { | |
872 | tb_start = 0; | |
873 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
874 | } | |
875 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
876 | tb = tb->page_next[n]; | |
877 | } | |
878 | } | |
879 | ||
2e70f6ef PB |
880 | TranslationBlock *tb_gen_code(CPUState *env, |
881 | target_ulong pc, target_ulong cs_base, | |
882 | int flags, int cflags) | |
d720b93d FB |
883 | { |
884 | TranslationBlock *tb; | |
885 | uint8_t *tc_ptr; | |
886 | target_ulong phys_pc, phys_page2, virt_page2; | |
887 | int code_gen_size; | |
888 | ||
c27004ec FB |
889 | phys_pc = get_phys_addr_code(env, pc); |
890 | tb = tb_alloc(pc); | |
d720b93d FB |
891 | if (!tb) { |
892 | /* flush must be done */ | |
893 | tb_flush(env); | |
894 | /* cannot fail at this point */ | |
c27004ec | 895 | tb = tb_alloc(pc); |
2e70f6ef PB |
896 | /* Don't forget to invalidate previous TB info. */ |
897 | tb_invalidated_flag = 1; | |
d720b93d FB |
898 | } |
899 | tc_ptr = code_gen_ptr; | |
900 | tb->tc_ptr = tc_ptr; | |
901 | tb->cs_base = cs_base; | |
902 | tb->flags = flags; | |
903 | tb->cflags = cflags; | |
d07bde88 | 904 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 905 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 906 | |
d720b93d | 907 | /* check next page if needed */ |
c27004ec | 908 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 909 | phys_page2 = -1; |
c27004ec | 910 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
d720b93d FB |
911 | phys_page2 = get_phys_addr_code(env, virt_page2); |
912 | } | |
913 | tb_link_phys(tb, phys_pc, phys_page2); | |
2e70f6ef | 914 | return tb; |
d720b93d | 915 | } |
3b46e624 | 916 | |
9fa3e853 FB |
917 | /* invalidate all TBs which intersect with the target physical page |
918 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
919 | the same physical page. 'is_cpu_write_access' should be true if called |
920 | from a real cpu write access: the virtual CPU will exit the current | |
921 | TB if code is modified inside this TB. */ | |
00f82b8a | 922 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
d720b93d FB |
923 | int is_cpu_write_access) |
924 | { | |
6b917547 | 925 | TranslationBlock *tb, *tb_next, *saved_tb; |
d720b93d | 926 | CPUState *env = cpu_single_env; |
9fa3e853 | 927 | target_ulong tb_start, tb_end; |
6b917547 AL |
928 | PageDesc *p; |
929 | int n; | |
930 | #ifdef TARGET_HAS_PRECISE_SMC | |
931 | int current_tb_not_found = is_cpu_write_access; | |
932 | TranslationBlock *current_tb = NULL; | |
933 | int current_tb_modified = 0; | |
934 | target_ulong current_pc = 0; | |
935 | target_ulong current_cs_base = 0; | |
936 | int current_flags = 0; | |
937 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
938 | |
939 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 940 | if (!p) |
9fa3e853 | 941 | return; |
5fafdf24 | 942 | if (!p->code_bitmap && |
d720b93d FB |
943 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
944 | is_cpu_write_access) { | |
9fa3e853 FB |
945 | /* build code bitmap */ |
946 | build_page_bitmap(p); | |
947 | } | |
948 | ||
949 | /* we remove all the TBs in the range [start, end[ */ | |
950 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
951 | tb = p->first_tb; | |
952 | while (tb != NULL) { | |
953 | n = (long)tb & 3; | |
954 | tb = (TranslationBlock *)((long)tb & ~3); | |
955 | tb_next = tb->page_next[n]; | |
956 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
957 | if (n == 0) { | |
958 | /* NOTE: tb_end may be after the end of the page, but | |
959 | it is not a problem */ | |
960 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
961 | tb_end = tb_start + tb->size; | |
962 | } else { | |
963 | tb_start = tb->page_addr[1]; | |
964 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
965 | } | |
966 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
967 | #ifdef TARGET_HAS_PRECISE_SMC |
968 | if (current_tb_not_found) { | |
969 | current_tb_not_found = 0; | |
970 | current_tb = NULL; | |
2e70f6ef | 971 | if (env->mem_io_pc) { |
d720b93d | 972 | /* now we have a real cpu fault */ |
2e70f6ef | 973 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
974 | } |
975 | } | |
976 | if (current_tb == tb && | |
2e70f6ef | 977 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
978 | /* If we are modifying the current TB, we must stop |
979 | its execution. We could be more precise by checking | |
980 | that the modification is after the current PC, but it | |
981 | would require a specialized function to partially | |
982 | restore the CPU state */ | |
3b46e624 | 983 | |
d720b93d | 984 | current_tb_modified = 1; |
5fafdf24 | 985 | cpu_restore_state(current_tb, env, |
2e70f6ef | 986 | env->mem_io_pc, NULL); |
6b917547 AL |
987 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
988 | ¤t_flags); | |
d720b93d FB |
989 | } |
990 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
991 | /* we need to do that to handle the case where a signal |
992 | occurs while doing tb_phys_invalidate() */ | |
993 | saved_tb = NULL; | |
994 | if (env) { | |
995 | saved_tb = env->current_tb; | |
996 | env->current_tb = NULL; | |
997 | } | |
9fa3e853 | 998 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
999 | if (env) { |
1000 | env->current_tb = saved_tb; | |
1001 | if (env->interrupt_request && env->current_tb) | |
1002 | cpu_interrupt(env, env->interrupt_request); | |
1003 | } | |
9fa3e853 FB |
1004 | } |
1005 | tb = tb_next; | |
1006 | } | |
1007 | #if !defined(CONFIG_USER_ONLY) | |
1008 | /* if no code remaining, no need to continue to use slow writes */ | |
1009 | if (!p->first_tb) { | |
1010 | invalidate_page_bitmap(p); | |
d720b93d | 1011 | if (is_cpu_write_access) { |
2e70f6ef | 1012 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
1013 | } |
1014 | } | |
1015 | #endif | |
1016 | #ifdef TARGET_HAS_PRECISE_SMC | |
1017 | if (current_tb_modified) { | |
1018 | /* we generate a block containing just the instruction | |
1019 | modifying the memory. It will ensure that it cannot modify | |
1020 | itself */ | |
ea1c1802 | 1021 | env->current_tb = NULL; |
2e70f6ef | 1022 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 1023 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 1024 | } |
fd6ce8f6 | 1025 | #endif |
9fa3e853 | 1026 | } |
fd6ce8f6 | 1027 | |
9fa3e853 | 1028 | /* len must be <= 8 and start must be a multiple of len */ |
00f82b8a | 1029 | static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len) |
9fa3e853 FB |
1030 | { |
1031 | PageDesc *p; | |
1032 | int offset, b; | |
59817ccb | 1033 | #if 0 |
a4193c8a | 1034 | if (1) { |
93fcfe39 AL |
1035 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
1036 | cpu_single_env->mem_io_vaddr, len, | |
1037 | cpu_single_env->eip, | |
1038 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
59817ccb FB |
1039 | } |
1040 | #endif | |
9fa3e853 | 1041 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1042 | if (!p) |
9fa3e853 FB |
1043 | return; |
1044 | if (p->code_bitmap) { | |
1045 | offset = start & ~TARGET_PAGE_MASK; | |
1046 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1047 | if (b & ((1 << len) - 1)) | |
1048 | goto do_invalidate; | |
1049 | } else { | |
1050 | do_invalidate: | |
d720b93d | 1051 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1052 | } |
1053 | } | |
1054 | ||
9fa3e853 | 1055 | #if !defined(CONFIG_SOFTMMU) |
00f82b8a | 1056 | static void tb_invalidate_phys_page(target_phys_addr_t addr, |
d720b93d | 1057 | unsigned long pc, void *puc) |
9fa3e853 | 1058 | { |
6b917547 | 1059 | TranslationBlock *tb; |
9fa3e853 | 1060 | PageDesc *p; |
6b917547 | 1061 | int n; |
d720b93d | 1062 | #ifdef TARGET_HAS_PRECISE_SMC |
6b917547 | 1063 | TranslationBlock *current_tb = NULL; |
d720b93d | 1064 | CPUState *env = cpu_single_env; |
6b917547 AL |
1065 | int current_tb_modified = 0; |
1066 | target_ulong current_pc = 0; | |
1067 | target_ulong current_cs_base = 0; | |
1068 | int current_flags = 0; | |
d720b93d | 1069 | #endif |
9fa3e853 FB |
1070 | |
1071 | addr &= TARGET_PAGE_MASK; | |
1072 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1073 | if (!p) |
9fa3e853 FB |
1074 | return; |
1075 | tb = p->first_tb; | |
d720b93d FB |
1076 | #ifdef TARGET_HAS_PRECISE_SMC |
1077 | if (tb && pc != 0) { | |
1078 | current_tb = tb_find_pc(pc); | |
1079 | } | |
1080 | #endif | |
9fa3e853 FB |
1081 | while (tb != NULL) { |
1082 | n = (long)tb & 3; | |
1083 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1084 | #ifdef TARGET_HAS_PRECISE_SMC |
1085 | if (current_tb == tb && | |
2e70f6ef | 1086 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1087 | /* If we are modifying the current TB, we must stop |
1088 | its execution. We could be more precise by checking | |
1089 | that the modification is after the current PC, but it | |
1090 | would require a specialized function to partially | |
1091 | restore the CPU state */ | |
3b46e624 | 1092 | |
d720b93d FB |
1093 | current_tb_modified = 1; |
1094 | cpu_restore_state(current_tb, env, pc, puc); | |
6b917547 AL |
1095 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1096 | ¤t_flags); | |
d720b93d FB |
1097 | } |
1098 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1099 | tb_phys_invalidate(tb, addr); |
1100 | tb = tb->page_next[n]; | |
1101 | } | |
fd6ce8f6 | 1102 | p->first_tb = NULL; |
d720b93d FB |
1103 | #ifdef TARGET_HAS_PRECISE_SMC |
1104 | if (current_tb_modified) { | |
1105 | /* we generate a block containing just the instruction | |
1106 | modifying the memory. It will ensure that it cannot modify | |
1107 | itself */ | |
ea1c1802 | 1108 | env->current_tb = NULL; |
2e70f6ef | 1109 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1110 | cpu_resume_from_signal(env, puc); |
1111 | } | |
1112 | #endif | |
fd6ce8f6 | 1113 | } |
9fa3e853 | 1114 | #endif |
fd6ce8f6 FB |
1115 | |
1116 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1117 | static inline void tb_alloc_page(TranslationBlock *tb, |
53a5960a | 1118 | unsigned int n, target_ulong page_addr) |
fd6ce8f6 FB |
1119 | { |
1120 | PageDesc *p; | |
9fa3e853 FB |
1121 | TranslationBlock *last_first_tb; |
1122 | ||
1123 | tb->page_addr[n] = page_addr; | |
3a7d929e | 1124 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
1125 | tb->page_next[n] = p->first_tb; |
1126 | last_first_tb = p->first_tb; | |
1127 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1128 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1129 | |
107db443 | 1130 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1131 | |
9fa3e853 | 1132 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1133 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1134 | target_ulong addr; |
1135 | PageDesc *p2; | |
9fa3e853 FB |
1136 | int prot; |
1137 | ||
fd6ce8f6 FB |
1138 | /* force the host page as non writable (writes will have a |
1139 | page fault + mprotect overhead) */ | |
53a5960a | 1140 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1141 | prot = 0; |
53a5960a PB |
1142 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1143 | addr += TARGET_PAGE_SIZE) { | |
1144 | ||
1145 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1146 | if (!p2) | |
1147 | continue; | |
1148 | prot |= p2->flags; | |
1149 | p2->flags &= ~PAGE_WRITE; | |
1150 | page_get_flags(addr); | |
1151 | } | |
5fafdf24 | 1152 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1153 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1154 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1155 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1156 | page_addr); |
fd6ce8f6 | 1157 | #endif |
fd6ce8f6 | 1158 | } |
9fa3e853 FB |
1159 | #else |
1160 | /* if some code is already present, then the pages are already | |
1161 | protected. So we handle the case where only the first TB is | |
1162 | allocated in a physical page */ | |
1163 | if (!last_first_tb) { | |
6a00d601 | 1164 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1165 | } |
1166 | #endif | |
d720b93d FB |
1167 | |
1168 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1169 | } |
1170 | ||
1171 | /* Allocate a new translation block. Flush the translation buffer if | |
1172 | too many translation blocks or too much generated code. */ | |
c27004ec | 1173 | TranslationBlock *tb_alloc(target_ulong pc) |
fd6ce8f6 FB |
1174 | { |
1175 | TranslationBlock *tb; | |
fd6ce8f6 | 1176 | |
26a5f13b FB |
1177 | if (nb_tbs >= code_gen_max_blocks || |
1178 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
d4e8164f | 1179 | return NULL; |
fd6ce8f6 FB |
1180 | tb = &tbs[nb_tbs++]; |
1181 | tb->pc = pc; | |
b448f2f3 | 1182 | tb->cflags = 0; |
d4e8164f FB |
1183 | return tb; |
1184 | } | |
1185 | ||
2e70f6ef PB |
1186 | void tb_free(TranslationBlock *tb) |
1187 | { | |
bf20dc07 | 1188 | /* In practice this is mostly used for single use temporary TB |
2e70f6ef PB |
1189 | Ignore the hard cases and just back up if this TB happens to |
1190 | be the last one generated. */ | |
1191 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
1192 | code_gen_ptr = tb->tc_ptr; | |
1193 | nb_tbs--; | |
1194 | } | |
1195 | } | |
1196 | ||
9fa3e853 FB |
1197 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1198 | (-1) to indicate that only one page contains the TB. */ | |
5fafdf24 | 1199 | void tb_link_phys(TranslationBlock *tb, |
9fa3e853 | 1200 | target_ulong phys_pc, target_ulong phys_page2) |
d4e8164f | 1201 | { |
9fa3e853 FB |
1202 | unsigned int h; |
1203 | TranslationBlock **ptb; | |
1204 | ||
c8a706fe PB |
1205 | /* Grab the mmap lock to stop another thread invalidating this TB |
1206 | before we are done. */ | |
1207 | mmap_lock(); | |
9fa3e853 FB |
1208 | /* add in the physical hash table */ |
1209 | h = tb_phys_hash_func(phys_pc); | |
1210 | ptb = &tb_phys_hash[h]; | |
1211 | tb->phys_hash_next = *ptb; | |
1212 | *ptb = tb; | |
fd6ce8f6 FB |
1213 | |
1214 | /* add in the page list */ | |
9fa3e853 FB |
1215 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1216 | if (phys_page2 != -1) | |
1217 | tb_alloc_page(tb, 1, phys_page2); | |
1218 | else | |
1219 | tb->page_addr[1] = -1; | |
9fa3e853 | 1220 | |
d4e8164f FB |
1221 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1222 | tb->jmp_next[0] = NULL; | |
1223 | tb->jmp_next[1] = NULL; | |
1224 | ||
1225 | /* init original jump addresses */ | |
1226 | if (tb->tb_next_offset[0] != 0xffff) | |
1227 | tb_reset_jump(tb, 0); | |
1228 | if (tb->tb_next_offset[1] != 0xffff) | |
1229 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1230 | |
1231 | #ifdef DEBUG_TB_CHECK | |
1232 | tb_page_check(); | |
1233 | #endif | |
c8a706fe | 1234 | mmap_unlock(); |
fd6ce8f6 FB |
1235 | } |
1236 | ||
9fa3e853 FB |
1237 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1238 | tb[1].tc_ptr. Return NULL if not found */ | |
1239 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1240 | { |
9fa3e853 FB |
1241 | int m_min, m_max, m; |
1242 | unsigned long v; | |
1243 | TranslationBlock *tb; | |
a513fe19 FB |
1244 | |
1245 | if (nb_tbs <= 0) | |
1246 | return NULL; | |
1247 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1248 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1249 | return NULL; | |
1250 | /* binary search (cf Knuth) */ | |
1251 | m_min = 0; | |
1252 | m_max = nb_tbs - 1; | |
1253 | while (m_min <= m_max) { | |
1254 | m = (m_min + m_max) >> 1; | |
1255 | tb = &tbs[m]; | |
1256 | v = (unsigned long)tb->tc_ptr; | |
1257 | if (v == tc_ptr) | |
1258 | return tb; | |
1259 | else if (tc_ptr < v) { | |
1260 | m_max = m - 1; | |
1261 | } else { | |
1262 | m_min = m + 1; | |
1263 | } | |
5fafdf24 | 1264 | } |
a513fe19 FB |
1265 | return &tbs[m_max]; |
1266 | } | |
7501267e | 1267 | |
ea041c0e FB |
1268 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1269 | ||
1270 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1271 | { | |
1272 | TranslationBlock *tb1, *tb_next, **ptb; | |
1273 | unsigned int n1; | |
1274 | ||
1275 | tb1 = tb->jmp_next[n]; | |
1276 | if (tb1 != NULL) { | |
1277 | /* find head of list */ | |
1278 | for(;;) { | |
1279 | n1 = (long)tb1 & 3; | |
1280 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1281 | if (n1 == 2) | |
1282 | break; | |
1283 | tb1 = tb1->jmp_next[n1]; | |
1284 | } | |
1285 | /* we are now sure now that tb jumps to tb1 */ | |
1286 | tb_next = tb1; | |
1287 | ||
1288 | /* remove tb from the jmp_first list */ | |
1289 | ptb = &tb_next->jmp_first; | |
1290 | for(;;) { | |
1291 | tb1 = *ptb; | |
1292 | n1 = (long)tb1 & 3; | |
1293 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1294 | if (n1 == n && tb1 == tb) | |
1295 | break; | |
1296 | ptb = &tb1->jmp_next[n1]; | |
1297 | } | |
1298 | *ptb = tb->jmp_next[n]; | |
1299 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1300 | |
ea041c0e FB |
1301 | /* suppress the jump to next tb in generated code */ |
1302 | tb_reset_jump(tb, n); | |
1303 | ||
0124311e | 1304 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1305 | tb_reset_jump_recursive(tb_next); |
1306 | } | |
1307 | } | |
1308 | ||
1309 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1310 | { | |
1311 | tb_reset_jump_recursive2(tb, 0); | |
1312 | tb_reset_jump_recursive2(tb, 1); | |
1313 | } | |
1314 | ||
1fddef4b | 1315 | #if defined(TARGET_HAS_ICE) |
d720b93d FB |
1316 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1317 | { | |
9b3c35e0 JM |
1318 | target_phys_addr_t addr; |
1319 | target_ulong pd; | |
c2f07f81 PB |
1320 | ram_addr_t ram_addr; |
1321 | PhysPageDesc *p; | |
d720b93d | 1322 | |
c2f07f81 PB |
1323 | addr = cpu_get_phys_page_debug(env, pc); |
1324 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1325 | if (!p) { | |
1326 | pd = IO_MEM_UNASSIGNED; | |
1327 | } else { | |
1328 | pd = p->phys_offset; | |
1329 | } | |
1330 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1331 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1332 | } |
c27004ec | 1333 | #endif |
d720b93d | 1334 | |
6658ffb8 | 1335 | /* Add a watchpoint. */ |
a1d1bb31 AL |
1336 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
1337 | int flags, CPUWatchpoint **watchpoint) | |
6658ffb8 | 1338 | { |
b4051334 | 1339 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 1340 | CPUWatchpoint *wp; |
6658ffb8 | 1341 | |
b4051334 AL |
1342 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
1343 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1344 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1345 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1346 | return -EINVAL; | |
1347 | } | |
a1d1bb31 | 1348 | wp = qemu_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1349 | |
1350 | wp->vaddr = addr; | |
b4051334 | 1351 | wp->len_mask = len_mask; |
a1d1bb31 AL |
1352 | wp->flags = flags; |
1353 | ||
2dc9f411 | 1354 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e AL |
1355 | if (flags & BP_GDB) |
1356 | TAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); | |
1357 | else | |
1358 | TAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); | |
6658ffb8 | 1359 | |
6658ffb8 | 1360 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
1361 | |
1362 | if (watchpoint) | |
1363 | *watchpoint = wp; | |
1364 | return 0; | |
6658ffb8 PB |
1365 | } |
1366 | ||
a1d1bb31 AL |
1367 | /* Remove a specific watchpoint. */ |
1368 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1369 | int flags) | |
6658ffb8 | 1370 | { |
b4051334 | 1371 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 1372 | CPUWatchpoint *wp; |
6658ffb8 | 1373 | |
c0ce998e | 1374 | TAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 1375 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 1376 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 1377 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
1378 | return 0; |
1379 | } | |
1380 | } | |
a1d1bb31 | 1381 | return -ENOENT; |
6658ffb8 PB |
1382 | } |
1383 | ||
a1d1bb31 AL |
1384 | /* Remove a specific watchpoint by reference. */ |
1385 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1386 | { | |
c0ce998e | 1387 | TAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 1388 | |
a1d1bb31 AL |
1389 | tlb_flush_page(env, watchpoint->vaddr); |
1390 | ||
1391 | qemu_free(watchpoint); | |
1392 | } | |
1393 | ||
1394 | /* Remove all matching watchpoints. */ | |
1395 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1396 | { | |
c0ce998e | 1397 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1398 | |
c0ce998e | 1399 | TAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
1400 | if (wp->flags & mask) |
1401 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 1402 | } |
7d03f82f EI |
1403 | } |
1404 | ||
a1d1bb31 AL |
1405 | /* Add a breakpoint. */ |
1406 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1407 | CPUBreakpoint **breakpoint) | |
4c3a88a2 | 1408 | { |
1fddef4b | 1409 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1410 | CPUBreakpoint *bp; |
3b46e624 | 1411 | |
a1d1bb31 | 1412 | bp = qemu_malloc(sizeof(*bp)); |
4c3a88a2 | 1413 | |
a1d1bb31 AL |
1414 | bp->pc = pc; |
1415 | bp->flags = flags; | |
1416 | ||
2dc9f411 | 1417 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e AL |
1418 | if (flags & BP_GDB) |
1419 | TAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); | |
1420 | else | |
1421 | TAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); | |
3b46e624 | 1422 | |
d720b93d | 1423 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
1424 | |
1425 | if (breakpoint) | |
1426 | *breakpoint = bp; | |
4c3a88a2 FB |
1427 | return 0; |
1428 | #else | |
a1d1bb31 | 1429 | return -ENOSYS; |
4c3a88a2 FB |
1430 | #endif |
1431 | } | |
1432 | ||
a1d1bb31 AL |
1433 | /* Remove a specific breakpoint. */ |
1434 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1435 | { | |
7d03f82f | 1436 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
1437 | CPUBreakpoint *bp; |
1438 | ||
c0ce998e | 1439 | TAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
1440 | if (bp->pc == pc && bp->flags == flags) { |
1441 | cpu_breakpoint_remove_by_ref(env, bp); | |
1442 | return 0; | |
1443 | } | |
7d03f82f | 1444 | } |
a1d1bb31 AL |
1445 | return -ENOENT; |
1446 | #else | |
1447 | return -ENOSYS; | |
7d03f82f EI |
1448 | #endif |
1449 | } | |
1450 | ||
a1d1bb31 AL |
1451 | /* Remove a specific breakpoint by reference. */ |
1452 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
4c3a88a2 | 1453 | { |
1fddef4b | 1454 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1455 | TAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 1456 | |
a1d1bb31 AL |
1457 | breakpoint_invalidate(env, breakpoint->pc); |
1458 | ||
1459 | qemu_free(breakpoint); | |
1460 | #endif | |
1461 | } | |
1462 | ||
1463 | /* Remove all matching breakpoints. */ | |
1464 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1465 | { | |
1466 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 1467 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1468 | |
c0ce998e | 1469 | TAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
1470 | if (bp->flags & mask) |
1471 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 1472 | } |
4c3a88a2 FB |
1473 | #endif |
1474 | } | |
1475 | ||
c33a346e FB |
1476 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1477 | CPU loop after each instruction */ | |
1478 | void cpu_single_step(CPUState *env, int enabled) | |
1479 | { | |
1fddef4b | 1480 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1481 | if (env->singlestep_enabled != enabled) { |
1482 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
1483 | if (kvm_enabled()) |
1484 | kvm_update_guest_debug(env, 0); | |
1485 | else { | |
ccbb4d44 | 1486 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
1487 | /* XXX: only flush what is necessary */ |
1488 | tb_flush(env); | |
1489 | } | |
c33a346e FB |
1490 | } |
1491 | #endif | |
1492 | } | |
1493 | ||
34865134 FB |
1494 | /* enable or disable low levels log */ |
1495 | void cpu_set_log(int log_flags) | |
1496 | { | |
1497 | loglevel = log_flags; | |
1498 | if (loglevel && !logfile) { | |
11fcfab4 | 1499 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1500 | if (!logfile) { |
1501 | perror(logfilename); | |
1502 | _exit(1); | |
1503 | } | |
9fa3e853 FB |
1504 | #if !defined(CONFIG_SOFTMMU) |
1505 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1506 | { | |
b55266b5 | 1507 | static char logfile_buf[4096]; |
9fa3e853 FB |
1508 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1509 | } | |
1510 | #else | |
34865134 | 1511 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1512 | #endif |
e735b91c PB |
1513 | log_append = 1; |
1514 | } | |
1515 | if (!loglevel && logfile) { | |
1516 | fclose(logfile); | |
1517 | logfile = NULL; | |
34865134 FB |
1518 | } |
1519 | } | |
1520 | ||
1521 | void cpu_set_log_filename(const char *filename) | |
1522 | { | |
1523 | logfilename = strdup(filename); | |
e735b91c PB |
1524 | if (logfile) { |
1525 | fclose(logfile); | |
1526 | logfile = NULL; | |
1527 | } | |
1528 | cpu_set_log(loglevel); | |
34865134 | 1529 | } |
c33a346e | 1530 | |
3098dba0 | 1531 | static void cpu_unlink_tb(CPUState *env) |
ea041c0e | 1532 | { |
3098dba0 AJ |
1533 | #if defined(USE_NPTL) |
1534 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the | |
1535 | problem and hope the cpu will stop of its own accord. For userspace | |
1536 | emulation this often isn't actually as bad as it sounds. Often | |
1537 | signals are used primarily to interrupt blocking syscalls. */ | |
1538 | #else | |
ea041c0e | 1539 | TranslationBlock *tb; |
15a51156 | 1540 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1541 | |
3098dba0 AJ |
1542 | tb = env->current_tb; |
1543 | /* if the cpu is currently executing code, we must unlink it and | |
1544 | all the potentially executing TB */ | |
1545 | if (tb && !testandset(&interrupt_lock)) { | |
1546 | env->current_tb = NULL; | |
1547 | tb_reset_jump_recursive(tb); | |
1548 | resetlock(&interrupt_lock); | |
be214e6c | 1549 | } |
3098dba0 AJ |
1550 | #endif |
1551 | } | |
1552 | ||
1553 | /* mask must never be zero, except for A20 change call */ | |
1554 | void cpu_interrupt(CPUState *env, int mask) | |
1555 | { | |
1556 | int old_mask; | |
be214e6c | 1557 | |
2e70f6ef | 1558 | old_mask = env->interrupt_request; |
68a79315 | 1559 | env->interrupt_request |= mask; |
3098dba0 | 1560 | |
8edac960 AL |
1561 | #ifndef CONFIG_USER_ONLY |
1562 | /* | |
1563 | * If called from iothread context, wake the target cpu in | |
1564 | * case its halted. | |
1565 | */ | |
1566 | if (!qemu_cpu_self(env)) { | |
1567 | qemu_cpu_kick(env); | |
1568 | return; | |
1569 | } | |
1570 | #endif | |
1571 | ||
2e70f6ef | 1572 | if (use_icount) { |
266910c4 | 1573 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef | 1574 | #ifndef CONFIG_USER_ONLY |
2e70f6ef | 1575 | if (!can_do_io(env) |
be214e6c | 1576 | && (mask & ~old_mask) != 0) { |
2e70f6ef PB |
1577 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
1578 | } | |
1579 | #endif | |
1580 | } else { | |
3098dba0 | 1581 | cpu_unlink_tb(env); |
ea041c0e FB |
1582 | } |
1583 | } | |
1584 | ||
b54ad049 FB |
1585 | void cpu_reset_interrupt(CPUState *env, int mask) |
1586 | { | |
1587 | env->interrupt_request &= ~mask; | |
1588 | } | |
1589 | ||
3098dba0 AJ |
1590 | void cpu_exit(CPUState *env) |
1591 | { | |
1592 | env->exit_request = 1; | |
1593 | cpu_unlink_tb(env); | |
1594 | } | |
1595 | ||
c7cd6a37 | 1596 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1597 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1598 | "show generated host assembly code for each compiled TB" }, |
1599 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1600 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1601 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1602 | "show micro ops for each compiled TB" }, |
f193c797 | 1603 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1604 | "show micro ops " |
1605 | #ifdef TARGET_I386 | |
1606 | "before eflags optimization and " | |
f193c797 | 1607 | #endif |
e01a1157 | 1608 | "after liveness analysis" }, |
f193c797 FB |
1609 | { CPU_LOG_INT, "int", |
1610 | "show interrupts/exceptions in short format" }, | |
1611 | { CPU_LOG_EXEC, "exec", | |
1612 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1613 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1614 | "show CPU state before block translation" }, |
f193c797 FB |
1615 | #ifdef TARGET_I386 |
1616 | { CPU_LOG_PCALL, "pcall", | |
1617 | "show protected mode far calls/returns/exceptions" }, | |
eca1bdf4 AL |
1618 | { CPU_LOG_RESET, "cpu_reset", |
1619 | "show CPU state before CPU resets" }, | |
f193c797 | 1620 | #endif |
8e3a9fd2 | 1621 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1622 | { CPU_LOG_IOPORT, "ioport", |
1623 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1624 | #endif |
f193c797 FB |
1625 | { 0, NULL, NULL }, |
1626 | }; | |
1627 | ||
1628 | static int cmp1(const char *s1, int n, const char *s2) | |
1629 | { | |
1630 | if (strlen(s2) != n) | |
1631 | return 0; | |
1632 | return memcmp(s1, s2, n) == 0; | |
1633 | } | |
3b46e624 | 1634 | |
f193c797 FB |
1635 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1636 | int cpu_str_to_log_mask(const char *str) | |
1637 | { | |
c7cd6a37 | 1638 | const CPULogItem *item; |
f193c797 FB |
1639 | int mask; |
1640 | const char *p, *p1; | |
1641 | ||
1642 | p = str; | |
1643 | mask = 0; | |
1644 | for(;;) { | |
1645 | p1 = strchr(p, ','); | |
1646 | if (!p1) | |
1647 | p1 = p + strlen(p); | |
8e3a9fd2 FB |
1648 | if(cmp1(p,p1-p,"all")) { |
1649 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1650 | mask |= item->mask; | |
1651 | } | |
1652 | } else { | |
f193c797 FB |
1653 | for(item = cpu_log_items; item->mask != 0; item++) { |
1654 | if (cmp1(p, p1 - p, item->name)) | |
1655 | goto found; | |
1656 | } | |
1657 | return 0; | |
8e3a9fd2 | 1658 | } |
f193c797 FB |
1659 | found: |
1660 | mask |= item->mask; | |
1661 | if (*p1 != ',') | |
1662 | break; | |
1663 | p = p1 + 1; | |
1664 | } | |
1665 | return mask; | |
1666 | } | |
ea041c0e | 1667 | |
7501267e FB |
1668 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1669 | { | |
1670 | va_list ap; | |
493ae1f0 | 1671 | va_list ap2; |
7501267e FB |
1672 | |
1673 | va_start(ap, fmt); | |
493ae1f0 | 1674 | va_copy(ap2, ap); |
7501267e FB |
1675 | fprintf(stderr, "qemu: fatal: "); |
1676 | vfprintf(stderr, fmt, ap); | |
1677 | fprintf(stderr, "\n"); | |
1678 | #ifdef TARGET_I386 | |
7fe48483 FB |
1679 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1680 | #else | |
1681 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1682 | #endif |
93fcfe39 AL |
1683 | if (qemu_log_enabled()) { |
1684 | qemu_log("qemu: fatal: "); | |
1685 | qemu_log_vprintf(fmt, ap2); | |
1686 | qemu_log("\n"); | |
f9373291 | 1687 | #ifdef TARGET_I386 |
93fcfe39 | 1688 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
f9373291 | 1689 | #else |
93fcfe39 | 1690 | log_cpu_state(env, 0); |
f9373291 | 1691 | #endif |
31b1a7b4 | 1692 | qemu_log_flush(); |
93fcfe39 | 1693 | qemu_log_close(); |
924edcae | 1694 | } |
493ae1f0 | 1695 | va_end(ap2); |
f9373291 | 1696 | va_end(ap); |
7501267e FB |
1697 | abort(); |
1698 | } | |
1699 | ||
c5be9f08 TS |
1700 | CPUState *cpu_copy(CPUState *env) |
1701 | { | |
01ba9816 | 1702 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1703 | CPUState *next_cpu = new_env->next_cpu; |
1704 | int cpu_index = new_env->cpu_index; | |
5a38f081 AL |
1705 | #if defined(TARGET_HAS_ICE) |
1706 | CPUBreakpoint *bp; | |
1707 | CPUWatchpoint *wp; | |
1708 | #endif | |
1709 | ||
c5be9f08 | 1710 | memcpy(new_env, env, sizeof(CPUState)); |
5a38f081 AL |
1711 | |
1712 | /* Preserve chaining and index. */ | |
c5be9f08 TS |
1713 | new_env->next_cpu = next_cpu; |
1714 | new_env->cpu_index = cpu_index; | |
5a38f081 AL |
1715 | |
1716 | /* Clone all break/watchpoints. | |
1717 | Note: Once we support ptrace with hw-debug register access, make sure | |
1718 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
1719 | TAILQ_INIT(&env->breakpoints); | |
1720 | TAILQ_INIT(&env->watchpoints); | |
1721 | #if defined(TARGET_HAS_ICE) | |
1722 | TAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
1723 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); | |
1724 | } | |
1725 | TAILQ_FOREACH(wp, &env->watchpoints, entry) { | |
1726 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, | |
1727 | wp->flags, NULL); | |
1728 | } | |
1729 | #endif | |
1730 | ||
c5be9f08 TS |
1731 | return new_env; |
1732 | } | |
1733 | ||
0124311e FB |
1734 | #if !defined(CONFIG_USER_ONLY) |
1735 | ||
5c751e99 EI |
1736 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1737 | { | |
1738 | unsigned int i; | |
1739 | ||
1740 | /* Discard jump cache entries for any tb which might potentially | |
1741 | overlap the flushed page. */ | |
1742 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1743 | memset (&env->tb_jmp_cache[i], 0, | |
1744 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1745 | ||
1746 | i = tb_jmp_cache_hash_page(addr); | |
1747 | memset (&env->tb_jmp_cache[i], 0, | |
1748 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1749 | } | |
1750 | ||
ee8b7021 FB |
1751 | /* NOTE: if flush_global is true, also flush global entries (not |
1752 | implemented yet) */ | |
1753 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1754 | { |
33417e70 | 1755 | int i; |
0124311e | 1756 | |
9fa3e853 FB |
1757 | #if defined(DEBUG_TLB) |
1758 | printf("tlb_flush:\n"); | |
1759 | #endif | |
0124311e FB |
1760 | /* must reset current TB so that interrupts cannot modify the |
1761 | links while we are modifying them */ | |
1762 | env->current_tb = NULL; | |
1763 | ||
33417e70 | 1764 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
84b7b8e7 FB |
1765 | env->tlb_table[0][i].addr_read = -1; |
1766 | env->tlb_table[0][i].addr_write = -1; | |
1767 | env->tlb_table[0][i].addr_code = -1; | |
1768 | env->tlb_table[1][i].addr_read = -1; | |
1769 | env->tlb_table[1][i].addr_write = -1; | |
1770 | env->tlb_table[1][i].addr_code = -1; | |
6fa4cea9 JM |
1771 | #if (NB_MMU_MODES >= 3) |
1772 | env->tlb_table[2][i].addr_read = -1; | |
1773 | env->tlb_table[2][i].addr_write = -1; | |
1774 | env->tlb_table[2][i].addr_code = -1; | |
e37e6ee6 AJ |
1775 | #endif |
1776 | #if (NB_MMU_MODES >= 4) | |
6fa4cea9 JM |
1777 | env->tlb_table[3][i].addr_read = -1; |
1778 | env->tlb_table[3][i].addr_write = -1; | |
1779 | env->tlb_table[3][i].addr_code = -1; | |
1780 | #endif | |
e37e6ee6 AJ |
1781 | #if (NB_MMU_MODES >= 5) |
1782 | env->tlb_table[4][i].addr_read = -1; | |
1783 | env->tlb_table[4][i].addr_write = -1; | |
1784 | env->tlb_table[4][i].addr_code = -1; | |
6fa4cea9 | 1785 | #endif |
e37e6ee6 | 1786 | |
33417e70 | 1787 | } |
9fa3e853 | 1788 | |
8a40a180 | 1789 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1790 | |
640f42e4 | 1791 | #ifdef CONFIG_KQEMU |
0a962c02 FB |
1792 | if (env->kqemu_enabled) { |
1793 | kqemu_flush(env, flush_global); | |
1794 | } | |
9fa3e853 | 1795 | #endif |
e3db7226 | 1796 | tlb_flush_count++; |
33417e70 FB |
1797 | } |
1798 | ||
274da6b2 | 1799 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1800 | { |
5fafdf24 | 1801 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 1802 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1803 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 1804 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1805 | addr == (tlb_entry->addr_code & |
84b7b8e7 FB |
1806 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
1807 | tlb_entry->addr_read = -1; | |
1808 | tlb_entry->addr_write = -1; | |
1809 | tlb_entry->addr_code = -1; | |
1810 | } | |
61382a50 FB |
1811 | } |
1812 | ||
2e12669a | 1813 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 1814 | { |
8a40a180 | 1815 | int i; |
0124311e | 1816 | |
9fa3e853 | 1817 | #if defined(DEBUG_TLB) |
108c49b8 | 1818 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 1819 | #endif |
0124311e FB |
1820 | /* must reset current TB so that interrupts cannot modify the |
1821 | links while we are modifying them */ | |
1822 | env->current_tb = NULL; | |
61382a50 FB |
1823 | |
1824 | addr &= TARGET_PAGE_MASK; | |
1825 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
84b7b8e7 FB |
1826 | tlb_flush_entry(&env->tlb_table[0][i], addr); |
1827 | tlb_flush_entry(&env->tlb_table[1][i], addr); | |
6fa4cea9 JM |
1828 | #if (NB_MMU_MODES >= 3) |
1829 | tlb_flush_entry(&env->tlb_table[2][i], addr); | |
e37e6ee6 AJ |
1830 | #endif |
1831 | #if (NB_MMU_MODES >= 4) | |
6fa4cea9 JM |
1832 | tlb_flush_entry(&env->tlb_table[3][i], addr); |
1833 | #endif | |
e37e6ee6 AJ |
1834 | #if (NB_MMU_MODES >= 5) |
1835 | tlb_flush_entry(&env->tlb_table[4][i], addr); | |
6fa4cea9 | 1836 | #endif |
0124311e | 1837 | |
5c751e99 | 1838 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 | 1839 | |
640f42e4 | 1840 | #ifdef CONFIG_KQEMU |
0a962c02 FB |
1841 | if (env->kqemu_enabled) { |
1842 | kqemu_flush_page(env, addr); | |
1843 | } | |
1844 | #endif | |
9fa3e853 FB |
1845 | } |
1846 | ||
9fa3e853 FB |
1847 | /* update the TLBs so that writes to code in the virtual page 'addr' |
1848 | can be detected */ | |
6a00d601 | 1849 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 1850 | { |
5fafdf24 | 1851 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
1852 | ram_addr + TARGET_PAGE_SIZE, |
1853 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
1854 | } |
1855 | ||
9fa3e853 | 1856 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 1857 | tested for self modifying code */ |
5fafdf24 | 1858 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 1859 | target_ulong vaddr) |
9fa3e853 | 1860 | { |
3a7d929e | 1861 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG; |
1ccde1cb FB |
1862 | } |
1863 | ||
5fafdf24 | 1864 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
1865 | unsigned long start, unsigned long length) |
1866 | { | |
1867 | unsigned long addr; | |
84b7b8e7 FB |
1868 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
1869 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 1870 | if ((addr - start) < length) { |
0f459d16 | 1871 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
1872 | } |
1873 | } | |
1874 | } | |
1875 | ||
5579c7f3 | 1876 | /* Note: start and end must be within the same ram block. */ |
3a7d929e | 1877 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 1878 | int dirty_flags) |
1ccde1cb FB |
1879 | { |
1880 | CPUState *env; | |
4f2ac237 | 1881 | unsigned long length, start1; |
0a962c02 FB |
1882 | int i, mask, len; |
1883 | uint8_t *p; | |
1ccde1cb FB |
1884 | |
1885 | start &= TARGET_PAGE_MASK; | |
1886 | end = TARGET_PAGE_ALIGN(end); | |
1887 | ||
1888 | length = end - start; | |
1889 | if (length == 0) | |
1890 | return; | |
0a962c02 | 1891 | len = length >> TARGET_PAGE_BITS; |
640f42e4 | 1892 | #ifdef CONFIG_KQEMU |
6a00d601 FB |
1893 | /* XXX: should not depend on cpu context */ |
1894 | env = first_cpu; | |
3a7d929e | 1895 | if (env->kqemu_enabled) { |
f23db169 FB |
1896 | ram_addr_t addr; |
1897 | addr = start; | |
1898 | for(i = 0; i < len; i++) { | |
1899 | kqemu_set_notdirty(env, addr); | |
1900 | addr += TARGET_PAGE_SIZE; | |
1901 | } | |
3a7d929e FB |
1902 | } |
1903 | #endif | |
f23db169 FB |
1904 | mask = ~dirty_flags; |
1905 | p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); | |
1906 | for(i = 0; i < len; i++) | |
1907 | p[i] &= mask; | |
1908 | ||
1ccde1cb FB |
1909 | /* we modify the TLB cache so that the dirty bit will be set again |
1910 | when accessing the range */ | |
5579c7f3 PB |
1911 | start1 = (unsigned long)qemu_get_ram_ptr(start); |
1912 | /* Chek that we don't span multiple blocks - this breaks the | |
1913 | address comparisons below. */ | |
1914 | if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1 | |
1915 | != (end - 1) - start) { | |
1916 | abort(); | |
1917 | } | |
1918 | ||
6a00d601 FB |
1919 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
1920 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
84b7b8e7 | 1921 | tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length); |
6a00d601 | 1922 | for(i = 0; i < CPU_TLB_SIZE; i++) |
84b7b8e7 | 1923 | tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length); |
6fa4cea9 JM |
1924 | #if (NB_MMU_MODES >= 3) |
1925 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1926 | tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length); | |
e37e6ee6 AJ |
1927 | #endif |
1928 | #if (NB_MMU_MODES >= 4) | |
6fa4cea9 JM |
1929 | for(i = 0; i < CPU_TLB_SIZE; i++) |
1930 | tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length); | |
1931 | #endif | |
e37e6ee6 AJ |
1932 | #if (NB_MMU_MODES >= 5) |
1933 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1934 | tlb_reset_dirty_range(&env->tlb_table[4][i], start1, length); | |
6fa4cea9 | 1935 | #endif |
6a00d601 | 1936 | } |
1ccde1cb FB |
1937 | } |
1938 | ||
74576198 AL |
1939 | int cpu_physical_memory_set_dirty_tracking(int enable) |
1940 | { | |
1941 | in_migration = enable; | |
b0a46a33 JK |
1942 | if (kvm_enabled()) { |
1943 | return kvm_set_migration_log(enable); | |
1944 | } | |
74576198 AL |
1945 | return 0; |
1946 | } | |
1947 | ||
1948 | int cpu_physical_memory_get_dirty_tracking(void) | |
1949 | { | |
1950 | return in_migration; | |
1951 | } | |
1952 | ||
151f7749 JK |
1953 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
1954 | target_phys_addr_t end_addr) | |
2bec46dc | 1955 | { |
151f7749 JK |
1956 | int ret = 0; |
1957 | ||
2bec46dc | 1958 | if (kvm_enabled()) |
151f7749 JK |
1959 | ret = kvm_physical_sync_dirty_bitmap(start_addr, end_addr); |
1960 | return ret; | |
2bec46dc AL |
1961 | } |
1962 | ||
3a7d929e FB |
1963 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
1964 | { | |
1965 | ram_addr_t ram_addr; | |
5579c7f3 | 1966 | void *p; |
3a7d929e | 1967 | |
84b7b8e7 | 1968 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5579c7f3 PB |
1969 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
1970 | + tlb_entry->addend); | |
1971 | ram_addr = qemu_ram_addr_from_host(p); | |
3a7d929e | 1972 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
0f459d16 | 1973 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
1974 | } |
1975 | } | |
1976 | } | |
1977 | ||
1978 | /* update the TLB according to the current state of the dirty bits */ | |
1979 | void cpu_tlb_update_dirty(CPUState *env) | |
1980 | { | |
1981 | int i; | |
1982 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
84b7b8e7 | 1983 | tlb_update_dirty(&env->tlb_table[0][i]); |
3a7d929e | 1984 | for(i = 0; i < CPU_TLB_SIZE; i++) |
84b7b8e7 | 1985 | tlb_update_dirty(&env->tlb_table[1][i]); |
6fa4cea9 JM |
1986 | #if (NB_MMU_MODES >= 3) |
1987 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1988 | tlb_update_dirty(&env->tlb_table[2][i]); | |
e37e6ee6 AJ |
1989 | #endif |
1990 | #if (NB_MMU_MODES >= 4) | |
6fa4cea9 JM |
1991 | for(i = 0; i < CPU_TLB_SIZE; i++) |
1992 | tlb_update_dirty(&env->tlb_table[3][i]); | |
1993 | #endif | |
e37e6ee6 AJ |
1994 | #if (NB_MMU_MODES >= 5) |
1995 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1996 | tlb_update_dirty(&env->tlb_table[4][i]); | |
6fa4cea9 | 1997 | #endif |
3a7d929e FB |
1998 | } |
1999 | ||
0f459d16 | 2000 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 2001 | { |
0f459d16 PB |
2002 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
2003 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
2004 | } |
2005 | ||
0f459d16 PB |
2006 | /* update the TLB corresponding to virtual page vaddr |
2007 | so that it is no longer dirty */ | |
2008 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 2009 | { |
1ccde1cb FB |
2010 | int i; |
2011 | ||
0f459d16 | 2012 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 2013 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
0f459d16 PB |
2014 | tlb_set_dirty1(&env->tlb_table[0][i], vaddr); |
2015 | tlb_set_dirty1(&env->tlb_table[1][i], vaddr); | |
6fa4cea9 | 2016 | #if (NB_MMU_MODES >= 3) |
0f459d16 | 2017 | tlb_set_dirty1(&env->tlb_table[2][i], vaddr); |
e37e6ee6 AJ |
2018 | #endif |
2019 | #if (NB_MMU_MODES >= 4) | |
0f459d16 | 2020 | tlb_set_dirty1(&env->tlb_table[3][i], vaddr); |
6fa4cea9 | 2021 | #endif |
e37e6ee6 AJ |
2022 | #if (NB_MMU_MODES >= 5) |
2023 | tlb_set_dirty1(&env->tlb_table[4][i], vaddr); | |
6fa4cea9 | 2024 | #endif |
9fa3e853 FB |
2025 | } |
2026 | ||
59817ccb FB |
2027 | /* add a new TLB entry. At most one entry for a given virtual address |
2028 | is permitted. Return 0 if OK or 2 if the page could not be mapped | |
2029 | (can only happen in non SOFTMMU mode for I/O pages or pages | |
2030 | conflicting with the host address space). */ | |
5fafdf24 TS |
2031 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
2032 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 2033 | int mmu_idx, int is_softmmu) |
9fa3e853 | 2034 | { |
92e873b9 | 2035 | PhysPageDesc *p; |
4f2ac237 | 2036 | unsigned long pd; |
9fa3e853 | 2037 | unsigned int index; |
4f2ac237 | 2038 | target_ulong address; |
0f459d16 | 2039 | target_ulong code_address; |
108c49b8 | 2040 | target_phys_addr_t addend; |
9fa3e853 | 2041 | int ret; |
84b7b8e7 | 2042 | CPUTLBEntry *te; |
a1d1bb31 | 2043 | CPUWatchpoint *wp; |
0f459d16 | 2044 | target_phys_addr_t iotlb; |
9fa3e853 | 2045 | |
92e873b9 | 2046 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
2047 | if (!p) { |
2048 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
2049 | } else { |
2050 | pd = p->phys_offset; | |
9fa3e853 FB |
2051 | } |
2052 | #if defined(DEBUG_TLB) | |
6ebbf390 JM |
2053 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n", |
2054 | vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd); | |
9fa3e853 FB |
2055 | #endif |
2056 | ||
2057 | ret = 0; | |
0f459d16 PB |
2058 | address = vaddr; |
2059 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
2060 | /* IO memory case (romd handled later) */ | |
2061 | address |= TLB_MMIO; | |
2062 | } | |
5579c7f3 | 2063 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
0f459d16 PB |
2064 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
2065 | /* Normal RAM. */ | |
2066 | iotlb = pd & TARGET_PAGE_MASK; | |
2067 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
2068 | iotlb |= IO_MEM_NOTDIRTY; | |
2069 | else | |
2070 | iotlb |= IO_MEM_ROM; | |
2071 | } else { | |
ccbb4d44 | 2072 | /* IO handlers are currently passed a physical address. |
0f459d16 PB |
2073 | It would be nice to pass an offset from the base address |
2074 | of that region. This would avoid having to special case RAM, | |
2075 | and avoid full address decoding in every device. | |
2076 | We can't use the high bits of pd for this because | |
2077 | IO_MEM_ROMD uses these as a ram address. */ | |
8da3ff18 PB |
2078 | iotlb = (pd & ~TARGET_PAGE_MASK); |
2079 | if (p) { | |
8da3ff18 PB |
2080 | iotlb += p->region_offset; |
2081 | } else { | |
2082 | iotlb += paddr; | |
2083 | } | |
0f459d16 PB |
2084 | } |
2085 | ||
2086 | code_address = address; | |
2087 | /* Make accesses to pages with watchpoints go via the | |
2088 | watchpoint trap routines. */ | |
c0ce998e | 2089 | TAILQ_FOREACH(wp, &env->watchpoints, entry) { |
a1d1bb31 | 2090 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
0f459d16 PB |
2091 | iotlb = io_mem_watch + paddr; |
2092 | /* TODO: The memory case can be optimized by not trapping | |
2093 | reads of pages with a write breakpoint. */ | |
2094 | address |= TLB_MMIO; | |
6658ffb8 | 2095 | } |
0f459d16 | 2096 | } |
d79acba4 | 2097 | |
0f459d16 PB |
2098 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
2099 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2100 | te = &env->tlb_table[mmu_idx][index]; | |
2101 | te->addend = addend - vaddr; | |
2102 | if (prot & PAGE_READ) { | |
2103 | te->addr_read = address; | |
2104 | } else { | |
2105 | te->addr_read = -1; | |
2106 | } | |
5c751e99 | 2107 | |
0f459d16 PB |
2108 | if (prot & PAGE_EXEC) { |
2109 | te->addr_code = code_address; | |
2110 | } else { | |
2111 | te->addr_code = -1; | |
2112 | } | |
2113 | if (prot & PAGE_WRITE) { | |
2114 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
2115 | (pd & IO_MEM_ROMD)) { | |
2116 | /* Write access calls the I/O callback. */ | |
2117 | te->addr_write = address | TLB_MMIO; | |
2118 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
2119 | !cpu_physical_memory_is_dirty(pd)) { | |
2120 | te->addr_write = address | TLB_NOTDIRTY; | |
9fa3e853 | 2121 | } else { |
0f459d16 | 2122 | te->addr_write = address; |
9fa3e853 | 2123 | } |
0f459d16 PB |
2124 | } else { |
2125 | te->addr_write = -1; | |
9fa3e853 | 2126 | } |
9fa3e853 FB |
2127 | return ret; |
2128 | } | |
2129 | ||
0124311e FB |
2130 | #else |
2131 | ||
ee8b7021 | 2132 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
2133 | { |
2134 | } | |
2135 | ||
2e12669a | 2136 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
2137 | { |
2138 | } | |
2139 | ||
5fafdf24 TS |
2140 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
2141 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 2142 | int mmu_idx, int is_softmmu) |
9fa3e853 FB |
2143 | { |
2144 | return 0; | |
2145 | } | |
0124311e | 2146 | |
edf8e2af MW |
2147 | /* |
2148 | * Walks guest process memory "regions" one by one | |
2149 | * and calls callback function 'fn' for each region. | |
2150 | */ | |
2151 | int walk_memory_regions(void *priv, | |
2152 | int (*fn)(void *, unsigned long, unsigned long, unsigned long)) | |
33417e70 | 2153 | { |
9fa3e853 | 2154 | unsigned long start, end; |
edf8e2af | 2155 | PageDesc *p = NULL; |
9fa3e853 | 2156 | int i, j, prot, prot1; |
edf8e2af | 2157 | int rc = 0; |
33417e70 | 2158 | |
edf8e2af | 2159 | start = end = -1; |
9fa3e853 | 2160 | prot = 0; |
edf8e2af MW |
2161 | |
2162 | for (i = 0; i <= L1_SIZE; i++) { | |
2163 | p = (i < L1_SIZE) ? l1_map[i] : NULL; | |
2164 | for (j = 0; j < L2_SIZE; j++) { | |
2165 | prot1 = (p == NULL) ? 0 : p[j].flags; | |
2166 | /* | |
2167 | * "region" is one continuous chunk of memory | |
2168 | * that has same protection flags set. | |
2169 | */ | |
9fa3e853 FB |
2170 | if (prot1 != prot) { |
2171 | end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS); | |
2172 | if (start != -1) { | |
edf8e2af MW |
2173 | rc = (*fn)(priv, start, end, prot); |
2174 | /* callback can stop iteration by returning != 0 */ | |
2175 | if (rc != 0) | |
2176 | return (rc); | |
9fa3e853 FB |
2177 | } |
2178 | if (prot1 != 0) | |
2179 | start = end; | |
2180 | else | |
2181 | start = -1; | |
2182 | prot = prot1; | |
2183 | } | |
edf8e2af | 2184 | if (p == NULL) |
9fa3e853 FB |
2185 | break; |
2186 | } | |
33417e70 | 2187 | } |
edf8e2af MW |
2188 | return (rc); |
2189 | } | |
2190 | ||
2191 | static int dump_region(void *priv, unsigned long start, | |
2192 | unsigned long end, unsigned long prot) | |
2193 | { | |
2194 | FILE *f = (FILE *)priv; | |
2195 | ||
2196 | (void) fprintf(f, "%08lx-%08lx %08lx %c%c%c\n", | |
2197 | start, end, end - start, | |
2198 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2199 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2200 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2201 | ||
2202 | return (0); | |
2203 | } | |
2204 | ||
2205 | /* dump memory mappings */ | |
2206 | void page_dump(FILE *f) | |
2207 | { | |
2208 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2209 | "start", "end", "size", "prot"); | |
2210 | walk_memory_regions(f, dump_region); | |
33417e70 FB |
2211 | } |
2212 | ||
53a5960a | 2213 | int page_get_flags(target_ulong address) |
33417e70 | 2214 | { |
9fa3e853 FB |
2215 | PageDesc *p; |
2216 | ||
2217 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2218 | if (!p) |
9fa3e853 FB |
2219 | return 0; |
2220 | return p->flags; | |
2221 | } | |
2222 | ||
2223 | /* modify the flags of a page and invalidate the code if | |
ccbb4d44 | 2224 | necessary. The flag PAGE_WRITE_ORG is positioned automatically |
9fa3e853 | 2225 | depending on PAGE_WRITE */ |
53a5960a | 2226 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 FB |
2227 | { |
2228 | PageDesc *p; | |
53a5960a | 2229 | target_ulong addr; |
9fa3e853 | 2230 | |
c8a706fe | 2231 | /* mmap_lock should already be held. */ |
9fa3e853 FB |
2232 | start = start & TARGET_PAGE_MASK; |
2233 | end = TARGET_PAGE_ALIGN(end); | |
2234 | if (flags & PAGE_WRITE) | |
2235 | flags |= PAGE_WRITE_ORG; | |
9fa3e853 FB |
2236 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
2237 | p = page_find_alloc(addr >> TARGET_PAGE_BITS); | |
17e2377a PB |
2238 | /* We may be called for host regions that are outside guest |
2239 | address space. */ | |
2240 | if (!p) | |
2241 | return; | |
9fa3e853 FB |
2242 | /* if the write protection is set, then we invalidate the code |
2243 | inside */ | |
5fafdf24 | 2244 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2245 | (flags & PAGE_WRITE) && |
2246 | p->first_tb) { | |
d720b93d | 2247 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2248 | } |
2249 | p->flags = flags; | |
2250 | } | |
33417e70 FB |
2251 | } |
2252 | ||
3d97b40b TS |
2253 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2254 | { | |
2255 | PageDesc *p; | |
2256 | target_ulong end; | |
2257 | target_ulong addr; | |
2258 | ||
55f280c9 AZ |
2259 | if (start + len < start) |
2260 | /* we've wrapped around */ | |
2261 | return -1; | |
2262 | ||
3d97b40b TS |
2263 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2264 | start = start & TARGET_PAGE_MASK; | |
2265 | ||
3d97b40b TS |
2266 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
2267 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2268 | if( !p ) | |
2269 | return -1; | |
2270 | if( !(p->flags & PAGE_VALID) ) | |
2271 | return -1; | |
2272 | ||
dae3270c | 2273 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2274 | return -1; |
dae3270c FB |
2275 | if (flags & PAGE_WRITE) { |
2276 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2277 | return -1; | |
2278 | /* unprotect the page if it was put read-only because it | |
2279 | contains translated code */ | |
2280 | if (!(p->flags & PAGE_WRITE)) { | |
2281 | if (!page_unprotect(addr, 0, NULL)) | |
2282 | return -1; | |
2283 | } | |
2284 | return 0; | |
2285 | } | |
3d97b40b TS |
2286 | } |
2287 | return 0; | |
2288 | } | |
2289 | ||
9fa3e853 | 2290 | /* called from signal handler: invalidate the code and unprotect the |
ccbb4d44 | 2291 | page. Return TRUE if the fault was successfully handled. */ |
53a5960a | 2292 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 FB |
2293 | { |
2294 | unsigned int page_index, prot, pindex; | |
2295 | PageDesc *p, *p1; | |
53a5960a | 2296 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2297 | |
c8a706fe PB |
2298 | /* Technically this isn't safe inside a signal handler. However we |
2299 | know this only ever happens in a synchronous SEGV handler, so in | |
2300 | practice it seems to be ok. */ | |
2301 | mmap_lock(); | |
2302 | ||
83fb7adf | 2303 | host_start = address & qemu_host_page_mask; |
9fa3e853 FB |
2304 | page_index = host_start >> TARGET_PAGE_BITS; |
2305 | p1 = page_find(page_index); | |
c8a706fe PB |
2306 | if (!p1) { |
2307 | mmap_unlock(); | |
9fa3e853 | 2308 | return 0; |
c8a706fe | 2309 | } |
83fb7adf | 2310 | host_end = host_start + qemu_host_page_size; |
9fa3e853 FB |
2311 | p = p1; |
2312 | prot = 0; | |
2313 | for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) { | |
2314 | prot |= p->flags; | |
2315 | p++; | |
2316 | } | |
2317 | /* if the page was really writable, then we change its | |
2318 | protection back to writable */ | |
2319 | if (prot & PAGE_WRITE_ORG) { | |
2320 | pindex = (address - host_start) >> TARGET_PAGE_BITS; | |
2321 | if (!(p1[pindex].flags & PAGE_WRITE)) { | |
5fafdf24 | 2322 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
9fa3e853 FB |
2323 | (prot & PAGE_BITS) | PAGE_WRITE); |
2324 | p1[pindex].flags |= PAGE_WRITE; | |
2325 | /* and since the content will be modified, we must invalidate | |
2326 | the corresponding translated code. */ | |
d720b93d | 2327 | tb_invalidate_phys_page(address, pc, puc); |
9fa3e853 FB |
2328 | #ifdef DEBUG_TB_CHECK |
2329 | tb_invalidate_check(address); | |
2330 | #endif | |
c8a706fe | 2331 | mmap_unlock(); |
9fa3e853 FB |
2332 | return 1; |
2333 | } | |
2334 | } | |
c8a706fe | 2335 | mmap_unlock(); |
9fa3e853 FB |
2336 | return 0; |
2337 | } | |
2338 | ||
6a00d601 FB |
2339 | static inline void tlb_set_dirty(CPUState *env, |
2340 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2341 | { |
2342 | } | |
9fa3e853 FB |
2343 | #endif /* defined(CONFIG_USER_ONLY) */ |
2344 | ||
e2eef170 | 2345 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 2346 | |
db7b5426 | 2347 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
8da3ff18 | 2348 | ram_addr_t memory, ram_addr_t region_offset); |
00f82b8a | 2349 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
8da3ff18 | 2350 | ram_addr_t orig_memory, ram_addr_t region_offset); |
db7b5426 BS |
2351 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2352 | need_subpage) \ | |
2353 | do { \ | |
2354 | if (addr > start_addr) \ | |
2355 | start_addr2 = 0; \ | |
2356 | else { \ | |
2357 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2358 | if (start_addr2 > 0) \ | |
2359 | need_subpage = 1; \ | |
2360 | } \ | |
2361 | \ | |
49e9fba2 | 2362 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2363 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2364 | else { \ | |
2365 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2366 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2367 | need_subpage = 1; \ | |
2368 | } \ | |
2369 | } while (0) | |
2370 | ||
33417e70 FB |
2371 | /* register physical memory. 'size' must be a multiple of the target |
2372 | page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
8da3ff18 PB |
2373 | io memory page. The address used when calling the IO function is |
2374 | the offset from the start of the region, plus region_offset. Both | |
ccbb4d44 | 2375 | start_addr and region_offset are rounded down to a page boundary |
8da3ff18 PB |
2376 | before calculating this offset. This should not be a problem unless |
2377 | the low bits of start_addr and region_offset differ. */ | |
2378 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, | |
2379 | ram_addr_t size, | |
2380 | ram_addr_t phys_offset, | |
2381 | ram_addr_t region_offset) | |
33417e70 | 2382 | { |
108c49b8 | 2383 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2384 | PhysPageDesc *p; |
9d42037b | 2385 | CPUState *env; |
00f82b8a | 2386 | ram_addr_t orig_size = size; |
db7b5426 | 2387 | void *subpage; |
33417e70 | 2388 | |
640f42e4 | 2389 | #ifdef CONFIG_KQEMU |
da260249 FB |
2390 | /* XXX: should not depend on cpu context */ |
2391 | env = first_cpu; | |
2392 | if (env->kqemu_enabled) { | |
2393 | kqemu_set_phys_mem(start_addr, size, phys_offset); | |
2394 | } | |
2395 | #endif | |
7ba1e619 AL |
2396 | if (kvm_enabled()) |
2397 | kvm_set_phys_mem(start_addr, size, phys_offset); | |
2398 | ||
67c4d23c PB |
2399 | if (phys_offset == IO_MEM_UNASSIGNED) { |
2400 | region_offset = start_addr; | |
2401 | } | |
8da3ff18 | 2402 | region_offset &= TARGET_PAGE_MASK; |
5fd386f6 | 2403 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
49e9fba2 BS |
2404 | end_addr = start_addr + (target_phys_addr_t)size; |
2405 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { | |
db7b5426 BS |
2406 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2407 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
00f82b8a | 2408 | ram_addr_t orig_memory = p->phys_offset; |
db7b5426 BS |
2409 | target_phys_addr_t start_addr2, end_addr2; |
2410 | int need_subpage = 0; | |
2411 | ||
2412 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2413 | need_subpage); | |
4254fab8 | 2414 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 BS |
2415 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2416 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
8da3ff18 PB |
2417 | &p->phys_offset, orig_memory, |
2418 | p->region_offset); | |
db7b5426 BS |
2419 | } else { |
2420 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2421 | >> IO_MEM_SHIFT]; | |
2422 | } | |
8da3ff18 PB |
2423 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
2424 | region_offset); | |
2425 | p->region_offset = 0; | |
db7b5426 BS |
2426 | } else { |
2427 | p->phys_offset = phys_offset; | |
2428 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2429 | (phys_offset & IO_MEM_ROMD)) | |
2430 | phys_offset += TARGET_PAGE_SIZE; | |
2431 | } | |
2432 | } else { | |
2433 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2434 | p->phys_offset = phys_offset; | |
8da3ff18 | 2435 | p->region_offset = region_offset; |
db7b5426 | 2436 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
8da3ff18 | 2437 | (phys_offset & IO_MEM_ROMD)) { |
db7b5426 | 2438 | phys_offset += TARGET_PAGE_SIZE; |
0e8f0967 | 2439 | } else { |
db7b5426 BS |
2440 | target_phys_addr_t start_addr2, end_addr2; |
2441 | int need_subpage = 0; | |
2442 | ||
2443 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2444 | end_addr2, need_subpage); | |
2445 | ||
4254fab8 | 2446 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 | 2447 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
8da3ff18 | 2448 | &p->phys_offset, IO_MEM_UNASSIGNED, |
67c4d23c | 2449 | addr & TARGET_PAGE_MASK); |
db7b5426 | 2450 | subpage_register(subpage, start_addr2, end_addr2, |
8da3ff18 PB |
2451 | phys_offset, region_offset); |
2452 | p->region_offset = 0; | |
db7b5426 BS |
2453 | } |
2454 | } | |
2455 | } | |
8da3ff18 | 2456 | region_offset += TARGET_PAGE_SIZE; |
33417e70 | 2457 | } |
3b46e624 | 2458 | |
9d42037b FB |
2459 | /* since each CPU stores ram addresses in its TLB cache, we must |
2460 | reset the modified entries */ | |
2461 | /* XXX: slow ! */ | |
2462 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2463 | tlb_flush(env, 1); | |
2464 | } | |
33417e70 FB |
2465 | } |
2466 | ||
ba863458 | 2467 | /* XXX: temporary until new memory mapping API */ |
00f82b8a | 2468 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2469 | { |
2470 | PhysPageDesc *p; | |
2471 | ||
2472 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2473 | if (!p) | |
2474 | return IO_MEM_UNASSIGNED; | |
2475 | return p->phys_offset; | |
2476 | } | |
2477 | ||
f65ed4c1 AL |
2478 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
2479 | { | |
2480 | if (kvm_enabled()) | |
2481 | kvm_coalesce_mmio_region(addr, size); | |
2482 | } | |
2483 | ||
2484 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) | |
2485 | { | |
2486 | if (kvm_enabled()) | |
2487 | kvm_uncoalesce_mmio_region(addr, size); | |
2488 | } | |
2489 | ||
640f42e4 | 2490 | #ifdef CONFIG_KQEMU |
e9a1ab19 | 2491 | /* XXX: better than nothing */ |
94a6b54f | 2492 | static ram_addr_t kqemu_ram_alloc(ram_addr_t size) |
e9a1ab19 FB |
2493 | { |
2494 | ram_addr_t addr; | |
94a6b54f | 2495 | if ((last_ram_offset + size) > kqemu_phys_ram_size) { |
012a7045 | 2496 | fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n", |
94a6b54f | 2497 | (uint64_t)size, (uint64_t)kqemu_phys_ram_size); |
e9a1ab19 FB |
2498 | abort(); |
2499 | } | |
94a6b54f PB |
2500 | addr = last_ram_offset; |
2501 | last_ram_offset = TARGET_PAGE_ALIGN(last_ram_offset + size); | |
e9a1ab19 FB |
2502 | return addr; |
2503 | } | |
94a6b54f PB |
2504 | #endif |
2505 | ||
2506 | ram_addr_t qemu_ram_alloc(ram_addr_t size) | |
2507 | { | |
2508 | RAMBlock *new_block; | |
2509 | ||
640f42e4 | 2510 | #ifdef CONFIG_KQEMU |
94a6b54f PB |
2511 | if (kqemu_phys_ram_base) { |
2512 | return kqemu_ram_alloc(size); | |
2513 | } | |
2514 | #endif | |
2515 | ||
2516 | size = TARGET_PAGE_ALIGN(size); | |
2517 | new_block = qemu_malloc(sizeof(*new_block)); | |
2518 | ||
2519 | new_block->host = qemu_vmalloc(size); | |
2520 | new_block->offset = last_ram_offset; | |
2521 | new_block->length = size; | |
2522 | ||
2523 | new_block->next = ram_blocks; | |
2524 | ram_blocks = new_block; | |
2525 | ||
2526 | phys_ram_dirty = qemu_realloc(phys_ram_dirty, | |
2527 | (last_ram_offset + size) >> TARGET_PAGE_BITS); | |
2528 | memset(phys_ram_dirty + (last_ram_offset >> TARGET_PAGE_BITS), | |
2529 | 0xff, size >> TARGET_PAGE_BITS); | |
2530 | ||
2531 | last_ram_offset += size; | |
2532 | ||
6f0437e8 JK |
2533 | if (kvm_enabled()) |
2534 | kvm_setup_guest_memory(new_block->host, size); | |
2535 | ||
94a6b54f PB |
2536 | return new_block->offset; |
2537 | } | |
e9a1ab19 FB |
2538 | |
2539 | void qemu_ram_free(ram_addr_t addr) | |
2540 | { | |
94a6b54f | 2541 | /* TODO: implement this. */ |
e9a1ab19 FB |
2542 | } |
2543 | ||
dc828ca1 | 2544 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
5579c7f3 PB |
2545 | With the exception of the softmmu code in this file, this should |
2546 | only be used for local memory (e.g. video ram) that the device owns, | |
2547 | and knows it isn't going to access beyond the end of the block. | |
2548 | ||
2549 | It should not be used for general purpose DMA. | |
2550 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
2551 | */ | |
dc828ca1 PB |
2552 | void *qemu_get_ram_ptr(ram_addr_t addr) |
2553 | { | |
94a6b54f PB |
2554 | RAMBlock *prev; |
2555 | RAMBlock **prevp; | |
2556 | RAMBlock *block; | |
2557 | ||
640f42e4 | 2558 | #ifdef CONFIG_KQEMU |
94a6b54f PB |
2559 | if (kqemu_phys_ram_base) { |
2560 | return kqemu_phys_ram_base + addr; | |
2561 | } | |
2562 | #endif | |
2563 | ||
2564 | prev = NULL; | |
2565 | prevp = &ram_blocks; | |
2566 | block = ram_blocks; | |
2567 | while (block && (block->offset > addr | |
2568 | || block->offset + block->length <= addr)) { | |
2569 | if (prev) | |
2570 | prevp = &prev->next; | |
2571 | prev = block; | |
2572 | block = block->next; | |
2573 | } | |
2574 | if (!block) { | |
2575 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
2576 | abort(); | |
2577 | } | |
2578 | /* Move this entry to to start of the list. */ | |
2579 | if (prev) { | |
2580 | prev->next = block->next; | |
2581 | block->next = *prevp; | |
2582 | *prevp = block; | |
2583 | } | |
2584 | return block->host + (addr - block->offset); | |
dc828ca1 PB |
2585 | } |
2586 | ||
5579c7f3 PB |
2587 | /* Some of the softmmu routines need to translate from a host pointer |
2588 | (typically a TLB entry) back to a ram offset. */ | |
2589 | ram_addr_t qemu_ram_addr_from_host(void *ptr) | |
2590 | { | |
94a6b54f PB |
2591 | RAMBlock *prev; |
2592 | RAMBlock **prevp; | |
2593 | RAMBlock *block; | |
2594 | uint8_t *host = ptr; | |
2595 | ||
640f42e4 | 2596 | #ifdef CONFIG_KQEMU |
94a6b54f PB |
2597 | if (kqemu_phys_ram_base) { |
2598 | return host - kqemu_phys_ram_base; | |
2599 | } | |
2600 | #endif | |
2601 | ||
2602 | prev = NULL; | |
2603 | prevp = &ram_blocks; | |
2604 | block = ram_blocks; | |
2605 | while (block && (block->host > host | |
2606 | || block->host + block->length <= host)) { | |
2607 | if (prev) | |
2608 | prevp = &prev->next; | |
2609 | prev = block; | |
2610 | block = block->next; | |
2611 | } | |
2612 | if (!block) { | |
2613 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
2614 | abort(); | |
2615 | } | |
2616 | return block->offset + (host - block->host); | |
5579c7f3 PB |
2617 | } |
2618 | ||
a4193c8a | 2619 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 2620 | { |
67d3b957 | 2621 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2622 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 | 2623 | #endif |
0a6f8a6d | 2624 | #if defined(TARGET_SPARC) |
e18231a3 BS |
2625 | do_unassigned_access(addr, 0, 0, 0, 1); |
2626 | #endif | |
2627 | return 0; | |
2628 | } | |
2629 | ||
2630 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) | |
2631 | { | |
2632 | #ifdef DEBUG_UNASSIGNED | |
2633 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2634 | #endif | |
0a6f8a6d | 2635 | #if defined(TARGET_SPARC) |
e18231a3 BS |
2636 | do_unassigned_access(addr, 0, 0, 0, 2); |
2637 | #endif | |
2638 | return 0; | |
2639 | } | |
2640 | ||
2641 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) | |
2642 | { | |
2643 | #ifdef DEBUG_UNASSIGNED | |
2644 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2645 | #endif | |
0a6f8a6d | 2646 | #if defined(TARGET_SPARC) |
e18231a3 | 2647 | do_unassigned_access(addr, 0, 0, 0, 4); |
67d3b957 | 2648 | #endif |
33417e70 FB |
2649 | return 0; |
2650 | } | |
2651 | ||
a4193c8a | 2652 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 2653 | { |
67d3b957 | 2654 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2655 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 2656 | #endif |
0a6f8a6d | 2657 | #if defined(TARGET_SPARC) |
e18231a3 BS |
2658 | do_unassigned_access(addr, 1, 0, 0, 1); |
2659 | #endif | |
2660 | } | |
2661 | ||
2662 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | |
2663 | { | |
2664 | #ifdef DEBUG_UNASSIGNED | |
2665 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2666 | #endif | |
0a6f8a6d | 2667 | #if defined(TARGET_SPARC) |
e18231a3 BS |
2668 | do_unassigned_access(addr, 1, 0, 0, 2); |
2669 | #endif | |
2670 | } | |
2671 | ||
2672 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
2673 | { | |
2674 | #ifdef DEBUG_UNASSIGNED | |
2675 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2676 | #endif | |
0a6f8a6d | 2677 | #if defined(TARGET_SPARC) |
e18231a3 | 2678 | do_unassigned_access(addr, 1, 0, 0, 4); |
b4f0a316 | 2679 | #endif |
33417e70 FB |
2680 | } |
2681 | ||
2682 | static CPUReadMemoryFunc *unassigned_mem_read[3] = { | |
2683 | unassigned_mem_readb, | |
e18231a3 BS |
2684 | unassigned_mem_readw, |
2685 | unassigned_mem_readl, | |
33417e70 FB |
2686 | }; |
2687 | ||
2688 | static CPUWriteMemoryFunc *unassigned_mem_write[3] = { | |
2689 | unassigned_mem_writeb, | |
e18231a3 BS |
2690 | unassigned_mem_writew, |
2691 | unassigned_mem_writel, | |
33417e70 FB |
2692 | }; |
2693 | ||
0f459d16 PB |
2694 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
2695 | uint32_t val) | |
9fa3e853 | 2696 | { |
3a7d929e | 2697 | int dirty_flags; |
3a7d929e FB |
2698 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2699 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2700 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2701 | tb_invalidate_phys_page_fast(ram_addr, 1); |
2702 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2703 | #endif |
3a7d929e | 2704 | } |
5579c7f3 | 2705 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
640f42e4 | 2706 | #ifdef CONFIG_KQEMU |
f32fc648 FB |
2707 | if (cpu_single_env->kqemu_enabled && |
2708 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) | |
2709 | kqemu_modify_page(cpu_single_env, ram_addr); | |
2710 | #endif | |
f23db169 FB |
2711 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2712 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2713 | /* we remove the notdirty callback only if the code has been | |
2714 | flushed */ | |
2715 | if (dirty_flags == 0xff) | |
2e70f6ef | 2716 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2717 | } |
2718 | ||
0f459d16 PB |
2719 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
2720 | uint32_t val) | |
9fa3e853 | 2721 | { |
3a7d929e | 2722 | int dirty_flags; |
3a7d929e FB |
2723 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2724 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2725 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2726 | tb_invalidate_phys_page_fast(ram_addr, 2); |
2727 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2728 | #endif |
3a7d929e | 2729 | } |
5579c7f3 | 2730 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
640f42e4 | 2731 | #ifdef CONFIG_KQEMU |
f32fc648 FB |
2732 | if (cpu_single_env->kqemu_enabled && |
2733 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) | |
2734 | kqemu_modify_page(cpu_single_env, ram_addr); | |
2735 | #endif | |
f23db169 FB |
2736 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2737 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2738 | /* we remove the notdirty callback only if the code has been | |
2739 | flushed */ | |
2740 | if (dirty_flags == 0xff) | |
2e70f6ef | 2741 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2742 | } |
2743 | ||
0f459d16 PB |
2744 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
2745 | uint32_t val) | |
9fa3e853 | 2746 | { |
3a7d929e | 2747 | int dirty_flags; |
3a7d929e FB |
2748 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2749 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2750 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2751 | tb_invalidate_phys_page_fast(ram_addr, 4); |
2752 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2753 | #endif |
3a7d929e | 2754 | } |
5579c7f3 | 2755 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
640f42e4 | 2756 | #ifdef CONFIG_KQEMU |
f32fc648 FB |
2757 | if (cpu_single_env->kqemu_enabled && |
2758 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) | |
2759 | kqemu_modify_page(cpu_single_env, ram_addr); | |
2760 | #endif | |
f23db169 FB |
2761 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2762 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2763 | /* we remove the notdirty callback only if the code has been | |
2764 | flushed */ | |
2765 | if (dirty_flags == 0xff) | |
2e70f6ef | 2766 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2767 | } |
2768 | ||
3a7d929e | 2769 | static CPUReadMemoryFunc *error_mem_read[3] = { |
9fa3e853 FB |
2770 | NULL, /* never used */ |
2771 | NULL, /* never used */ | |
2772 | NULL, /* never used */ | |
2773 | }; | |
2774 | ||
1ccde1cb FB |
2775 | static CPUWriteMemoryFunc *notdirty_mem_write[3] = { |
2776 | notdirty_mem_writeb, | |
2777 | notdirty_mem_writew, | |
2778 | notdirty_mem_writel, | |
2779 | }; | |
2780 | ||
0f459d16 | 2781 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 2782 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 PB |
2783 | { |
2784 | CPUState *env = cpu_single_env; | |
06d55cc1 AL |
2785 | target_ulong pc, cs_base; |
2786 | TranslationBlock *tb; | |
0f459d16 | 2787 | target_ulong vaddr; |
a1d1bb31 | 2788 | CPUWatchpoint *wp; |
06d55cc1 | 2789 | int cpu_flags; |
0f459d16 | 2790 | |
06d55cc1 AL |
2791 | if (env->watchpoint_hit) { |
2792 | /* We re-entered the check after replacing the TB. Now raise | |
2793 | * the debug interrupt so that is will trigger after the | |
2794 | * current instruction. */ | |
2795 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
2796 | return; | |
2797 | } | |
2e70f6ef | 2798 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
c0ce998e | 2799 | TAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
2800 | if ((vaddr == (wp->vaddr & len_mask) || |
2801 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
2802 | wp->flags |= BP_WATCHPOINT_HIT; |
2803 | if (!env->watchpoint_hit) { | |
2804 | env->watchpoint_hit = wp; | |
2805 | tb = tb_find_pc(env->mem_io_pc); | |
2806 | if (!tb) { | |
2807 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
2808 | "pc=%p", (void *)env->mem_io_pc); | |
2809 | } | |
2810 | cpu_restore_state(tb, env, env->mem_io_pc, NULL); | |
2811 | tb_phys_invalidate(tb, -1); | |
2812 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
2813 | env->exception_index = EXCP_DEBUG; | |
2814 | } else { | |
2815 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
2816 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
2817 | } | |
2818 | cpu_resume_from_signal(env, NULL); | |
06d55cc1 | 2819 | } |
6e140f28 AL |
2820 | } else { |
2821 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
2822 | } |
2823 | } | |
2824 | } | |
2825 | ||
6658ffb8 PB |
2826 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
2827 | so these check for a hit then pass through to the normal out-of-line | |
2828 | phys routines. */ | |
2829 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) | |
2830 | { | |
b4051334 | 2831 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
6658ffb8 PB |
2832 | return ldub_phys(addr); |
2833 | } | |
2834 | ||
2835 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) | |
2836 | { | |
b4051334 | 2837 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
6658ffb8 PB |
2838 | return lduw_phys(addr); |
2839 | } | |
2840 | ||
2841 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) | |
2842 | { | |
b4051334 | 2843 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
6658ffb8 PB |
2844 | return ldl_phys(addr); |
2845 | } | |
2846 | ||
6658ffb8 PB |
2847 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
2848 | uint32_t val) | |
2849 | { | |
b4051334 | 2850 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
6658ffb8 PB |
2851 | stb_phys(addr, val); |
2852 | } | |
2853 | ||
2854 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, | |
2855 | uint32_t val) | |
2856 | { | |
b4051334 | 2857 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
6658ffb8 PB |
2858 | stw_phys(addr, val); |
2859 | } | |
2860 | ||
2861 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, | |
2862 | uint32_t val) | |
2863 | { | |
b4051334 | 2864 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
6658ffb8 PB |
2865 | stl_phys(addr, val); |
2866 | } | |
2867 | ||
2868 | static CPUReadMemoryFunc *watch_mem_read[3] = { | |
2869 | watch_mem_readb, | |
2870 | watch_mem_readw, | |
2871 | watch_mem_readl, | |
2872 | }; | |
2873 | ||
2874 | static CPUWriteMemoryFunc *watch_mem_write[3] = { | |
2875 | watch_mem_writeb, | |
2876 | watch_mem_writew, | |
2877 | watch_mem_writel, | |
2878 | }; | |
6658ffb8 | 2879 | |
db7b5426 BS |
2880 | static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr, |
2881 | unsigned int len) | |
2882 | { | |
db7b5426 BS |
2883 | uint32_t ret; |
2884 | unsigned int idx; | |
2885 | ||
8da3ff18 | 2886 | idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
2887 | #if defined(DEBUG_SUBPAGE) |
2888 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
2889 | mmio, len, addr, idx); | |
2890 | #endif | |
8da3ff18 PB |
2891 | ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], |
2892 | addr + mmio->region_offset[idx][0][len]); | |
db7b5426 BS |
2893 | |
2894 | return ret; | |
2895 | } | |
2896 | ||
2897 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, | |
2898 | uint32_t value, unsigned int len) | |
2899 | { | |
db7b5426 BS |
2900 | unsigned int idx; |
2901 | ||
8da3ff18 | 2902 | idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
2903 | #if defined(DEBUG_SUBPAGE) |
2904 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__, | |
2905 | mmio, len, addr, idx, value); | |
2906 | #endif | |
8da3ff18 PB |
2907 | (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], |
2908 | addr + mmio->region_offset[idx][1][len], | |
2909 | value); | |
db7b5426 BS |
2910 | } |
2911 | ||
2912 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) | |
2913 | { | |
2914 | #if defined(DEBUG_SUBPAGE) | |
2915 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2916 | #endif | |
2917 | ||
2918 | return subpage_readlen(opaque, addr, 0); | |
2919 | } | |
2920 | ||
2921 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, | |
2922 | uint32_t value) | |
2923 | { | |
2924 | #if defined(DEBUG_SUBPAGE) | |
2925 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2926 | #endif | |
2927 | subpage_writelen(opaque, addr, value, 0); | |
2928 | } | |
2929 | ||
2930 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) | |
2931 | { | |
2932 | #if defined(DEBUG_SUBPAGE) | |
2933 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2934 | #endif | |
2935 | ||
2936 | return subpage_readlen(opaque, addr, 1); | |
2937 | } | |
2938 | ||
2939 | static void subpage_writew (void *opaque, target_phys_addr_t addr, | |
2940 | uint32_t value) | |
2941 | { | |
2942 | #if defined(DEBUG_SUBPAGE) | |
2943 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2944 | #endif | |
2945 | subpage_writelen(opaque, addr, value, 1); | |
2946 | } | |
2947 | ||
2948 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) | |
2949 | { | |
2950 | #if defined(DEBUG_SUBPAGE) | |
2951 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2952 | #endif | |
2953 | ||
2954 | return subpage_readlen(opaque, addr, 2); | |
2955 | } | |
2956 | ||
2957 | static void subpage_writel (void *opaque, | |
2958 | target_phys_addr_t addr, uint32_t value) | |
2959 | { | |
2960 | #if defined(DEBUG_SUBPAGE) | |
2961 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2962 | #endif | |
2963 | subpage_writelen(opaque, addr, value, 2); | |
2964 | } | |
2965 | ||
2966 | static CPUReadMemoryFunc *subpage_read[] = { | |
2967 | &subpage_readb, | |
2968 | &subpage_readw, | |
2969 | &subpage_readl, | |
2970 | }; | |
2971 | ||
2972 | static CPUWriteMemoryFunc *subpage_write[] = { | |
2973 | &subpage_writeb, | |
2974 | &subpage_writew, | |
2975 | &subpage_writel, | |
2976 | }; | |
2977 | ||
2978 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, | |
8da3ff18 | 2979 | ram_addr_t memory, ram_addr_t region_offset) |
db7b5426 BS |
2980 | { |
2981 | int idx, eidx; | |
4254fab8 | 2982 | unsigned int i; |
db7b5426 BS |
2983 | |
2984 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2985 | return -1; | |
2986 | idx = SUBPAGE_IDX(start); | |
2987 | eidx = SUBPAGE_IDX(end); | |
2988 | #if defined(DEBUG_SUBPAGE) | |
2989 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__, | |
2990 | mmio, start, end, idx, eidx, memory); | |
2991 | #endif | |
2992 | memory >>= IO_MEM_SHIFT; | |
2993 | for (; idx <= eidx; idx++) { | |
4254fab8 | 2994 | for (i = 0; i < 4; i++) { |
3ee89922 BS |
2995 | if (io_mem_read[memory][i]) { |
2996 | mmio->mem_read[idx][i] = &io_mem_read[memory][i]; | |
2997 | mmio->opaque[idx][0][i] = io_mem_opaque[memory]; | |
8da3ff18 | 2998 | mmio->region_offset[idx][0][i] = region_offset; |
3ee89922 BS |
2999 | } |
3000 | if (io_mem_write[memory][i]) { | |
3001 | mmio->mem_write[idx][i] = &io_mem_write[memory][i]; | |
3002 | mmio->opaque[idx][1][i] = io_mem_opaque[memory]; | |
8da3ff18 | 3003 | mmio->region_offset[idx][1][i] = region_offset; |
3ee89922 | 3004 | } |
4254fab8 | 3005 | } |
db7b5426 BS |
3006 | } |
3007 | ||
3008 | return 0; | |
3009 | } | |
3010 | ||
00f82b8a | 3011 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
8da3ff18 | 3012 | ram_addr_t orig_memory, ram_addr_t region_offset) |
db7b5426 BS |
3013 | { |
3014 | subpage_t *mmio; | |
3015 | int subpage_memory; | |
3016 | ||
3017 | mmio = qemu_mallocz(sizeof(subpage_t)); | |
1eec614b AL |
3018 | |
3019 | mmio->base = base; | |
1eed09cb | 3020 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio); |
db7b5426 | 3021 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
3022 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
3023 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 3024 | #endif |
1eec614b AL |
3025 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
3026 | subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory, | |
8da3ff18 | 3027 | region_offset); |
db7b5426 BS |
3028 | |
3029 | return mmio; | |
3030 | } | |
3031 | ||
88715657 AL |
3032 | static int get_free_io_mem_idx(void) |
3033 | { | |
3034 | int i; | |
3035 | ||
3036 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
3037 | if (!io_mem_used[i]) { | |
3038 | io_mem_used[i] = 1; | |
3039 | return i; | |
3040 | } | |
3041 | ||
3042 | return -1; | |
3043 | } | |
3044 | ||
33417e70 FB |
3045 | /* mem_read and mem_write are arrays of functions containing the |
3046 | function to access byte (index 0), word (index 1) and dword (index | |
0b4e6e3e | 3047 | 2). Functions can be omitted with a NULL function pointer. |
3ee89922 | 3048 | If io_index is non zero, the corresponding io zone is |
4254fab8 BS |
3049 | modified. If it is zero, a new io zone is allocated. The return |
3050 | value can be used with cpu_register_physical_memory(). (-1) is | |
3051 | returned if error. */ | |
1eed09cb AK |
3052 | static int cpu_register_io_memory_fixed(int io_index, |
3053 | CPUReadMemoryFunc **mem_read, | |
3054 | CPUWriteMemoryFunc **mem_write, | |
3055 | void *opaque) | |
33417e70 | 3056 | { |
4254fab8 | 3057 | int i, subwidth = 0; |
33417e70 FB |
3058 | |
3059 | if (io_index <= 0) { | |
88715657 AL |
3060 | io_index = get_free_io_mem_idx(); |
3061 | if (io_index == -1) | |
3062 | return io_index; | |
33417e70 | 3063 | } else { |
1eed09cb | 3064 | io_index >>= IO_MEM_SHIFT; |
33417e70 FB |
3065 | if (io_index >= IO_MEM_NB_ENTRIES) |
3066 | return -1; | |
3067 | } | |
b5ff1b31 | 3068 | |
33417e70 | 3069 | for(i = 0;i < 3; i++) { |
4254fab8 BS |
3070 | if (!mem_read[i] || !mem_write[i]) |
3071 | subwidth = IO_MEM_SUBWIDTH; | |
33417e70 FB |
3072 | io_mem_read[io_index][i] = mem_read[i]; |
3073 | io_mem_write[io_index][i] = mem_write[i]; | |
3074 | } | |
a4193c8a | 3075 | io_mem_opaque[io_index] = opaque; |
4254fab8 | 3076 | return (io_index << IO_MEM_SHIFT) | subwidth; |
33417e70 | 3077 | } |
61382a50 | 3078 | |
1eed09cb AK |
3079 | int cpu_register_io_memory(CPUReadMemoryFunc **mem_read, |
3080 | CPUWriteMemoryFunc **mem_write, | |
3081 | void *opaque) | |
3082 | { | |
3083 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque); | |
3084 | } | |
3085 | ||
88715657 AL |
3086 | void cpu_unregister_io_memory(int io_table_address) |
3087 | { | |
3088 | int i; | |
3089 | int io_index = io_table_address >> IO_MEM_SHIFT; | |
3090 | ||
3091 | for (i=0;i < 3; i++) { | |
3092 | io_mem_read[io_index][i] = unassigned_mem_read[i]; | |
3093 | io_mem_write[io_index][i] = unassigned_mem_write[i]; | |
3094 | } | |
3095 | io_mem_opaque[io_index] = NULL; | |
3096 | io_mem_used[io_index] = 0; | |
3097 | } | |
3098 | ||
e9179ce1 AK |
3099 | static void io_mem_init(void) |
3100 | { | |
3101 | int i; | |
3102 | ||
3103 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL); | |
3104 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL); | |
3105 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL); | |
3106 | for (i=0; i<5; i++) | |
3107 | io_mem_used[i] = 1; | |
3108 | ||
3109 | io_mem_watch = cpu_register_io_memory(watch_mem_read, | |
3110 | watch_mem_write, NULL); | |
3111 | #ifdef CONFIG_KQEMU | |
3112 | if (kqemu_phys_ram_base) { | |
3113 | /* alloc dirty bits array */ | |
3114 | phys_ram_dirty = qemu_vmalloc(kqemu_phys_ram_size >> TARGET_PAGE_BITS); | |
3115 | memset(phys_ram_dirty, 0xff, kqemu_phys_ram_size >> TARGET_PAGE_BITS); | |
3116 | } | |
3117 | #endif | |
3118 | } | |
3119 | ||
e2eef170 PB |
3120 | #endif /* !defined(CONFIG_USER_ONLY) */ |
3121 | ||
13eb76e0 FB |
3122 | /* physical memory access (slow version, mainly for debug) */ |
3123 | #if defined(CONFIG_USER_ONLY) | |
5fafdf24 | 3124 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3125 | int len, int is_write) |
3126 | { | |
3127 | int l, flags; | |
3128 | target_ulong page; | |
53a5960a | 3129 | void * p; |
13eb76e0 FB |
3130 | |
3131 | while (len > 0) { | |
3132 | page = addr & TARGET_PAGE_MASK; | |
3133 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3134 | if (l > len) | |
3135 | l = len; | |
3136 | flags = page_get_flags(page); | |
3137 | if (!(flags & PAGE_VALID)) | |
3138 | return; | |
3139 | if (is_write) { | |
3140 | if (!(flags & PAGE_WRITE)) | |
3141 | return; | |
579a97f7 | 3142 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3143 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
579a97f7 FB |
3144 | /* FIXME - should this return an error rather than just fail? */ |
3145 | return; | |
72fb7daa AJ |
3146 | memcpy(p, buf, l); |
3147 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3148 | } else { |
3149 | if (!(flags & PAGE_READ)) | |
3150 | return; | |
579a97f7 | 3151 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3152 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
579a97f7 FB |
3153 | /* FIXME - should this return an error rather than just fail? */ |
3154 | return; | |
72fb7daa | 3155 | memcpy(buf, p, l); |
5b257578 | 3156 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3157 | } |
3158 | len -= l; | |
3159 | buf += l; | |
3160 | addr += l; | |
3161 | } | |
3162 | } | |
8df1cd07 | 3163 | |
13eb76e0 | 3164 | #else |
5fafdf24 | 3165 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3166 | int len, int is_write) |
3167 | { | |
3168 | int l, io_index; | |
3169 | uint8_t *ptr; | |
3170 | uint32_t val; | |
2e12669a FB |
3171 | target_phys_addr_t page; |
3172 | unsigned long pd; | |
92e873b9 | 3173 | PhysPageDesc *p; |
3b46e624 | 3174 | |
13eb76e0 FB |
3175 | while (len > 0) { |
3176 | page = addr & TARGET_PAGE_MASK; | |
3177 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3178 | if (l > len) | |
3179 | l = len; | |
92e873b9 | 3180 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
3181 | if (!p) { |
3182 | pd = IO_MEM_UNASSIGNED; | |
3183 | } else { | |
3184 | pd = p->phys_offset; | |
3185 | } | |
3b46e624 | 3186 | |
13eb76e0 | 3187 | if (is_write) { |
3a7d929e | 3188 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
6c2934db | 3189 | target_phys_addr_t addr1 = addr; |
13eb76e0 | 3190 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 | 3191 | if (p) |
6c2934db | 3192 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
6a00d601 FB |
3193 | /* XXX: could force cpu_single_env to NULL to avoid |
3194 | potential bugs */ | |
6c2934db | 3195 | if (l >= 4 && ((addr1 & 3) == 0)) { |
1c213d19 | 3196 | /* 32 bit write access */ |
c27004ec | 3197 | val = ldl_p(buf); |
6c2934db | 3198 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
13eb76e0 | 3199 | l = 4; |
6c2934db | 3200 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
1c213d19 | 3201 | /* 16 bit write access */ |
c27004ec | 3202 | val = lduw_p(buf); |
6c2934db | 3203 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3204 | l = 2; |
3205 | } else { | |
1c213d19 | 3206 | /* 8 bit write access */ |
c27004ec | 3207 | val = ldub_p(buf); |
6c2934db | 3208 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3209 | l = 1; |
3210 | } | |
3211 | } else { | |
b448f2f3 FB |
3212 | unsigned long addr1; |
3213 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 3214 | /* RAM case */ |
5579c7f3 | 3215 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 3216 | memcpy(ptr, buf, l); |
3a7d929e FB |
3217 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3218 | /* invalidate code */ | |
3219 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3220 | /* set dirty bit */ | |
5fafdf24 | 3221 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
f23db169 | 3222 | (0xff & ~CODE_DIRTY_FLAG); |
3a7d929e | 3223 | } |
13eb76e0 FB |
3224 | } |
3225 | } else { | |
5fafdf24 | 3226 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3227 | !(pd & IO_MEM_ROMD)) { |
6c2934db | 3228 | target_phys_addr_t addr1 = addr; |
13eb76e0 FB |
3229 | /* I/O case */ |
3230 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 | 3231 | if (p) |
6c2934db AJ |
3232 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
3233 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
13eb76e0 | 3234 | /* 32 bit read access */ |
6c2934db | 3235 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
c27004ec | 3236 | stl_p(buf, val); |
13eb76e0 | 3237 | l = 4; |
6c2934db | 3238 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
13eb76e0 | 3239 | /* 16 bit read access */ |
6c2934db | 3240 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
c27004ec | 3241 | stw_p(buf, val); |
13eb76e0 FB |
3242 | l = 2; |
3243 | } else { | |
1c213d19 | 3244 | /* 8 bit read access */ |
6c2934db | 3245 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
c27004ec | 3246 | stb_p(buf, val); |
13eb76e0 FB |
3247 | l = 1; |
3248 | } | |
3249 | } else { | |
3250 | /* RAM case */ | |
5579c7f3 | 3251 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
13eb76e0 FB |
3252 | (addr & ~TARGET_PAGE_MASK); |
3253 | memcpy(buf, ptr, l); | |
3254 | } | |
3255 | } | |
3256 | len -= l; | |
3257 | buf += l; | |
3258 | addr += l; | |
3259 | } | |
3260 | } | |
8df1cd07 | 3261 | |
d0ecd2aa | 3262 | /* used for ROM loading : can write in RAM and ROM */ |
5fafdf24 | 3263 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
3264 | const uint8_t *buf, int len) |
3265 | { | |
3266 | int l; | |
3267 | uint8_t *ptr; | |
3268 | target_phys_addr_t page; | |
3269 | unsigned long pd; | |
3270 | PhysPageDesc *p; | |
3b46e624 | 3271 | |
d0ecd2aa FB |
3272 | while (len > 0) { |
3273 | page = addr & TARGET_PAGE_MASK; | |
3274 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3275 | if (l > len) | |
3276 | l = len; | |
3277 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3278 | if (!p) { | |
3279 | pd = IO_MEM_UNASSIGNED; | |
3280 | } else { | |
3281 | pd = p->phys_offset; | |
3282 | } | |
3b46e624 | 3283 | |
d0ecd2aa | 3284 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
3285 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
3286 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
3287 | /* do nothing */ |
3288 | } else { | |
3289 | unsigned long addr1; | |
3290 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3291 | /* ROM/RAM case */ | |
5579c7f3 | 3292 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa FB |
3293 | memcpy(ptr, buf, l); |
3294 | } | |
3295 | len -= l; | |
3296 | buf += l; | |
3297 | addr += l; | |
3298 | } | |
3299 | } | |
3300 | ||
6d16c2f8 AL |
3301 | typedef struct { |
3302 | void *buffer; | |
3303 | target_phys_addr_t addr; | |
3304 | target_phys_addr_t len; | |
3305 | } BounceBuffer; | |
3306 | ||
3307 | static BounceBuffer bounce; | |
3308 | ||
ba223c29 AL |
3309 | typedef struct MapClient { |
3310 | void *opaque; | |
3311 | void (*callback)(void *opaque); | |
3312 | LIST_ENTRY(MapClient) link; | |
3313 | } MapClient; | |
3314 | ||
3315 | static LIST_HEAD(map_client_list, MapClient) map_client_list | |
3316 | = LIST_HEAD_INITIALIZER(map_client_list); | |
3317 | ||
3318 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
3319 | { | |
3320 | MapClient *client = qemu_malloc(sizeof(*client)); | |
3321 | ||
3322 | client->opaque = opaque; | |
3323 | client->callback = callback; | |
3324 | LIST_INSERT_HEAD(&map_client_list, client, link); | |
3325 | return client; | |
3326 | } | |
3327 | ||
3328 | void cpu_unregister_map_client(void *_client) | |
3329 | { | |
3330 | MapClient *client = (MapClient *)_client; | |
3331 | ||
3332 | LIST_REMOVE(client, link); | |
3333 | } | |
3334 | ||
3335 | static void cpu_notify_map_clients(void) | |
3336 | { | |
3337 | MapClient *client; | |
3338 | ||
3339 | while (!LIST_EMPTY(&map_client_list)) { | |
3340 | client = LIST_FIRST(&map_client_list); | |
3341 | client->callback(client->opaque); | |
3342 | LIST_REMOVE(client, link); | |
3343 | } | |
3344 | } | |
3345 | ||
6d16c2f8 AL |
3346 | /* Map a physical memory region into a host virtual address. |
3347 | * May map a subset of the requested range, given by and returned in *plen. | |
3348 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3349 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3350 | * Use cpu_register_map_client() to know when retrying the map operation is |
3351 | * likely to succeed. | |
6d16c2f8 AL |
3352 | */ |
3353 | void *cpu_physical_memory_map(target_phys_addr_t addr, | |
3354 | target_phys_addr_t *plen, | |
3355 | int is_write) | |
3356 | { | |
3357 | target_phys_addr_t len = *plen; | |
3358 | target_phys_addr_t done = 0; | |
3359 | int l; | |
3360 | uint8_t *ret = NULL; | |
3361 | uint8_t *ptr; | |
3362 | target_phys_addr_t page; | |
3363 | unsigned long pd; | |
3364 | PhysPageDesc *p; | |
3365 | unsigned long addr1; | |
3366 | ||
3367 | while (len > 0) { | |
3368 | page = addr & TARGET_PAGE_MASK; | |
3369 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3370 | if (l > len) | |
3371 | l = len; | |
3372 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3373 | if (!p) { | |
3374 | pd = IO_MEM_UNASSIGNED; | |
3375 | } else { | |
3376 | pd = p->phys_offset; | |
3377 | } | |
3378 | ||
3379 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3380 | if (done || bounce.buffer) { | |
3381 | break; | |
3382 | } | |
3383 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
3384 | bounce.addr = addr; | |
3385 | bounce.len = l; | |
3386 | if (!is_write) { | |
3387 | cpu_physical_memory_rw(addr, bounce.buffer, l, 0); | |
3388 | } | |
3389 | ptr = bounce.buffer; | |
3390 | } else { | |
3391 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
5579c7f3 | 3392 | ptr = qemu_get_ram_ptr(addr1); |
6d16c2f8 AL |
3393 | } |
3394 | if (!done) { | |
3395 | ret = ptr; | |
3396 | } else if (ret + done != ptr) { | |
3397 | break; | |
3398 | } | |
3399 | ||
3400 | len -= l; | |
3401 | addr += l; | |
3402 | done += l; | |
3403 | } | |
3404 | *plen = done; | |
3405 | return ret; | |
3406 | } | |
3407 | ||
3408 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
3409 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
3410 | * the amount of memory that was actually read or written by the caller. | |
3411 | */ | |
3412 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, | |
3413 | int is_write, target_phys_addr_t access_len) | |
3414 | { | |
3415 | if (buffer != bounce.buffer) { | |
3416 | if (is_write) { | |
5579c7f3 | 3417 | ram_addr_t addr1 = qemu_ram_addr_from_host(buffer); |
6d16c2f8 AL |
3418 | while (access_len) { |
3419 | unsigned l; | |
3420 | l = TARGET_PAGE_SIZE; | |
3421 | if (l > access_len) | |
3422 | l = access_len; | |
3423 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3424 | /* invalidate code */ | |
3425 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3426 | /* set dirty bit */ | |
3427 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= | |
3428 | (0xff & ~CODE_DIRTY_FLAG); | |
3429 | } | |
3430 | addr1 += l; | |
3431 | access_len -= l; | |
3432 | } | |
3433 | } | |
3434 | return; | |
3435 | } | |
3436 | if (is_write) { | |
3437 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
3438 | } | |
3439 | qemu_free(bounce.buffer); | |
3440 | bounce.buffer = NULL; | |
ba223c29 | 3441 | cpu_notify_map_clients(); |
6d16c2f8 | 3442 | } |
d0ecd2aa | 3443 | |
8df1cd07 FB |
3444 | /* warning: addr must be aligned */ |
3445 | uint32_t ldl_phys(target_phys_addr_t addr) | |
3446 | { | |
3447 | int io_index; | |
3448 | uint8_t *ptr; | |
3449 | uint32_t val; | |
3450 | unsigned long pd; | |
3451 | PhysPageDesc *p; | |
3452 | ||
3453 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3454 | if (!p) { | |
3455 | pd = IO_MEM_UNASSIGNED; | |
3456 | } else { | |
3457 | pd = p->phys_offset; | |
3458 | } | |
3b46e624 | 3459 | |
5fafdf24 | 3460 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3461 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
3462 | /* I/O case */ |
3463 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3464 | if (p) |
3465 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3466 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
3467 | } else { | |
3468 | /* RAM case */ | |
5579c7f3 | 3469 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
3470 | (addr & ~TARGET_PAGE_MASK); |
3471 | val = ldl_p(ptr); | |
3472 | } | |
3473 | return val; | |
3474 | } | |
3475 | ||
84b7b8e7 FB |
3476 | /* warning: addr must be aligned */ |
3477 | uint64_t ldq_phys(target_phys_addr_t addr) | |
3478 | { | |
3479 | int io_index; | |
3480 | uint8_t *ptr; | |
3481 | uint64_t val; | |
3482 | unsigned long pd; | |
3483 | PhysPageDesc *p; | |
3484 | ||
3485 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3486 | if (!p) { | |
3487 | pd = IO_MEM_UNASSIGNED; | |
3488 | } else { | |
3489 | pd = p->phys_offset; | |
3490 | } | |
3b46e624 | 3491 | |
2a4188a3 FB |
3492 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
3493 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
3494 | /* I/O case */ |
3495 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3496 | if (p) |
3497 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
84b7b8e7 FB |
3498 | #ifdef TARGET_WORDS_BIGENDIAN |
3499 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
3500 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
3501 | #else | |
3502 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
3503 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
3504 | #endif | |
3505 | } else { | |
3506 | /* RAM case */ | |
5579c7f3 | 3507 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
3508 | (addr & ~TARGET_PAGE_MASK); |
3509 | val = ldq_p(ptr); | |
3510 | } | |
3511 | return val; | |
3512 | } | |
3513 | ||
aab33094 FB |
3514 | /* XXX: optimize */ |
3515 | uint32_t ldub_phys(target_phys_addr_t addr) | |
3516 | { | |
3517 | uint8_t val; | |
3518 | cpu_physical_memory_read(addr, &val, 1); | |
3519 | return val; | |
3520 | } | |
3521 | ||
3522 | /* XXX: optimize */ | |
3523 | uint32_t lduw_phys(target_phys_addr_t addr) | |
3524 | { | |
3525 | uint16_t val; | |
3526 | cpu_physical_memory_read(addr, (uint8_t *)&val, 2); | |
3527 | return tswap16(val); | |
3528 | } | |
3529 | ||
8df1cd07 FB |
3530 | /* warning: addr must be aligned. The ram page is not masked as dirty |
3531 | and the code inside is not invalidated. It is useful if the dirty | |
3532 | bits are used to track modified PTEs */ | |
3533 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) | |
3534 | { | |
3535 | int io_index; | |
3536 | uint8_t *ptr; | |
3537 | unsigned long pd; | |
3538 | PhysPageDesc *p; | |
3539 | ||
3540 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3541 | if (!p) { | |
3542 | pd = IO_MEM_UNASSIGNED; | |
3543 | } else { | |
3544 | pd = p->phys_offset; | |
3545 | } | |
3b46e624 | 3546 | |
3a7d929e | 3547 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3548 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3549 | if (p) |
3550 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3551 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3552 | } else { | |
74576198 | 3553 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
5579c7f3 | 3554 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3555 | stl_p(ptr, val); |
74576198 AL |
3556 | |
3557 | if (unlikely(in_migration)) { | |
3558 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3559 | /* invalidate code */ | |
3560 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3561 | /* set dirty bit */ | |
3562 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= | |
3563 | (0xff & ~CODE_DIRTY_FLAG); | |
3564 | } | |
3565 | } | |
8df1cd07 FB |
3566 | } |
3567 | } | |
3568 | ||
bc98a7ef JM |
3569 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
3570 | { | |
3571 | int io_index; | |
3572 | uint8_t *ptr; | |
3573 | unsigned long pd; | |
3574 | PhysPageDesc *p; | |
3575 | ||
3576 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3577 | if (!p) { | |
3578 | pd = IO_MEM_UNASSIGNED; | |
3579 | } else { | |
3580 | pd = p->phys_offset; | |
3581 | } | |
3b46e624 | 3582 | |
bc98a7ef JM |
3583 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
3584 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3585 | if (p) |
3586 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
bc98a7ef JM |
3587 | #ifdef TARGET_WORDS_BIGENDIAN |
3588 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
3589 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
3590 | #else | |
3591 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
3592 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
3593 | #endif | |
3594 | } else { | |
5579c7f3 | 3595 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
3596 | (addr & ~TARGET_PAGE_MASK); |
3597 | stq_p(ptr, val); | |
3598 | } | |
3599 | } | |
3600 | ||
8df1cd07 | 3601 | /* warning: addr must be aligned */ |
8df1cd07 FB |
3602 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
3603 | { | |
3604 | int io_index; | |
3605 | uint8_t *ptr; | |
3606 | unsigned long pd; | |
3607 | PhysPageDesc *p; | |
3608 | ||
3609 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3610 | if (!p) { | |
3611 | pd = IO_MEM_UNASSIGNED; | |
3612 | } else { | |
3613 | pd = p->phys_offset; | |
3614 | } | |
3b46e624 | 3615 | |
3a7d929e | 3616 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3617 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3618 | if (p) |
3619 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3620 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3621 | } else { | |
3622 | unsigned long addr1; | |
3623 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3624 | /* RAM case */ | |
5579c7f3 | 3625 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3626 | stl_p(ptr, val); |
3a7d929e FB |
3627 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3628 | /* invalidate code */ | |
3629 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3630 | /* set dirty bit */ | |
f23db169 FB |
3631 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
3632 | (0xff & ~CODE_DIRTY_FLAG); | |
3a7d929e | 3633 | } |
8df1cd07 FB |
3634 | } |
3635 | } | |
3636 | ||
aab33094 FB |
3637 | /* XXX: optimize */ |
3638 | void stb_phys(target_phys_addr_t addr, uint32_t val) | |
3639 | { | |
3640 | uint8_t v = val; | |
3641 | cpu_physical_memory_write(addr, &v, 1); | |
3642 | } | |
3643 | ||
3644 | /* XXX: optimize */ | |
3645 | void stw_phys(target_phys_addr_t addr, uint32_t val) | |
3646 | { | |
3647 | uint16_t v = tswap16(val); | |
3648 | cpu_physical_memory_write(addr, (const uint8_t *)&v, 2); | |
3649 | } | |
3650 | ||
3651 | /* XXX: optimize */ | |
3652 | void stq_phys(target_phys_addr_t addr, uint64_t val) | |
3653 | { | |
3654 | val = tswap64(val); | |
3655 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); | |
3656 | } | |
3657 | ||
13eb76e0 FB |
3658 | #endif |
3659 | ||
5e2972fd | 3660 | /* virtual memory access for debug (includes writing to ROM) */ |
5fafdf24 | 3661 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 3662 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3663 | { |
3664 | int l; | |
9b3c35e0 JM |
3665 | target_phys_addr_t phys_addr; |
3666 | target_ulong page; | |
13eb76e0 FB |
3667 | |
3668 | while (len > 0) { | |
3669 | page = addr & TARGET_PAGE_MASK; | |
3670 | phys_addr = cpu_get_phys_page_debug(env, page); | |
3671 | /* if no physical page mapped, return an error */ | |
3672 | if (phys_addr == -1) | |
3673 | return -1; | |
3674 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3675 | if (l > len) | |
3676 | l = len; | |
5e2972fd AL |
3677 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
3678 | #if !defined(CONFIG_USER_ONLY) | |
3679 | if (is_write) | |
3680 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
3681 | else | |
3682 | #endif | |
3683 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); | |
13eb76e0 FB |
3684 | len -= l; |
3685 | buf += l; | |
3686 | addr += l; | |
3687 | } | |
3688 | return 0; | |
3689 | } | |
3690 | ||
2e70f6ef PB |
3691 | /* in deterministic execution mode, instructions doing device I/Os |
3692 | must be at the end of the TB */ | |
3693 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
3694 | { | |
3695 | TranslationBlock *tb; | |
3696 | uint32_t n, cflags; | |
3697 | target_ulong pc, cs_base; | |
3698 | uint64_t flags; | |
3699 | ||
3700 | tb = tb_find_pc((unsigned long)retaddr); | |
3701 | if (!tb) { | |
3702 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
3703 | retaddr); | |
3704 | } | |
3705 | n = env->icount_decr.u16.low + tb->icount; | |
3706 | cpu_restore_state(tb, env, (unsigned long)retaddr, NULL); | |
3707 | /* Calculate how many instructions had been executed before the fault | |
bf20dc07 | 3708 | occurred. */ |
2e70f6ef PB |
3709 | n = n - env->icount_decr.u16.low; |
3710 | /* Generate a new TB ending on the I/O insn. */ | |
3711 | n++; | |
3712 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
3713 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 3714 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
3715 | branch. */ |
3716 | #if defined(TARGET_MIPS) | |
3717 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
3718 | env->active_tc.PC -= 4; | |
3719 | env->icount_decr.u16.low++; | |
3720 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
3721 | } | |
3722 | #elif defined(TARGET_SH4) | |
3723 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
3724 | && n > 1) { | |
3725 | env->pc -= 2; | |
3726 | env->icount_decr.u16.low++; | |
3727 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
3728 | } | |
3729 | #endif | |
3730 | /* This should never happen. */ | |
3731 | if (n > CF_COUNT_MASK) | |
3732 | cpu_abort(env, "TB too big during recompile"); | |
3733 | ||
3734 | cflags = n | CF_LAST_IO; | |
3735 | pc = tb->pc; | |
3736 | cs_base = tb->cs_base; | |
3737 | flags = tb->flags; | |
3738 | tb_phys_invalidate(tb, -1); | |
3739 | /* FIXME: In theory this could raise an exception. In practice | |
3740 | we have already translated the block once so it's probably ok. */ | |
3741 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 3742 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
3743 | the first in the TB) then we end up generating a whole new TB and |
3744 | repeating the fault, which is horribly inefficient. | |
3745 | Better would be to execute just this insn uncached, or generate a | |
3746 | second new TB. */ | |
3747 | cpu_resume_from_signal(env, NULL); | |
3748 | } | |
3749 | ||
e3db7226 FB |
3750 | void dump_exec_info(FILE *f, |
3751 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
3752 | { | |
3753 | int i, target_code_size, max_target_code_size; | |
3754 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
3755 | TranslationBlock *tb; | |
3b46e624 | 3756 | |
e3db7226 FB |
3757 | target_code_size = 0; |
3758 | max_target_code_size = 0; | |
3759 | cross_page = 0; | |
3760 | direct_jmp_count = 0; | |
3761 | direct_jmp2_count = 0; | |
3762 | for(i = 0; i < nb_tbs; i++) { | |
3763 | tb = &tbs[i]; | |
3764 | target_code_size += tb->size; | |
3765 | if (tb->size > max_target_code_size) | |
3766 | max_target_code_size = tb->size; | |
3767 | if (tb->page_addr[1] != -1) | |
3768 | cross_page++; | |
3769 | if (tb->tb_next_offset[0] != 0xffff) { | |
3770 | direct_jmp_count++; | |
3771 | if (tb->tb_next_offset[1] != 0xffff) { | |
3772 | direct_jmp2_count++; | |
3773 | } | |
3774 | } | |
3775 | } | |
3776 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 3777 | cpu_fprintf(f, "Translation buffer state:\n"); |
26a5f13b FB |
3778 | cpu_fprintf(f, "gen code size %ld/%ld\n", |
3779 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); | |
3780 | cpu_fprintf(f, "TB count %d/%d\n", | |
3781 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 3782 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
3783 | nb_tbs ? target_code_size / nb_tbs : 0, |
3784 | max_target_code_size); | |
5fafdf24 | 3785 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
3786 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
3787 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
3788 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
3789 | cross_page, | |
e3db7226 FB |
3790 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
3791 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 3792 | direct_jmp_count, |
e3db7226 FB |
3793 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
3794 | direct_jmp2_count, | |
3795 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 3796 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
3797 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
3798 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
3799 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 3800 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
3801 | } |
3802 | ||
5fafdf24 | 3803 | #if !defined(CONFIG_USER_ONLY) |
61382a50 FB |
3804 | |
3805 | #define MMUSUFFIX _cmmu | |
3806 | #define GETPC() NULL | |
3807 | #define env cpu_single_env | |
b769d8fe | 3808 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
3809 | |
3810 | #define SHIFT 0 | |
3811 | #include "softmmu_template.h" | |
3812 | ||
3813 | #define SHIFT 1 | |
3814 | #include "softmmu_template.h" | |
3815 | ||
3816 | #define SHIFT 2 | |
3817 | #include "softmmu_template.h" | |
3818 | ||
3819 | #define SHIFT 3 | |
3820 | #include "softmmu_template.h" | |
3821 | ||
3822 | #undef env | |
3823 | ||
3824 | #endif |