[qemu.git] / exec.h

/*
 * internal execution defines for qemu
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];

#if defined(TARGET_I386)

#define GEN_FLAG_CODE32_SHIFT 0
#define GEN_FLAG_ADDSEG_SHIFT 1
#define GEN_FLAG_SS32_SHIFT   2
#define GEN_FLAG_VM_SHIFT     3
#define GEN_FLAG_ST_SHIFT     4
#define GEN_FLAG_TF_SHIFT     8 /* same position as eflags */
#define GEN_FLAG_CPL_SHIFT    9
#define GEN_FLAG_IOPL_SHIFT   12 /* same position as eflags */

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(struct TranslationBlock *tb);
int gen_intermediate_code_pc(struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb, 
                      CPUState *env, unsigned long searched_pc);
void cpu_exec_init(void);
int page_unprotect(unsigned long address);
void page_unmap(void);

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_HASH_BITS     15
#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)

/* maximum total translate dcode allocated */
#define CODE_GEN_BUFFER_SIZE     (2048 * 1024)
//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

#if defined(__powerpc__)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    unsigned long pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    unsigned long cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint8_t *tc_ptr;    /* pointer to the translated code */
    struct TranslationBlock *hash_next; /* next matching block */
    struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */
    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2]; 
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(unsigned long pc);
void tb_flush(void);
void tb_link(TranslationBlock *tb);

extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

/* find a translation block in the translation cache. If not found,
   return NULL and the pointer to the last element of the list in pptb */
static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
                                        unsigned long pc, 
                                        unsigned long cs_base,
                                        unsigned int flags)
{
    TranslationBlock **ptb, *tb;
    unsigned int h;
 
    h = tb_hash_func(pc);
    ptb = &tb_hash[h];
    for(;;) {
        tb = *ptb;
        if (!tb)
            break;
        if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
            return tb;
        ptb = &tb->hash_next;
    }
    *pptb = ptb;
    return NULL;
}

#if defined(__powerpc__)

static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    uint32_t val, *ptr;
    unsigned long offset;

    offset = (unsigned long)(tb->tc_ptr + tb->tb_jmp_offset[n]);

    /* patch the branch destination */
    ptr = (uint32_t *)offset;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - offset) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n, 
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
        
        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(__powerpc__)

/* on PowerPC we patch the jump instruction directly */
#define JUMP_TB(tbparam, n, eip)\
do {\
    static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
    asm volatile ("b %0" : : "i" (&__op_jmp ## n));\
label ## n:\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define JUMP_TB(tbparam, n, eip)\
do {\
    static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n:\
    T0 = (long)(tbparam) + (n);\
    EIP = eip;\
dummy_label ## n:\
} while (0)

#endif

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1 ;"
                          "      xor. %0,%3,%0;"
                          "      bne 1f;"
                          "      stwcx. %2,0,%1;"
                          "      bne- 0b;"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    char ret;
    long int readval;
    
    __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
                          : "=q" (ret), "=m" (*p), "=a" (readval)
                          : "r" (1), "m" (*p), "a" (0)
                          : "memory");
    return ret;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

#ifdef __arm__
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));
    
    return ret;
}
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}

extern spinlock_t tb_lock;
Commit	Line	Data
d4e8164f FB	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
	24	/* is_jmp field values */
	25	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	26	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	27	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	28	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	29
	30	struct TranslationBlock;
	31
	32	/* XXX: make safe guess about sizes */
	33	#define MAX_OP_PER_INSTR 32
	34	#define OPC_BUF_SIZE 512
	35	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	36
	37	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	38
	39	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	40	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
	41	extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
66e85a21	42	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46 FB	43	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
	44
	45	#if defined(TARGET_I386)
	46
d4e8164f FB	47	#define GEN_FLAG_CODE32_SHIFT 0
	48	#define GEN_FLAG_ADDSEG_SHIFT 1
	49	#define GEN_FLAG_SS32_SHIFT 2
	50	#define GEN_FLAG_VM_SHIFT 3
	51	#define GEN_FLAG_ST_SHIFT 4
cf25629d FB	52	#define GEN_FLAG_TF_SHIFT 8 /* same position as eflags */
	53	#define GEN_FLAG_CPL_SHIFT 9
	54	#define GEN_FLAG_IOPL_SHIFT 12 /* same position as eflags */
d4e8164f	55
b346ff46 FB	56	#endif
	57
	58	extern FILE *logfile;
	59	extern int loglevel;
	60
66e85a21 FB	61	int gen_intermediate_code(struct TranslationBlock *tb);
66e85a21 FB	62	int gen_intermediate_code_pc(struct TranslationBlock *tb);
b346ff46 FB	63	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
	64	int cpu_gen_code(struct TranslationBlock *tb,
	65	int max_code_size, int *gen_code_size_ptr);
66e85a21 FB	66	int cpu_restore_state(struct TranslationBlock *tb,
66e85a21 FB	67	CPUState *env, unsigned long searched_pc);
b346ff46	68	void cpu_exec_init(void);
d4e8164f	69	int page_unprotect(unsigned long address);
66e85a21	70	void page_unmap(void);
d4e8164f FB	71
	72	#define CODE_GEN_MAX_SIZE 65536
	73	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	74
	75	#define CODE_GEN_HASH_BITS 15
	76	#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
	77
	78	/* maximum total translate dcode allocated */
	79	#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
	80	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
	81
	82	#if defined(__powerpc__)
	83	#define USE_DIRECT_JUMP
	84	#endif
	85
	86	typedef struct TranslationBlock {
	87	unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
	88	unsigned long cs_base; /* CS base for this block */
	89	unsigned int flags; /* flags defining in which context the code was generated */
	90	uint16_t size; /* size of target code for this block (1 <=
	91	size <= TARGET_PAGE_SIZE) */
	92	uint8_t tc_ptr; / pointer to the translated code */
	93	struct TranslationBlock hash_next; / next matching block */
	94	struct TranslationBlock page_next[2]; / next blocks in even/odd page */
	95	/* the following data are used to directly call another TB from
	96	the code of this one. */
	97	uint16_t tb_next_offset[2]; /* offset of original jump target */
	98	#ifdef USE_DIRECT_JUMP
	99	uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
	100	#else
95f7652d	101	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	102	#endif
	103	/* list of TBs jumping to this one. This is a circular list using
	104	the two least significant bits of the pointers to tell what is
	105	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	106	jmp_first */
	107	struct TranslationBlock *jmp_next[2];
	108	struct TranslationBlock *jmp_first;
	109	} TranslationBlock;
	110
	111	static inline unsigned int tb_hash_func(unsigned long pc)
	112	{
	113	return pc & (CODE_GEN_HASH_SIZE - 1);
	114	}
	115
	116	TranslationBlock *tb_alloc(unsigned long pc);
	117	void tb_flush(void);
	118	void tb_link(TranslationBlock *tb);
	119
	120	extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
	121
	122	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	123	extern uint8_t *code_gen_ptr;
	124
	125	/* find a translation block in the translation cache. If not found,
	126	return NULL and the pointer to the last element of the list in pptb */
	127	static inline TranslationBlock tb_find(TranslationBlock **pptb,
	128	unsigned long pc,
	129	unsigned long cs_base,
	130	unsigned int flags)
	131	{
	132	TranslationBlock *ptb, tb;
	133	unsigned int h;
	134
	135	h = tb_hash_func(pc);
	136	ptb = &tb_hash[h];
	137	for(;;) {
	138	tb = *ptb;
	139	if (!tb)
	140	break;
	141	if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
	142	return tb;
	143	ptb = &tb->hash_next;
	144	}
	145	*pptb = ptb;
	146	return NULL;
	147	}
	148
	149	#if defined(__powerpc__)
	150
	151	static inline void tb_set_jmp_target(TranslationBlock *tb,
	152	int n, unsigned long addr)
	153	{
	154	uint32_t val, *ptr;
	155	unsigned long offset;
	156
	157	offset = (unsigned long)(tb->tc_ptr + tb->tb_jmp_offset[n]);
	158
	159	/* patch the branch destination */
	160	ptr = (uint32_t *)offset;
	161	val = *ptr;
	162	val = (val & ~0x03fffffc) \| ((addr - offset) & 0x03fffffc);
	163	*ptr = val;
	164	/* flush icache */
	165	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
166	asm volatile ("sync" : : : "memory");
167	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
168	asm volatile ("sync" : : : "memory");
169	asm volatile ("isync" : : : "memory");
170	}
171
172	#else
173
174	/* set the jump target */
175	static inline void tb_set_jmp_target(TranslationBlock *tb,
176	int n, unsigned long addr)
177	{
95f7652d	178	tb->tb_next[n] = addr;
d4e8164f FB	179	}
	180
	181	#endif
	182
	183	static inline void tb_add_jump(TranslationBlock *tb, int n,
	184	TranslationBlock *tb_next)
	185	{
cf25629d FB	186	/* NOTE: this test is only needed for thread safety */
	187	if (!tb->jmp_next[n]) {
	188	/* patch the native jump address */
	189	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	190
	191	/* add in TB jmp circular list */
	192	tb->jmp_next[n] = tb_next->jmp_first;
	193	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	194	}
d4e8164f FB	195	}
d4e8164f FB	196
a513fe19 FB	197	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	198
d4e8164f FB	199	#ifndef offsetof
	200	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	201	#endif
	202
b346ff46 FB	203	#if defined(__powerpc__)
	204
	205	/* on PowerPC we patch the jump instruction directly */
	206	#define JUMP_TB(tbparam, n, eip)\
	207	do {\
	208	static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
	209	asm volatile ("b %0" : : "i" (&__op_jmp ## n));\
	210	label ## n:\
	211	T0 = (long)(tbparam) + (n);\
	212	EIP = eip;\
	213	} while (0)
	214
	215	#else
	216
	217	/* jump to next block operations (more portable code, does not need
	218	cache flushing, but slower because of indirect jump) */
	219	#define JUMP_TB(tbparam, n, eip)\
	220	do {\
	221	static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
2f62b397	222	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
b346ff46 FB	223	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
	224	label ## n:\
	225	T0 = (long)(tbparam) + (n);\
	226	EIP = eip;\
2f62b397	227	dummy_label ## n:\
b346ff46 FB	228	} while (0)
	229
	230	#endif
	231
d4e8164f FB	232	#ifdef __powerpc__
	233	static inline int testandset (int *p)
	234	{
	235	int ret;
	236	__asm__ __volatile__ (
	237	"0: lwarx %0,0,%1 ;"
	238	" xor. %0,%3,%0;"
	239	" bne 1f;"
	240	" stwcx. %2,0,%1;"
	241	" bne- 0b;"
	242	"1: "
	243	: "=&r" (ret)
	244	: "r" (p), "r" (1), "r" (0)
	245	: "cr0", "memory");
	246	return ret;
	247	}
	248	#endif
	249
	250	#ifdef __i386__
	251	static inline int testandset (int *p)
	252	{
	253	char ret;
	254	long int readval;
	255
	256	__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
	257	: "=q" (ret), "=m" (*p), "=a" (readval)
	258	: "r" (1), "m" (*p), "a" (0)
	259	: "memory");
	260	return ret;
	261	}
	262	#endif
	263
	264	#ifdef __s390__
	265	static inline int testandset (int *p)
	266	{
	267	int ret;
	268
	269	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	270	" jl 0b"
	271	: "=&d" (ret)
	272	: "r" (1), "a" (p), "0" (*p)
	273	: "cc", "memory" );
	274	return ret;
	275	}
	276	#endif
	277
	278	#ifdef __alpha__
2f87c607	279	static inline int testandset (int *p)
d4e8164f FB	280	{
	281	int ret;
	282	unsigned long one;
	283
	284	__asm__ __volatile__ ("0: mov 1,%2\n"
	285	" ldl_l %0,%1\n"
	286	" stl_c %2,%1\n"
	287	" beq %2,1f\n"
	288	".subsection 2\n"
	289	"1: br 0b\n"
	290	".previous"
	291	: "=r" (ret), "=m" (*p), "=r" (one)
	292	: "m" (*p));
	293	return ret;
	294	}
	295	#endif
	296
	297	#ifdef __sparc__
	298	static inline int testandset (int *p)
	299	{
	300	int ret;
	301
	302	__asm__ __volatile__("ldstub [%1], %0"
	303	: "=r" (ret)
	304	: "r" (p)
	305	: "memory");
	306
	307	return (ret ? 1 : 0);
	308	}
	309	#endif
	310
a95c6790 FB	311	#ifdef __arm__
	312	static inline int testandset (int *spinlock)
	313	{
	314	register unsigned int ret;
	315	__asm__ __volatile__("swp %0, %1, [%2]"
	316	: "=r"(ret)
	317	: "0"(1), "r"(spinlock));
	318
	319	return ret;
	320	}
	321	#endif
	322
d4e8164f FB	323	typedef int spinlock_t;
	324
	325	#define SPIN_LOCK_UNLOCKED 0
	326
	327	static inline void spin_lock(spinlock_t *lock)
	328	{
	329	while (testandset(lock));
	330	}
	331
	332	static inline void spin_unlock(spinlock_t *lock)
	333	{
	334	*lock = 0;
	335	}
	336
	337	static inline int spin_trylock(spinlock_t *lock)
	338	{
	339	return !testandset(lock);
	340	}
	341
	342	extern spinlock_t tb_lock;
	343