]>
Commit | Line | Data |
---|---|---|
93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 | 20 | */ |
83c9f4ca | 21 | #include "hw/hw.h" |
0d09e41a PB |
22 | #include "hw/i386/pc.h" |
23 | #include "hw/isa/apm.h" | |
24 | #include "hw/i2c/pm_smbus.h" | |
83c9f4ca | 25 | #include "hw/pci/pci.h" |
0d09e41a | 26 | #include "hw/acpi/acpi.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
1de7afc9 | 28 | #include "qemu/range.h" |
022c62cb | 29 | #include "exec/ioport.h" |
0d09e41a | 30 | #include "hw/nvram/fw_cfg.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
93d89f63 IY |
32 | |
33 | //#define DEBUG | |
34 | ||
50d8ff8b IY |
35 | #ifdef DEBUG |
36 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
37 | #else | |
38 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
39 | #endif | |
40 | ||
ac404095 | 41 | #define GPE_BASE 0xafe0 |
23910d3f | 42 | #define GPE_LEN 4 |
c177684c GH |
43 | |
44 | #define PCI_HOTPLUG_ADDR 0xae00 | |
45 | #define PCI_HOTPLUG_SIZE 0x000f | |
ba737541 AW |
46 | #define PCI_UP_BASE 0xae00 |
47 | #define PCI_DOWN_BASE 0xae04 | |
ac404095 | 48 | #define PCI_EJ_BASE 0xae08 |
668643b0 | 49 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 50 | |
b8622725 IM |
51 | #define PIIX4_PROC_BASE 0xaf00 |
52 | #define PIIX4_PROC_LEN 32 | |
53 | ||
4441a287 | 54 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
b8622725 | 55 | #define PIIX4_CPU_HOTPLUG_STATUS 4 |
4441a287 | 56 | |
ac404095 | 57 | struct pci_status { |
7faa8075 | 58 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
59 | uint32_t down; |
60 | }; | |
61 | ||
b8622725 IM |
62 | typedef struct CPUStatus { |
63 | uint8_t sts[PIIX4_PROC_LEN]; | |
64 | } CPUStatus; | |
65 | ||
93d89f63 IY |
66 | typedef struct PIIX4PMState { |
67 | PCIDevice dev; | |
56e5b2a1 | 68 | |
af11110b | 69 | MemoryRegion io; |
b65b93f2 | 70 | MemoryRegion io_gpe; |
c177684c | 71 | MemoryRegion io_pci; |
b8622725 | 72 | MemoryRegion io_cpu; |
355bf2e5 | 73 | ACPIREGS ar; |
93d89f63 IY |
74 | |
75 | APMState apm; | |
76 | ||
93d89f63 | 77 | PMSMBus smb; |
e8ec0571 | 78 | uint32_t smb_io_base; |
93d89f63 IY |
79 | |
80 | qemu_irq irq; | |
93d89f63 IY |
81 | qemu_irq smi_irq; |
82 | int kvm_enabled; | |
6141dbfe | 83 | Notifier machine_ready; |
d010f91c | 84 | Notifier powerdown_notifier; |
ac404095 IY |
85 | |
86 | /* for pci hotplug */ | |
ac404095 | 87 | struct pci_status pci0_status; |
668643b0 | 88 | uint32_t pci0_hotplug_enable; |
7faa8075 | 89 | uint32_t pci0_slot_device_present; |
459ae5ea GN |
90 | |
91 | uint8_t disable_s3; | |
92 | uint8_t disable_s4; | |
93 | uint8_t s4_val; | |
b8622725 IM |
94 | |
95 | CPUStatus gpe_cpu; | |
96 | Notifier cpu_added_notifier; | |
93d89f63 IY |
97 | } PIIX4PMState; |
98 | ||
56e5b2a1 GH |
99 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
100 | PCIBus *bus, PIIX4PMState *s); | |
ac404095 | 101 | |
93d89f63 IY |
102 | #define ACPI_ENABLE 0xf1 |
103 | #define ACPI_DISABLE 0xf0 | |
104 | ||
93d89f63 IY |
105 | static void pm_update_sci(PIIX4PMState *s) |
106 | { | |
107 | int sci_level, pmsts; | |
93d89f63 | 108 | |
2886be1b | 109 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 110 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
93d89f63 IY |
111 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
112 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
113 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 114 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
b8622725 IM |
115 | (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & |
116 | (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0); | |
633aa0ac | 117 | |
93d89f63 IY |
118 | qemu_set_irq(s->irq, sci_level); |
119 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 120 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 121 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
122 | } |
123 | ||
355bf2e5 | 124 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 125 | { |
355bf2e5 | 126 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
93d89f63 IY |
127 | pm_update_sci(s); |
128 | } | |
129 | ||
93d89f63 IY |
130 | static void apm_ctrl_changed(uint32_t val, void *arg) |
131 | { | |
132 | PIIX4PMState *s = arg; | |
133 | ||
134 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 135 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 IY |
136 | |
137 | if (s->dev.config[0x5b] & (1 << 1)) { | |
138 | if (s->smi_irq) { | |
139 | qemu_irq_raise(s->smi_irq); | |
140 | } | |
141 | } | |
142 | } | |
143 | ||
93d89f63 IY |
144 | static void pm_io_space_update(PIIX4PMState *s) |
145 | { | |
146 | uint32_t pm_io_base; | |
147 | ||
af11110b GH |
148 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); |
149 | pm_io_base &= 0xffc0; | |
93d89f63 | 150 | |
af11110b GH |
151 | memory_region_transaction_begin(); |
152 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
153 | memory_region_set_address(&s->io, pm_io_base); | |
154 | memory_region_transaction_commit(); | |
93d89f63 IY |
155 | } |
156 | ||
24fe083d GH |
157 | static void smbus_io_space_update(PIIX4PMState *s) |
158 | { | |
159 | s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90)); | |
160 | s->smb_io_base &= 0xffc0; | |
161 | ||
162 | memory_region_transaction_begin(); | |
163 | memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1); | |
164 | memory_region_set_address(&s->smb.io, s->smb_io_base); | |
165 | memory_region_transaction_commit(); | |
93d89f63 IY |
166 | } |
167 | ||
168 | static void pm_write_config(PCIDevice *d, | |
169 | uint32_t address, uint32_t val, int len) | |
170 | { | |
171 | pci_default_write_config(d, address, val, len); | |
24fe083d GH |
172 | if (range_covers_byte(address, len, 0x80) || |
173 | ranges_overlap(address, len, 0x40, 4)) { | |
93d89f63 | 174 | pm_io_space_update((PIIX4PMState *)d); |
24fe083d GH |
175 | } |
176 | if (range_covers_byte(address, len, 0xd2) || | |
177 | ranges_overlap(address, len, 0x90, 4)) { | |
178 | smbus_io_space_update((PIIX4PMState *)d); | |
179 | } | |
93d89f63 IY |
180 | } |
181 | ||
7faa8075 AW |
182 | static void vmstate_pci_status_pre_save(void *opaque) |
183 | { | |
184 | struct pci_status *pci0_status = opaque; | |
185 | PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); | |
186 | ||
187 | /* We no longer track up, so build a safe value for migrating | |
188 | * to a version that still does... of course these might get lost | |
189 | * by an old buggy implementation, but we try. */ | |
190 | pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
191 | } | |
192 | ||
93d89f63 IY |
193 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
194 | { | |
195 | PIIX4PMState *s = opaque; | |
196 | ||
197 | pm_io_space_update(s); | |
198 | return 0; | |
199 | } | |
200 | ||
23910d3f IY |
201 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
202 | { \ | |
203 | .name = (stringify(_field)), \ | |
204 | .version_id = 0, \ | |
23910d3f IY |
205 | .info = &vmstate_info_uint16, \ |
206 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 207 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
208 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
209 | } | |
210 | ||
4cf3e6f3 AW |
211 | static const VMStateDescription vmstate_gpe = { |
212 | .name = "gpe", | |
213 | .version_id = 1, | |
214 | .minimum_version_id = 1, | |
215 | .minimum_version_id_old = 1, | |
216 | .fields = (VMStateField []) { | |
23910d3f IY |
217 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
218 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
219 | VMSTATE_END_OF_LIST() |
220 | } | |
221 | }; | |
222 | ||
223 | static const VMStateDescription vmstate_pci_status = { | |
224 | .name = "pci_status", | |
225 | .version_id = 1, | |
226 | .minimum_version_id = 1, | |
227 | .minimum_version_id_old = 1, | |
7faa8075 | 228 | .pre_save = vmstate_pci_status_pre_save, |
4cf3e6f3 AW |
229 | .fields = (VMStateField []) { |
230 | VMSTATE_UINT32(up, struct pci_status), | |
231 | VMSTATE_UINT32(down, struct pci_status), | |
232 | VMSTATE_END_OF_LIST() | |
233 | } | |
234 | }; | |
235 | ||
b0b873a0 MT |
236 | static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
237 | { | |
238 | PIIX4PMState *s = opaque; | |
239 | int ret, i; | |
240 | uint16_t temp; | |
241 | ||
242 | ret = pci_device_load(&s->dev, f); | |
243 | if (ret < 0) { | |
244 | return ret; | |
245 | } | |
246 | qemu_get_be16s(f, &s->ar.pm1.evt.sts); | |
247 | qemu_get_be16s(f, &s->ar.pm1.evt.en); | |
248 | qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); | |
249 | ||
ded67782 | 250 | ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); |
b0b873a0 MT |
251 | if (ret) { |
252 | return ret; | |
253 | } | |
254 | ||
255 | qemu_get_timer(f, s->ar.tmr.timer); | |
256 | qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); | |
257 | ||
258 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); | |
259 | for (i = 0; i < 3; i++) { | |
260 | qemu_get_be16s(f, &temp); | |
261 | } | |
262 | ||
263 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); | |
264 | for (i = 0; i < 3; i++) { | |
265 | qemu_get_be16s(f, &temp); | |
266 | } | |
267 | ||
ded67782 | 268 | ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1); |
b0b873a0 MT |
269 | return ret; |
270 | } | |
271 | ||
272 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 | |
273 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
274 | * and minimum_version_id to 2 below (which breaks migration from | |
275 | * qemu 1.2). | |
276 | * | |
277 | */ | |
93d89f63 IY |
278 | static const VMStateDescription vmstate_acpi = { |
279 | .name = "piix4_pm", | |
b0b873a0 MT |
280 | .version_id = 3, |
281 | .minimum_version_id = 3, | |
93d89f63 | 282 | .minimum_version_id_old = 1, |
b0b873a0 | 283 | .load_state_old = acpi_load_old, |
93d89f63 IY |
284 | .post_load = vmstate_acpi_post_load, |
285 | .fields = (VMStateField []) { | |
286 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
355bf2e5 GH |
287 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
288 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
289 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 290 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
291 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
292 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
293 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
4cf3e6f3 AW |
294 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
295 | struct pci_status), | |
93d89f63 IY |
296 | VMSTATE_END_OF_LIST() |
297 | } | |
298 | }; | |
299 | ||
7faa8075 AW |
300 | static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) |
301 | { | |
0866aca1 | 302 | BusChild *kid, *next; |
7faa8075 AW |
303 | BusState *bus = qdev_get_parent_bus(&s->dev.qdev); |
304 | int slot = ffs(slots) - 1; | |
54bfa546 | 305 | bool slot_free = true; |
7faa8075 AW |
306 | |
307 | /* Mark request as complete */ | |
308 | s->pci0_status.down &= ~(1U << slot); | |
309 | ||
0866aca1 AL |
310 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
311 | DeviceState *qdev = kid->child; | |
7faa8075 AW |
312 | PCIDevice *dev = PCI_DEVICE(qdev); |
313 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
54bfa546 MT |
314 | if (PCI_SLOT(dev->devfn) == slot) { |
315 | if (pc->no_hotplug) { | |
316 | slot_free = false; | |
317 | } else { | |
318 | qdev_free(qdev); | |
319 | } | |
7faa8075 AW |
320 | } |
321 | } | |
54bfa546 MT |
322 | if (slot_free) { |
323 | s->pci0_slot_device_present &= ~(1U << slot); | |
324 | } | |
7faa8075 AW |
325 | } |
326 | ||
668643b0 MT |
327 | static void piix4_update_hotplug(PIIX4PMState *s) |
328 | { | |
329 | PCIDevice *dev = &s->dev; | |
330 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
0866aca1 | 331 | BusChild *kid, *next; |
668643b0 | 332 | |
7faa8075 AW |
333 | /* Execute any pending removes during reset */ |
334 | while (s->pci0_status.down) { | |
335 | acpi_piix_eject_slot(s, s->pci0_status.down); | |
336 | } | |
337 | ||
668643b0 | 338 | s->pci0_hotplug_enable = ~0; |
7faa8075 | 339 | s->pci0_slot_device_present = 0; |
668643b0 | 340 | |
0866aca1 AL |
341 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
342 | DeviceState *qdev = kid->child; | |
40021f08 AL |
343 | PCIDevice *pdev = PCI_DEVICE(qdev); |
344 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); | |
668643b0 MT |
345 | int slot = PCI_SLOT(pdev->devfn); |
346 | ||
40021f08 | 347 | if (pc->no_hotplug) { |
7faa8075 | 348 | s->pci0_hotplug_enable &= ~(1U << slot); |
668643b0 | 349 | } |
7faa8075 AW |
350 | |
351 | s->pci0_slot_device_present |= (1U << slot); | |
668643b0 MT |
352 | } |
353 | } | |
354 | ||
93d89f63 IY |
355 | static void piix4_reset(void *opaque) |
356 | { | |
357 | PIIX4PMState *s = opaque; | |
358 | uint8_t *pci_conf = s->dev.config; | |
359 | ||
360 | pci_conf[0x58] = 0; | |
361 | pci_conf[0x59] = 0; | |
362 | pci_conf[0x5a] = 0; | |
363 | pci_conf[0x5b] = 0; | |
364 | ||
4d09d37c GN |
365 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
366 | pci_conf[0x80] = 0; | |
367 | ||
93d89f63 IY |
368 | if (s->kvm_enabled) { |
369 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
370 | pci_conf[0x5B] = 0x02; | |
371 | } | |
668643b0 | 372 | piix4_update_hotplug(s); |
93d89f63 IY |
373 | } |
374 | ||
d010f91c | 375 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 376 | { |
d010f91c | 377 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 378 | |
355bf2e5 GH |
379 | assert(s != NULL); |
380 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
381 | } |
382 | ||
9e8dd451 | 383 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
384 | { |
385 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
386 | uint8_t *pci_conf; | |
387 | ||
388 | pci_conf = s->dev.config; | |
389 | pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; | |
390 | pci_conf[0x63] = 0x60; | |
391 | pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | | |
392 | (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); | |
393 | ||
394 | } | |
395 | ||
e8ec0571 | 396 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 397 | { |
e8ec0571 | 398 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
399 | uint8_t *pci_conf; |
400 | ||
93d89f63 | 401 | pci_conf = s->dev.config; |
93d89f63 IY |
402 | pci_conf[0x06] = 0x80; |
403 | pci_conf[0x07] = 0x02; | |
93d89f63 | 404 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
405 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
406 | ||
93d89f63 | 407 | /* APM */ |
42d8a3cf | 408 | apm_init(dev, &s->apm, apm_ctrl_changed, s); |
93d89f63 | 409 | |
93d89f63 IY |
410 | if (s->kvm_enabled) { |
411 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
412 | * support SMM mode. */ | |
413 | pci_conf[0x5B] = 0x02; | |
414 | } | |
415 | ||
416 | /* XXX: which specification is used ? The i82731AB has different | |
417 | mappings */ | |
e8ec0571 IY |
418 | pci_conf[0x90] = s->smb_io_base | 1; |
419 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 420 | pci_conf[0xd2] = 0x09; |
798512e5 | 421 | pm_smbus_init(&s->dev.qdev, &s->smb); |
24fe083d | 422 | memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
56e5b2a1 GH |
423 | memory_region_add_subregion(pci_address_space_io(dev), |
424 | s->smb_io_base, &s->smb.io); | |
93d89f63 | 425 | |
ca5d64b4 | 426 | memory_region_init(&s->io, "piix4-pm", 64); |
af11110b | 427 | memory_region_set_enabled(&s->io, false); |
56e5b2a1 GH |
428 | memory_region_add_subregion(pci_address_space_io(dev), |
429 | 0, &s->io); | |
93d89f63 | 430 | |
77d58b1e | 431 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 432 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
560e6396 | 433 | acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); |
355bf2e5 | 434 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 435 | |
d010f91c IM |
436 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
437 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 438 | |
6141dbfe PB |
439 | s->machine_ready.notify = piix4_pm_machine_ready; |
440 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 441 | qemu_register_reset(piix4_reset, s); |
56e5b2a1 GH |
442 | |
443 | piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); | |
e8ec0571 IY |
444 | |
445 | return 0; | |
446 | } | |
447 | ||
448 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
da98c8eb | 449 | qemu_irq sci_irq, qemu_irq smi_irq, |
459ae5ea | 450 | int kvm_enabled, void *fw_cfg) |
e8ec0571 IY |
451 | { |
452 | PCIDevice *dev; | |
453 | PIIX4PMState *s; | |
454 | ||
455 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
456 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 457 | |
e8ec0571 | 458 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 | 459 | s->irq = sci_irq; |
93d89f63 | 460 | s->smi_irq = smi_irq; |
e8ec0571 IY |
461 | s->kvm_enabled = kvm_enabled; |
462 | ||
463 | qdev_init_nofail(&dev->qdev); | |
93d89f63 | 464 | |
459ae5ea GN |
465 | if (fw_cfg) { |
466 | uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; | |
467 | suspend[3] = 1 | ((!s->disable_s3) << 7); | |
468 | suspend[4] = s->s4_val | ((!s->disable_s4) << 7); | |
469 | ||
470 | fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); | |
471 | } | |
472 | ||
93d89f63 IY |
473 | return s->smb.smbus; |
474 | } | |
475 | ||
40021f08 AL |
476 | static Property piix4_pm_properties[] = { |
477 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
459ae5ea GN |
478 | DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), |
479 | DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), | |
480 | DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), | |
40021f08 AL |
481 | DEFINE_PROP_END_OF_LIST(), |
482 | }; | |
483 | ||
484 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
485 | { | |
39bffca2 | 486 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
487 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
488 | ||
489 | k->no_hotplug = 1; | |
490 | k->init = piix4_pm_initfn; | |
491 | k->config_write = pm_write_config; | |
492 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
493 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
494 | k->revision = 0x03; | |
495 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
39bffca2 AL |
496 | dc->desc = "PM"; |
497 | dc->no_user = 1; | |
498 | dc->vmsd = &vmstate_acpi; | |
499 | dc->props = piix4_pm_properties; | |
40021f08 AL |
500 | } |
501 | ||
8c43a6f0 | 502 | static const TypeInfo piix4_pm_info = { |
39bffca2 AL |
503 | .name = "PIIX4_PM", |
504 | .parent = TYPE_PCI_DEVICE, | |
505 | .instance_size = sizeof(PIIX4PMState), | |
506 | .class_init = piix4_pm_class_init, | |
e8ec0571 IY |
507 | }; |
508 | ||
83f7d43a | 509 | static void piix4_pm_register_types(void) |
e8ec0571 | 510 | { |
39bffca2 | 511 | type_register_static(&piix4_pm_info); |
e8ec0571 IY |
512 | } |
513 | ||
83f7d43a | 514 | type_init(piix4_pm_register_types) |
e8ec0571 | 515 | |
b65b93f2 | 516 | static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
93d89f63 | 517 | { |
633aa0ac | 518 | PIIX4PMState *s = opaque; |
355bf2e5 | 519 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 520 | |
50d8ff8b | 521 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
522 | return val; |
523 | } | |
524 | ||
b65b93f2 GH |
525 | static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
526 | unsigned width) | |
93d89f63 | 527 | { |
633aa0ac | 528 | PIIX4PMState *s = opaque; |
633aa0ac | 529 | |
355bf2e5 | 530 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
633aa0ac | 531 | pm_update_sci(s); |
93d89f63 | 532 | |
50d8ff8b | 533 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
534 | } |
535 | ||
b65b93f2 GH |
536 | static const MemoryRegionOps piix4_gpe_ops = { |
537 | .read = gpe_readb, | |
538 | .write = gpe_writeb, | |
539 | .valid.min_access_size = 1, | |
540 | .valid.max_access_size = 4, | |
541 | .impl.min_access_size = 1, | |
542 | .impl.max_access_size = 1, | |
543 | .endianness = DEVICE_LITTLE_ENDIAN, | |
544 | }; | |
545 | ||
c3a29809 | 546 | static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) |
93d89f63 | 547 | { |
ba737541 | 548 | PIIX4PMState *s = opaque; |
c3a29809 HP |
549 | uint32_t val = 0; |
550 | ||
551 | switch (addr) { | |
552 | case PCI_UP_BASE - PCI_HOTPLUG_ADDR: | |
553 | /* Manufacture an "up" value to cause a device check on any hotplug | |
554 | * slot with a device. Extra device checks are harmless. */ | |
555 | val = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
556 | PIIX4_DPRINTF("pci_up_read %x\n", val); | |
557 | break; | |
558 | case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: | |
559 | val = s->pci0_status.down; | |
560 | PIIX4_DPRINTF("pci_down_read %x\n", val); | |
561 | break; | |
562 | case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: | |
563 | /* No feature defined yet */ | |
564 | PIIX4_DPRINTF("pci_features_read %x\n", val); | |
565 | break; | |
566 | case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: | |
567 | val = s->pci0_hotplug_enable; | |
568 | break; | |
569 | default: | |
570 | break; | |
571 | } | |
ba737541 | 572 | |
ba737541 | 573 | return val; |
93d89f63 IY |
574 | } |
575 | ||
c3a29809 HP |
576 | static void pci_write(void *opaque, hwaddr addr, uint64_t data, |
577 | unsigned int size) | |
93d89f63 | 578 | { |
c3a29809 HP |
579 | switch (addr) { |
580 | case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: | |
581 | acpi_piix_eject_slot(opaque, (uint32_t)data); | |
582 | PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n", | |
583 | addr, data); | |
584 | break; | |
585 | default: | |
586 | break; | |
587 | } | |
668643b0 MT |
588 | } |
589 | ||
c177684c | 590 | static const MemoryRegionOps piix4_pci_ops = { |
c3a29809 HP |
591 | .read = pci_read, |
592 | .write = pci_write, | |
c177684c | 593 | .endianness = DEVICE_LITTLE_ENDIAN, |
c3a29809 HP |
594 | .valid = { |
595 | .min_access_size = 4, | |
596 | .max_access_size = 4, | |
597 | }, | |
c177684c GH |
598 | }; |
599 | ||
b8622725 IM |
600 | static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) |
601 | { | |
602 | PIIX4PMState *s = opaque; | |
603 | CPUStatus *cpus = &s->gpe_cpu; | |
604 | uint64_t val = cpus->sts[addr]; | |
605 | ||
606 | return val; | |
607 | } | |
608 | ||
609 | static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, | |
610 | unsigned int size) | |
611 | { | |
612 | /* TODO: implement VCPU removal on guest signal that CPU can be removed */ | |
613 | } | |
614 | ||
615 | static const MemoryRegionOps cpu_hotplug_ops = { | |
616 | .read = cpu_status_read, | |
617 | .write = cpu_status_write, | |
618 | .endianness = DEVICE_LITTLE_ENDIAN, | |
619 | .valid = { | |
620 | .min_access_size = 1, | |
621 | .max_access_size = 1, | |
622 | }, | |
623 | }; | |
624 | ||
625 | typedef enum { | |
626 | PLUG, | |
627 | UNPLUG, | |
628 | } HotplugEventType; | |
629 | ||
630 | static void piix4_cpu_hotplug_req(PIIX4PMState *s, CPUState *cpu, | |
631 | HotplugEventType action) | |
632 | { | |
633 | CPUStatus *g = &s->gpe_cpu; | |
634 | ACPIGPE *gpe = &s->ar.gpe; | |
635 | CPUClass *k = CPU_GET_CLASS(cpu); | |
636 | int64_t cpu_id; | |
637 | ||
638 | assert(s != NULL); | |
639 | ||
640 | *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS; | |
641 | cpu_id = k->get_arch_id(CPU(cpu)); | |
642 | if (action == PLUG) { | |
643 | g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); | |
644 | } else { | |
645 | g->sts[cpu_id / 8] &= ~(1 << (cpu_id % 8)); | |
646 | } | |
647 | pm_update_sci(s); | |
648 | } | |
649 | ||
650 | static void piix4_cpu_added_req(Notifier *n, void *opaque) | |
651 | { | |
652 | PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); | |
653 | ||
654 | piix4_cpu_hotplug_req(s, CPU(opaque), PLUG); | |
655 | } | |
656 | ||
657 | static void piix4_init_cpu_status(CPUState *cpu, void *data) | |
658 | { | |
659 | CPUStatus *g = (CPUStatus *)data; | |
660 | CPUClass *k = CPU_GET_CLASS(cpu); | |
661 | int64_t id = k->get_arch_id(cpu); | |
662 | ||
663 | g_assert((id / 8) < PIIX4_PROC_LEN); | |
664 | g->sts[id / 8] |= (1 << (id % 8)); | |
665 | } | |
666 | ||
4cff0a59 MT |
667 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
668 | PCIHotplugState state); | |
93d89f63 | 669 | |
56e5b2a1 GH |
670 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
671 | PCIBus *bus, PIIX4PMState *s) | |
93d89f63 | 672 | { |
b65b93f2 GH |
673 | memory_region_init_io(&s->io_gpe, &piix4_gpe_ops, s, "apci-gpe0", |
674 | GPE_LEN); | |
56e5b2a1 | 675 | memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); |
ac404095 | 676 | |
c177684c GH |
677 | memory_region_init_io(&s->io_pci, &piix4_pci_ops, s, "apci-pci-hotplug", |
678 | PCI_HOTPLUG_SIZE); | |
56e5b2a1 | 679 | memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR, |
c177684c | 680 | &s->io_pci); |
ac404095 | 681 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
b8622725 IM |
682 | |
683 | qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe_cpu); | |
684 | memory_region_init_io(&s->io_cpu, &cpu_hotplug_ops, s, "apci-cpu-hotplug", | |
685 | PIIX4_PROC_LEN); | |
686 | memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu); | |
687 | s->cpu_added_notifier.notify = piix4_cpu_added_req; | |
688 | qemu_register_cpu_added_notifier(&s->cpu_added_notifier); | |
93d89f63 IY |
689 | } |
690 | ||
ac404095 | 691 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 692 | { |
355bf2e5 | 693 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 694 | s->pci0_slot_device_present |= (1U << slot); |
93d89f63 IY |
695 | } |
696 | ||
ac404095 | 697 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 698 | { |
355bf2e5 | 699 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 700 | s->pci0_status.down |= (1U << slot); |
93d89f63 IY |
701 | } |
702 | ||
4cff0a59 MT |
703 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
704 | PCIHotplugState state) | |
93d89f63 IY |
705 | { |
706 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 | 707 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
40021f08 | 708 | PCI_DEVICE(qdev)); |
93d89f63 | 709 | |
4cff0a59 MT |
710 | /* Don't send event when device is enabled during qemu machine creation: |
711 | * it is present on boot, no hotplug event is necessary. We do send an | |
712 | * event when the device is disabled later. */ | |
713 | if (state == PCI_COLDPLUG_ENABLED) { | |
7faa8075 | 714 | s->pci0_slot_device_present |= (1U << slot); |
5beb8ad5 | 715 | return 0; |
4cff0a59 | 716 | } |
5beb8ad5 | 717 | |
4cff0a59 | 718 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
719 | enable_device(s, slot); |
720 | } else { | |
721 | disable_device(s, slot); | |
722 | } | |
633aa0ac GN |
723 | |
724 | pm_update_sci(s); | |
725 | ||
93d89f63 IY |
726 | return 0; |
727 | } |