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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 | 20 | */ |
83c9f4ca | 21 | #include "hw/hw.h" |
0d09e41a PB |
22 | #include "hw/i386/pc.h" |
23 | #include "hw/isa/apm.h" | |
24 | #include "hw/i2c/pm_smbus.h" | |
83c9f4ca | 25 | #include "hw/pci/pci.h" |
0d09e41a | 26 | #include "hw/acpi/acpi.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
1de7afc9 | 28 | #include "qemu/range.h" |
022c62cb | 29 | #include "exec/ioport.h" |
0d09e41a | 30 | #include "hw/nvram/fw_cfg.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
93d89f63 IY |
32 | |
33 | //#define DEBUG | |
34 | ||
50d8ff8b IY |
35 | #ifdef DEBUG |
36 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
37 | #else | |
38 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
39 | #endif | |
40 | ||
ac404095 | 41 | #define GPE_BASE 0xafe0 |
23910d3f | 42 | #define GPE_LEN 4 |
c177684c GH |
43 | |
44 | #define PCI_HOTPLUG_ADDR 0xae00 | |
45 | #define PCI_HOTPLUG_SIZE 0x000f | |
ba737541 AW |
46 | #define PCI_UP_BASE 0xae00 |
47 | #define PCI_DOWN_BASE 0xae04 | |
ac404095 | 48 | #define PCI_EJ_BASE 0xae08 |
668643b0 | 49 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 50 | |
b8622725 IM |
51 | #define PIIX4_PROC_BASE 0xaf00 |
52 | #define PIIX4_PROC_LEN 32 | |
53 | ||
4441a287 | 54 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
b8622725 | 55 | #define PIIX4_CPU_HOTPLUG_STATUS 4 |
4441a287 | 56 | |
ac404095 | 57 | struct pci_status { |
7faa8075 | 58 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
59 | uint32_t down; |
60 | }; | |
61 | ||
b8622725 IM |
62 | typedef struct CPUStatus { |
63 | uint8_t sts[PIIX4_PROC_LEN]; | |
64 | } CPUStatus; | |
65 | ||
93d89f63 | 66 | typedef struct PIIX4PMState { |
6a6b5580 AF |
67 | /*< private >*/ |
68 | PCIDevice parent_obj; | |
69 | /*< public >*/ | |
56e5b2a1 | 70 | |
af11110b | 71 | MemoryRegion io; |
b65b93f2 | 72 | MemoryRegion io_gpe; |
c177684c | 73 | MemoryRegion io_pci; |
b8622725 | 74 | MemoryRegion io_cpu; |
355bf2e5 | 75 | ACPIREGS ar; |
93d89f63 IY |
76 | |
77 | APMState apm; | |
78 | ||
93d89f63 | 79 | PMSMBus smb; |
e8ec0571 | 80 | uint32_t smb_io_base; |
93d89f63 IY |
81 | |
82 | qemu_irq irq; | |
93d89f63 IY |
83 | qemu_irq smi_irq; |
84 | int kvm_enabled; | |
6141dbfe | 85 | Notifier machine_ready; |
d010f91c | 86 | Notifier powerdown_notifier; |
ac404095 IY |
87 | |
88 | /* for pci hotplug */ | |
ac404095 | 89 | struct pci_status pci0_status; |
668643b0 | 90 | uint32_t pci0_hotplug_enable; |
7faa8075 | 91 | uint32_t pci0_slot_device_present; |
459ae5ea GN |
92 | |
93 | uint8_t disable_s3; | |
94 | uint8_t disable_s4; | |
95 | uint8_t s4_val; | |
b8622725 IM |
96 | |
97 | CPUStatus gpe_cpu; | |
98 | Notifier cpu_added_notifier; | |
93d89f63 IY |
99 | } PIIX4PMState; |
100 | ||
74e445f6 PC |
101 | #define TYPE_PIIX4_PM "PIIX4_PM" |
102 | ||
103 | #define PIIX4_PM(obj) \ | |
104 | OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) | |
105 | ||
56e5b2a1 GH |
106 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
107 | PCIBus *bus, PIIX4PMState *s); | |
ac404095 | 108 | |
93d89f63 IY |
109 | #define ACPI_ENABLE 0xf1 |
110 | #define ACPI_DISABLE 0xf0 | |
111 | ||
93d89f63 IY |
112 | static void pm_update_sci(PIIX4PMState *s) |
113 | { | |
114 | int sci_level, pmsts; | |
93d89f63 | 115 | |
2886be1b | 116 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 117 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
93d89f63 IY |
118 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
119 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
120 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 121 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
b8622725 IM |
122 | (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & |
123 | (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0); | |
633aa0ac | 124 | |
93d89f63 IY |
125 | qemu_set_irq(s->irq, sci_level); |
126 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 127 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 128 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
129 | } |
130 | ||
355bf2e5 | 131 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 132 | { |
355bf2e5 | 133 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
93d89f63 IY |
134 | pm_update_sci(s); |
135 | } | |
136 | ||
93d89f63 IY |
137 | static void apm_ctrl_changed(uint32_t val, void *arg) |
138 | { | |
139 | PIIX4PMState *s = arg; | |
6a6b5580 | 140 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 IY |
141 | |
142 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 143 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 | 144 | |
6a6b5580 | 145 | if (d->config[0x5b] & (1 << 1)) { |
93d89f63 IY |
146 | if (s->smi_irq) { |
147 | qemu_irq_raise(s->smi_irq); | |
148 | } | |
149 | } | |
150 | } | |
151 | ||
93d89f63 IY |
152 | static void pm_io_space_update(PIIX4PMState *s) |
153 | { | |
6a6b5580 | 154 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 IY |
155 | uint32_t pm_io_base; |
156 | ||
6a6b5580 | 157 | pm_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); |
af11110b | 158 | pm_io_base &= 0xffc0; |
93d89f63 | 159 | |
af11110b | 160 | memory_region_transaction_begin(); |
6a6b5580 | 161 | memory_region_set_enabled(&s->io, d->config[0x80] & 1); |
af11110b GH |
162 | memory_region_set_address(&s->io, pm_io_base); |
163 | memory_region_transaction_commit(); | |
93d89f63 IY |
164 | } |
165 | ||
24fe083d GH |
166 | static void smbus_io_space_update(PIIX4PMState *s) |
167 | { | |
6a6b5580 AF |
168 | PCIDevice *d = PCI_DEVICE(s); |
169 | ||
170 | s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); | |
24fe083d GH |
171 | s->smb_io_base &= 0xffc0; |
172 | ||
173 | memory_region_transaction_begin(); | |
6a6b5580 | 174 | memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); |
24fe083d GH |
175 | memory_region_set_address(&s->smb.io, s->smb_io_base); |
176 | memory_region_transaction_commit(); | |
93d89f63 IY |
177 | } |
178 | ||
179 | static void pm_write_config(PCIDevice *d, | |
180 | uint32_t address, uint32_t val, int len) | |
181 | { | |
182 | pci_default_write_config(d, address, val, len); | |
24fe083d GH |
183 | if (range_covers_byte(address, len, 0x80) || |
184 | ranges_overlap(address, len, 0x40, 4)) { | |
93d89f63 | 185 | pm_io_space_update((PIIX4PMState *)d); |
24fe083d GH |
186 | } |
187 | if (range_covers_byte(address, len, 0xd2) || | |
188 | ranges_overlap(address, len, 0x90, 4)) { | |
189 | smbus_io_space_update((PIIX4PMState *)d); | |
190 | } | |
93d89f63 IY |
191 | } |
192 | ||
7faa8075 AW |
193 | static void vmstate_pci_status_pre_save(void *opaque) |
194 | { | |
195 | struct pci_status *pci0_status = opaque; | |
196 | PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); | |
197 | ||
198 | /* We no longer track up, so build a safe value for migrating | |
199 | * to a version that still does... of course these might get lost | |
200 | * by an old buggy implementation, but we try. */ | |
201 | pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
202 | } | |
203 | ||
93d89f63 IY |
204 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
205 | { | |
206 | PIIX4PMState *s = opaque; | |
207 | ||
208 | pm_io_space_update(s); | |
209 | return 0; | |
210 | } | |
211 | ||
23910d3f IY |
212 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
213 | { \ | |
214 | .name = (stringify(_field)), \ | |
215 | .version_id = 0, \ | |
23910d3f IY |
216 | .info = &vmstate_info_uint16, \ |
217 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 218 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
219 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
220 | } | |
221 | ||
4cf3e6f3 AW |
222 | static const VMStateDescription vmstate_gpe = { |
223 | .name = "gpe", | |
224 | .version_id = 1, | |
225 | .minimum_version_id = 1, | |
226 | .minimum_version_id_old = 1, | |
227 | .fields = (VMStateField []) { | |
23910d3f IY |
228 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
229 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
230 | VMSTATE_END_OF_LIST() |
231 | } | |
232 | }; | |
233 | ||
234 | static const VMStateDescription vmstate_pci_status = { | |
235 | .name = "pci_status", | |
236 | .version_id = 1, | |
237 | .minimum_version_id = 1, | |
238 | .minimum_version_id_old = 1, | |
7faa8075 | 239 | .pre_save = vmstate_pci_status_pre_save, |
4cf3e6f3 AW |
240 | .fields = (VMStateField []) { |
241 | VMSTATE_UINT32(up, struct pci_status), | |
242 | VMSTATE_UINT32(down, struct pci_status), | |
243 | VMSTATE_END_OF_LIST() | |
244 | } | |
245 | }; | |
246 | ||
b0b873a0 MT |
247 | static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
248 | { | |
249 | PIIX4PMState *s = opaque; | |
250 | int ret, i; | |
251 | uint16_t temp; | |
252 | ||
6a6b5580 | 253 | ret = pci_device_load(PCI_DEVICE(s), f); |
b0b873a0 MT |
254 | if (ret < 0) { |
255 | return ret; | |
256 | } | |
257 | qemu_get_be16s(f, &s->ar.pm1.evt.sts); | |
258 | qemu_get_be16s(f, &s->ar.pm1.evt.en); | |
259 | qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); | |
260 | ||
ded67782 | 261 | ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); |
b0b873a0 MT |
262 | if (ret) { |
263 | return ret; | |
264 | } | |
265 | ||
266 | qemu_get_timer(f, s->ar.tmr.timer); | |
267 | qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); | |
268 | ||
269 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); | |
270 | for (i = 0; i < 3; i++) { | |
271 | qemu_get_be16s(f, &temp); | |
272 | } | |
273 | ||
274 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); | |
275 | for (i = 0; i < 3; i++) { | |
276 | qemu_get_be16s(f, &temp); | |
277 | } | |
278 | ||
ded67782 | 279 | ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1); |
b0b873a0 MT |
280 | return ret; |
281 | } | |
282 | ||
283 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 | |
284 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
285 | * and minimum_version_id to 2 below (which breaks migration from | |
286 | * qemu 1.2). | |
287 | * | |
288 | */ | |
93d89f63 IY |
289 | static const VMStateDescription vmstate_acpi = { |
290 | .name = "piix4_pm", | |
b0b873a0 MT |
291 | .version_id = 3, |
292 | .minimum_version_id = 3, | |
93d89f63 | 293 | .minimum_version_id_old = 1, |
b0b873a0 | 294 | .load_state_old = acpi_load_old, |
93d89f63 IY |
295 | .post_load = vmstate_acpi_post_load, |
296 | .fields = (VMStateField []) { | |
6a6b5580 | 297 | VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), |
355bf2e5 GH |
298 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
299 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
300 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 301 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
302 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
303 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
304 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
4cf3e6f3 AW |
305 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
306 | struct pci_status), | |
93d89f63 IY |
307 | VMSTATE_END_OF_LIST() |
308 | } | |
309 | }; | |
310 | ||
7faa8075 AW |
311 | static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) |
312 | { | |
0866aca1 | 313 | BusChild *kid, *next; |
74e445f6 | 314 | BusState *bus = qdev_get_parent_bus(DEVICE(s)); |
7faa8075 | 315 | int slot = ffs(slots) - 1; |
54bfa546 | 316 | bool slot_free = true; |
7faa8075 AW |
317 | |
318 | /* Mark request as complete */ | |
319 | s->pci0_status.down &= ~(1U << slot); | |
320 | ||
0866aca1 AL |
321 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
322 | DeviceState *qdev = kid->child; | |
7faa8075 AW |
323 | PCIDevice *dev = PCI_DEVICE(qdev); |
324 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
54bfa546 MT |
325 | if (PCI_SLOT(dev->devfn) == slot) { |
326 | if (pc->no_hotplug) { | |
327 | slot_free = false; | |
328 | } else { | |
329 | qdev_free(qdev); | |
330 | } | |
7faa8075 AW |
331 | } |
332 | } | |
54bfa546 MT |
333 | if (slot_free) { |
334 | s->pci0_slot_device_present &= ~(1U << slot); | |
335 | } | |
7faa8075 AW |
336 | } |
337 | ||
668643b0 MT |
338 | static void piix4_update_hotplug(PIIX4PMState *s) |
339 | { | |
74e445f6 | 340 | BusState *bus = qdev_get_parent_bus(DEVICE(s)); |
0866aca1 | 341 | BusChild *kid, *next; |
668643b0 | 342 | |
7faa8075 AW |
343 | /* Execute any pending removes during reset */ |
344 | while (s->pci0_status.down) { | |
345 | acpi_piix_eject_slot(s, s->pci0_status.down); | |
346 | } | |
347 | ||
668643b0 | 348 | s->pci0_hotplug_enable = ~0; |
7faa8075 | 349 | s->pci0_slot_device_present = 0; |
668643b0 | 350 | |
0866aca1 AL |
351 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
352 | DeviceState *qdev = kid->child; | |
40021f08 AL |
353 | PCIDevice *pdev = PCI_DEVICE(qdev); |
354 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); | |
668643b0 MT |
355 | int slot = PCI_SLOT(pdev->devfn); |
356 | ||
40021f08 | 357 | if (pc->no_hotplug) { |
7faa8075 | 358 | s->pci0_hotplug_enable &= ~(1U << slot); |
668643b0 | 359 | } |
7faa8075 AW |
360 | |
361 | s->pci0_slot_device_present |= (1U << slot); | |
668643b0 MT |
362 | } |
363 | } | |
364 | ||
93d89f63 IY |
365 | static void piix4_reset(void *opaque) |
366 | { | |
367 | PIIX4PMState *s = opaque; | |
6a6b5580 AF |
368 | PCIDevice *d = PCI_DEVICE(s); |
369 | uint8_t *pci_conf = d->config; | |
93d89f63 IY |
370 | |
371 | pci_conf[0x58] = 0; | |
372 | pci_conf[0x59] = 0; | |
373 | pci_conf[0x5a] = 0; | |
374 | pci_conf[0x5b] = 0; | |
375 | ||
4d09d37c GN |
376 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
377 | pci_conf[0x80] = 0; | |
378 | ||
93d89f63 IY |
379 | if (s->kvm_enabled) { |
380 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
381 | pci_conf[0x5B] = 0x02; | |
382 | } | |
668643b0 | 383 | piix4_update_hotplug(s); |
93d89f63 IY |
384 | } |
385 | ||
d010f91c | 386 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 387 | { |
d010f91c | 388 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 389 | |
355bf2e5 GH |
390 | assert(s != NULL); |
391 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
392 | } |
393 | ||
9e8dd451 | 394 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
395 | { |
396 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
6a6b5580 AF |
397 | PCIDevice *d = PCI_DEVICE(s); |
398 | MemoryRegion *io_as = pci_address_space_io(d); | |
6141dbfe PB |
399 | uint8_t *pci_conf; |
400 | ||
6a6b5580 | 401 | pci_conf = d->config; |
b6f32962 | 402 | pci_conf[0x5f] = 0x10 | |
3ce10901 | 403 | (memory_region_present(io_as, 0x378) ? 0x80 : 0); |
6141dbfe | 404 | pci_conf[0x63] = 0x60; |
3ce10901 PB |
405 | pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | |
406 | (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); | |
6141dbfe PB |
407 | } |
408 | ||
e8ec0571 | 409 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 410 | { |
74e445f6 | 411 | PIIX4PMState *s = PIIX4_PM(dev); |
93d89f63 IY |
412 | uint8_t *pci_conf; |
413 | ||
6a6b5580 | 414 | pci_conf = dev->config; |
93d89f63 IY |
415 | pci_conf[0x06] = 0x80; |
416 | pci_conf[0x07] = 0x02; | |
93d89f63 | 417 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
418 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
419 | ||
93d89f63 | 420 | /* APM */ |
42d8a3cf | 421 | apm_init(dev, &s->apm, apm_ctrl_changed, s); |
93d89f63 | 422 | |
93d89f63 IY |
423 | if (s->kvm_enabled) { |
424 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
425 | * support SMM mode. */ | |
426 | pci_conf[0x5B] = 0x02; | |
427 | } | |
428 | ||
429 | /* XXX: which specification is used ? The i82731AB has different | |
430 | mappings */ | |
e8ec0571 IY |
431 | pci_conf[0x90] = s->smb_io_base | 1; |
432 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 433 | pci_conf[0xd2] = 0x09; |
74e445f6 | 434 | pm_smbus_init(DEVICE(dev), &s->smb); |
24fe083d | 435 | memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
56e5b2a1 GH |
436 | memory_region_add_subregion(pci_address_space_io(dev), |
437 | s->smb_io_base, &s->smb.io); | |
93d89f63 | 438 | |
64bde0f3 | 439 | memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); |
af11110b | 440 | memory_region_set_enabled(&s->io, false); |
56e5b2a1 GH |
441 | memory_region_add_subregion(pci_address_space_io(dev), |
442 | 0, &s->io); | |
93d89f63 | 443 | |
77d58b1e | 444 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 445 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
560e6396 | 446 | acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); |
355bf2e5 | 447 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 448 | |
d010f91c IM |
449 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
450 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 451 | |
6141dbfe PB |
452 | s->machine_ready.notify = piix4_pm_machine_ready; |
453 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 454 | qemu_register_reset(piix4_reset, s); |
56e5b2a1 GH |
455 | |
456 | piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); | |
e8ec0571 IY |
457 | |
458 | return 0; | |
459 | } | |
460 | ||
461 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
da98c8eb | 462 | qemu_irq sci_irq, qemu_irq smi_irq, |
a88b362c | 463 | int kvm_enabled, FWCfgState *fw_cfg) |
e8ec0571 | 464 | { |
74e445f6 | 465 | DeviceState *dev; |
e8ec0571 IY |
466 | PIIX4PMState *s; |
467 | ||
74e445f6 PC |
468 | dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); |
469 | qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); | |
93d89f63 | 470 | |
74e445f6 | 471 | s = PIIX4_PM(dev); |
93d89f63 | 472 | s->irq = sci_irq; |
93d89f63 | 473 | s->smi_irq = smi_irq; |
e8ec0571 IY |
474 | s->kvm_enabled = kvm_enabled; |
475 | ||
74e445f6 | 476 | qdev_init_nofail(dev); |
93d89f63 | 477 | |
459ae5ea GN |
478 | if (fw_cfg) { |
479 | uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; | |
480 | suspend[3] = 1 | ((!s->disable_s3) << 7); | |
481 | suspend[4] = s->s4_val | ((!s->disable_s4) << 7); | |
482 | ||
483 | fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); | |
484 | } | |
485 | ||
93d89f63 IY |
486 | return s->smb.smbus; |
487 | } | |
488 | ||
40021f08 AL |
489 | static Property piix4_pm_properties[] = { |
490 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
459ae5ea GN |
491 | DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), |
492 | DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), | |
493 | DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), | |
40021f08 AL |
494 | DEFINE_PROP_END_OF_LIST(), |
495 | }; | |
496 | ||
497 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
498 | { | |
39bffca2 | 499 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
500 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
501 | ||
502 | k->no_hotplug = 1; | |
503 | k->init = piix4_pm_initfn; | |
504 | k->config_write = pm_write_config; | |
505 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
506 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
507 | k->revision = 0x03; | |
508 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
39bffca2 AL |
509 | dc->desc = "PM"; |
510 | dc->no_user = 1; | |
511 | dc->vmsd = &vmstate_acpi; | |
512 | dc->props = piix4_pm_properties; | |
40021f08 AL |
513 | } |
514 | ||
8c43a6f0 | 515 | static const TypeInfo piix4_pm_info = { |
74e445f6 | 516 | .name = TYPE_PIIX4_PM, |
39bffca2 AL |
517 | .parent = TYPE_PCI_DEVICE, |
518 | .instance_size = sizeof(PIIX4PMState), | |
519 | .class_init = piix4_pm_class_init, | |
e8ec0571 IY |
520 | }; |
521 | ||
83f7d43a | 522 | static void piix4_pm_register_types(void) |
e8ec0571 | 523 | { |
39bffca2 | 524 | type_register_static(&piix4_pm_info); |
e8ec0571 IY |
525 | } |
526 | ||
83f7d43a | 527 | type_init(piix4_pm_register_types) |
e8ec0571 | 528 | |
b65b93f2 | 529 | static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
93d89f63 | 530 | { |
633aa0ac | 531 | PIIX4PMState *s = opaque; |
355bf2e5 | 532 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 533 | |
ba275adb | 534 | PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); |
93d89f63 IY |
535 | return val; |
536 | } | |
537 | ||
b65b93f2 GH |
538 | static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
539 | unsigned width) | |
93d89f63 | 540 | { |
633aa0ac | 541 | PIIX4PMState *s = opaque; |
633aa0ac | 542 | |
355bf2e5 | 543 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
633aa0ac | 544 | pm_update_sci(s); |
93d89f63 | 545 | |
ba275adb | 546 | PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); |
93d89f63 IY |
547 | } |
548 | ||
b65b93f2 GH |
549 | static const MemoryRegionOps piix4_gpe_ops = { |
550 | .read = gpe_readb, | |
551 | .write = gpe_writeb, | |
552 | .valid.min_access_size = 1, | |
553 | .valid.max_access_size = 4, | |
554 | .impl.min_access_size = 1, | |
555 | .impl.max_access_size = 1, | |
556 | .endianness = DEVICE_LITTLE_ENDIAN, | |
557 | }; | |
558 | ||
c3a29809 | 559 | static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) |
93d89f63 | 560 | { |
ba737541 | 561 | PIIX4PMState *s = opaque; |
c3a29809 HP |
562 | uint32_t val = 0; |
563 | ||
564 | switch (addr) { | |
565 | case PCI_UP_BASE - PCI_HOTPLUG_ADDR: | |
566 | /* Manufacture an "up" value to cause a device check on any hotplug | |
567 | * slot with a device. Extra device checks are harmless. */ | |
568 | val = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
ba275adb | 569 | PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); |
c3a29809 HP |
570 | break; |
571 | case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: | |
572 | val = s->pci0_status.down; | |
ba275adb | 573 | PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); |
c3a29809 HP |
574 | break; |
575 | case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: | |
576 | /* No feature defined yet */ | |
ba275adb | 577 | PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); |
c3a29809 HP |
578 | break; |
579 | case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: | |
580 | val = s->pci0_hotplug_enable; | |
581 | break; | |
582 | default: | |
583 | break; | |
584 | } | |
ba737541 | 585 | |
ba737541 | 586 | return val; |
93d89f63 IY |
587 | } |
588 | ||
c3a29809 HP |
589 | static void pci_write(void *opaque, hwaddr addr, uint64_t data, |
590 | unsigned int size) | |
93d89f63 | 591 | { |
c3a29809 HP |
592 | switch (addr) { |
593 | case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: | |
594 | acpi_piix_eject_slot(opaque, (uint32_t)data); | |
ba275adb | 595 | PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", |
c3a29809 HP |
596 | addr, data); |
597 | break; | |
598 | default: | |
599 | break; | |
600 | } | |
668643b0 MT |
601 | } |
602 | ||
c177684c | 603 | static const MemoryRegionOps piix4_pci_ops = { |
c3a29809 HP |
604 | .read = pci_read, |
605 | .write = pci_write, | |
c177684c | 606 | .endianness = DEVICE_LITTLE_ENDIAN, |
c3a29809 HP |
607 | .valid = { |
608 | .min_access_size = 4, | |
609 | .max_access_size = 4, | |
610 | }, | |
c177684c GH |
611 | }; |
612 | ||
b8622725 IM |
613 | static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) |
614 | { | |
615 | PIIX4PMState *s = opaque; | |
616 | CPUStatus *cpus = &s->gpe_cpu; | |
617 | uint64_t val = cpus->sts[addr]; | |
618 | ||
619 | return val; | |
620 | } | |
621 | ||
622 | static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, | |
623 | unsigned int size) | |
624 | { | |
625 | /* TODO: implement VCPU removal on guest signal that CPU can be removed */ | |
626 | } | |
627 | ||
628 | static const MemoryRegionOps cpu_hotplug_ops = { | |
629 | .read = cpu_status_read, | |
630 | .write = cpu_status_write, | |
631 | .endianness = DEVICE_LITTLE_ENDIAN, | |
632 | .valid = { | |
633 | .min_access_size = 1, | |
634 | .max_access_size = 1, | |
635 | }, | |
636 | }; | |
637 | ||
638 | typedef enum { | |
639 | PLUG, | |
640 | UNPLUG, | |
641 | } HotplugEventType; | |
642 | ||
643 | static void piix4_cpu_hotplug_req(PIIX4PMState *s, CPUState *cpu, | |
644 | HotplugEventType action) | |
645 | { | |
646 | CPUStatus *g = &s->gpe_cpu; | |
647 | ACPIGPE *gpe = &s->ar.gpe; | |
648 | CPUClass *k = CPU_GET_CLASS(cpu); | |
649 | int64_t cpu_id; | |
650 | ||
651 | assert(s != NULL); | |
652 | ||
653 | *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS; | |
654 | cpu_id = k->get_arch_id(CPU(cpu)); | |
655 | if (action == PLUG) { | |
656 | g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); | |
657 | } else { | |
658 | g->sts[cpu_id / 8] &= ~(1 << (cpu_id % 8)); | |
659 | } | |
660 | pm_update_sci(s); | |
661 | } | |
662 | ||
663 | static void piix4_cpu_added_req(Notifier *n, void *opaque) | |
664 | { | |
665 | PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); | |
666 | ||
667 | piix4_cpu_hotplug_req(s, CPU(opaque), PLUG); | |
668 | } | |
669 | ||
670 | static void piix4_init_cpu_status(CPUState *cpu, void *data) | |
671 | { | |
672 | CPUStatus *g = (CPUStatus *)data; | |
673 | CPUClass *k = CPU_GET_CLASS(cpu); | |
674 | int64_t id = k->get_arch_id(cpu); | |
675 | ||
676 | g_assert((id / 8) < PIIX4_PROC_LEN); | |
677 | g->sts[id / 8] |= (1 << (id % 8)); | |
678 | } | |
679 | ||
4cff0a59 MT |
680 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
681 | PCIHotplugState state); | |
93d89f63 | 682 | |
56e5b2a1 GH |
683 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
684 | PCIBus *bus, PIIX4PMState *s) | |
93d89f63 | 685 | { |
64bde0f3 PB |
686 | memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, |
687 | "acpi-gpe0", GPE_LEN); | |
56e5b2a1 | 688 | memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); |
ac404095 | 689 | |
64bde0f3 PB |
690 | memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s, |
691 | "acpi-pci-hotplug", PCI_HOTPLUG_SIZE); | |
56e5b2a1 | 692 | memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR, |
c177684c | 693 | &s->io_pci); |
74e445f6 | 694 | pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s)); |
b8622725 IM |
695 | |
696 | qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe_cpu); | |
64bde0f3 PB |
697 | memory_region_init_io(&s->io_cpu, OBJECT(s), &cpu_hotplug_ops, s, |
698 | "acpi-cpu-hotplug", PIIX4_PROC_LEN); | |
b8622725 IM |
699 | memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu); |
700 | s->cpu_added_notifier.notify = piix4_cpu_added_req; | |
701 | qemu_register_cpu_added_notifier(&s->cpu_added_notifier); | |
93d89f63 IY |
702 | } |
703 | ||
ac404095 | 704 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 705 | { |
355bf2e5 | 706 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 707 | s->pci0_slot_device_present |= (1U << slot); |
93d89f63 IY |
708 | } |
709 | ||
ac404095 | 710 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 711 | { |
355bf2e5 | 712 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 713 | s->pci0_status.down |= (1U << slot); |
93d89f63 IY |
714 | } |
715 | ||
4cff0a59 MT |
716 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
717 | PCIHotplugState state) | |
93d89f63 IY |
718 | { |
719 | int slot = PCI_SLOT(dev->devfn); | |
74e445f6 | 720 | PIIX4PMState *s = PIIX4_PM(qdev); |
93d89f63 | 721 | |
4cff0a59 MT |
722 | /* Don't send event when device is enabled during qemu machine creation: |
723 | * it is present on boot, no hotplug event is necessary. We do send an | |
724 | * event when the device is disabled later. */ | |
725 | if (state == PCI_COLDPLUG_ENABLED) { | |
7faa8075 | 726 | s->pci0_slot_device_present |= (1U << slot); |
5beb8ad5 | 727 | return 0; |
4cff0a59 | 728 | } |
5beb8ad5 | 729 | |
4cff0a59 | 730 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
731 | enable_device(s, slot); |
732 | } else { | |
733 | disable_device(s, slot); | |
734 | } | |
633aa0ac GN |
735 | |
736 | pm_update_sci(s); | |
737 | ||
93d89f63 IY |
738 | return 0; |
739 | } |