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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
17 | */ | |
18 | #include "hw.h" | |
19 | #include "pc.h" | |
20 | #include "apm.h" | |
21 | #include "pm_smbus.h" | |
22 | #include "pci.h" | |
93d89f63 | 23 | #include "acpi.h" |
666daa68 | 24 | #include "sysemu.h" |
bf1b0071 | 25 | #include "range.h" |
93d89f63 IY |
26 | |
27 | //#define DEBUG | |
28 | ||
50d8ff8b IY |
29 | #ifdef DEBUG |
30 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
31 | #else | |
32 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
33 | #endif | |
34 | ||
93d89f63 IY |
35 | #define ACPI_DBG_IO_ADDR 0xb044 |
36 | ||
ac404095 | 37 | #define GPE_BASE 0xafe0 |
23910d3f | 38 | #define GPE_LEN 4 |
ac404095 IY |
39 | #define PCI_BASE 0xae00 |
40 | #define PCI_EJ_BASE 0xae08 | |
668643b0 | 41 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 42 | |
4441a287 GN |
43 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
44 | ||
ac404095 IY |
45 | struct pci_status { |
46 | uint32_t up; | |
47 | uint32_t down; | |
48 | }; | |
49 | ||
93d89f63 IY |
50 | typedef struct PIIX4PMState { |
51 | PCIDevice dev; | |
2871a3f6 | 52 | IORange ioport; |
04dc308f | 53 | ACPIPM1EVT pm1a; |
eaba51c5 | 54 | ACPIPM1CNT pm1_cnt; |
93d89f63 IY |
55 | |
56 | APMState apm; | |
57 | ||
a54d41a8 | 58 | ACPIPMTimer tmr; |
93d89f63 IY |
59 | |
60 | PMSMBus smb; | |
e8ec0571 | 61 | uint32_t smb_io_base; |
93d89f63 IY |
62 | |
63 | qemu_irq irq; | |
93d89f63 IY |
64 | qemu_irq smi_irq; |
65 | int kvm_enabled; | |
ac404095 IY |
66 | |
67 | /* for pci hotplug */ | |
23910d3f | 68 | ACPIGPE gpe; |
ac404095 | 69 | struct pci_status pci0_status; |
668643b0 | 70 | uint32_t pci0_hotplug_enable; |
93d89f63 IY |
71 | } PIIX4PMState; |
72 | ||
ac404095 IY |
73 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
74 | ||
93d89f63 IY |
75 | #define ACPI_ENABLE 0xf1 |
76 | #define ACPI_DISABLE 0xf0 | |
77 | ||
93d89f63 IY |
78 | static void pm_update_sci(PIIX4PMState *s) |
79 | { | |
80 | int sci_level, pmsts; | |
93d89f63 | 81 | |
04dc308f IY |
82 | pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
83 | sci_level = (((pmsts & s->pm1a.en) & | |
93d89f63 IY |
84 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
85 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
86 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 87 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
23910d3f | 88 | (((s->gpe.sts[0] & s->gpe.en[0]) & PIIX4_PCI_HOTPLUG_STATUS) != 0); |
633aa0ac | 89 | |
93d89f63 IY |
90 | qemu_set_irq(s->irq, sci_level); |
91 | /* schedule a timer interruption if needed */ | |
04dc308f | 92 | acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 93 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
94 | } |
95 | ||
a54d41a8 | 96 | static void pm_tmr_timer(ACPIPMTimer *tmr) |
93d89f63 | 97 | { |
a54d41a8 | 98 | PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr); |
93d89f63 IY |
99 | pm_update_sci(s); |
100 | } | |
101 | ||
2871a3f6 AK |
102 | static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, |
103 | uint64_t val) | |
93d89f63 | 104 | { |
2871a3f6 AK |
105 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
106 | ||
107 | if (width != 2) { | |
108 | PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", | |
109 | (unsigned)addr, width, (unsigned)val); | |
110 | } | |
111 | ||
93d89f63 IY |
112 | switch(addr) { |
113 | case 0x00: | |
04dc308f IY |
114 | acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val); |
115 | pm_update_sci(s); | |
93d89f63 IY |
116 | break; |
117 | case 0x02: | |
04dc308f | 118 | s->pm1a.en = val; |
93d89f63 IY |
119 | pm_update_sci(s); |
120 | break; | |
121 | case 0x04: | |
eaba51c5 | 122 | acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val); |
93d89f63 IY |
123 | break; |
124 | default: | |
125 | break; | |
126 | } | |
59df4c11 WC |
127 | PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr, |
128 | (unsigned int)val); | |
93d89f63 IY |
129 | } |
130 | ||
2871a3f6 AK |
131 | static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, |
132 | uint64_t *data) | |
93d89f63 | 133 | { |
2871a3f6 | 134 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
93d89f63 IY |
135 | uint32_t val; |
136 | ||
93d89f63 IY |
137 | switch(addr) { |
138 | case 0x00: | |
04dc308f | 139 | val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
93d89f63 IY |
140 | break; |
141 | case 0x02: | |
04dc308f | 142 | val = s->pm1a.en; |
93d89f63 IY |
143 | break; |
144 | case 0x04: | |
eaba51c5 | 145 | val = s->pm1_cnt.cnt; |
93d89f63 | 146 | break; |
93d89f63 | 147 | case 0x08: |
a54d41a8 | 148 | val = acpi_pm_tmr_get(&s->tmr); |
93d89f63 IY |
149 | break; |
150 | default: | |
151 | val = 0; | |
152 | break; | |
153 | } | |
59df4c11 | 154 | PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val); |
2871a3f6 | 155 | *data = val; |
93d89f63 IY |
156 | } |
157 | ||
2871a3f6 AK |
158 | static const IORangeOps pm_iorange_ops = { |
159 | .read = pm_ioport_read, | |
160 | .write = pm_ioport_write, | |
161 | }; | |
162 | ||
93d89f63 IY |
163 | static void apm_ctrl_changed(uint32_t val, void *arg) |
164 | { | |
165 | PIIX4PMState *s = arg; | |
166 | ||
167 | /* ACPI specs 3.0, 4.7.2.5 */ | |
eaba51c5 | 168 | acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 IY |
169 | |
170 | if (s->dev.config[0x5b] & (1 << 1)) { | |
171 | if (s->smi_irq) { | |
172 | qemu_irq_raise(s->smi_irq); | |
173 | } | |
174 | } | |
175 | } | |
176 | ||
177 | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) | |
178 | { | |
50d8ff8b | 179 | PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); |
93d89f63 IY |
180 | } |
181 | ||
182 | static void pm_io_space_update(PIIX4PMState *s) | |
183 | { | |
184 | uint32_t pm_io_base; | |
185 | ||
186 | if (s->dev.config[0x80] & 1) { | |
187 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); | |
188 | pm_io_base &= 0xffc0; | |
189 | ||
190 | /* XXX: need to improve memory and ioport allocation */ | |
50d8ff8b | 191 | PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); |
2871a3f6 AK |
192 | iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); |
193 | ioport_register(&s->ioport); | |
93d89f63 IY |
194 | } |
195 | } | |
196 | ||
197 | static void pm_write_config(PCIDevice *d, | |
198 | uint32_t address, uint32_t val, int len) | |
199 | { | |
200 | pci_default_write_config(d, address, val, len); | |
201 | if (range_covers_byte(address, len, 0x80)) | |
202 | pm_io_space_update((PIIX4PMState *)d); | |
203 | } | |
204 | ||
205 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
206 | { | |
207 | PIIX4PMState *s = opaque; | |
208 | ||
209 | pm_io_space_update(s); | |
210 | return 0; | |
211 | } | |
212 | ||
23910d3f IY |
213 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
214 | { \ | |
215 | .name = (stringify(_field)), \ | |
216 | .version_id = 0, \ | |
217 | .num = GPE_LEN, \ | |
218 | .info = &vmstate_info_uint16, \ | |
219 | .size = sizeof(uint16_t), \ | |
220 | .flags = VMS_ARRAY | VMS_POINTER, \ | |
221 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ | |
222 | } | |
223 | ||
4cf3e6f3 AW |
224 | static const VMStateDescription vmstate_gpe = { |
225 | .name = "gpe", | |
226 | .version_id = 1, | |
227 | .minimum_version_id = 1, | |
228 | .minimum_version_id_old = 1, | |
229 | .fields = (VMStateField []) { | |
23910d3f IY |
230 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
231 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
232 | VMSTATE_END_OF_LIST() |
233 | } | |
234 | }; | |
235 | ||
236 | static const VMStateDescription vmstate_pci_status = { | |
237 | .name = "pci_status", | |
238 | .version_id = 1, | |
239 | .minimum_version_id = 1, | |
240 | .minimum_version_id_old = 1, | |
241 | .fields = (VMStateField []) { | |
242 | VMSTATE_UINT32(up, struct pci_status), | |
243 | VMSTATE_UINT32(down, struct pci_status), | |
244 | VMSTATE_END_OF_LIST() | |
245 | } | |
246 | }; | |
247 | ||
93d89f63 IY |
248 | static const VMStateDescription vmstate_acpi = { |
249 | .name = "piix4_pm", | |
4cf3e6f3 | 250 | .version_id = 2, |
93d89f63 IY |
251 | .minimum_version_id = 1, |
252 | .minimum_version_id_old = 1, | |
253 | .post_load = vmstate_acpi_post_load, | |
254 | .fields = (VMStateField []) { | |
255 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
04dc308f IY |
256 | VMSTATE_UINT16(pm1a.sts, PIIX4PMState), |
257 | VMSTATE_UINT16(pm1a.en, PIIX4PMState), | |
eaba51c5 | 258 | VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState), |
93d89f63 | 259 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
a54d41a8 IY |
260 | VMSTATE_TIMER(tmr.timer, PIIX4PMState), |
261 | VMSTATE_INT64(tmr.overflow_time, PIIX4PMState), | |
23910d3f | 262 | VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), |
4cf3e6f3 AW |
263 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
264 | struct pci_status), | |
93d89f63 IY |
265 | VMSTATE_END_OF_LIST() |
266 | } | |
267 | }; | |
268 | ||
668643b0 MT |
269 | static void piix4_update_hotplug(PIIX4PMState *s) |
270 | { | |
271 | PCIDevice *dev = &s->dev; | |
272 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
273 | DeviceState *qdev, *next; | |
274 | ||
275 | s->pci0_hotplug_enable = ~0; | |
276 | ||
277 | QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) { | |
278 | PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev); | |
279 | PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev); | |
280 | int slot = PCI_SLOT(pdev->devfn); | |
281 | ||
282 | if (info->no_hotplug) { | |
283 | s->pci0_hotplug_enable &= ~(1 << slot); | |
284 | } | |
285 | } | |
286 | } | |
287 | ||
93d89f63 IY |
288 | static void piix4_reset(void *opaque) |
289 | { | |
290 | PIIX4PMState *s = opaque; | |
291 | uint8_t *pci_conf = s->dev.config; | |
292 | ||
293 | pci_conf[0x58] = 0; | |
294 | pci_conf[0x59] = 0; | |
295 | pci_conf[0x5a] = 0; | |
296 | pci_conf[0x5b] = 0; | |
297 | ||
298 | if (s->kvm_enabled) { | |
299 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
300 | pci_conf[0x5B] = 0x02; | |
301 | } | |
668643b0 | 302 | piix4_update_hotplug(s); |
93d89f63 IY |
303 | } |
304 | ||
305 | static void piix4_powerdown(void *opaque, int irq, int power_failing) | |
306 | { | |
307 | PIIX4PMState *s = opaque; | |
04dc308f IY |
308 | ACPIPM1EVT *pm1a = s? &s->pm1a: NULL; |
309 | ACPIPMTimer *tmr = s? &s->tmr: NULL; | |
93d89f63 | 310 | |
04dc308f | 311 | acpi_pm1_evt_power_down(pm1a, tmr); |
93d89f63 IY |
312 | } |
313 | ||
e8ec0571 | 314 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 315 | { |
e8ec0571 | 316 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
317 | uint8_t *pci_conf; |
318 | ||
93d89f63 | 319 | pci_conf = s->dev.config; |
93d89f63 IY |
320 | pci_conf[0x06] = 0x80; |
321 | pci_conf[0x07] = 0x02; | |
93d89f63 | 322 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
323 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
324 | ||
325 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ | |
326 | ||
327 | /* APM */ | |
328 | apm_init(&s->apm, apm_ctrl_changed, s); | |
329 | ||
330 | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); | |
331 | ||
93d89f63 IY |
332 | if (s->kvm_enabled) { |
333 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
334 | * support SMM mode. */ | |
335 | pci_conf[0x5B] = 0x02; | |
336 | } | |
337 | ||
338 | /* XXX: which specification is used ? The i82731AB has different | |
339 | mappings */ | |
340 | pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; | |
341 | pci_conf[0x63] = 0x60; | |
342 | pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | | |
343 | (serial_hds[1] != NULL ? 0x90 : 0); | |
344 | ||
e8ec0571 IY |
345 | pci_conf[0x90] = s->smb_io_base | 1; |
346 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 347 | pci_conf[0xd2] = 0x09; |
e8ec0571 IY |
348 | register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
349 | register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); | |
93d89f63 | 350 | |
a54d41a8 | 351 | acpi_pm_tmr_init(&s->tmr, pm_tmr_timer); |
23910d3f | 352 | acpi_gpe_init(&s->gpe, GPE_LEN); |
93d89f63 IY |
353 | |
354 | qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1); | |
355 | ||
e8ec0571 IY |
356 | pm_smbus_init(&s->dev.qdev, &s->smb); |
357 | qemu_register_reset(piix4_reset, s); | |
ac404095 | 358 | piix4_acpi_system_hot_add_init(dev->bus, s); |
e8ec0571 IY |
359 | |
360 | return 0; | |
361 | } | |
362 | ||
363 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
364 | qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, | |
365 | int kvm_enabled) | |
366 | { | |
367 | PCIDevice *dev; | |
368 | PIIX4PMState *s; | |
369 | ||
370 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
371 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 372 | |
e8ec0571 | 373 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 | 374 | s->irq = sci_irq; |
eaba51c5 | 375 | acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3); |
93d89f63 | 376 | s->smi_irq = smi_irq; |
e8ec0571 IY |
377 | s->kvm_enabled = kvm_enabled; |
378 | ||
379 | qdev_init_nofail(&dev->qdev); | |
93d89f63 IY |
380 | |
381 | return s->smb.smbus; | |
382 | } | |
383 | ||
e8ec0571 IY |
384 | static PCIDeviceInfo piix4_pm_info = { |
385 | .qdev.name = "PIIX4_PM", | |
386 | .qdev.desc = "PM", | |
387 | .qdev.size = sizeof(PIIX4PMState), | |
388 | .qdev.vmsd = &vmstate_acpi, | |
0965f12d GH |
389 | .qdev.no_user = 1, |
390 | .no_hotplug = 1, | |
e8ec0571 IY |
391 | .init = piix4_pm_initfn, |
392 | .config_write = pm_write_config, | |
580b7295 IY |
393 | .vendor_id = PCI_VENDOR_ID_INTEL, |
394 | .device_id = PCI_DEVICE_ID_INTEL_82371AB_3, | |
395 | .revision = 0x03, | |
396 | .class_id = PCI_CLASS_BRIDGE_OTHER, | |
e8ec0571 IY |
397 | .qdev.props = (Property[]) { |
398 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
399 | DEFINE_PROP_END_OF_LIST(), | |
400 | } | |
401 | }; | |
402 | ||
403 | static void piix4_pm_register(void) | |
404 | { | |
405 | pci_qdev_register(&piix4_pm_info); | |
406 | } | |
407 | ||
408 | device_init(piix4_pm_register); | |
409 | ||
93d89f63 IY |
410 | static uint32_t gpe_readb(void *opaque, uint32_t addr) |
411 | { | |
633aa0ac | 412 | PIIX4PMState *s = opaque; |
23910d3f | 413 | uint32_t val = acpi_gpe_ioport_readb(&s->gpe, addr); |
93d89f63 | 414 | |
50d8ff8b | 415 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
416 | return val; |
417 | } | |
418 | ||
93d89f63 IY |
419 | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
420 | { | |
633aa0ac | 421 | PIIX4PMState *s = opaque; |
633aa0ac | 422 | |
23910d3f | 423 | acpi_gpe_ioport_writeb(&s->gpe, addr, val); |
633aa0ac | 424 | pm_update_sci(s); |
93d89f63 | 425 | |
50d8ff8b | 426 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
427 | } |
428 | ||
429 | static uint32_t pcihotplug_read(void *opaque, uint32_t addr) | |
430 | { | |
431 | uint32_t val = 0; | |
432 | struct pci_status *g = opaque; | |
433 | switch (addr) { | |
434 | case PCI_BASE: | |
435 | val = g->up; | |
436 | break; | |
437 | case PCI_BASE + 4: | |
438 | val = g->down; | |
439 | break; | |
440 | default: | |
441 | break; | |
442 | } | |
443 | ||
50d8ff8b | 444 | PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val); |
93d89f63 IY |
445 | return val; |
446 | } | |
447 | ||
448 | static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) | |
449 | { | |
450 | struct pci_status *g = opaque; | |
451 | switch (addr) { | |
452 | case PCI_BASE: | |
453 | g->up = val; | |
454 | break; | |
455 | case PCI_BASE + 4: | |
456 | g->down = val; | |
457 | break; | |
458 | } | |
459 | ||
50d8ff8b | 460 | PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val); |
93d89f63 IY |
461 | } |
462 | ||
463 | static uint32_t pciej_read(void *opaque, uint32_t addr) | |
464 | { | |
50d8ff8b | 465 | PIIX4_DPRINTF("pciej read %x\n", addr); |
93d89f63 IY |
466 | return 0; |
467 | } | |
468 | ||
469 | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) | |
470 | { | |
471 | BusState *bus = opaque; | |
472 | DeviceState *qdev, *next; | |
473 | PCIDevice *dev; | |
505597e4 | 474 | PCIDeviceInfo *info; |
93d89f63 IY |
475 | int slot = ffs(val) - 1; |
476 | ||
477 | QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) { | |
478 | dev = DO_UPCAST(PCIDevice, qdev, qdev); | |
505597e4 GH |
479 | info = container_of(qdev->info, PCIDeviceInfo, qdev); |
480 | if (PCI_SLOT(dev->devfn) == slot && !info->no_hotplug) { | |
93d89f63 IY |
481 | qdev_free(qdev); |
482 | } | |
483 | } | |
484 | ||
485 | ||
50d8ff8b | 486 | PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); |
93d89f63 IY |
487 | } |
488 | ||
668643b0 MT |
489 | static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
490 | { | |
491 | PIIX4PMState *s = opaque; | |
492 | ||
493 | return s->pci0_hotplug_enable; | |
494 | } | |
495 | ||
496 | static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val) | |
497 | { | |
498 | return; | |
499 | } | |
500 | ||
4cff0a59 MT |
501 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
502 | PCIHotplugState state); | |
93d89f63 | 503 | |
ac404095 | 504 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
93d89f63 | 505 | { |
ac404095 | 506 | struct pci_status *pci0_status = &s->pci0_status; |
93d89f63 | 507 | |
23910d3f IY |
508 | register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); |
509 | register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); | |
510 | acpi_gpe_blk(&s->gpe, GPE_BASE); | |
ac404095 IY |
511 | |
512 | register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); | |
513 | register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); | |
93d89f63 IY |
514 | |
515 | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); | |
516 | register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus); | |
517 | ||
668643b0 MT |
518 | register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s); |
519 | register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); | |
520 | ||
ac404095 | 521 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
93d89f63 IY |
522 | } |
523 | ||
ac404095 | 524 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 525 | { |
23910d3f | 526 | s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
ac404095 | 527 | s->pci0_status.up |= (1 << slot); |
93d89f63 IY |
528 | } |
529 | ||
ac404095 | 530 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 531 | { |
23910d3f | 532 | s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
ac404095 | 533 | s->pci0_status.down |= (1 << slot); |
93d89f63 IY |
534 | } |
535 | ||
4cff0a59 MT |
536 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
537 | PCIHotplugState state) | |
93d89f63 IY |
538 | { |
539 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 IY |
540 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
541 | DO_UPCAST(PCIDevice, qdev, qdev)); | |
93d89f63 | 542 | |
4cff0a59 MT |
543 | /* Don't send event when device is enabled during qemu machine creation: |
544 | * it is present on boot, no hotplug event is necessary. We do send an | |
545 | * event when the device is disabled later. */ | |
546 | if (state == PCI_COLDPLUG_ENABLED) { | |
5beb8ad5 | 547 | return 0; |
4cff0a59 | 548 | } |
5beb8ad5 | 549 | |
ac404095 IY |
550 | s->pci0_status.up = 0; |
551 | s->pci0_status.down = 0; | |
4cff0a59 | 552 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
553 | enable_device(s, slot); |
554 | } else { | |
555 | disable_device(s, slot); | |
556 | } | |
633aa0ac GN |
557 | |
558 | pm_update_sci(s); | |
559 | ||
93d89f63 IY |
560 | return 0; |
561 | } |