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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 IY |
20 | */ |
21 | #include "hw.h" | |
22 | #include "pc.h" | |
23 | #include "apm.h" | |
24 | #include "pm_smbus.h" | |
25 | #include "pci.h" | |
93d89f63 | 26 | #include "acpi.h" |
666daa68 | 27 | #include "sysemu.h" |
bf1b0071 | 28 | #include "range.h" |
6141dbfe | 29 | #include "ioport.h" |
459ae5ea | 30 | #include "fw_cfg.h" |
93d89f63 IY |
31 | |
32 | //#define DEBUG | |
33 | ||
50d8ff8b IY |
34 | #ifdef DEBUG |
35 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
36 | #else | |
37 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
38 | #endif | |
39 | ||
93d89f63 IY |
40 | #define ACPI_DBG_IO_ADDR 0xb044 |
41 | ||
ac404095 | 42 | #define GPE_BASE 0xafe0 |
23910d3f | 43 | #define GPE_LEN 4 |
ba737541 AW |
44 | #define PCI_UP_BASE 0xae00 |
45 | #define PCI_DOWN_BASE 0xae04 | |
ac404095 | 46 | #define PCI_EJ_BASE 0xae08 |
668643b0 | 47 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 48 | |
4441a287 GN |
49 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
50 | ||
ac404095 | 51 | struct pci_status { |
7faa8075 | 52 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
53 | uint32_t down; |
54 | }; | |
55 | ||
93d89f63 IY |
56 | typedef struct PIIX4PMState { |
57 | PCIDevice dev; | |
2871a3f6 | 58 | IORange ioport; |
355bf2e5 | 59 | ACPIREGS ar; |
93d89f63 IY |
60 | |
61 | APMState apm; | |
62 | ||
93d89f63 | 63 | PMSMBus smb; |
e8ec0571 | 64 | uint32_t smb_io_base; |
93d89f63 IY |
65 | |
66 | qemu_irq irq; | |
93d89f63 IY |
67 | qemu_irq smi_irq; |
68 | int kvm_enabled; | |
6141dbfe | 69 | Notifier machine_ready; |
d010f91c | 70 | Notifier powerdown_notifier; |
ac404095 IY |
71 | |
72 | /* for pci hotplug */ | |
ac404095 | 73 | struct pci_status pci0_status; |
668643b0 | 74 | uint32_t pci0_hotplug_enable; |
7faa8075 | 75 | uint32_t pci0_slot_device_present; |
459ae5ea GN |
76 | |
77 | uint8_t disable_s3; | |
78 | uint8_t disable_s4; | |
79 | uint8_t s4_val; | |
93d89f63 IY |
80 | } PIIX4PMState; |
81 | ||
ac404095 IY |
82 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
83 | ||
93d89f63 IY |
84 | #define ACPI_ENABLE 0xf1 |
85 | #define ACPI_DISABLE 0xf0 | |
86 | ||
93d89f63 IY |
87 | static void pm_update_sci(PIIX4PMState *s) |
88 | { | |
89 | int sci_level, pmsts; | |
93d89f63 | 90 | |
2886be1b | 91 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 92 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
93d89f63 IY |
93 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
94 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
95 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 96 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
355bf2e5 GH |
97 | (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) |
98 | & PIIX4_PCI_HOTPLUG_STATUS) != 0); | |
633aa0ac | 99 | |
93d89f63 IY |
100 | qemu_set_irq(s->irq, sci_level); |
101 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 102 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 103 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
104 | } |
105 | ||
355bf2e5 | 106 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 107 | { |
355bf2e5 | 108 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
93d89f63 IY |
109 | pm_update_sci(s); |
110 | } | |
111 | ||
2871a3f6 AK |
112 | static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, |
113 | uint64_t val) | |
93d89f63 | 114 | { |
2871a3f6 AK |
115 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
116 | ||
117 | if (width != 2) { | |
118 | PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", | |
119 | (unsigned)addr, width, (unsigned)val); | |
120 | } | |
121 | ||
93d89f63 IY |
122 | switch(addr) { |
123 | case 0x00: | |
355bf2e5 | 124 | acpi_pm1_evt_write_sts(&s->ar, val); |
04dc308f | 125 | pm_update_sci(s); |
93d89f63 IY |
126 | break; |
127 | case 0x02: | |
8283c4f5 | 128 | acpi_pm1_evt_write_en(&s->ar, val); |
93d89f63 IY |
129 | pm_update_sci(s); |
130 | break; | |
131 | case 0x04: | |
459ae5ea | 132 | acpi_pm1_cnt_write(&s->ar, val, s->s4_val); |
93d89f63 IY |
133 | break; |
134 | default: | |
135 | break; | |
136 | } | |
59df4c11 WC |
137 | PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr, |
138 | (unsigned int)val); | |
93d89f63 IY |
139 | } |
140 | ||
2871a3f6 AK |
141 | static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, |
142 | uint64_t *data) | |
93d89f63 | 143 | { |
2871a3f6 | 144 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
93d89f63 IY |
145 | uint32_t val; |
146 | ||
93d89f63 IY |
147 | switch(addr) { |
148 | case 0x00: | |
2886be1b | 149 | val = acpi_pm1_evt_get_sts(&s->ar); |
93d89f63 IY |
150 | break; |
151 | case 0x02: | |
355bf2e5 | 152 | val = s->ar.pm1.evt.en; |
93d89f63 IY |
153 | break; |
154 | case 0x04: | |
355bf2e5 | 155 | val = s->ar.pm1.cnt.cnt; |
93d89f63 | 156 | break; |
93d89f63 | 157 | case 0x08: |
355bf2e5 | 158 | val = acpi_pm_tmr_get(&s->ar); |
93d89f63 IY |
159 | break; |
160 | default: | |
161 | val = 0; | |
162 | break; | |
163 | } | |
59df4c11 | 164 | PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val); |
2871a3f6 | 165 | *data = val; |
93d89f63 IY |
166 | } |
167 | ||
2871a3f6 AK |
168 | static const IORangeOps pm_iorange_ops = { |
169 | .read = pm_ioport_read, | |
170 | .write = pm_ioport_write, | |
171 | }; | |
172 | ||
93d89f63 IY |
173 | static void apm_ctrl_changed(uint32_t val, void *arg) |
174 | { | |
175 | PIIX4PMState *s = arg; | |
176 | ||
177 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 178 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 IY |
179 | |
180 | if (s->dev.config[0x5b] & (1 << 1)) { | |
181 | if (s->smi_irq) { | |
182 | qemu_irq_raise(s->smi_irq); | |
183 | } | |
184 | } | |
185 | } | |
186 | ||
187 | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) | |
188 | { | |
50d8ff8b | 189 | PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); |
93d89f63 IY |
190 | } |
191 | ||
192 | static void pm_io_space_update(PIIX4PMState *s) | |
193 | { | |
194 | uint32_t pm_io_base; | |
195 | ||
196 | if (s->dev.config[0x80] & 1) { | |
197 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); | |
198 | pm_io_base &= 0xffc0; | |
199 | ||
200 | /* XXX: need to improve memory and ioport allocation */ | |
50d8ff8b | 201 | PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); |
2871a3f6 AK |
202 | iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); |
203 | ioport_register(&s->ioport); | |
93d89f63 IY |
204 | } |
205 | } | |
206 | ||
207 | static void pm_write_config(PCIDevice *d, | |
208 | uint32_t address, uint32_t val, int len) | |
209 | { | |
210 | pci_default_write_config(d, address, val, len); | |
211 | if (range_covers_byte(address, len, 0x80)) | |
212 | pm_io_space_update((PIIX4PMState *)d); | |
213 | } | |
214 | ||
7faa8075 AW |
215 | static void vmstate_pci_status_pre_save(void *opaque) |
216 | { | |
217 | struct pci_status *pci0_status = opaque; | |
218 | PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); | |
219 | ||
220 | /* We no longer track up, so build a safe value for migrating | |
221 | * to a version that still does... of course these might get lost | |
222 | * by an old buggy implementation, but we try. */ | |
223 | pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
224 | } | |
225 | ||
93d89f63 IY |
226 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
227 | { | |
228 | PIIX4PMState *s = opaque; | |
229 | ||
230 | pm_io_space_update(s); | |
231 | return 0; | |
232 | } | |
233 | ||
23910d3f IY |
234 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
235 | { \ | |
236 | .name = (stringify(_field)), \ | |
237 | .version_id = 0, \ | |
23910d3f IY |
238 | .info = &vmstate_info_uint16, \ |
239 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 240 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
241 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
242 | } | |
243 | ||
4cf3e6f3 AW |
244 | static const VMStateDescription vmstate_gpe = { |
245 | .name = "gpe", | |
246 | .version_id = 1, | |
247 | .minimum_version_id = 1, | |
248 | .minimum_version_id_old = 1, | |
249 | .fields = (VMStateField []) { | |
23910d3f IY |
250 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
251 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
252 | VMSTATE_END_OF_LIST() |
253 | } | |
254 | }; | |
255 | ||
256 | static const VMStateDescription vmstate_pci_status = { | |
257 | .name = "pci_status", | |
258 | .version_id = 1, | |
259 | .minimum_version_id = 1, | |
260 | .minimum_version_id_old = 1, | |
7faa8075 | 261 | .pre_save = vmstate_pci_status_pre_save, |
4cf3e6f3 AW |
262 | .fields = (VMStateField []) { |
263 | VMSTATE_UINT32(up, struct pci_status), | |
264 | VMSTATE_UINT32(down, struct pci_status), | |
265 | VMSTATE_END_OF_LIST() | |
266 | } | |
267 | }; | |
268 | ||
b0b873a0 MT |
269 | static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
270 | { | |
271 | PIIX4PMState *s = opaque; | |
272 | int ret, i; | |
273 | uint16_t temp; | |
274 | ||
275 | ret = pci_device_load(&s->dev, f); | |
276 | if (ret < 0) { | |
277 | return ret; | |
278 | } | |
279 | qemu_get_be16s(f, &s->ar.pm1.evt.sts); | |
280 | qemu_get_be16s(f, &s->ar.pm1.evt.en); | |
281 | qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); | |
282 | ||
283 | ret = vmstate_load_state(f, &vmstate_apm, opaque, 1); | |
284 | if (ret) { | |
285 | return ret; | |
286 | } | |
287 | ||
288 | qemu_get_timer(f, s->ar.tmr.timer); | |
289 | qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); | |
290 | ||
291 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); | |
292 | for (i = 0; i < 3; i++) { | |
293 | qemu_get_be16s(f, &temp); | |
294 | } | |
295 | ||
296 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); | |
297 | for (i = 0; i < 3; i++) { | |
298 | qemu_get_be16s(f, &temp); | |
299 | } | |
300 | ||
301 | ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1); | |
302 | return ret; | |
303 | } | |
304 | ||
305 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 | |
306 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
307 | * and minimum_version_id to 2 below (which breaks migration from | |
308 | * qemu 1.2). | |
309 | * | |
310 | */ | |
93d89f63 IY |
311 | static const VMStateDescription vmstate_acpi = { |
312 | .name = "piix4_pm", | |
b0b873a0 MT |
313 | .version_id = 3, |
314 | .minimum_version_id = 3, | |
93d89f63 | 315 | .minimum_version_id_old = 1, |
b0b873a0 | 316 | .load_state_old = acpi_load_old, |
93d89f63 IY |
317 | .post_load = vmstate_acpi_post_load, |
318 | .fields = (VMStateField []) { | |
319 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
355bf2e5 GH |
320 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
321 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
322 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 323 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
324 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
325 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
326 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
4cf3e6f3 AW |
327 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
328 | struct pci_status), | |
93d89f63 IY |
329 | VMSTATE_END_OF_LIST() |
330 | } | |
331 | }; | |
332 | ||
7faa8075 AW |
333 | static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) |
334 | { | |
0866aca1 | 335 | BusChild *kid, *next; |
7faa8075 AW |
336 | BusState *bus = qdev_get_parent_bus(&s->dev.qdev); |
337 | int slot = ffs(slots) - 1; | |
54bfa546 | 338 | bool slot_free = true; |
7faa8075 AW |
339 | |
340 | /* Mark request as complete */ | |
341 | s->pci0_status.down &= ~(1U << slot); | |
342 | ||
0866aca1 AL |
343 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
344 | DeviceState *qdev = kid->child; | |
7faa8075 AW |
345 | PCIDevice *dev = PCI_DEVICE(qdev); |
346 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
54bfa546 MT |
347 | if (PCI_SLOT(dev->devfn) == slot) { |
348 | if (pc->no_hotplug) { | |
349 | slot_free = false; | |
350 | } else { | |
351 | qdev_free(qdev); | |
352 | } | |
7faa8075 AW |
353 | } |
354 | } | |
54bfa546 MT |
355 | if (slot_free) { |
356 | s->pci0_slot_device_present &= ~(1U << slot); | |
357 | } | |
7faa8075 AW |
358 | } |
359 | ||
668643b0 MT |
360 | static void piix4_update_hotplug(PIIX4PMState *s) |
361 | { | |
362 | PCIDevice *dev = &s->dev; | |
363 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
0866aca1 | 364 | BusChild *kid, *next; |
668643b0 | 365 | |
7faa8075 AW |
366 | /* Execute any pending removes during reset */ |
367 | while (s->pci0_status.down) { | |
368 | acpi_piix_eject_slot(s, s->pci0_status.down); | |
369 | } | |
370 | ||
668643b0 | 371 | s->pci0_hotplug_enable = ~0; |
7faa8075 | 372 | s->pci0_slot_device_present = 0; |
668643b0 | 373 | |
0866aca1 AL |
374 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
375 | DeviceState *qdev = kid->child; | |
40021f08 AL |
376 | PCIDevice *pdev = PCI_DEVICE(qdev); |
377 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); | |
668643b0 MT |
378 | int slot = PCI_SLOT(pdev->devfn); |
379 | ||
40021f08 | 380 | if (pc->no_hotplug) { |
7faa8075 | 381 | s->pci0_hotplug_enable &= ~(1U << slot); |
668643b0 | 382 | } |
7faa8075 AW |
383 | |
384 | s->pci0_slot_device_present |= (1U << slot); | |
668643b0 MT |
385 | } |
386 | } | |
387 | ||
93d89f63 IY |
388 | static void piix4_reset(void *opaque) |
389 | { | |
390 | PIIX4PMState *s = opaque; | |
391 | uint8_t *pci_conf = s->dev.config; | |
392 | ||
393 | pci_conf[0x58] = 0; | |
394 | pci_conf[0x59] = 0; | |
395 | pci_conf[0x5a] = 0; | |
396 | pci_conf[0x5b] = 0; | |
397 | ||
4d09d37c GN |
398 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
399 | pci_conf[0x80] = 0; | |
400 | ||
93d89f63 IY |
401 | if (s->kvm_enabled) { |
402 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
403 | pci_conf[0x5B] = 0x02; | |
404 | } | |
668643b0 | 405 | piix4_update_hotplug(s); |
93d89f63 IY |
406 | } |
407 | ||
d010f91c | 408 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 409 | { |
d010f91c | 410 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 411 | |
355bf2e5 GH |
412 | assert(s != NULL); |
413 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
414 | } |
415 | ||
9e8dd451 | 416 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
417 | { |
418 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
419 | uint8_t *pci_conf; | |
420 | ||
421 | pci_conf = s->dev.config; | |
422 | pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; | |
423 | pci_conf[0x63] = 0x60; | |
424 | pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | | |
425 | (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); | |
426 | ||
427 | } | |
428 | ||
e8ec0571 | 429 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 430 | { |
e8ec0571 | 431 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
432 | uint8_t *pci_conf; |
433 | ||
93d89f63 | 434 | pci_conf = s->dev.config; |
93d89f63 IY |
435 | pci_conf[0x06] = 0x80; |
436 | pci_conf[0x07] = 0x02; | |
93d89f63 | 437 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
438 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
439 | ||
93d89f63 IY |
440 | /* APM */ |
441 | apm_init(&s->apm, apm_ctrl_changed, s); | |
442 | ||
443 | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); | |
444 | ||
93d89f63 IY |
445 | if (s->kvm_enabled) { |
446 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
447 | * support SMM mode. */ | |
448 | pci_conf[0x5B] = 0x02; | |
449 | } | |
450 | ||
451 | /* XXX: which specification is used ? The i82731AB has different | |
452 | mappings */ | |
e8ec0571 IY |
453 | pci_conf[0x90] = s->smb_io_base | 1; |
454 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 455 | pci_conf[0xd2] = 0x09; |
e8ec0571 IY |
456 | register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
457 | register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); | |
93d89f63 | 458 | |
355bf2e5 GH |
459 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer); |
460 | acpi_gpe_init(&s->ar, GPE_LEN); | |
93d89f63 | 461 | |
d010f91c IM |
462 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
463 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 464 | |
e8ec0571 | 465 | pm_smbus_init(&s->dev.qdev, &s->smb); |
6141dbfe PB |
466 | s->machine_ready.notify = piix4_pm_machine_ready; |
467 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 468 | qemu_register_reset(piix4_reset, s); |
ac404095 | 469 | piix4_acpi_system_hot_add_init(dev->bus, s); |
e8ec0571 IY |
470 | |
471 | return 0; | |
472 | } | |
473 | ||
474 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
da98c8eb | 475 | qemu_irq sci_irq, qemu_irq smi_irq, |
459ae5ea | 476 | int kvm_enabled, void *fw_cfg) |
e8ec0571 IY |
477 | { |
478 | PCIDevice *dev; | |
479 | PIIX4PMState *s; | |
480 | ||
481 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
482 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 483 | |
e8ec0571 | 484 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 | 485 | s->irq = sci_irq; |
da98c8eb | 486 | acpi_pm1_cnt_init(&s->ar); |
93d89f63 | 487 | s->smi_irq = smi_irq; |
e8ec0571 IY |
488 | s->kvm_enabled = kvm_enabled; |
489 | ||
490 | qdev_init_nofail(&dev->qdev); | |
93d89f63 | 491 | |
459ae5ea GN |
492 | if (fw_cfg) { |
493 | uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; | |
494 | suspend[3] = 1 | ((!s->disable_s3) << 7); | |
495 | suspend[4] = s->s4_val | ((!s->disable_s4) << 7); | |
496 | ||
497 | fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); | |
498 | } | |
499 | ||
93d89f63 IY |
500 | return s->smb.smbus; |
501 | } | |
502 | ||
40021f08 AL |
503 | static Property piix4_pm_properties[] = { |
504 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
459ae5ea GN |
505 | DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), |
506 | DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), | |
507 | DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), | |
40021f08 AL |
508 | DEFINE_PROP_END_OF_LIST(), |
509 | }; | |
510 | ||
511 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
512 | { | |
39bffca2 | 513 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
514 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
515 | ||
516 | k->no_hotplug = 1; | |
517 | k->init = piix4_pm_initfn; | |
518 | k->config_write = pm_write_config; | |
519 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
520 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
521 | k->revision = 0x03; | |
522 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
39bffca2 AL |
523 | dc->desc = "PM"; |
524 | dc->no_user = 1; | |
525 | dc->vmsd = &vmstate_acpi; | |
526 | dc->props = piix4_pm_properties; | |
40021f08 AL |
527 | } |
528 | ||
39bffca2 AL |
529 | static TypeInfo piix4_pm_info = { |
530 | .name = "PIIX4_PM", | |
531 | .parent = TYPE_PCI_DEVICE, | |
532 | .instance_size = sizeof(PIIX4PMState), | |
533 | .class_init = piix4_pm_class_init, | |
e8ec0571 IY |
534 | }; |
535 | ||
83f7d43a | 536 | static void piix4_pm_register_types(void) |
e8ec0571 | 537 | { |
39bffca2 | 538 | type_register_static(&piix4_pm_info); |
e8ec0571 IY |
539 | } |
540 | ||
83f7d43a | 541 | type_init(piix4_pm_register_types) |
e8ec0571 | 542 | |
93d89f63 IY |
543 | static uint32_t gpe_readb(void *opaque, uint32_t addr) |
544 | { | |
633aa0ac | 545 | PIIX4PMState *s = opaque; |
355bf2e5 | 546 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 547 | |
50d8ff8b | 548 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
549 | return val; |
550 | } | |
551 | ||
93d89f63 IY |
552 | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
553 | { | |
633aa0ac | 554 | PIIX4PMState *s = opaque; |
633aa0ac | 555 | |
355bf2e5 | 556 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
633aa0ac | 557 | pm_update_sci(s); |
93d89f63 | 558 | |
50d8ff8b | 559 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
560 | } |
561 | ||
ba737541 | 562 | static uint32_t pci_up_read(void *opaque, uint32_t addr) |
93d89f63 | 563 | { |
ba737541 | 564 | PIIX4PMState *s = opaque; |
7faa8075 AW |
565 | uint32_t val; |
566 | ||
567 | /* Manufacture an "up" value to cause a device check on any hotplug | |
568 | * slot with a device. Extra device checks are harmless. */ | |
569 | val = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
93d89f63 | 570 | |
ba737541 | 571 | PIIX4_DPRINTF("pci_up_read %x\n", val); |
93d89f63 IY |
572 | return val; |
573 | } | |
574 | ||
ba737541 | 575 | static uint32_t pci_down_read(void *opaque, uint32_t addr) |
93d89f63 | 576 | { |
ba737541 AW |
577 | PIIX4PMState *s = opaque; |
578 | uint32_t val = s->pci0_status.down; | |
579 | ||
580 | PIIX4_DPRINTF("pci_down_read %x\n", val); | |
581 | return val; | |
93d89f63 IY |
582 | } |
583 | ||
9290f364 | 584 | static uint32_t pci_features_read(void *opaque, uint32_t addr) |
93d89f63 | 585 | { |
9290f364 AW |
586 | /* No feature defined yet */ |
587 | PIIX4_DPRINTF("pci_features_read %x\n", 0); | |
93d89f63 IY |
588 | return 0; |
589 | } | |
590 | ||
591 | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) | |
592 | { | |
7faa8075 | 593 | acpi_piix_eject_slot(opaque, val); |
93d89f63 | 594 | |
50d8ff8b | 595 | PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); |
93d89f63 IY |
596 | } |
597 | ||
668643b0 MT |
598 | static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
599 | { | |
600 | PIIX4PMState *s = opaque; | |
601 | ||
602 | return s->pci0_hotplug_enable; | |
603 | } | |
604 | ||
4cff0a59 MT |
605 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
606 | PCIHotplugState state); | |
93d89f63 | 607 | |
ac404095 | 608 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
93d89f63 | 609 | { |
93d89f63 | 610 | |
23910d3f IY |
611 | register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); |
612 | register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); | |
355bf2e5 | 613 | acpi_gpe_blk(&s->ar, GPE_BASE); |
ac404095 | 614 | |
ba737541 AW |
615 | register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s); |
616 | register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); | |
93d89f63 | 617 | |
7faa8075 | 618 | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s); |
9290f364 | 619 | register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s); |
93d89f63 | 620 | |
668643b0 MT |
621 | register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); |
622 | ||
ac404095 | 623 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
93d89f63 IY |
624 | } |
625 | ||
ac404095 | 626 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 627 | { |
355bf2e5 | 628 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 629 | s->pci0_slot_device_present |= (1U << slot); |
93d89f63 IY |
630 | } |
631 | ||
ac404095 | 632 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 633 | { |
355bf2e5 | 634 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 635 | s->pci0_status.down |= (1U << slot); |
93d89f63 IY |
636 | } |
637 | ||
4cff0a59 MT |
638 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
639 | PCIHotplugState state) | |
93d89f63 IY |
640 | { |
641 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 | 642 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
40021f08 | 643 | PCI_DEVICE(qdev)); |
93d89f63 | 644 | |
4cff0a59 MT |
645 | /* Don't send event when device is enabled during qemu machine creation: |
646 | * it is present on boot, no hotplug event is necessary. We do send an | |
647 | * event when the device is disabled later. */ | |
648 | if (state == PCI_COLDPLUG_ENABLED) { | |
7faa8075 | 649 | s->pci0_slot_device_present |= (1U << slot); |
5beb8ad5 | 650 | return 0; |
4cff0a59 | 651 | } |
5beb8ad5 | 652 | |
4cff0a59 | 653 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
654 | enable_device(s, slot); |
655 | } else { | |
656 | disable_device(s, slot); | |
657 | } | |
633aa0ac GN |
658 | |
659 | pm_update_sci(s); | |
660 | ||
93d89f63 IY |
661 | return 0; |
662 | } |