[qemu.git] / hw / acpi_piix4.c

/*
 * ACPI implementation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */
#include "hw.h"
#include "pc.h"
#include "apm.h"
#include "pm_smbus.h"
#include "pci.h"
#include "acpi.h"
#include "sysemu.h"
#include "range.h"
#include "ioport.h"
#include "fw_cfg.h"
#include "exec-memory.h"

//#define DEBUG

#ifdef DEBUG
# define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
#else
# define PIIX4_DPRINTF(format, ...)     do { } while (0)
#endif

#define ACPI_DBG_IO_ADDR  0xb044

#define GPE_BASE 0xafe0
#define GPE_LEN 4
#define PCI_UP_BASE 0xae00
#define PCI_DOWN_BASE 0xae04
#define PCI_EJ_BASE 0xae08
#define PCI_RMV_BASE 0xae0c

#define PIIX4_PCI_HOTPLUG_STATUS 2

struct pci_status {
    uint32_t up; /* deprecated, maintained for migration compatibility */
    uint32_t down;
};

typedef struct PIIX4PMState {
    PCIDevice dev;
    MemoryRegion io;
    ACPIREGS ar;

    APMState apm;

    PMSMBus smb;
    uint32_t smb_io_base;

    qemu_irq irq;
    qemu_irq smi_irq;
    int kvm_enabled;
    Notifier machine_ready;
    Notifier powerdown_notifier;

    /* for pci hotplug */
    struct pci_status pci0_status;
    uint32_t pci0_hotplug_enable;
    uint32_t pci0_slot_device_present;

    uint8_t disable_s3;
    uint8_t disable_s4;
    uint8_t s4_val;
} PIIX4PMState;

static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);

#define ACPI_ENABLE 0xf1
#define ACPI_DISABLE 0xf0

static void pm_update_sci(PIIX4PMState *s)
{
    int sci_level, pmsts;

    pmsts = acpi_pm1_evt_get_sts(&s->ar);
    sci_level = (((pmsts & s->ar.pm1.evt.en) &
                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                   ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
        (((s->ar.gpe.sts[0] & s->ar.gpe.en[0])
          & PIIX4_PCI_HOTPLUG_STATUS) != 0);

    qemu_set_irq(s->irq, sci_level);
    /* schedule a timer interruption if needed */
    acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
                       !(pmsts & ACPI_BITMASK_TIMER_STATUS));
}

static void pm_tmr_timer(ACPIREGS *ar)
{
    PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
    pm_update_sci(s);
}

static void apm_ctrl_changed(uint32_t val, void *arg)
{
    PIIX4PMState *s = arg;

    /* ACPI specs 3.0, 4.7.2.5 */
    acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);

    if (s->dev.config[0x5b] & (1 << 1)) {
        if (s->smi_irq) {
            qemu_irq_raise(s->smi_irq);
        }
    }
}

static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
}

static void pm_io_space_update(PIIX4PMState *s)
{
    uint32_t pm_io_base;

    pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
    pm_io_base &= 0xffc0;

    memory_region_transaction_begin();
    memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
    memory_region_set_address(&s->io, pm_io_base);
    memory_region_transaction_commit();
}

static void smbus_io_space_update(PIIX4PMState *s)
{
    s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90));
    s->smb_io_base &= 0xffc0;

    memory_region_transaction_begin();
    memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1);
    memory_region_set_address(&s->smb.io, s->smb_io_base);
    memory_region_transaction_commit();
}

static void pm_write_config(PCIDevice *d,
                            uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(d, address, val, len);
    if (range_covers_byte(address, len, 0x80) ||
        ranges_overlap(address, len, 0x40, 4)) {
        pm_io_space_update((PIIX4PMState *)d);
    }
    if (range_covers_byte(address, len, 0xd2) ||
        ranges_overlap(address, len, 0x90, 4)) {
        smbus_io_space_update((PIIX4PMState *)d);
    }
}

static void vmstate_pci_status_pre_save(void *opaque)
{
    struct pci_status *pci0_status = opaque;
    PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status);

    /* We no longer track up, so build a safe value for migrating
     * to a version that still does... of course these might get lost
     * by an old buggy implementation, but we try. */
    pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable;
}

static int vmstate_acpi_post_load(void *opaque, int version_id)
{
    PIIX4PMState *s = opaque;

    pm_io_space_update(s);
    return 0;
}

#define VMSTATE_GPE_ARRAY(_field, _state)                            \
 {                                                                   \
     .name       = (stringify(_field)),                              \
     .version_id = 0,                                                \
     .info       = &vmstate_info_uint16,                             \
     .size       = sizeof(uint16_t),                                 \
     .flags      = VMS_SINGLE | VMS_POINTER,                         \
     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 }

static const VMStateDescription vmstate_gpe = {
    .name = "gpe",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_GPE_ARRAY(sts, ACPIGPE),
        VMSTATE_GPE_ARRAY(en, ACPIGPE),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_status = {
    .name = "pci_status",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .pre_save = vmstate_pci_status_pre_save,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(up, struct pci_status),
        VMSTATE_UINT32(down, struct pci_status),
        VMSTATE_END_OF_LIST()
    }
};

static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
{
    PIIX4PMState *s = opaque;
    int ret, i;
    uint16_t temp;

    ret = pci_device_load(&s->dev, f);
    if (ret < 0) {
        return ret;
    }
    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
    qemu_get_be16s(f, &s->ar.pm1.evt.en);
    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);

    ret = vmstate_load_state(f, &vmstate_apm, opaque, 1);
    if (ret) {
        return ret;
    }

    qemu_get_timer(f, s->ar.tmr.timer);
    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);

    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
    for (i = 0; i < 3; i++) {
        qemu_get_be16s(f, &temp);
    }

    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
    for (i = 0; i < 3; i++) {
        qemu_get_be16s(f, &temp);
    }

    ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1);
    return ret;
}

/* qemu-kvm 1.2 uses version 3 but advertised as 2
 * To support incoming qemu-kvm 1.2 migration, change version_id
 * and minimum_version_id to 2 below (which breaks migration from
 * qemu 1.2).
 *
 */
static const VMStateDescription vmstate_acpi = {
    .name = "piix4_pm",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 1,
    .load_state_old = acpi_load_old,
    .post_load = vmstate_acpi_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
        VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
        VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
        VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
        VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
        VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
        VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
        VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
                       struct pci_status),
        VMSTATE_END_OF_LIST()
    }
};

static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
{
    BusChild *kid, *next;
    BusState *bus = qdev_get_parent_bus(&s->dev.qdev);
    int slot = ffs(slots) - 1;
    bool slot_free = true;

    /* Mark request as complete */
    s->pci0_status.down &= ~(1U << slot);

    QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
        DeviceState *qdev = kid->child;
        PCIDevice *dev = PCI_DEVICE(qdev);
        PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
        if (PCI_SLOT(dev->devfn) == slot) {
            if (pc->no_hotplug) {
                slot_free = false;
            } else {
                qdev_free(qdev);
            }
        }
    }
    if (slot_free) {
        s->pci0_slot_device_present &= ~(1U << slot);
    }
}

static void piix4_update_hotplug(PIIX4PMState *s)
{
    PCIDevice *dev = &s->dev;
    BusState *bus = qdev_get_parent_bus(&dev->qdev);
    BusChild *kid, *next;

    /* Execute any pending removes during reset */
    while (s->pci0_status.down) {
        acpi_piix_eject_slot(s, s->pci0_status.down);
    }

    s->pci0_hotplug_enable = ~0;
    s->pci0_slot_device_present = 0;

    QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
        DeviceState *qdev = kid->child;
        PCIDevice *pdev = PCI_DEVICE(qdev);
        PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
        int slot = PCI_SLOT(pdev->devfn);

        if (pc->no_hotplug) {
            s->pci0_hotplug_enable &= ~(1U << slot);
        }

        s->pci0_slot_device_present |= (1U << slot);
    }
}

static void piix4_reset(void *opaque)
{
    PIIX4PMState *s = opaque;
    uint8_t *pci_conf = s->dev.config;

    pci_conf[0x58] = 0;
    pci_conf[0x59] = 0;
    pci_conf[0x5a] = 0;
    pci_conf[0x5b] = 0;

    pci_conf[0x40] = 0x01; /* PM io base read only bit */
    pci_conf[0x80] = 0;

    if (s->kvm_enabled) {
        /* Mark SMM as already inited (until KVM supports SMM). */
        pci_conf[0x5B] = 0x02;
    }
    piix4_update_hotplug(s);
}

static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
{
    PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);

    assert(s != NULL);
    acpi_pm1_evt_power_down(&s->ar);
}

static void piix4_pm_machine_ready(Notifier *n, void *opaque)
{
    PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
    uint8_t *pci_conf;

    pci_conf = s->dev.config;
    pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
    pci_conf[0x63] = 0x60;
    pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
	(isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);

}

static int piix4_pm_initfn(PCIDevice *dev)
{
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
    uint8_t *pci_conf;

    pci_conf = s->dev.config;
    pci_conf[0x06] = 0x80;
    pci_conf[0x07] = 0x02;
    pci_conf[0x09] = 0x00;
    pci_conf[0x3d] = 0x01; // interrupt pin 1

    /* APM */
    apm_init(&s->apm, apm_ctrl_changed, s);

    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);

    if (s->kvm_enabled) {
        /* Mark SMM as already inited to prevent SMM from running.  KVM does not
         * support SMM mode. */
        pci_conf[0x5B] = 0x02;
    }

    /* XXX: which specification is used ? The i82731AB has different
       mappings */
    pci_conf[0x90] = s->smb_io_base | 1;
    pci_conf[0x91] = s->smb_io_base >> 8;
    pci_conf[0xd2] = 0x09;
    pm_smbus_init(&s->dev.qdev, &s->smb);
    memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
    memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);

    memory_region_init(&s->io, "piix4-pm", 64);
    memory_region_set_enabled(&s->io, false);
    memory_region_add_subregion(get_system_io(), 0, &s->io);

    acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
    acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
    acpi_pm1_cnt_init(&s->ar, &s->io);
    acpi_gpe_init(&s->ar, GPE_LEN);

    s->powerdown_notifier.notify = piix4_pm_powerdown_req;
    qemu_register_powerdown_notifier(&s->powerdown_notifier);

    s->machine_ready.notify = piix4_pm_machine_ready;
    qemu_add_machine_init_done_notifier(&s->machine_ready);
    qemu_register_reset(piix4_reset, s);
    piix4_acpi_system_hot_add_init(dev->bus, s);

    return 0;
}

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int kvm_enabled, void *fw_cfg)
{
    PCIDevice *dev;
    PIIX4PMState *s;

    dev = pci_create(bus, devfn, "PIIX4_PM");
    qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);

    s = DO_UPCAST(PIIX4PMState, dev, dev);
    s->irq = sci_irq;
    s->smi_irq = smi_irq;
    s->kvm_enabled = kvm_enabled;

    qdev_init_nofail(&dev->qdev);

    if (fw_cfg) {
        uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
        suspend[3] = 1 | ((!s->disable_s3) << 7);
        suspend[4] = s->s4_val | ((!s->disable_s4) << 7);

        fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
    }

    return s->smb.smbus;
}

static Property piix4_pm_properties[] = {
    DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
    DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0),
    DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0),
    DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2),
    DEFINE_PROP_END_OF_LIST(),
};

static void piix4_pm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->no_hotplug = 1;
    k->init = piix4_pm_initfn;
    k->config_write = pm_write_config;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
    k->revision = 0x03;
    k->class_id = PCI_CLASS_BRIDGE_OTHER;
    dc->desc = "PM";
    dc->no_user = 1;
    dc->vmsd = &vmstate_acpi;
    dc->props = piix4_pm_properties;
}

static TypeInfo piix4_pm_info = {
    .name          = "PIIX4_PM",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PIIX4PMState),
    .class_init    = piix4_pm_class_init,
};

static void piix4_pm_register_types(void)
{
    type_register_static(&piix4_pm_info);
}

type_init(piix4_pm_register_types)

static uint32_t gpe_readb(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);

    PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
    return val;
}

static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;

    acpi_gpe_ioport_writeb(&s->ar, addr, val);
    pm_update_sci(s);

    PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
}

static uint32_t pci_up_read(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    /* Manufacture an "up" value to cause a device check on any hotplug
     * slot with a device.  Extra device checks are harmless. */
    val = s->pci0_slot_device_present & s->pci0_hotplug_enable;

    PIIX4_DPRINTF("pci_up_read %x\n", val);
    return val;
}

static uint32_t pci_down_read(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val = s->pci0_status.down;

    PIIX4_DPRINTF("pci_down_read %x\n", val);
    return val;
}

static uint32_t pci_features_read(void *opaque, uint32_t addr)
{
    /* No feature defined yet */
    PIIX4_DPRINTF("pci_features_read %x\n", 0);
    return 0;
}

static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
{
    acpi_piix_eject_slot(opaque, val);

    PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
}

static uint32_t pcirmv_read(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;

    return s->pci0_hotplug_enable;
}

static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
                                PCIHotplugState state);

static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
{

    register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
    register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
    acpi_gpe_blk(&s->ar, GPE_BASE);

    register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
    register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);

    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
    register_ioport_read(PCI_EJ_BASE, 4, 4,  pci_features_read, s);

    register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);

    pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
}

static void enable_device(PIIX4PMState *s, int slot)
{
    s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
    s->pci0_slot_device_present |= (1U << slot);
}

static void disable_device(PIIX4PMState *s, int slot)
{
    s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
    s->pci0_status.down |= (1U << slot);
}

static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
				PCIHotplugState state)
{
    int slot = PCI_SLOT(dev->devfn);
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
                                PCI_DEVICE(qdev));

    /* Don't send event when device is enabled during qemu machine creation:
     * it is present on boot, no hotplug event is necessary. We do send an
     * event when the device is disabled later. */
    if (state == PCI_COLDPLUG_ENABLED) {
        s->pci0_slot_device_present |= (1U << slot);
        return 0;
    }

    if (state == PCI_HOTPLUG_ENABLED) {
        enable_device(s, slot);
    } else {
        disable_device(s, slot);
    }

    pm_update_sci(s);

    return 0;
}
Commit	Line	Data
93d89f63 IY	1	/*
	2	* ACPI implementation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, see <http://www.gnu.org/licenses/>
6b620ca3 PB	17	*
	18	* Contributions after 2012-01-13 are licensed under the terms of the
	19	* GNU GPL, version 2 or (at your option) any later version.
93d89f63 IY	20	*/
	21	#include "hw.h"
	22	#include "pc.h"
	23	#include "apm.h"
	24	#include "pm_smbus.h"
	25	#include "pci.h"
93d89f63	26	#include "acpi.h"
666daa68	27	#include "sysemu.h"
bf1b0071	28	#include "range.h"
6141dbfe	29	#include "ioport.h"
459ae5ea	30	#include "fw_cfg.h"
af11110b	31	#include "exec-memory.h"
93d89f63 IY	32
	33	//#define DEBUG
	34
50d8ff8b IY	35	#ifdef DEBUG
	36	# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
	37	#else
	38	# define PIIX4_DPRINTF(format, ...) do { } while (0)
	39	#endif
	40
93d89f63 IY	41	#define ACPI_DBG_IO_ADDR 0xb044
93d89f63 IY	42
ac404095	43	#define GPE_BASE 0xafe0
23910d3f	44	#define GPE_LEN 4
ba737541 AW	45	#define PCI_UP_BASE 0xae00
ba737541 AW	46	#define PCI_DOWN_BASE 0xae04
ac404095	47	#define PCI_EJ_BASE 0xae08
668643b0	48	#define PCI_RMV_BASE 0xae0c
ac404095	49
4441a287 GN	50	#define PIIX4_PCI_HOTPLUG_STATUS 2
4441a287 GN	51
ac404095	52	struct pci_status {
7faa8075	53	uint32_t up; /* deprecated, maintained for migration compatibility */
ac404095 IY	54	uint32_t down;
	55	};
	56
93d89f63 IY	57	typedef struct PIIX4PMState {
93d89f63 IY	58	PCIDevice dev;
af11110b	59	MemoryRegion io;
355bf2e5	60	ACPIREGS ar;
93d89f63 IY	61
	62	APMState apm;
	63
93d89f63	64	PMSMBus smb;
e8ec0571	65	uint32_t smb_io_base;
93d89f63 IY	66
93d89f63 IY	67	qemu_irq irq;
93d89f63 IY	68	qemu_irq smi_irq;
93d89f63 IY	69	int kvm_enabled;
6141dbfe	70	Notifier machine_ready;
d010f91c	71	Notifier powerdown_notifier;
ac404095 IY	72
ac404095 IY	73	/* for pci hotplug */
ac404095	74	struct pci_status pci0_status;
668643b0	75	uint32_t pci0_hotplug_enable;
7faa8075	76	uint32_t pci0_slot_device_present;
459ae5ea GN	77
	78	uint8_t disable_s3;
	79	uint8_t disable_s4;
	80	uint8_t s4_val;
93d89f63 IY	81	} PIIX4PMState;
93d89f63 IY	82
ac404095 IY	83	static void piix4_acpi_system_hot_add_init(PCIBus bus, PIIX4PMState s);
ac404095 IY	84
93d89f63 IY	85	#define ACPI_ENABLE 0xf1
	86	#define ACPI_DISABLE 0xf0
	87
93d89f63 IY	88	static void pm_update_sci(PIIX4PMState *s)
	89	{
	90	int sci_level, pmsts;
93d89f63	91
2886be1b	92	pmsts = acpi_pm1_evt_get_sts(&s->ar);
355bf2e5	93	sci_level = (((pmsts & s->ar.pm1.evt.en) &
93d89f63 IY	94	(ACPI_BITMASK_RT_CLOCK_ENABLE \|
	95	ACPI_BITMASK_POWER_BUTTON_ENABLE \|
	96	ACPI_BITMASK_GLOBAL_LOCK_ENABLE \|
633aa0ac	97	ACPI_BITMASK_TIMER_ENABLE)) != 0) \|\|
355bf2e5 GH	98	(((s->ar.gpe.sts[0] & s->ar.gpe.en[0])
355bf2e5 GH	99	& PIIX4_PCI_HOTPLUG_STATUS) != 0);
633aa0ac	100
93d89f63 IY	101	qemu_set_irq(s->irq, sci_level);
93d89f63 IY	102	/* schedule a timer interruption if needed */
355bf2e5	103	acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
a54d41a8	104	!(pmsts & ACPI_BITMASK_TIMER_STATUS));
93d89f63 IY	105	}
93d89f63 IY	106
355bf2e5	107	static void pm_tmr_timer(ACPIREGS *ar)
93d89f63	108	{
355bf2e5	109	PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
93d89f63 IY	110	pm_update_sci(s);
	111	}
	112
93d89f63 IY	113	static void apm_ctrl_changed(uint32_t val, void *arg)
	114	{
	115	PIIX4PMState *s = arg;
	116
	117	/* ACPI specs 3.0, 4.7.2.5 */
355bf2e5	118	acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
93d89f63 IY	119
	120	if (s->dev.config[0x5b] & (1 << 1)) {
	121	if (s->smi_irq) {
	122	qemu_irq_raise(s->smi_irq);
	123	}
	124	}
	125	}
	126
	127	static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
	128	{
50d8ff8b	129	PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
93d89f63 IY	130	}
	131
	132	static void pm_io_space_update(PIIX4PMState *s)
	133	{
	134	uint32_t pm_io_base;
	135
af11110b GH	136	pm_io_base = le32_to_cpu((uint32_t )(s->dev.config + 0x40));
af11110b GH	137	pm_io_base &= 0xffc0;
93d89f63	138
af11110b GH	139	memory_region_transaction_begin();
	140	memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
	141	memory_region_set_address(&s->io, pm_io_base);
	142	memory_region_transaction_commit();
93d89f63 IY	143	}
93d89f63 IY	144
24fe083d GH	145	static void smbus_io_space_update(PIIX4PMState *s)
	146	{
	147	s->smb_io_base = le32_to_cpu((uint32_t )(s->dev.config + 0x90));
	148	s->smb_io_base &= 0xffc0;
	149
	150	memory_region_transaction_begin();
	151	memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1);
	152	memory_region_set_address(&s->smb.io, s->smb_io_base);
	153	memory_region_transaction_commit();
	154	}
	155
93d89f63 IY	156	static void pm_write_config(PCIDevice *d,
	157	uint32_t address, uint32_t val, int len)
	158	{
	159	pci_default_write_config(d, address, val, len);
24fe083d GH	160	if (range_covers_byte(address, len, 0x80) \|\|
24fe083d GH	161	ranges_overlap(address, len, 0x40, 4)) {
93d89f63	162	pm_io_space_update((PIIX4PMState *)d);
24fe083d GH	163	}
	164	if (range_covers_byte(address, len, 0xd2) \|\|
	165	ranges_overlap(address, len, 0x90, 4)) {
	166	smbus_io_space_update((PIIX4PMState *)d);
	167	}
93d89f63 IY	168	}
93d89f63 IY	169
7faa8075 AW	170	static void vmstate_pci_status_pre_save(void *opaque)
	171	{
	172	struct pci_status *pci0_status = opaque;
	173	PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status);
	174
	175	/* We no longer track up, so build a safe value for migrating
	176	* to a version that still does... of course these might get lost
	177	* by an old buggy implementation, but we try. */
	178	pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable;
	179	}
	180
93d89f63 IY	181	static int vmstate_acpi_post_load(void *opaque, int version_id)
	182	{
	183	PIIX4PMState *s = opaque;
	184
	185	pm_io_space_update(s);
	186	return 0;
	187	}
	188
23910d3f IY	189	#define VMSTATE_GPE_ARRAY(_field, _state) \
	190	{ \
	191	.name = (stringify(_field)), \
	192	.version_id = 0, \
23910d3f IY	193	.info = &vmstate_info_uint16, \
23910d3f IY	194	.size = sizeof(uint16_t), \
b0b873a0	195	.flags = VMS_SINGLE \| VMS_POINTER, \
23910d3f IY	196	.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
	197	}
	198
4cf3e6f3 AW	199	static const VMStateDescription vmstate_gpe = {
	200	.name = "gpe",
	201	.version_id = 1,
	202	.minimum_version_id = 1,
	203	.minimum_version_id_old = 1,
	204	.fields = (VMStateField []) {
23910d3f IY	205	VMSTATE_GPE_ARRAY(sts, ACPIGPE),
23910d3f IY	206	VMSTATE_GPE_ARRAY(en, ACPIGPE),
4cf3e6f3 AW	207	VMSTATE_END_OF_LIST()
	208	}
	209	};
	210
	211	static const VMStateDescription vmstate_pci_status = {
	212	.name = "pci_status",
	213	.version_id = 1,
	214	.minimum_version_id = 1,
	215	.minimum_version_id_old = 1,
7faa8075	216	.pre_save = vmstate_pci_status_pre_save,
4cf3e6f3 AW	217	.fields = (VMStateField []) {
	218	VMSTATE_UINT32(up, struct pci_status),
	219	VMSTATE_UINT32(down, struct pci_status),
	220	VMSTATE_END_OF_LIST()
	221	}
	222	};
	223
b0b873a0 MT	224	static int acpi_load_old(QEMUFile f, void opaque, int version_id)
	225	{
	226	PIIX4PMState *s = opaque;
	227	int ret, i;
	228	uint16_t temp;
	229
	230	ret = pci_device_load(&s->dev, f);
	231	if (ret < 0) {
	232	return ret;
	233	}
	234	qemu_get_be16s(f, &s->ar.pm1.evt.sts);
	235	qemu_get_be16s(f, &s->ar.pm1.evt.en);
	236	qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
	237
	238	ret = vmstate_load_state(f, &vmstate_apm, opaque, 1);
	239	if (ret) {
	240	return ret;
	241	}
	242
	243	qemu_get_timer(f, s->ar.tmr.timer);
	244	qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
	245
	246	qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
	247	for (i = 0; i < 3; i++) {
	248	qemu_get_be16s(f, &temp);
	249	}
	250
	251	qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
	252	for (i = 0; i < 3; i++) {
	253	qemu_get_be16s(f, &temp);
	254	}
	255
	256	ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1);
	257	return ret;
	258	}
	259
	260	/* qemu-kvm 1.2 uses version 3 but advertised as 2
	261	* To support incoming qemu-kvm 1.2 migration, change version_id
	262	* and minimum_version_id to 2 below (which breaks migration from
	263	* qemu 1.2).
	264	*
	265	*/
93d89f63 IY	266	static const VMStateDescription vmstate_acpi = {
93d89f63 IY	267	.name = "piix4_pm",
b0b873a0 MT	268	.version_id = 3,
b0b873a0 MT	269	.minimum_version_id = 3,
93d89f63	270	.minimum_version_id_old = 1,
b0b873a0	271	.load_state_old = acpi_load_old,
93d89f63 IY	272	.post_load = vmstate_acpi_post_load,
	273	.fields = (VMStateField []) {
	274	VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
355bf2e5 GH	275	VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
	276	VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
	277	VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
93d89f63	278	VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
355bf2e5 GH	279	VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
	280	VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
	281	VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
4cf3e6f3 AW	282	VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
4cf3e6f3 AW	283	struct pci_status),
93d89f63 IY	284	VMSTATE_END_OF_LIST()
	285	}
	286	};
	287
7faa8075 AW	288	static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
7faa8075 AW	289	{
0866aca1	290	BusChild kid, next;
7faa8075 AW	291	BusState *bus = qdev_get_parent_bus(&s->dev.qdev);
7faa8075 AW	292	int slot = ffs(slots) - 1;
54bfa546	293	bool slot_free = true;
7faa8075 AW	294
	295	/* Mark request as complete */
	296	s->pci0_status.down &= ~(1U << slot);
	297
0866aca1 AL	298	QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
0866aca1 AL	299	DeviceState *qdev = kid->child;
7faa8075 AW	300	PCIDevice *dev = PCI_DEVICE(qdev);
7faa8075 AW	301	PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
54bfa546 MT	302	if (PCI_SLOT(dev->devfn) == slot) {
	303	if (pc->no_hotplug) {
	304	slot_free = false;
	305	} else {
	306	qdev_free(qdev);
	307	}
7faa8075 AW	308	}
7faa8075 AW	309	}
54bfa546 MT	310	if (slot_free) {
	311	s->pci0_slot_device_present &= ~(1U << slot);
	312	}
7faa8075 AW	313	}
7faa8075 AW	314
668643b0 MT	315	static void piix4_update_hotplug(PIIX4PMState *s)
	316	{
	317	PCIDevice *dev = &s->dev;
	318	BusState *bus = qdev_get_parent_bus(&dev->qdev);
0866aca1	319	BusChild kid, next;
668643b0	320
7faa8075 AW	321	/* Execute any pending removes during reset */
	322	while (s->pci0_status.down) {
	323	acpi_piix_eject_slot(s, s->pci0_status.down);
	324	}
	325
668643b0	326	s->pci0_hotplug_enable = ~0;
7faa8075	327	s->pci0_slot_device_present = 0;
668643b0	328
0866aca1 AL	329	QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
0866aca1 AL	330	DeviceState *qdev = kid->child;
40021f08 AL	331	PCIDevice *pdev = PCI_DEVICE(qdev);
40021f08 AL	332	PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
668643b0 MT	333	int slot = PCI_SLOT(pdev->devfn);
668643b0 MT	334
40021f08	335	if (pc->no_hotplug) {
7faa8075	336	s->pci0_hotplug_enable &= ~(1U << slot);
668643b0	337	}
7faa8075 AW	338
7faa8075 AW	339	s->pci0_slot_device_present \|= (1U << slot);
668643b0 MT	340	}
	341	}
	342
93d89f63 IY	343	static void piix4_reset(void *opaque)
	344	{
	345	PIIX4PMState *s = opaque;
	346	uint8_t *pci_conf = s->dev.config;
	347
	348	pci_conf[0x58] = 0;
	349	pci_conf[0x59] = 0;
	350	pci_conf[0x5a] = 0;
	351	pci_conf[0x5b] = 0;
	352
4d09d37c GN	353	pci_conf[0x40] = 0x01; /* PM io base read only bit */
	354	pci_conf[0x80] = 0;
	355
93d89f63 IY	356	if (s->kvm_enabled) {
	357	/* Mark SMM as already inited (until KVM supports SMM). */
	358	pci_conf[0x5B] = 0x02;
	359	}
668643b0	360	piix4_update_hotplug(s);
93d89f63 IY	361	}
93d89f63 IY	362
d010f91c	363	static void piix4_pm_powerdown_req(Notifier n, void opaque)
93d89f63	364	{
d010f91c	365	PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
93d89f63	366
355bf2e5 GH	367	assert(s != NULL);
355bf2e5 GH	368	acpi_pm1_evt_power_down(&s->ar);
93d89f63 IY	369	}
93d89f63 IY	370
9e8dd451	371	static void piix4_pm_machine_ready(Notifier n, void opaque)
6141dbfe PB	372	{
	373	PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
	374	uint8_t *pci_conf;
	375
	376	pci_conf = s->dev.config;
	377	pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) \| 0x10;
	378	pci_conf[0x63] = 0x60;
	379	pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) \|
	380	(isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
	381
	382	}
	383
e8ec0571	384	static int piix4_pm_initfn(PCIDevice *dev)
93d89f63	385	{
e8ec0571	386	PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
93d89f63 IY	387	uint8_t *pci_conf;
93d89f63 IY	388
93d89f63	389	pci_conf = s->dev.config;
93d89f63 IY	390	pci_conf[0x06] = 0x80;
93d89f63 IY	391	pci_conf[0x07] = 0x02;
93d89f63	392	pci_conf[0x09] = 0x00;
93d89f63 IY	393	pci_conf[0x3d] = 0x01; // interrupt pin 1
93d89f63 IY	394
93d89f63 IY	395	/* APM */
	396	apm_init(&s->apm, apm_ctrl_changed, s);
	397
	398	register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
	399
93d89f63 IY	400	if (s->kvm_enabled) {
	401	/* Mark SMM as already inited to prevent SMM from running. KVM does not
	402	* support SMM mode. */
	403	pci_conf[0x5B] = 0x02;
	404	}
	405
	406	/* XXX: which specification is used ? The i82731AB has different
	407	mappings */
e8ec0571 IY	408	pci_conf[0x90] = s->smb_io_base \| 1;
e8ec0571 IY	409	pci_conf[0x91] = s->smb_io_base >> 8;
93d89f63	410	pci_conf[0xd2] = 0x09;
798512e5	411	pm_smbus_init(&s->dev.qdev, &s->smb);
24fe083d	412	memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
798512e5	413	memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
93d89f63	414
ca5d64b4	415	memory_region_init(&s->io, "piix4-pm", 64);
af11110b GH	416	memory_region_set_enabled(&s->io, false);
	417	memory_region_add_subregion(get_system_io(), 0, &s->io);
	418
77d58b1e	419	acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
b5a7c024	420	acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
afafe4bb	421	acpi_pm1_cnt_init(&s->ar, &s->io);
355bf2e5	422	acpi_gpe_init(&s->ar, GPE_LEN);
93d89f63	423
d010f91c IM	424	s->powerdown_notifier.notify = piix4_pm_powerdown_req;
d010f91c IM	425	qemu_register_powerdown_notifier(&s->powerdown_notifier);
93d89f63	426
6141dbfe PB	427	s->machine_ready.notify = piix4_pm_machine_ready;
6141dbfe PB	428	qemu_add_machine_init_done_notifier(&s->machine_ready);
e8ec0571	429	qemu_register_reset(piix4_reset, s);
ac404095	430	piix4_acpi_system_hot_add_init(dev->bus, s);
e8ec0571 IY	431
	432	return 0;
	433	}
	434
	435	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
da98c8eb	436	qemu_irq sci_irq, qemu_irq smi_irq,
459ae5ea	437	int kvm_enabled, void *fw_cfg)
e8ec0571 IY	438	{
	439	PCIDevice *dev;
	440	PIIX4PMState *s;
	441
	442	dev = pci_create(bus, devfn, "PIIX4_PM");
	443	qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
93d89f63	444
e8ec0571	445	s = DO_UPCAST(PIIX4PMState, dev, dev);
93d89f63	446	s->irq = sci_irq;
93d89f63	447	s->smi_irq = smi_irq;
e8ec0571 IY	448	s->kvm_enabled = kvm_enabled;
	449
	450	qdev_init_nofail(&dev->qdev);
93d89f63	451
459ae5ea GN	452	if (fw_cfg) {
	453	uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
	454	suspend[3] = 1 \| ((!s->disable_s3) << 7);
	455	suspend[4] = s->s4_val \| ((!s->disable_s4) << 7);
	456
	457	fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
	458	}
	459
93d89f63 IY	460	return s->smb.smbus;
	461	}
	462
40021f08 AL	463	static Property piix4_pm_properties[] = {
40021f08 AL	464	DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
459ae5ea GN	465	DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0),
	466	DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0),
	467	DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2),
40021f08 AL	468	DEFINE_PROP_END_OF_LIST(),
	469	};
	470
	471	static void piix4_pm_class_init(ObjectClass klass, void data)
	472	{
39bffca2	473	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	474	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	475
	476	k->no_hotplug = 1;
	477	k->init = piix4_pm_initfn;
	478	k->config_write = pm_write_config;
	479	k->vendor_id = PCI_VENDOR_ID_INTEL;
	480	k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
	481	k->revision = 0x03;
	482	k->class_id = PCI_CLASS_BRIDGE_OTHER;
39bffca2 AL	483	dc->desc = "PM";
	484	dc->no_user = 1;
	485	dc->vmsd = &vmstate_acpi;
	486	dc->props = piix4_pm_properties;
40021f08 AL	487	}
40021f08 AL	488
39bffca2 AL	489	static TypeInfo piix4_pm_info = {
	490	.name = "PIIX4_PM",
	491	.parent = TYPE_PCI_DEVICE,
	492	.instance_size = sizeof(PIIX4PMState),
	493	.class_init = piix4_pm_class_init,
e8ec0571 IY	494	};
e8ec0571 IY	495
83f7d43a	496	static void piix4_pm_register_types(void)
e8ec0571	497	{
39bffca2	498	type_register_static(&piix4_pm_info);
e8ec0571 IY	499	}
e8ec0571 IY	500
83f7d43a	501	type_init(piix4_pm_register_types)
e8ec0571	502
93d89f63 IY	503	static uint32_t gpe_readb(void *opaque, uint32_t addr)
93d89f63 IY	504	{
633aa0ac	505	PIIX4PMState *s = opaque;
355bf2e5	506	uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
93d89f63	507
50d8ff8b	508	PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
93d89f63 IY	509	return val;
	510	}
	511
93d89f63 IY	512	static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
93d89f63 IY	513	{
633aa0ac	514	PIIX4PMState *s = opaque;
633aa0ac	515
355bf2e5	516	acpi_gpe_ioport_writeb(&s->ar, addr, val);
633aa0ac	517	pm_update_sci(s);
93d89f63	518
50d8ff8b	519	PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
93d89f63 IY	520	}
93d89f63 IY	521
ba737541	522	static uint32_t pci_up_read(void *opaque, uint32_t addr)
93d89f63	523	{
ba737541	524	PIIX4PMState *s = opaque;
7faa8075 AW	525	uint32_t val;
	526
	527	/* Manufacture an "up" value to cause a device check on any hotplug
	528	* slot with a device. Extra device checks are harmless. */
	529	val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
93d89f63	530
ba737541	531	PIIX4_DPRINTF("pci_up_read %x\n", val);
93d89f63 IY	532	return val;
	533	}
	534
ba737541	535	static uint32_t pci_down_read(void *opaque, uint32_t addr)
93d89f63	536	{
ba737541 AW	537	PIIX4PMState *s = opaque;
	538	uint32_t val = s->pci0_status.down;
	539
	540	PIIX4_DPRINTF("pci_down_read %x\n", val);
	541	return val;
93d89f63 IY	542	}
93d89f63 IY	543
9290f364	544	static uint32_t pci_features_read(void *opaque, uint32_t addr)
93d89f63	545	{
9290f364 AW	546	/* No feature defined yet */
9290f364 AW	547	PIIX4_DPRINTF("pci_features_read %x\n", 0);
93d89f63 IY	548	return 0;
	549	}
	550
	551	static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
	552	{
7faa8075	553	acpi_piix_eject_slot(opaque, val);
93d89f63	554
50d8ff8b	555	PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
93d89f63 IY	556	}
93d89f63 IY	557
668643b0 MT	558	static uint32_t pcirmv_read(void *opaque, uint32_t addr)
	559	{
	560	PIIX4PMState *s = opaque;
	561
	562	return s->pci0_hotplug_enable;
	563	}
	564
4cff0a59 MT	565	static int piix4_device_hotplug(DeviceState qdev, PCIDevice dev,
4cff0a59 MT	566	PCIHotplugState state);
93d89f63	567
ac404095	568	static void piix4_acpi_system_hot_add_init(PCIBus bus, PIIX4PMState s)
93d89f63	569	{
93d89f63	570
23910d3f IY	571	register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
23910d3f IY	572	register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s);
355bf2e5	573	acpi_gpe_blk(&s->ar, GPE_BASE);
ac404095	574
ba737541 AW	575	register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
ba737541 AW	576	register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
93d89f63	577
7faa8075	578	register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
9290f364	579	register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s);
93d89f63	580
668643b0 MT	581	register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
668643b0 MT	582
ac404095	583	pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
93d89f63 IY	584	}
93d89f63 IY	585
ac404095	586	static void enable_device(PIIX4PMState *s, int slot)
93d89f63	587	{
355bf2e5	588	s->ar.gpe.sts[0] \|= PIIX4_PCI_HOTPLUG_STATUS;
7faa8075	589	s->pci0_slot_device_present \|= (1U << slot);
93d89f63 IY	590	}
93d89f63 IY	591
ac404095	592	static void disable_device(PIIX4PMState *s, int slot)
93d89f63	593	{
355bf2e5	594	s->ar.gpe.sts[0] \|= PIIX4_PCI_HOTPLUG_STATUS;
7faa8075	595	s->pci0_status.down \|= (1U << slot);
93d89f63 IY	596	}
93d89f63 IY	597
4cff0a59 MT	598	static int piix4_device_hotplug(DeviceState qdev, PCIDevice dev,
4cff0a59 MT	599	PCIHotplugState state)
93d89f63 IY	600	{
93d89f63 IY	601	int slot = PCI_SLOT(dev->devfn);
ac404095	602	PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
40021f08	603	PCI_DEVICE(qdev));
93d89f63	604
4cff0a59 MT	605	/* Don't send event when device is enabled during qemu machine creation:
	606	* it is present on boot, no hotplug event is necessary. We do send an
	607	* event when the device is disabled later. */
	608	if (state == PCI_COLDPLUG_ENABLED) {
7faa8075	609	s->pci0_slot_device_present \|= (1U << slot);
5beb8ad5	610	return 0;
4cff0a59	611	}
5beb8ad5	612
4cff0a59	613	if (state == PCI_HOTPLUG_ENABLED) {
ac404095 IY	614	enable_device(s, slot);
	615	} else {
	616	disable_device(s, slot);
	617	}
633aa0ac GN	618
	619	pm_update_sci(s);
	620
93d89f63 IY	621	return 0;
93d89f63 IY	622	}