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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 IY |
20 | */ |
21 | #include "hw.h" | |
22 | #include "pc.h" | |
23 | #include "apm.h" | |
24 | #include "pm_smbus.h" | |
25 | #include "pci.h" | |
93d89f63 | 26 | #include "acpi.h" |
666daa68 | 27 | #include "sysemu.h" |
bf1b0071 | 28 | #include "range.h" |
6141dbfe | 29 | #include "ioport.h" |
459ae5ea | 30 | #include "fw_cfg.h" |
af11110b | 31 | #include "exec-memory.h" |
93d89f63 IY |
32 | |
33 | //#define DEBUG | |
34 | ||
50d8ff8b IY |
35 | #ifdef DEBUG |
36 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
37 | #else | |
38 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
39 | #endif | |
40 | ||
93d89f63 IY |
41 | #define ACPI_DBG_IO_ADDR 0xb044 |
42 | ||
ac404095 | 43 | #define GPE_BASE 0xafe0 |
23910d3f | 44 | #define GPE_LEN 4 |
ba737541 AW |
45 | #define PCI_UP_BASE 0xae00 |
46 | #define PCI_DOWN_BASE 0xae04 | |
ac404095 | 47 | #define PCI_EJ_BASE 0xae08 |
668643b0 | 48 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 49 | |
4441a287 GN |
50 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
51 | ||
ac404095 | 52 | struct pci_status { |
7faa8075 | 53 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
54 | uint32_t down; |
55 | }; | |
56 | ||
93d89f63 IY |
57 | typedef struct PIIX4PMState { |
58 | PCIDevice dev; | |
af11110b | 59 | MemoryRegion io; |
355bf2e5 | 60 | ACPIREGS ar; |
93d89f63 IY |
61 | |
62 | APMState apm; | |
63 | ||
93d89f63 | 64 | PMSMBus smb; |
e8ec0571 | 65 | uint32_t smb_io_base; |
93d89f63 IY |
66 | |
67 | qemu_irq irq; | |
93d89f63 IY |
68 | qemu_irq smi_irq; |
69 | int kvm_enabled; | |
6141dbfe | 70 | Notifier machine_ready; |
d010f91c | 71 | Notifier powerdown_notifier; |
ac404095 IY |
72 | |
73 | /* for pci hotplug */ | |
ac404095 | 74 | struct pci_status pci0_status; |
668643b0 | 75 | uint32_t pci0_hotplug_enable; |
7faa8075 | 76 | uint32_t pci0_slot_device_present; |
459ae5ea GN |
77 | |
78 | uint8_t disable_s3; | |
79 | uint8_t disable_s4; | |
80 | uint8_t s4_val; | |
93d89f63 IY |
81 | } PIIX4PMState; |
82 | ||
ac404095 IY |
83 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
84 | ||
93d89f63 IY |
85 | #define ACPI_ENABLE 0xf1 |
86 | #define ACPI_DISABLE 0xf0 | |
87 | ||
93d89f63 IY |
88 | static void pm_update_sci(PIIX4PMState *s) |
89 | { | |
90 | int sci_level, pmsts; | |
93d89f63 | 91 | |
2886be1b | 92 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 93 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
93d89f63 IY |
94 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
95 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
96 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 97 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
355bf2e5 GH |
98 | (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) |
99 | & PIIX4_PCI_HOTPLUG_STATUS) != 0); | |
633aa0ac | 100 | |
93d89f63 IY |
101 | qemu_set_irq(s->irq, sci_level); |
102 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 103 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 104 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
105 | } |
106 | ||
355bf2e5 | 107 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 108 | { |
355bf2e5 | 109 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
93d89f63 IY |
110 | pm_update_sci(s); |
111 | } | |
112 | ||
af11110b GH |
113 | static void pm_ioport_write(void *opaque, hwaddr addr, uint64_t val, |
114 | unsigned width) | |
93d89f63 | 115 | { |
af11110b | 116 | PIIX4PMState *s = opaque; |
2871a3f6 AK |
117 | |
118 | if (width != 2) { | |
119 | PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", | |
120 | (unsigned)addr, width, (unsigned)val); | |
121 | } | |
122 | ||
93d89f63 IY |
123 | switch(addr) { |
124 | case 0x00: | |
355bf2e5 | 125 | acpi_pm1_evt_write_sts(&s->ar, val); |
04dc308f | 126 | pm_update_sci(s); |
93d89f63 IY |
127 | break; |
128 | case 0x02: | |
8283c4f5 | 129 | acpi_pm1_evt_write_en(&s->ar, val); |
93d89f63 IY |
130 | pm_update_sci(s); |
131 | break; | |
93d89f63 IY |
132 | default: |
133 | break; | |
134 | } | |
59df4c11 WC |
135 | PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr, |
136 | (unsigned int)val); | |
93d89f63 IY |
137 | } |
138 | ||
af11110b | 139 | static uint64_t pm_ioport_read(void *opaque, hwaddr addr, unsigned width) |
93d89f63 | 140 | { |
af11110b | 141 | PIIX4PMState *s = opaque; |
93d89f63 IY |
142 | uint32_t val; |
143 | ||
93d89f63 IY |
144 | switch(addr) { |
145 | case 0x00: | |
2886be1b | 146 | val = acpi_pm1_evt_get_sts(&s->ar); |
93d89f63 IY |
147 | break; |
148 | case 0x02: | |
355bf2e5 | 149 | val = s->ar.pm1.evt.en; |
93d89f63 | 150 | break; |
93d89f63 IY |
151 | default: |
152 | val = 0; | |
153 | break; | |
154 | } | |
59df4c11 | 155 | PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val); |
af11110b | 156 | return val; |
93d89f63 IY |
157 | } |
158 | ||
af11110b | 159 | static const MemoryRegionOps pm_io_ops = { |
2871a3f6 AK |
160 | .read = pm_ioport_read, |
161 | .write = pm_ioport_write, | |
af11110b GH |
162 | .valid.min_access_size = 1, |
163 | .valid.max_access_size = 4, | |
164 | .impl.min_access_size = 1, | |
165 | .impl.max_access_size = 4, | |
166 | .endianness = DEVICE_LITTLE_ENDIAN, | |
2871a3f6 AK |
167 | }; |
168 | ||
93d89f63 IY |
169 | static void apm_ctrl_changed(uint32_t val, void *arg) |
170 | { | |
171 | PIIX4PMState *s = arg; | |
172 | ||
173 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 174 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 IY |
175 | |
176 | if (s->dev.config[0x5b] & (1 << 1)) { | |
177 | if (s->smi_irq) { | |
178 | qemu_irq_raise(s->smi_irq); | |
179 | } | |
180 | } | |
181 | } | |
182 | ||
183 | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) | |
184 | { | |
50d8ff8b | 185 | PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); |
93d89f63 IY |
186 | } |
187 | ||
188 | static void pm_io_space_update(PIIX4PMState *s) | |
189 | { | |
190 | uint32_t pm_io_base; | |
191 | ||
af11110b GH |
192 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); |
193 | pm_io_base &= 0xffc0; | |
93d89f63 | 194 | |
af11110b GH |
195 | memory_region_transaction_begin(); |
196 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
197 | memory_region_set_address(&s->io, pm_io_base); | |
198 | memory_region_transaction_commit(); | |
93d89f63 IY |
199 | } |
200 | ||
201 | static void pm_write_config(PCIDevice *d, | |
202 | uint32_t address, uint32_t val, int len) | |
203 | { | |
204 | pci_default_write_config(d, address, val, len); | |
205 | if (range_covers_byte(address, len, 0x80)) | |
206 | pm_io_space_update((PIIX4PMState *)d); | |
207 | } | |
208 | ||
7faa8075 AW |
209 | static void vmstate_pci_status_pre_save(void *opaque) |
210 | { | |
211 | struct pci_status *pci0_status = opaque; | |
212 | PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); | |
213 | ||
214 | /* We no longer track up, so build a safe value for migrating | |
215 | * to a version that still does... of course these might get lost | |
216 | * by an old buggy implementation, but we try. */ | |
217 | pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
218 | } | |
219 | ||
93d89f63 IY |
220 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
221 | { | |
222 | PIIX4PMState *s = opaque; | |
223 | ||
224 | pm_io_space_update(s); | |
225 | return 0; | |
226 | } | |
227 | ||
23910d3f IY |
228 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
229 | { \ | |
230 | .name = (stringify(_field)), \ | |
231 | .version_id = 0, \ | |
23910d3f IY |
232 | .info = &vmstate_info_uint16, \ |
233 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 234 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
235 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
236 | } | |
237 | ||
4cf3e6f3 AW |
238 | static const VMStateDescription vmstate_gpe = { |
239 | .name = "gpe", | |
240 | .version_id = 1, | |
241 | .minimum_version_id = 1, | |
242 | .minimum_version_id_old = 1, | |
243 | .fields = (VMStateField []) { | |
23910d3f IY |
244 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
245 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
246 | VMSTATE_END_OF_LIST() |
247 | } | |
248 | }; | |
249 | ||
250 | static const VMStateDescription vmstate_pci_status = { | |
251 | .name = "pci_status", | |
252 | .version_id = 1, | |
253 | .minimum_version_id = 1, | |
254 | .minimum_version_id_old = 1, | |
7faa8075 | 255 | .pre_save = vmstate_pci_status_pre_save, |
4cf3e6f3 AW |
256 | .fields = (VMStateField []) { |
257 | VMSTATE_UINT32(up, struct pci_status), | |
258 | VMSTATE_UINT32(down, struct pci_status), | |
259 | VMSTATE_END_OF_LIST() | |
260 | } | |
261 | }; | |
262 | ||
b0b873a0 MT |
263 | static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
264 | { | |
265 | PIIX4PMState *s = opaque; | |
266 | int ret, i; | |
267 | uint16_t temp; | |
268 | ||
269 | ret = pci_device_load(&s->dev, f); | |
270 | if (ret < 0) { | |
271 | return ret; | |
272 | } | |
273 | qemu_get_be16s(f, &s->ar.pm1.evt.sts); | |
274 | qemu_get_be16s(f, &s->ar.pm1.evt.en); | |
275 | qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); | |
276 | ||
277 | ret = vmstate_load_state(f, &vmstate_apm, opaque, 1); | |
278 | if (ret) { | |
279 | return ret; | |
280 | } | |
281 | ||
282 | qemu_get_timer(f, s->ar.tmr.timer); | |
283 | qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); | |
284 | ||
285 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); | |
286 | for (i = 0; i < 3; i++) { | |
287 | qemu_get_be16s(f, &temp); | |
288 | } | |
289 | ||
290 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); | |
291 | for (i = 0; i < 3; i++) { | |
292 | qemu_get_be16s(f, &temp); | |
293 | } | |
294 | ||
295 | ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1); | |
296 | return ret; | |
297 | } | |
298 | ||
299 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 | |
300 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
301 | * and minimum_version_id to 2 below (which breaks migration from | |
302 | * qemu 1.2). | |
303 | * | |
304 | */ | |
93d89f63 IY |
305 | static const VMStateDescription vmstate_acpi = { |
306 | .name = "piix4_pm", | |
b0b873a0 MT |
307 | .version_id = 3, |
308 | .minimum_version_id = 3, | |
93d89f63 | 309 | .minimum_version_id_old = 1, |
b0b873a0 | 310 | .load_state_old = acpi_load_old, |
93d89f63 IY |
311 | .post_load = vmstate_acpi_post_load, |
312 | .fields = (VMStateField []) { | |
313 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
355bf2e5 GH |
314 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
315 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
316 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 317 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
318 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
319 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
320 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
4cf3e6f3 AW |
321 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
322 | struct pci_status), | |
93d89f63 IY |
323 | VMSTATE_END_OF_LIST() |
324 | } | |
325 | }; | |
326 | ||
7faa8075 AW |
327 | static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) |
328 | { | |
0866aca1 | 329 | BusChild *kid, *next; |
7faa8075 AW |
330 | BusState *bus = qdev_get_parent_bus(&s->dev.qdev); |
331 | int slot = ffs(slots) - 1; | |
54bfa546 | 332 | bool slot_free = true; |
7faa8075 AW |
333 | |
334 | /* Mark request as complete */ | |
335 | s->pci0_status.down &= ~(1U << slot); | |
336 | ||
0866aca1 AL |
337 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
338 | DeviceState *qdev = kid->child; | |
7faa8075 AW |
339 | PCIDevice *dev = PCI_DEVICE(qdev); |
340 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
54bfa546 MT |
341 | if (PCI_SLOT(dev->devfn) == slot) { |
342 | if (pc->no_hotplug) { | |
343 | slot_free = false; | |
344 | } else { | |
345 | qdev_free(qdev); | |
346 | } | |
7faa8075 AW |
347 | } |
348 | } | |
54bfa546 MT |
349 | if (slot_free) { |
350 | s->pci0_slot_device_present &= ~(1U << slot); | |
351 | } | |
7faa8075 AW |
352 | } |
353 | ||
668643b0 MT |
354 | static void piix4_update_hotplug(PIIX4PMState *s) |
355 | { | |
356 | PCIDevice *dev = &s->dev; | |
357 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
0866aca1 | 358 | BusChild *kid, *next; |
668643b0 | 359 | |
7faa8075 AW |
360 | /* Execute any pending removes during reset */ |
361 | while (s->pci0_status.down) { | |
362 | acpi_piix_eject_slot(s, s->pci0_status.down); | |
363 | } | |
364 | ||
668643b0 | 365 | s->pci0_hotplug_enable = ~0; |
7faa8075 | 366 | s->pci0_slot_device_present = 0; |
668643b0 | 367 | |
0866aca1 AL |
368 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
369 | DeviceState *qdev = kid->child; | |
40021f08 AL |
370 | PCIDevice *pdev = PCI_DEVICE(qdev); |
371 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); | |
668643b0 MT |
372 | int slot = PCI_SLOT(pdev->devfn); |
373 | ||
40021f08 | 374 | if (pc->no_hotplug) { |
7faa8075 | 375 | s->pci0_hotplug_enable &= ~(1U << slot); |
668643b0 | 376 | } |
7faa8075 AW |
377 | |
378 | s->pci0_slot_device_present |= (1U << slot); | |
668643b0 MT |
379 | } |
380 | } | |
381 | ||
93d89f63 IY |
382 | static void piix4_reset(void *opaque) |
383 | { | |
384 | PIIX4PMState *s = opaque; | |
385 | uint8_t *pci_conf = s->dev.config; | |
386 | ||
387 | pci_conf[0x58] = 0; | |
388 | pci_conf[0x59] = 0; | |
389 | pci_conf[0x5a] = 0; | |
390 | pci_conf[0x5b] = 0; | |
391 | ||
4d09d37c GN |
392 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
393 | pci_conf[0x80] = 0; | |
394 | ||
93d89f63 IY |
395 | if (s->kvm_enabled) { |
396 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
397 | pci_conf[0x5B] = 0x02; | |
398 | } | |
668643b0 | 399 | piix4_update_hotplug(s); |
93d89f63 IY |
400 | } |
401 | ||
d010f91c | 402 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 403 | { |
d010f91c | 404 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 405 | |
355bf2e5 GH |
406 | assert(s != NULL); |
407 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
408 | } |
409 | ||
9e8dd451 | 410 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
411 | { |
412 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
413 | uint8_t *pci_conf; | |
414 | ||
415 | pci_conf = s->dev.config; | |
416 | pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; | |
417 | pci_conf[0x63] = 0x60; | |
418 | pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | | |
419 | (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); | |
420 | ||
421 | } | |
422 | ||
e8ec0571 | 423 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 424 | { |
e8ec0571 | 425 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
426 | uint8_t *pci_conf; |
427 | ||
93d89f63 | 428 | pci_conf = s->dev.config; |
93d89f63 IY |
429 | pci_conf[0x06] = 0x80; |
430 | pci_conf[0x07] = 0x02; | |
93d89f63 | 431 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
432 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
433 | ||
93d89f63 IY |
434 | /* APM */ |
435 | apm_init(&s->apm, apm_ctrl_changed, s); | |
436 | ||
437 | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); | |
438 | ||
93d89f63 IY |
439 | if (s->kvm_enabled) { |
440 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
441 | * support SMM mode. */ | |
442 | pci_conf[0x5B] = 0x02; | |
443 | } | |
444 | ||
445 | /* XXX: which specification is used ? The i82731AB has different | |
446 | mappings */ | |
e8ec0571 IY |
447 | pci_conf[0x90] = s->smb_io_base | 1; |
448 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 449 | pci_conf[0xd2] = 0x09; |
e8ec0571 IY |
450 | register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
451 | register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); | |
93d89f63 | 452 | |
af11110b GH |
453 | memory_region_init_io(&s->io, &pm_io_ops, s, "piix4-pm", 64); |
454 | memory_region_set_enabled(&s->io, false); | |
455 | memory_region_add_subregion(get_system_io(), 0, &s->io); | |
456 | ||
77d58b1e | 457 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
afafe4bb | 458 | acpi_pm1_cnt_init(&s->ar, &s->io); |
355bf2e5 | 459 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 460 | |
d010f91c IM |
461 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
462 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 463 | |
e8ec0571 | 464 | pm_smbus_init(&s->dev.qdev, &s->smb); |
6141dbfe PB |
465 | s->machine_ready.notify = piix4_pm_machine_ready; |
466 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 467 | qemu_register_reset(piix4_reset, s); |
ac404095 | 468 | piix4_acpi_system_hot_add_init(dev->bus, s); |
e8ec0571 IY |
469 | |
470 | return 0; | |
471 | } | |
472 | ||
473 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
da98c8eb | 474 | qemu_irq sci_irq, qemu_irq smi_irq, |
459ae5ea | 475 | int kvm_enabled, void *fw_cfg) |
e8ec0571 IY |
476 | { |
477 | PCIDevice *dev; | |
478 | PIIX4PMState *s; | |
479 | ||
480 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
481 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 482 | |
e8ec0571 | 483 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 | 484 | s->irq = sci_irq; |
93d89f63 | 485 | s->smi_irq = smi_irq; |
e8ec0571 IY |
486 | s->kvm_enabled = kvm_enabled; |
487 | ||
488 | qdev_init_nofail(&dev->qdev); | |
93d89f63 | 489 | |
459ae5ea GN |
490 | if (fw_cfg) { |
491 | uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; | |
492 | suspend[3] = 1 | ((!s->disable_s3) << 7); | |
493 | suspend[4] = s->s4_val | ((!s->disable_s4) << 7); | |
494 | ||
495 | fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); | |
496 | } | |
497 | ||
93d89f63 IY |
498 | return s->smb.smbus; |
499 | } | |
500 | ||
40021f08 AL |
501 | static Property piix4_pm_properties[] = { |
502 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
459ae5ea GN |
503 | DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), |
504 | DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), | |
505 | DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), | |
40021f08 AL |
506 | DEFINE_PROP_END_OF_LIST(), |
507 | }; | |
508 | ||
509 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
510 | { | |
39bffca2 | 511 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
512 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
513 | ||
514 | k->no_hotplug = 1; | |
515 | k->init = piix4_pm_initfn; | |
516 | k->config_write = pm_write_config; | |
517 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
518 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
519 | k->revision = 0x03; | |
520 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
39bffca2 AL |
521 | dc->desc = "PM"; |
522 | dc->no_user = 1; | |
523 | dc->vmsd = &vmstate_acpi; | |
524 | dc->props = piix4_pm_properties; | |
40021f08 AL |
525 | } |
526 | ||
39bffca2 AL |
527 | static TypeInfo piix4_pm_info = { |
528 | .name = "PIIX4_PM", | |
529 | .parent = TYPE_PCI_DEVICE, | |
530 | .instance_size = sizeof(PIIX4PMState), | |
531 | .class_init = piix4_pm_class_init, | |
e8ec0571 IY |
532 | }; |
533 | ||
83f7d43a | 534 | static void piix4_pm_register_types(void) |
e8ec0571 | 535 | { |
39bffca2 | 536 | type_register_static(&piix4_pm_info); |
e8ec0571 IY |
537 | } |
538 | ||
83f7d43a | 539 | type_init(piix4_pm_register_types) |
e8ec0571 | 540 | |
93d89f63 IY |
541 | static uint32_t gpe_readb(void *opaque, uint32_t addr) |
542 | { | |
633aa0ac | 543 | PIIX4PMState *s = opaque; |
355bf2e5 | 544 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 545 | |
50d8ff8b | 546 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
547 | return val; |
548 | } | |
549 | ||
93d89f63 IY |
550 | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
551 | { | |
633aa0ac | 552 | PIIX4PMState *s = opaque; |
633aa0ac | 553 | |
355bf2e5 | 554 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
633aa0ac | 555 | pm_update_sci(s); |
93d89f63 | 556 | |
50d8ff8b | 557 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
558 | } |
559 | ||
ba737541 | 560 | static uint32_t pci_up_read(void *opaque, uint32_t addr) |
93d89f63 | 561 | { |
ba737541 | 562 | PIIX4PMState *s = opaque; |
7faa8075 AW |
563 | uint32_t val; |
564 | ||
565 | /* Manufacture an "up" value to cause a device check on any hotplug | |
566 | * slot with a device. Extra device checks are harmless. */ | |
567 | val = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
93d89f63 | 568 | |
ba737541 | 569 | PIIX4_DPRINTF("pci_up_read %x\n", val); |
93d89f63 IY |
570 | return val; |
571 | } | |
572 | ||
ba737541 | 573 | static uint32_t pci_down_read(void *opaque, uint32_t addr) |
93d89f63 | 574 | { |
ba737541 AW |
575 | PIIX4PMState *s = opaque; |
576 | uint32_t val = s->pci0_status.down; | |
577 | ||
578 | PIIX4_DPRINTF("pci_down_read %x\n", val); | |
579 | return val; | |
93d89f63 IY |
580 | } |
581 | ||
9290f364 | 582 | static uint32_t pci_features_read(void *opaque, uint32_t addr) |
93d89f63 | 583 | { |
9290f364 AW |
584 | /* No feature defined yet */ |
585 | PIIX4_DPRINTF("pci_features_read %x\n", 0); | |
93d89f63 IY |
586 | return 0; |
587 | } | |
588 | ||
589 | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) | |
590 | { | |
7faa8075 | 591 | acpi_piix_eject_slot(opaque, val); |
93d89f63 | 592 | |
50d8ff8b | 593 | PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); |
93d89f63 IY |
594 | } |
595 | ||
668643b0 MT |
596 | static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
597 | { | |
598 | PIIX4PMState *s = opaque; | |
599 | ||
600 | return s->pci0_hotplug_enable; | |
601 | } | |
602 | ||
4cff0a59 MT |
603 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
604 | PCIHotplugState state); | |
93d89f63 | 605 | |
ac404095 | 606 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
93d89f63 | 607 | { |
93d89f63 | 608 | |
23910d3f IY |
609 | register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); |
610 | register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); | |
355bf2e5 | 611 | acpi_gpe_blk(&s->ar, GPE_BASE); |
ac404095 | 612 | |
ba737541 AW |
613 | register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s); |
614 | register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); | |
93d89f63 | 615 | |
7faa8075 | 616 | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s); |
9290f364 | 617 | register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s); |
93d89f63 | 618 | |
668643b0 MT |
619 | register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); |
620 | ||
ac404095 | 621 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
93d89f63 IY |
622 | } |
623 | ||
ac404095 | 624 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 625 | { |
355bf2e5 | 626 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 627 | s->pci0_slot_device_present |= (1U << slot); |
93d89f63 IY |
628 | } |
629 | ||
ac404095 | 630 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 631 | { |
355bf2e5 | 632 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 633 | s->pci0_status.down |= (1U << slot); |
93d89f63 IY |
634 | } |
635 | ||
4cff0a59 MT |
636 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
637 | PCIHotplugState state) | |
93d89f63 IY |
638 | { |
639 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 | 640 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
40021f08 | 641 | PCI_DEVICE(qdev)); |
93d89f63 | 642 | |
4cff0a59 MT |
643 | /* Don't send event when device is enabled during qemu machine creation: |
644 | * it is present on boot, no hotplug event is necessary. We do send an | |
645 | * event when the device is disabled later. */ | |
646 | if (state == PCI_COLDPLUG_ENABLED) { | |
7faa8075 | 647 | s->pci0_slot_device_present |= (1U << slot); |
5beb8ad5 | 648 | return 0; |
4cff0a59 | 649 | } |
5beb8ad5 | 650 | |
4cff0a59 | 651 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
652 | enable_device(s, slot); |
653 | } else { | |
654 | disable_device(s, slot); | |
655 | } | |
633aa0ac GN |
656 | |
657 | pm_update_sci(s); | |
658 | ||
93d89f63 IY |
659 | return 0; |
660 | } |