]>
Commit | Line | Data |
---|---|---|
93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 IY |
20 | */ |
21 | #include "hw.h" | |
22 | #include "pc.h" | |
23 | #include "apm.h" | |
24 | #include "pm_smbus.h" | |
25 | #include "pci.h" | |
93d89f63 | 26 | #include "acpi.h" |
666daa68 | 27 | #include "sysemu.h" |
bf1b0071 | 28 | #include "range.h" |
6141dbfe | 29 | #include "ioport.h" |
93d89f63 IY |
30 | |
31 | //#define DEBUG | |
32 | ||
50d8ff8b IY |
33 | #ifdef DEBUG |
34 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
35 | #else | |
36 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
37 | #endif | |
38 | ||
93d89f63 IY |
39 | #define ACPI_DBG_IO_ADDR 0xb044 |
40 | ||
ac404095 | 41 | #define GPE_BASE 0xafe0 |
23910d3f | 42 | #define GPE_LEN 4 |
ba737541 AW |
43 | #define PCI_UP_BASE 0xae00 |
44 | #define PCI_DOWN_BASE 0xae04 | |
ac404095 | 45 | #define PCI_EJ_BASE 0xae08 |
668643b0 | 46 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 47 | |
4441a287 GN |
48 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
49 | ||
ac404095 IY |
50 | struct pci_status { |
51 | uint32_t up; | |
52 | uint32_t down; | |
53 | }; | |
54 | ||
93d89f63 IY |
55 | typedef struct PIIX4PMState { |
56 | PCIDevice dev; | |
2871a3f6 | 57 | IORange ioport; |
355bf2e5 | 58 | ACPIREGS ar; |
93d89f63 IY |
59 | |
60 | APMState apm; | |
61 | ||
93d89f63 | 62 | PMSMBus smb; |
e8ec0571 | 63 | uint32_t smb_io_base; |
93d89f63 IY |
64 | |
65 | qemu_irq irq; | |
93d89f63 IY |
66 | qemu_irq smi_irq; |
67 | int kvm_enabled; | |
6141dbfe | 68 | Notifier machine_ready; |
ac404095 IY |
69 | |
70 | /* for pci hotplug */ | |
ac404095 | 71 | struct pci_status pci0_status; |
668643b0 | 72 | uint32_t pci0_hotplug_enable; |
93d89f63 IY |
73 | } PIIX4PMState; |
74 | ||
ac404095 IY |
75 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
76 | ||
93d89f63 IY |
77 | #define ACPI_ENABLE 0xf1 |
78 | #define ACPI_DISABLE 0xf0 | |
79 | ||
93d89f63 IY |
80 | static void pm_update_sci(PIIX4PMState *s) |
81 | { | |
82 | int sci_level, pmsts; | |
93d89f63 | 83 | |
2886be1b | 84 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 85 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
93d89f63 IY |
86 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
87 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
88 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 89 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
355bf2e5 GH |
90 | (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) |
91 | & PIIX4_PCI_HOTPLUG_STATUS) != 0); | |
633aa0ac | 92 | |
93d89f63 IY |
93 | qemu_set_irq(s->irq, sci_level); |
94 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 95 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 96 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
97 | } |
98 | ||
355bf2e5 | 99 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 100 | { |
355bf2e5 | 101 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
93d89f63 IY |
102 | pm_update_sci(s); |
103 | } | |
104 | ||
2871a3f6 AK |
105 | static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, |
106 | uint64_t val) | |
93d89f63 | 107 | { |
2871a3f6 AK |
108 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
109 | ||
110 | if (width != 2) { | |
111 | PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", | |
112 | (unsigned)addr, width, (unsigned)val); | |
113 | } | |
114 | ||
93d89f63 IY |
115 | switch(addr) { |
116 | case 0x00: | |
355bf2e5 | 117 | acpi_pm1_evt_write_sts(&s->ar, val); |
04dc308f | 118 | pm_update_sci(s); |
93d89f63 IY |
119 | break; |
120 | case 0x02: | |
8283c4f5 | 121 | acpi_pm1_evt_write_en(&s->ar, val); |
93d89f63 IY |
122 | pm_update_sci(s); |
123 | break; | |
124 | case 0x04: | |
355bf2e5 | 125 | acpi_pm1_cnt_write(&s->ar, val); |
93d89f63 IY |
126 | break; |
127 | default: | |
128 | break; | |
129 | } | |
59df4c11 WC |
130 | PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr, |
131 | (unsigned int)val); | |
93d89f63 IY |
132 | } |
133 | ||
2871a3f6 AK |
134 | static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, |
135 | uint64_t *data) | |
93d89f63 | 136 | { |
2871a3f6 | 137 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
93d89f63 IY |
138 | uint32_t val; |
139 | ||
93d89f63 IY |
140 | switch(addr) { |
141 | case 0x00: | |
2886be1b | 142 | val = acpi_pm1_evt_get_sts(&s->ar); |
93d89f63 IY |
143 | break; |
144 | case 0x02: | |
355bf2e5 | 145 | val = s->ar.pm1.evt.en; |
93d89f63 IY |
146 | break; |
147 | case 0x04: | |
355bf2e5 | 148 | val = s->ar.pm1.cnt.cnt; |
93d89f63 | 149 | break; |
93d89f63 | 150 | case 0x08: |
355bf2e5 | 151 | val = acpi_pm_tmr_get(&s->ar); |
93d89f63 IY |
152 | break; |
153 | default: | |
154 | val = 0; | |
155 | break; | |
156 | } | |
59df4c11 | 157 | PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val); |
2871a3f6 | 158 | *data = val; |
93d89f63 IY |
159 | } |
160 | ||
2871a3f6 AK |
161 | static const IORangeOps pm_iorange_ops = { |
162 | .read = pm_ioport_read, | |
163 | .write = pm_ioport_write, | |
164 | }; | |
165 | ||
93d89f63 IY |
166 | static void apm_ctrl_changed(uint32_t val, void *arg) |
167 | { | |
168 | PIIX4PMState *s = arg; | |
169 | ||
170 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 171 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 IY |
172 | |
173 | if (s->dev.config[0x5b] & (1 << 1)) { | |
174 | if (s->smi_irq) { | |
175 | qemu_irq_raise(s->smi_irq); | |
176 | } | |
177 | } | |
178 | } | |
179 | ||
180 | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) | |
181 | { | |
50d8ff8b | 182 | PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); |
93d89f63 IY |
183 | } |
184 | ||
185 | static void pm_io_space_update(PIIX4PMState *s) | |
186 | { | |
187 | uint32_t pm_io_base; | |
188 | ||
189 | if (s->dev.config[0x80] & 1) { | |
190 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); | |
191 | pm_io_base &= 0xffc0; | |
192 | ||
193 | /* XXX: need to improve memory and ioport allocation */ | |
50d8ff8b | 194 | PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); |
2871a3f6 AK |
195 | iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); |
196 | ioport_register(&s->ioport); | |
93d89f63 IY |
197 | } |
198 | } | |
199 | ||
200 | static void pm_write_config(PCIDevice *d, | |
201 | uint32_t address, uint32_t val, int len) | |
202 | { | |
203 | pci_default_write_config(d, address, val, len); | |
204 | if (range_covers_byte(address, len, 0x80)) | |
205 | pm_io_space_update((PIIX4PMState *)d); | |
206 | } | |
207 | ||
208 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
209 | { | |
210 | PIIX4PMState *s = opaque; | |
211 | ||
212 | pm_io_space_update(s); | |
213 | return 0; | |
214 | } | |
215 | ||
23910d3f IY |
216 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
217 | { \ | |
218 | .name = (stringify(_field)), \ | |
219 | .version_id = 0, \ | |
220 | .num = GPE_LEN, \ | |
221 | .info = &vmstate_info_uint16, \ | |
222 | .size = sizeof(uint16_t), \ | |
223 | .flags = VMS_ARRAY | VMS_POINTER, \ | |
224 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ | |
225 | } | |
226 | ||
4cf3e6f3 AW |
227 | static const VMStateDescription vmstate_gpe = { |
228 | .name = "gpe", | |
229 | .version_id = 1, | |
230 | .minimum_version_id = 1, | |
231 | .minimum_version_id_old = 1, | |
232 | .fields = (VMStateField []) { | |
23910d3f IY |
233 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
234 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
235 | VMSTATE_END_OF_LIST() |
236 | } | |
237 | }; | |
238 | ||
239 | static const VMStateDescription vmstate_pci_status = { | |
240 | .name = "pci_status", | |
241 | .version_id = 1, | |
242 | .minimum_version_id = 1, | |
243 | .minimum_version_id_old = 1, | |
244 | .fields = (VMStateField []) { | |
245 | VMSTATE_UINT32(up, struct pci_status), | |
246 | VMSTATE_UINT32(down, struct pci_status), | |
247 | VMSTATE_END_OF_LIST() | |
248 | } | |
249 | }; | |
250 | ||
93d89f63 IY |
251 | static const VMStateDescription vmstate_acpi = { |
252 | .name = "piix4_pm", | |
4cf3e6f3 | 253 | .version_id = 2, |
93d89f63 IY |
254 | .minimum_version_id = 1, |
255 | .minimum_version_id_old = 1, | |
256 | .post_load = vmstate_acpi_post_load, | |
257 | .fields = (VMStateField []) { | |
258 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
355bf2e5 GH |
259 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
260 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
261 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 262 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
263 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
264 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
265 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
4cf3e6f3 AW |
266 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
267 | struct pci_status), | |
93d89f63 IY |
268 | VMSTATE_END_OF_LIST() |
269 | } | |
270 | }; | |
271 | ||
668643b0 MT |
272 | static void piix4_update_hotplug(PIIX4PMState *s) |
273 | { | |
274 | PCIDevice *dev = &s->dev; | |
275 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
276 | DeviceState *qdev, *next; | |
277 | ||
278 | s->pci0_hotplug_enable = ~0; | |
279 | ||
d8bb00d6 | 280 | QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) { |
40021f08 AL |
281 | PCIDevice *pdev = PCI_DEVICE(qdev); |
282 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); | |
668643b0 MT |
283 | int slot = PCI_SLOT(pdev->devfn); |
284 | ||
40021f08 | 285 | if (pc->no_hotplug) { |
668643b0 MT |
286 | s->pci0_hotplug_enable &= ~(1 << slot); |
287 | } | |
288 | } | |
289 | } | |
290 | ||
93d89f63 IY |
291 | static void piix4_reset(void *opaque) |
292 | { | |
293 | PIIX4PMState *s = opaque; | |
294 | uint8_t *pci_conf = s->dev.config; | |
295 | ||
296 | pci_conf[0x58] = 0; | |
297 | pci_conf[0x59] = 0; | |
298 | pci_conf[0x5a] = 0; | |
299 | pci_conf[0x5b] = 0; | |
300 | ||
301 | if (s->kvm_enabled) { | |
302 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
303 | pci_conf[0x5B] = 0x02; | |
304 | } | |
668643b0 | 305 | piix4_update_hotplug(s); |
93d89f63 IY |
306 | } |
307 | ||
308 | static void piix4_powerdown(void *opaque, int irq, int power_failing) | |
309 | { | |
310 | PIIX4PMState *s = opaque; | |
311 | ||
355bf2e5 GH |
312 | assert(s != NULL); |
313 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
314 | } |
315 | ||
9e8dd451 | 316 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
317 | { |
318 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
319 | uint8_t *pci_conf; | |
320 | ||
321 | pci_conf = s->dev.config; | |
322 | pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; | |
323 | pci_conf[0x63] = 0x60; | |
324 | pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | | |
325 | (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); | |
326 | ||
327 | } | |
328 | ||
e8ec0571 | 329 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 330 | { |
e8ec0571 | 331 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
332 | uint8_t *pci_conf; |
333 | ||
93d89f63 | 334 | pci_conf = s->dev.config; |
93d89f63 IY |
335 | pci_conf[0x06] = 0x80; |
336 | pci_conf[0x07] = 0x02; | |
93d89f63 | 337 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
338 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
339 | ||
340 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ | |
341 | ||
342 | /* APM */ | |
343 | apm_init(&s->apm, apm_ctrl_changed, s); | |
344 | ||
345 | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); | |
346 | ||
93d89f63 IY |
347 | if (s->kvm_enabled) { |
348 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
349 | * support SMM mode. */ | |
350 | pci_conf[0x5B] = 0x02; | |
351 | } | |
352 | ||
353 | /* XXX: which specification is used ? The i82731AB has different | |
354 | mappings */ | |
e8ec0571 IY |
355 | pci_conf[0x90] = s->smb_io_base | 1; |
356 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 357 | pci_conf[0xd2] = 0x09; |
e8ec0571 IY |
358 | register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
359 | register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); | |
93d89f63 | 360 | |
355bf2e5 GH |
361 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer); |
362 | acpi_gpe_init(&s->ar, GPE_LEN); | |
93d89f63 IY |
363 | |
364 | qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1); | |
365 | ||
e8ec0571 | 366 | pm_smbus_init(&s->dev.qdev, &s->smb); |
6141dbfe PB |
367 | s->machine_ready.notify = piix4_pm_machine_ready; |
368 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 369 | qemu_register_reset(piix4_reset, s); |
ac404095 | 370 | piix4_acpi_system_hot_add_init(dev->bus, s); |
e8ec0571 IY |
371 | |
372 | return 0; | |
373 | } | |
374 | ||
375 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
da98c8eb | 376 | qemu_irq sci_irq, qemu_irq smi_irq, |
e8ec0571 IY |
377 | int kvm_enabled) |
378 | { | |
379 | PCIDevice *dev; | |
380 | PIIX4PMState *s; | |
381 | ||
382 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
383 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 384 | |
e8ec0571 | 385 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 | 386 | s->irq = sci_irq; |
da98c8eb | 387 | acpi_pm1_cnt_init(&s->ar); |
93d89f63 | 388 | s->smi_irq = smi_irq; |
e8ec0571 IY |
389 | s->kvm_enabled = kvm_enabled; |
390 | ||
391 | qdev_init_nofail(&dev->qdev); | |
93d89f63 IY |
392 | |
393 | return s->smb.smbus; | |
394 | } | |
395 | ||
40021f08 AL |
396 | static Property piix4_pm_properties[] = { |
397 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
398 | DEFINE_PROP_END_OF_LIST(), | |
399 | }; | |
400 | ||
401 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
402 | { | |
39bffca2 | 403 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
404 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
405 | ||
406 | k->no_hotplug = 1; | |
407 | k->init = piix4_pm_initfn; | |
408 | k->config_write = pm_write_config; | |
409 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
410 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
411 | k->revision = 0x03; | |
412 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
39bffca2 AL |
413 | dc->desc = "PM"; |
414 | dc->no_user = 1; | |
415 | dc->vmsd = &vmstate_acpi; | |
416 | dc->props = piix4_pm_properties; | |
40021f08 AL |
417 | } |
418 | ||
39bffca2 AL |
419 | static TypeInfo piix4_pm_info = { |
420 | .name = "PIIX4_PM", | |
421 | .parent = TYPE_PCI_DEVICE, | |
422 | .instance_size = sizeof(PIIX4PMState), | |
423 | .class_init = piix4_pm_class_init, | |
e8ec0571 IY |
424 | }; |
425 | ||
83f7d43a | 426 | static void piix4_pm_register_types(void) |
e8ec0571 | 427 | { |
39bffca2 | 428 | type_register_static(&piix4_pm_info); |
e8ec0571 IY |
429 | } |
430 | ||
83f7d43a | 431 | type_init(piix4_pm_register_types) |
e8ec0571 | 432 | |
93d89f63 IY |
433 | static uint32_t gpe_readb(void *opaque, uint32_t addr) |
434 | { | |
633aa0ac | 435 | PIIX4PMState *s = opaque; |
355bf2e5 | 436 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 437 | |
50d8ff8b | 438 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
439 | return val; |
440 | } | |
441 | ||
93d89f63 IY |
442 | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
443 | { | |
633aa0ac | 444 | PIIX4PMState *s = opaque; |
633aa0ac | 445 | |
355bf2e5 | 446 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
633aa0ac | 447 | pm_update_sci(s); |
93d89f63 | 448 | |
50d8ff8b | 449 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
450 | } |
451 | ||
ba737541 | 452 | static uint32_t pci_up_read(void *opaque, uint32_t addr) |
93d89f63 | 453 | { |
ba737541 AW |
454 | PIIX4PMState *s = opaque; |
455 | uint32_t val = s->pci0_status.up; | |
93d89f63 | 456 | |
ba737541 | 457 | PIIX4_DPRINTF("pci_up_read %x\n", val); |
93d89f63 IY |
458 | return val; |
459 | } | |
460 | ||
ba737541 | 461 | static uint32_t pci_down_read(void *opaque, uint32_t addr) |
93d89f63 | 462 | { |
ba737541 AW |
463 | PIIX4PMState *s = opaque; |
464 | uint32_t val = s->pci0_status.down; | |
465 | ||
466 | PIIX4_DPRINTF("pci_down_read %x\n", val); | |
467 | return val; | |
93d89f63 IY |
468 | } |
469 | ||
470 | static uint32_t pciej_read(void *opaque, uint32_t addr) | |
471 | { | |
50d8ff8b | 472 | PIIX4_DPRINTF("pciej read %x\n", addr); |
93d89f63 IY |
473 | return 0; |
474 | } | |
475 | ||
476 | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) | |
477 | { | |
478 | BusState *bus = opaque; | |
479 | DeviceState *qdev, *next; | |
93d89f63 IY |
480 | int slot = ffs(val) - 1; |
481 | ||
d8bb00d6 | 482 | QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) { |
40021f08 AL |
483 | PCIDevice *dev = PCI_DEVICE(qdev); |
484 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
485 | if (PCI_SLOT(dev->devfn) == slot && !pc->no_hotplug) { | |
93d89f63 IY |
486 | qdev_free(qdev); |
487 | } | |
488 | } | |
489 | ||
490 | ||
50d8ff8b | 491 | PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); |
93d89f63 IY |
492 | } |
493 | ||
668643b0 MT |
494 | static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
495 | { | |
496 | PIIX4PMState *s = opaque; | |
497 | ||
498 | return s->pci0_hotplug_enable; | |
499 | } | |
500 | ||
501 | static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val) | |
502 | { | |
503 | return; | |
504 | } | |
505 | ||
4cff0a59 MT |
506 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
507 | PCIHotplugState state); | |
93d89f63 | 508 | |
ac404095 | 509 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
93d89f63 | 510 | { |
93d89f63 | 511 | |
23910d3f IY |
512 | register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); |
513 | register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); | |
355bf2e5 | 514 | acpi_gpe_blk(&s->ar, GPE_BASE); |
ac404095 | 515 | |
ba737541 AW |
516 | register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s); |
517 | register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); | |
93d89f63 IY |
518 | |
519 | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); | |
520 | register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus); | |
521 | ||
668643b0 MT |
522 | register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s); |
523 | register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); | |
524 | ||
ac404095 | 525 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
93d89f63 IY |
526 | } |
527 | ||
ac404095 | 528 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 529 | { |
355bf2e5 | 530 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
ac404095 | 531 | s->pci0_status.up |= (1 << slot); |
93d89f63 IY |
532 | } |
533 | ||
ac404095 | 534 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 535 | { |
355bf2e5 | 536 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
ac404095 | 537 | s->pci0_status.down |= (1 << slot); |
93d89f63 IY |
538 | } |
539 | ||
4cff0a59 MT |
540 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
541 | PCIHotplugState state) | |
93d89f63 IY |
542 | { |
543 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 | 544 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
40021f08 | 545 | PCI_DEVICE(qdev)); |
93d89f63 | 546 | |
4cff0a59 MT |
547 | /* Don't send event when device is enabled during qemu machine creation: |
548 | * it is present on boot, no hotplug event is necessary. We do send an | |
549 | * event when the device is disabled later. */ | |
550 | if (state == PCI_COLDPLUG_ENABLED) { | |
5beb8ad5 | 551 | return 0; |
4cff0a59 | 552 | } |
5beb8ad5 | 553 | |
ac404095 IY |
554 | s->pci0_status.up = 0; |
555 | s->pci0_status.down = 0; | |
4cff0a59 | 556 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
557 | enable_device(s, slot); |
558 | } else { | |
559 | disable_device(s, slot); | |
560 | } | |
633aa0ac GN |
561 | |
562 | pm_update_sci(s); | |
563 | ||
93d89f63 IY |
564 | return 0; |
565 | } |