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Commit | Line | Data |
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80bb2ff7 RH |
1 | /* |
2 | * QEMU Alpha PCI support functions. | |
3 | * | |
4 | * Some of this isn't very Alpha specific at all. | |
5 | * | |
6 | * ??? Sparse memory access not implemented. | |
7 | */ | |
8 | ||
9 | #include "config.h" | |
10 | #include "alpha_sys.h" | |
11 | #include "qemu-log.h" | |
12 | #include "sysemu.h" | |
13 | #include "vmware_vga.h" | |
c1195d16 | 14 | #include "vga-pci.h" |
80bb2ff7 RH |
15 | |
16 | ||
17 | /* PCI IO reads/writes, to byte-word addressable memory. */ | |
18 | /* ??? Doesn't handle multiple PCI busses. */ | |
19 | ||
20 | static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size) | |
21 | { | |
22 | switch (size) { | |
23 | case 1: | |
24 | return cpu_inb(addr); | |
25 | case 2: | |
26 | return cpu_inw(addr); | |
27 | case 4: | |
28 | return cpu_inl(addr); | |
29 | } | |
30 | abort(); | |
31 | } | |
32 | ||
33 | static void bw_io_write(void *opaque, target_phys_addr_t addr, | |
34 | uint64_t val, unsigned size) | |
35 | { | |
36 | switch (size) { | |
37 | case 1: | |
38 | cpu_outb(addr, val); | |
39 | break; | |
40 | case 2: | |
41 | cpu_outw(addr, val); | |
42 | break; | |
43 | case 4: | |
44 | cpu_outl(addr, val); | |
45 | break; | |
46 | default: | |
47 | abort(); | |
48 | } | |
49 | } | |
50 | ||
51 | const MemoryRegionOps alpha_pci_bw_io_ops = { | |
52 | .read = bw_io_read, | |
53 | .write = bw_io_write, | |
54 | .endianness = DEVICE_LITTLE_ENDIAN, | |
55 | .impl = { | |
56 | .min_access_size = 1, | |
57 | .max_access_size = 4, | |
58 | }, | |
59 | }; | |
60 | ||
61 | /* PCI config space reads/writes, to byte-word addressable memory. */ | |
62 | static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr, | |
63 | unsigned size) | |
64 | { | |
65 | PCIBus *b = opaque; | |
66 | return pci_data_read(b, addr, size); | |
67 | } | |
68 | ||
69 | static void bw_conf1_write(void *opaque, target_phys_addr_t addr, | |
70 | uint64_t val, unsigned size) | |
71 | { | |
72 | PCIBus *b = opaque; | |
73 | pci_data_write(b, addr, val, size); | |
74 | } | |
75 | ||
76 | const MemoryRegionOps alpha_pci_conf1_ops = { | |
77 | .read = bw_conf1_read, | |
78 | .write = bw_conf1_write, | |
79 | .endianness = DEVICE_LITTLE_ENDIAN, | |
80 | .impl = { | |
81 | .min_access_size = 1, | |
82 | .max_access_size = 4, | |
83 | }, | |
84 | }; | |
85 | ||
86 | /* PCI/EISA Interrupt Acknowledge Cycle. */ | |
87 | ||
88 | static uint64_t iack_read(void *opaque, target_phys_addr_t addr, unsigned size) | |
89 | { | |
90 | return pic_read_irq(isa_pic); | |
91 | } | |
92 | ||
93 | static void special_write(void *opaque, target_phys_addr_t addr, | |
94 | uint64_t val, unsigned size) | |
95 | { | |
96 | qemu_log("pci: special write cycle"); | |
97 | } | |
98 | ||
99 | const MemoryRegionOps alpha_pci_iack_ops = { | |
100 | .read = iack_read, | |
101 | .write = special_write, | |
102 | .endianness = DEVICE_LITTLE_ENDIAN, | |
103 | .valid = { | |
104 | .min_access_size = 4, | |
105 | .max_access_size = 4, | |
106 | }, | |
107 | .impl = { | |
108 | .min_access_size = 4, | |
109 | .max_access_size = 4, | |
110 | }, | |
111 | }; | |
112 | \f | |
113 | void alpha_pci_vga_setup(PCIBus *pci_bus) | |
114 | { | |
115 | switch (vga_interface_type) { | |
116 | #ifdef CONFIG_SPICE | |
117 | case VGA_QXL: | |
118 | pci_create_simple(pci_bus, -1, "qxl-vga"); | |
119 | return; | |
120 | #endif | |
121 | case VGA_CIRRUS: | |
122 | pci_cirrus_vga_init(pci_bus); | |
123 | return; | |
124 | case VGA_VMWARE: | |
a369da5f BS |
125 | pci_vmsvga_init(pci_bus); |
126 | return; | |
80bb2ff7 RH |
127 | } |
128 | /* If VGA is enabled at all, and one of the above didn't work, then | |
129 | fallback to Standard VGA. */ | |
130 | if (vga_interface_type != VGA_NONE) { | |
131 | pci_vga_init(pci_bus); | |
132 | } | |
133 | } |