[qemu.git] / hw / apb_pci.c

/*
 * QEMU Ultrasparc APB PCI host
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* XXX This file and most of its contents are somewhat misnamed.  The
   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
   the secondary PCI bridge.  */

#include "sysbus.h"
#include "pci.h"
#include "pci_host.h"
#include "pci_bridge.h"
#include "pci_internals.h"
#include "rwhandler.h"
#include "apb_pci.h"
#include "sysemu.h"

/* debug APB */
//#define DEBUG_APB

#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, ...) \
do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#else
#define APB_DPRINTF(fmt, ...)
#endif

/*
 * Chipset docs:
 * PBM: "UltraSPARC IIi User's Manual",
 * http://www.sun.com/processors/manuals/805-0087.pdf
 *
 * APB: "Advanced PCI Bridge (APB) User's Manual",
 * http://www.sun.com/processors/manuals/805-1251.pdf
 */

#define PBM_PCI_IMR_MASK    0x7fffffff
#define PBM_PCI_IMR_ENABLED 0x80000000

#define POR          (1 << 31)
#define SOFT_POR     (1 << 30)
#define SOFT_XIR     (1 << 29)
#define BTN_POR      (1 << 28)
#define BTN_XIR      (1 << 27)
#define RESET_MASK   0xf8000000
#define RESET_WCMASK 0x98000000
#define RESET_WMASK  0x60000000

typedef struct APBState {
    SysBusDevice busdev;
    PCIBus      *bus;
    ReadWriteHandler pci_config_handler;
    uint32_t iommu[4];
    uint32_t pci_control[16];
    uint32_t pci_irq_map[8];
    uint32_t obio_irq_map[32];
    qemu_irq pci_irqs[32];
    uint32_t reset_control;
    unsigned int nr_resets;
} APBState;

static void apb_config_writel (void *opaque, target_phys_addr_t addr,
                               uint32_t val)
{
    APBState *s = opaque;

    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        s->iommu[(addr & 0xf) >> 2] = val;
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
            s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        s->pci_control[(addr & 0x3f) >> 2] = val;
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val &= RESET_MASK;
            s->reset_control &= ~(val & RESET_WCMASK);
            s->reset_control |= val & RESET_WMASK;
            if (val & SOFT_POR) {
                s->nr_resets = 0;
                qemu_system_reset_request();
            } else if (val & SOFT_XIR) {
                qemu_system_reset_request();
            }
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        break;
    }
}

static uint32_t apb_config_readl (void *opaque,
                                  target_phys_addr_t addr)
{
    APBState *s = opaque;
    uint32_t val;

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        val = 0;
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        val = s->iommu[(addr & 0xf) >> 2];
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        val = 0;
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            val = s->pci_irq_map[(addr & 0x3f) >> 3];
        } else {
            val = 0;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        val = s->pci_control[(addr & 0x3f) >> 2];
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val = s->reset_control;
        } else {
            val = 0;
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        val = 0;
        break;
    }
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);

    return val;
}

static CPUWriteMemoryFunc * const apb_config_write[] = {
    &apb_config_writel,
    &apb_config_writel,
    &apb_config_writel,
};

static CPUReadMemoryFunc * const apb_config_read[] = {
    &apb_config_readl,
    &apb_config_readl,
    &apb_config_readl,
};

static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
                                 uint32_t val, int size)
{
    APBState *s = container_of(h, APBState, pci_config_handler);

    val = qemu_bswap_len(val, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
    pci_data_write(s->bus, addr, val, size);
}

static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
                                    int size)
{
    uint32_t ret;
    APBState *s = container_of(h, APBState, pci_config_handler);

    ret = pci_data_read(s->bus, addr, size);
    ret = qemu_bswap_len(ret, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
    return ret;
}

static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outb(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}

static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}

static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inb(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap16(cpu_inw(addr & IOPORTS_MASK));
    return val;
}

static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap32(cpu_inl(addr & IOPORTS_MASK));
    return val;
}

static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
    &pci_apb_iowriteb,
    &pci_apb_iowritew,
    &pci_apb_iowritel,
};

static CPUReadMemoryFunc * const pci_apb_ioread[] = {
    &pci_apb_ioreadb,
    &pci_apb_ioreadw,
    &pci_apb_ioreadl,
};

/* The APB host has an IRQ line for each IRQ line of each slot.  */
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}

static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int bus_offset;
    if (pci_dev->devfn & 1)
        bus_offset = 16;
    else
        bus_offset = 0;
    return bus_offset + irq_num;
}

static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
    APBState *s = opaque;

    /* PCI IRQ map onto the first 32 INO.  */
    if (irq_num < 32) {
        if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
            APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
            qemu_set_irq(s->pci_irqs[irq_num], level);
        } else {
            APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
            qemu_irq_lower(s->pci_irqs[irq_num]);
        }
    }
}

static int apb_pci_bridge_initfn(PCIDevice *dev)
{
    int rc;

    rc = pci_bridge_initfn(dev);
    if (rc < 0) {
        return rc;
    }

    /*
     * command register:
     * According to PCI bridge spec, after reset
     *   bus master bit is off
     *   memory space enable bit is off
     * According to manual (805-1251.pdf).
     *   the reset value should be zero unless the boot pin is tied high
     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
     */
    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY);
    pci_set_word(dev->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    return 0;
}

PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
    DeviceState *dev;
    SysBusDevice *s;
    APBState *d;
    unsigned int i;
    PCIDevice *pci_dev;
    PCIBridge *br;

    /* Ultrasparc PBM main bus */
    dev = qdev_create(NULL, "pbm");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    /* apb_config */
    sysbus_mmio_map(s, 0, special_base);
    /* PCI configuration space */
    sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
    /* pci_ioport */
    sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
    d = FROM_SYSBUS(APBState, s);

    d->bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_apb_set_irq, pci_pbm_map_irq, d,
                                         0, 32);
    pci_bus_set_mem_base(d->bus, mem_base);

    for (i = 0; i < 32; i++) {
        sysbus_connect_irq(s, i, pic[i]);
    }

    pci_create_simple(d->bus, 0, "pbm");

    /* APB secondary busses */
    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
                                   "pbm-bridge");
    br = DO_UPCAST(PCIBridge, dev, pci_dev);
    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
                       pci_apb_map_irq);
    qdev_init_nofail(&pci_dev->qdev);
    *bus2 = pci_bridge_get_sec_bus(br);

    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
                                   "pbm-bridge");
    br = DO_UPCAST(PCIBridge, dev, pci_dev);
    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
                       pci_apb_map_irq);
    qdev_init_nofail(&pci_dev->qdev);
    *bus3 = pci_bridge_get_sec_bus(br);

    return d->bus;
}

static void pci_pbm_reset(DeviceState *d)
{
    unsigned int i;
    APBState *s = container_of(d, APBState, busdev.qdev);

    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
    }

    if (s->nr_resets++ == 0) {
        /* Power on reset */
        s->reset_control = POR;
    }
}

static int pci_pbm_init_device(SysBusDevice *dev)
{
    APBState *s;
    int pci_config, apb_config, pci_ioport;
    unsigned int i;

    s = FROM_SYSBUS(APBState, dev);
    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
    }
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(dev, &s->pci_irqs[i]);
    }

    /* apb_config */
    apb_config = cpu_register_io_memory(apb_config_read,
                                        apb_config_write, s,
                                        DEVICE_NATIVE_ENDIAN);
    /* at region 0 */
    sysbus_init_mmio(dev, 0x10000ULL, apb_config);

    /* PCI configuration space */
    s->pci_config_handler.read = apb_pci_config_read;
    s->pci_config_handler.write = apb_pci_config_write;
    pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
                                               DEVICE_NATIVE_ENDIAN);
    assert(pci_config >= 0);
    /* at region 1 */
    sysbus_init_mmio(dev, 0x1000000ULL, pci_config);

    /* pci_ioport */
    pci_ioport = cpu_register_io_memory(pci_apb_ioread,
                                        pci_apb_iowrite, s,
                                        DEVICE_NATIVE_ENDIAN);
    /* at region 2 */
    sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);

    return 0;
}

static int pbm_pci_host_init(PCIDevice *d)
{
    pci_set_word(d->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    pci_set_word(d->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    return 0;
}

static PCIDeviceInfo pbm_pci_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(PCIDevice),
    .init      = pbm_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_SUN,
    .device_id = PCI_DEVICE_ID_SUN_SABRE,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
    .is_bridge = 1,
};

static SysBusDeviceInfo pbm_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(APBState),
    .qdev.reset = pci_pbm_reset,
    .init = pci_pbm_init_device,
};

static PCIDeviceInfo pbm_pci_bridge_info = {
    .qdev.name = "pbm-bridge",
    .qdev.size = sizeof(PCIBridge),
    .qdev.vmsd = &vmstate_pci_device,
    .qdev.reset = pci_bridge_reset,
    .init = apb_pci_bridge_initfn,
    .exit = pci_bridge_exitfn,
    .vendor_id = PCI_VENDOR_ID_SUN,
    .device_id = PCI_DEVICE_ID_SUN_SIMBA,
    .revision = 0x11,
    .config_write = pci_bridge_write_config,
    .is_bridge = 1,
};

static void pbm_register_devices(void)
{
    sysbus_register_withprop(&pbm_host_info);
    pci_qdev_register(&pbm_pci_host_info);
    pci_qdev_register(&pbm_pci_bridge_info);
}

device_init(pbm_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Ultrasparc APB PCI host
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80b3ada7	24
a94fd955	25	/* XXX This file and most of its contents are somewhat misnamed. The
80b3ada7 PB	26	Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
	27	the secondary PCI bridge. */
	28
72f44c8c	29	#include "sysbus.h"
87ecb68b	30	#include "pci.h"
4f5e19e6	31	#include "pci_host.h"
783753fd	32	#include "pci_bridge.h"
68f79994	33	#include "pci_internals.h"
63e6f31d	34	#include "rwhandler.h"
18e08a55	35	#include "apb_pci.h"
666daa68	36	#include "sysemu.h"
a94fd955 BS	37
	38	/* debug APB */
	39	//#define DEBUG_APB
	40
	41	#ifdef DEBUG_APB
001faf32 BS	42	#define APB_DPRINTF(fmt, ...) \
001faf32 BS	43	do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
a94fd955	44	#else
001faf32	45	#define APB_DPRINTF(fmt, ...)
a94fd955 BS	46	#endif
a94fd955 BS	47
930f3fe1 BS	48	/*
	49	* Chipset docs:
	50	* PBM: "UltraSPARC IIi User's Manual",
	51	* http://www.sun.com/processors/manuals/805-0087.pdf
	52	*
	53	* APB: "Advanced PCI Bridge (APB) User's Manual",
	54	* http://www.sun.com/processors/manuals/805-1251.pdf
	55	*/
	56
95819af0 BS	57	#define PBM_PCI_IMR_MASK 0x7fffffff
	58	#define PBM_PCI_IMR_ENABLED 0x80000000
	59
	60	#define POR (1 << 31)
	61	#define SOFT_POR (1 << 30)
	62	#define SOFT_XIR (1 << 29)
	63	#define BTN_POR (1 << 28)
	64	#define BTN_XIR (1 << 27)
	65	#define RESET_MASK 0xf8000000
	66	#define RESET_WCMASK 0x98000000
	67	#define RESET_WMASK 0x60000000
	68
72f44c8c BS	69	typedef struct APBState {
72f44c8c BS	70	SysBusDevice busdev;
d63baf92	71	PCIBus *bus;
63e6f31d	72	ReadWriteHandler pci_config_handler;
95819af0 BS	73	uint32_t iommu[4];
	74	uint32_t pci_control[16];
	75	uint32_t pci_irq_map[8];
	76	uint32_t obio_irq_map[32];
	77	qemu_irq pci_irqs[32];
	78	uint32_t reset_control;
9c0afd0e	79	unsigned int nr_resets;
72f44c8c	80	} APBState;
502a5395	81
c227f099	82	static void apb_config_writel (void *opaque, target_phys_addr_t addr,
f930d07e	83	uint32_t val)
502a5395	84	{
95819af0 BS	85	APBState *s = opaque;
	86
	87	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
	88
	89	switch (addr & 0xffff) {
	90	case 0x30 ... 0x4f: /* DMA error registers */
	91	/* XXX: not implemented yet */
	92	break;
	93	case 0x200 ... 0x20b: /* IOMMU */
	94	s->iommu[(addr & 0xf) >> 2] = val;
	95	break;
	96	case 0x20c ... 0x3ff: /* IOMMU flush */
	97	break;
	98	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	99	if (addr & 4) {
	100	s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
	101	s->pci_irq_map[(addr & 0x3f) >> 3] \|= val & ~PBM_PCI_IMR_MASK;
	102	}
	103	break;
	104	case 0x2000 ... 0x202f: /* PCI control */
	105	s->pci_control[(addr & 0x3f) >> 2] = val;
	106	break;
	107	case 0xf020 ... 0xf027: /* Reset control */
	108	if (addr & 4) {
	109	val &= RESET_MASK;
	110	s->reset_control &= ~(val & RESET_WCMASK);
	111	s->reset_control \|= val & RESET_WMASK;
	112	if (val & SOFT_POR) {
9c0afd0e	113	s->nr_resets = 0;
95819af0 BS	114	qemu_system_reset_request();
	115	} else if (val & SOFT_XIR) {
	116	qemu_system_reset_request();
	117	}
	118	}
	119	break;
	120	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	121	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	122	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	123	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	124	/* we don't care */
502a5395	125	default:
f930d07e	126	break;
502a5395 PB	127	}
	128	}
	129
	130	static uint32_t apb_config_readl (void *opaque,
c227f099	131	target_phys_addr_t addr)
502a5395	132	{
95819af0	133	APBState *s = opaque;
502a5395 PB	134	uint32_t val;
502a5395 PB	135
95819af0 BS	136	switch (addr & 0xffff) {
	137	case 0x30 ... 0x4f: /* DMA error registers */
	138	val = 0;
	139	/* XXX: not implemented yet */
	140	break;
	141	case 0x200 ... 0x20b: /* IOMMU */
	142	val = s->iommu[(addr & 0xf) >> 2];
	143	break;
	144	case 0x20c ... 0x3ff: /* IOMMU flush */
	145	val = 0;
	146	break;
	147	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	148	if (addr & 4) {
	149	val = s->pci_irq_map[(addr & 0x3f) >> 3];
	150	} else {
	151	val = 0;
	152	}
	153	break;
	154	case 0x2000 ... 0x202f: /* PCI control */
	155	val = s->pci_control[(addr & 0x3f) >> 2];
	156	break;
	157	case 0xf020 ... 0xf027: /* Reset control */
	158	if (addr & 4) {
	159	val = s->reset_control;
	160	} else {
	161	val = 0;
	162	}
	163	break;
	164	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	165	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	166	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	167	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	168	/* we don't care */
502a5395	169	default:
f930d07e BS	170	val = 0;
f930d07e BS	171	break;
502a5395	172	}
95819af0 BS	173	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
95819af0 BS	174
502a5395 PB	175	return val;
	176	}
	177
d60efc6b	178	static CPUWriteMemoryFunc * const apb_config_write[] = {
502a5395 PB	179	&apb_config_writel,
	180	&apb_config_writel,
	181	&apb_config_writel,
	182	};
	183
d60efc6b	184	static CPUReadMemoryFunc * const apb_config_read[] = {
502a5395 PB	185	&apb_config_readl,
	186	&apb_config_readl,
	187	&apb_config_readl,
	188	};
	189
63e6f31d	190	static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
5a5d4a76 BS	191	uint32_t val, int size)
5a5d4a76 BS	192	{
63e6f31d MT	193	APBState *s = container_of(h, APBState, pci_config_handler);
	194
	195	val = qemu_bswap_len(val, size);
5a5d4a76	196	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
d63baf92	197	pci_data_write(s->bus, addr, val, size);
5a5d4a76 BS	198	}
5a5d4a76 BS	199
63e6f31d	200	static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
5a5d4a76 BS	201	int size)
	202	{
	203	uint32_t ret;
63e6f31d	204	APBState *s = container_of(h, APBState, pci_config_handler);
5a5d4a76	205
d63baf92	206	ret = pci_data_read(s->bus, addr, size);
63e6f31d	207	ret = qemu_bswap_len(ret, size);
5a5d4a76 BS	208	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
	209	return ret;
	210	}
	211
c227f099	212	static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
502a5395 PB	213	uint32_t val)
502a5395 PB	214	{
afcea8cb	215	cpu_outb(addr & IOPORTS_MASK, val);
502a5395 PB	216	}
502a5395 PB	217
c227f099	218	static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
502a5395 PB	219	uint32_t val)
502a5395 PB	220	{
a4d5f62c	221	cpu_outw(addr & IOPORTS_MASK, bswap16(val));
502a5395 PB	222	}
502a5395 PB	223
c227f099	224	static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
502a5395 PB	225	uint32_t val)
502a5395 PB	226	{
a4d5f62c	227	cpu_outl(addr & IOPORTS_MASK, bswap32(val));
502a5395 PB	228	}
502a5395 PB	229
c227f099	230	static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
502a5395 PB	231	{
	232	uint32_t val;
	233
afcea8cb	234	val = cpu_inb(addr & IOPORTS_MASK);
502a5395 PB	235	return val;
	236	}
	237
c227f099	238	static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
502a5395 PB	239	{
	240	uint32_t val;
	241
a4d5f62c	242	val = bswap16(cpu_inw(addr & IOPORTS_MASK));
502a5395 PB	243	return val;
	244	}
	245
c227f099	246	static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
502a5395 PB	247	{
	248	uint32_t val;
	249
a4d5f62c	250	val = bswap32(cpu_inl(addr & IOPORTS_MASK));
502a5395 PB	251	return val;
	252	}
	253
d60efc6b	254	static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
502a5395 PB	255	&pci_apb_iowriteb,
	256	&pci_apb_iowritew,
	257	&pci_apb_iowritel,
	258	};
	259
d60efc6b	260	static CPUReadMemoryFunc * const pci_apb_ioread[] = {
502a5395 PB	261	&pci_apb_ioreadb,
	262	&pci_apb_ioreadw,
	263	&pci_apb_ioreadl,
	264	};
	265
80b3ada7	266	/* The APB host has an IRQ line for each IRQ line of each slot. */
d2b59317	267	static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	268	{
80b3ada7 PB	269	return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
	270	}
	271
	272	static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
	273	{
	274	int bus_offset;
	275	if (pci_dev->devfn & 1)
	276	bus_offset = 16;
	277	else
	278	bus_offset = 0;
	279	return bus_offset + irq_num;
d2b59317 PB	280	}
d2b59317 PB	281
5d4e84c8	282	static void pci_apb_set_irq(void *opaque, int irq_num, int level)
d2b59317	283	{
95819af0	284	APBState *s = opaque;
5d4e84c8	285
80b3ada7	286	/* PCI IRQ map onto the first 32 INO. */
95819af0 BS	287	if (irq_num < 32) {
	288	if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
	289	APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
	290	qemu_set_irq(s->pci_irqs[irq_num], level);
	291	} else {
	292	APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
	293	qemu_irq_lower(s->pci_irqs[irq_num]);
	294	}
	295	}
502a5395 PB	296	}
502a5395 PB	297
68f79994	298	static int apb_pci_bridge_initfn(PCIDevice *dev)
d6318738	299	{
68f79994 IY	300	int rc;
	301
	302	rc = pci_bridge_initfn(dev);
	303	if (rc < 0) {
	304	return rc;
	305	}
	306
d6318738 MT	307	/*
	308	* command register:
	309	* According to PCI bridge spec, after reset
	310	* bus master bit is off
	311	* memory space enable bit is off
	312	* According to manual (805-1251.pdf).
	313	* the reset value should be zero unless the boot pin is tied high
	314	* (which is true) and thus it should be PCI_COMMAND_MEMORY.
	315	*/
	316	pci_set_word(dev->config + PCI_COMMAND,
9fe52c7f BS	317	PCI_COMMAND_MEMORY);
	318	pci_set_word(dev->config + PCI_STATUS,
	319	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	320	PCI_STATUS_DEVSEL_MEDIUM);
68f79994	321	return 0;
d6318738 MT	322	}
d6318738 MT	323
c227f099 AL	324	PCIBus *pci_apb_init(target_phys_addr_t special_base,
c227f099 AL	325	target_phys_addr_t mem_base,
c190ea07	326	qemu_irq pic, PCIBus bus2, PCIBus *bus3)
502a5395	327	{
72f44c8c BS	328	DeviceState *dev;
	329	SysBusDevice *s;
	330	APBState *d;
95819af0	331	unsigned int i;
68f79994 IY	332	PCIDevice *pci_dev;
68f79994 IY	333	PCIBridge *br;
502a5395	334
80b3ada7	335	/* Ultrasparc PBM main bus */
72f44c8c	336	dev = qdev_create(NULL, "pbm");
e23a1b33	337	qdev_init_nofail(dev);
72f44c8c BS	338	s = sysbus_from_qdev(dev);
72f44c8c BS	339	/* apb_config */
bae7b517	340	sysbus_mmio_map(s, 0, special_base);
d63baf92 IK	341	/* PCI configuration space */
d63baf92 IK	342	sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
72f44c8c	343	/* pci_ioport */
d63baf92	344	sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
72f44c8c	345	d = FROM_SYSBUS(APBState, s);
d63baf92 IK	346
d63baf92 IK	347	d->bus = pci_register_bus(&d->busdev.qdev, "pci",
95819af0	348	pci_apb_set_irq, pci_pbm_map_irq, d,
72f44c8c	349	0, 32);
d63baf92	350	pci_bus_set_mem_base(d->bus, mem_base);
f6b6f1bc	351
95819af0 BS	352	for (i = 0; i < 32; i++) {
	353	sysbus_connect_irq(s, i, pic[i]);
	354	}
	355
d63baf92 IK	356	pci_create_simple(d->bus, 0, "pbm");
d63baf92 IK	357
72f44c8c	358	/* APB secondary busses */
68f79994 IY	359	pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
	360	"pbm-bridge");
	361	br = DO_UPCAST(PCIBridge, dev, pci_dev);
	362	pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
	363	pci_apb_map_irq);
	364	qdev_init_nofail(&pci_dev->qdev);
	365	*bus2 = pci_bridge_get_sec_bus(br);
	366
	367	pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
	368	"pbm-bridge");
	369	br = DO_UPCAST(PCIBridge, dev, pci_dev);
	370	pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
	371	pci_apb_map_irq);
	372	qdev_init_nofail(&pci_dev->qdev);
	373	*bus3 = pci_bridge_get_sec_bus(br);
502a5395	374
d63baf92	375	return d->bus;
72f44c8c BS	376	}
72f44c8c BS	377
95819af0	378	static void pci_pbm_reset(DeviceState *d)
72f44c8c	379	{
95819af0 BS	380	unsigned int i;
95819af0 BS	381	APBState *s = container_of(d, APBState, busdev.qdev);
72f44c8c	382
95819af0 BS	383	for (i = 0; i < 8; i++) {
	384	s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
	385	}
	386
9c0afd0e	387	if (s->nr_resets++ == 0) {
95819af0 BS	388	/* Power on reset */
	389	s->reset_control = POR;
	390	}
	391	}
	392
	393	static int pci_pbm_init_device(SysBusDevice *dev)
	394	{
72f44c8c	395	APBState *s;
d63baf92	396	int pci_config, apb_config, pci_ioport;
95819af0	397	unsigned int i;
72f44c8c BS	398
72f44c8c BS	399	s = FROM_SYSBUS(APBState, dev);
95819af0 BS	400	for (i = 0; i < 8; i++) {
	401	s->pci_irq_map[i] = (0x1f << 6) \| (i << 2);
	402	}
	403	for (i = 0; i < 32; i++) {
	404	sysbus_init_irq(dev, &s->pci_irqs[i]);
	405	}
	406
72f44c8c	407	/* apb_config */
1eed09cb	408	apb_config = cpu_register_io_memory(apb_config_read,
2507c12a AG	409	apb_config_write, s,
2507c12a AG	410	DEVICE_NATIVE_ENDIAN);
d63baf92	411	/* at region 0 */
bae7b517	412	sysbus_init_mmio(dev, 0x10000ULL, apb_config);
d63baf92 IK	413
d63baf92 IK	414	/* PCI configuration space */
63e6f31d MT	415	s->pci_config_handler.read = apb_pci_config_read;
63e6f31d MT	416	s->pci_config_handler.write = apb_pci_config_write;
6bef0436 AG	417	pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
6bef0436 AG	418	DEVICE_NATIVE_ENDIAN);
63e6f31d	419	assert(pci_config >= 0);
d63baf92	420	/* at region 1 */
5a5d4a76	421	sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
d63baf92 IK	422
	423	/* pci_ioport */
	424	pci_ioport = cpu_register_io_memory(pci_apb_ioread,
2507c12a AG	425	pci_apb_iowrite, s,
2507c12a AG	426	DEVICE_NATIVE_ENDIAN);
d63baf92 IK	427	/* at region 2 */
	428	sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
	429
81a322d4	430	return 0;
72f44c8c	431	}
502a5395	432
81a322d4	433	static int pbm_pci_host_init(PCIDevice *d)
72f44c8c	434	{
9fe52c7f BS	435	pci_set_word(d->config + PCI_COMMAND,
	436	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	437	pci_set_word(d->config + PCI_STATUS,
	438	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	439	PCI_STATUS_DEVSEL_MEDIUM);
81a322d4	440	return 0;
72f44c8c	441	}
80b3ada7	442
72f44c8c BS	443	static PCIDeviceInfo pbm_pci_host_info = {
	444	.qdev.name = "pbm",
	445	.qdev.size = sizeof(PCIDevice),
	446	.init = pbm_pci_host_init,
92f9a4f1 IY	447	.vendor_id = PCI_VENDOR_ID_SUN,
	448	.device_id = PCI_DEVICE_ID_SUN_SABRE,
	449	.class_id = PCI_CLASS_BRIDGE_HOST,
e327e323	450	.is_bridge = 1,
72f44c8c BS	451	};
72f44c8c BS	452
95819af0 BS	453	static SysBusDeviceInfo pbm_host_info = {
	454	.qdev.name = "pbm",
	455	.qdev.size = sizeof(APBState),
	456	.qdev.reset = pci_pbm_reset,
	457	.init = pci_pbm_init_device,
	458	};
68f79994 IY	459
	460	static PCIDeviceInfo pbm_pci_bridge_info = {
	461	.qdev.name = "pbm-bridge",
	462	.qdev.size = sizeof(PCIBridge),
	463	.qdev.vmsd = &vmstate_pci_device,
	464	.qdev.reset = pci_bridge_reset,
	465	.init = apb_pci_bridge_initfn,
	466	.exit = pci_bridge_exitfn,
92f9a4f1 IY	467	.vendor_id = PCI_VENDOR_ID_SUN,
	468	.device_id = PCI_DEVICE_ID_SUN_SIMBA,
	469	.revision = 0x11,
68f79994 IY	470	.config_write = pci_bridge_write_config,
	471	.is_bridge = 1,
	472	};
	473
72f44c8c BS	474	static void pbm_register_devices(void)
72f44c8c BS	475	{
95819af0	476	sysbus_register_withprop(&pbm_host_info);
72f44c8c	477	pci_qdev_register(&pbm_pci_host_info);
68f79994	478	pci_qdev_register(&pbm_pci_bridge_info);
502a5395	479	}
72f44c8c BS	480
72f44c8c BS	481	device_init(pbm_register_devices)