[qemu.git] / hw / apb_pci.c

/*
 * QEMU Ultrasparc APB PCI host
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* XXX This file and most of its contents are somewhat misnamed.  The
   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
   the secondary PCI bridge.  */

#include "sysbus.h"
#include "pci.h"
#include "pci_host.h"
#include "apb_pci.h"

/* debug APB */
//#define DEBUG_APB

#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, ...) \
do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#else
#define APB_DPRINTF(fmt, ...)
#endif

/*
 * Chipset docs:
 * PBM: "UltraSPARC IIi User's Manual",
 * http://www.sun.com/processors/manuals/805-0087.pdf
 *
 * APB: "Advanced PCI Bridge (APB) User's Manual",
 * http://www.sun.com/processors/manuals/805-1251.pdf
 */

typedef struct APBState {
    SysBusDevice busdev;
    PCIHostState host_state;
} APBState;

static void apb_config_writel (void *opaque, target_phys_addr_t addr,
                               uint32_t val)
{
    //PCIBus *s = opaque;

    switch (addr & 0x3f) {
    case 0x00: // Control/Status
    case 0x10: // AFSR
    case 0x18: // AFAR
    case 0x20: // Diagnostic
    case 0x28: // Target address space
        // XXX
    default:
        break;
    }
}

static uint32_t apb_config_readl (void *opaque,
                                  target_phys_addr_t addr)
{
    //PCIBus *s = opaque;
    uint32_t val;

    switch (addr & 0x3f) {
    case 0x00: // Control/Status
    case 0x10: // AFSR
    case 0x18: // AFAR
    case 0x20: // Diagnostic
    case 0x28: // Target address space
        // XXX
    default:
        val = 0;
        break;
    }
    return val;
}

static CPUWriteMemoryFunc * const apb_config_write[] = {
    &apb_config_writel,
    &apb_config_writel,
    &apb_config_writel,
};

static CPUReadMemoryFunc * const apb_config_read[] = {
    &apb_config_readl,
    &apb_config_readl,
    &apb_config_readl,
};

static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outb(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outw(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    cpu_outl(addr & IOPORTS_MASK, val);
}

static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inb(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inw(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inl(addr & IOPORTS_MASK);
    return val;
}

static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
    &pci_apb_iowriteb,
    &pci_apb_iowritew,
    &pci_apb_iowritel,
};

static CPUReadMemoryFunc * const pci_apb_ioread[] = {
    &pci_apb_ioreadb,
    &pci_apb_ioreadw,
    &pci_apb_ioreadl,
};

/* The APB host has an IRQ line for each IRQ line of each slot.  */
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}

static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int bus_offset;
    if (pci_dev->devfn & 1)
        bus_offset = 16;
    else
        bus_offset = 0;
    return bus_offset + irq_num;
}

static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    /* PCI IRQ map onto the first 32 INO.  */
    qemu_set_irq(pic[irq_num], level);
}

static void apb_pci_bridge_init(PCIBus *b)
{
    PCIDevice *dev = pci_bridge_get_device(b);

    /*
     * command register:
     * According to PCI bridge spec, after reset
     *   bus master bit is off
     *   memory space enable bit is off
     * According to manual (805-1251.pdf).
     *   the reset value should be zero unless the boot pin is tied high
     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
     */
    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    dev->config[PCI_LATENCY_TIMER] = 0x10;
    dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
}

PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
    DeviceState *dev;
    SysBusDevice *s;
    APBState *d;

    /* Ultrasparc PBM main bus */
    dev = qdev_create(NULL, "pbm");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    /* apb_config */
    sysbus_mmio_map(s, 0, special_base + 0x2000ULL);
    /* pci_ioport */
    sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
    /* mem_config: XXX size should be 4G-prom */
    sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
    /* mem_data */
    sysbus_mmio_map(s, 3, mem_base);
    d = FROM_SYSBUS(APBState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_apb_set_irq, pci_pbm_map_irq, pic,
                                         0, 32);
    pci_create_simple(d->host_state.bus, 0, "pbm");
    /* APB secondary busses */
    *bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                            pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 1");
    apb_pci_bridge_init(*bus2);

    *bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                            pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 2");
    apb_pci_bridge_init(*bus3);

    return d->host_state.bus;
}

static int pci_pbm_init_device(SysBusDevice *dev)
{

    APBState *s;
    int pci_mem_config, pci_mem_data, apb_config, pci_ioport;

    s = FROM_SYSBUS(APBState, dev);
    /* apb_config */
    apb_config = cpu_register_io_memory(apb_config_read,
                                        apb_config_write, s);
    sysbus_init_mmio(dev, 0x40ULL, apb_config);
    /* pci_ioport */
    pci_ioport = cpu_register_io_memory(pci_apb_ioread,
                                          pci_apb_iowrite, s);
    sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
    /* mem_config  */
    pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
    sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
    /* mem_data */
    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
    sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
    return 0;
}

static int pbm_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
    d->config[0x04] = 0x06; // command = bus master, pci mem
    d->config[0x05] = 0x00;
    d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
    d->config[0x07] = 0x03; // status = medium devsel
    d->config[0x08] = 0x00; // revision
    d->config[0x09] = 0x00; // programming i/f
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    return 0;
}

static PCIDeviceInfo pbm_pci_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(PCIDevice),
    .init      = pbm_pci_host_init,
};

static void pbm_register_devices(void)
{
    sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device);
    pci_qdev_register(&pbm_pci_host_info);
}

device_init(pbm_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Ultrasparc APB PCI host
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80b3ada7	24
a94fd955	25	/* XXX This file and most of its contents are somewhat misnamed. The
80b3ada7 PB	26	Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
	27	the secondary PCI bridge. */
	28
72f44c8c	29	#include "sysbus.h"
87ecb68b	30	#include "pci.h"
4f5e19e6	31	#include "pci_host.h"
18e08a55	32	#include "apb_pci.h"
a94fd955 BS	33
	34	/* debug APB */
	35	//#define DEBUG_APB
	36
	37	#ifdef DEBUG_APB
001faf32 BS	38	#define APB_DPRINTF(fmt, ...) \
001faf32 BS	39	do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
a94fd955	40	#else
001faf32	41	#define APB_DPRINTF(fmt, ...)
a94fd955 BS	42	#endif
a94fd955 BS	43
930f3fe1 BS	44	/*
	45	* Chipset docs:
	46	* PBM: "UltraSPARC IIi User's Manual",
	47	* http://www.sun.com/processors/manuals/805-0087.pdf
	48	*
	49	* APB: "Advanced PCI Bridge (APB) User's Manual",
	50	* http://www.sun.com/processors/manuals/805-1251.pdf
	51	*/
	52
72f44c8c BS	53	typedef struct APBState {
	54	SysBusDevice busdev;
	55	PCIHostState host_state;
	56	} APBState;
502a5395	57
c227f099	58	static void apb_config_writel (void *opaque, target_phys_addr_t addr,
f930d07e	59	uint32_t val)
502a5395 PB	60	{
	61	//PCIBus *s = opaque;
	62
	63	switch (addr & 0x3f) {
	64	case 0x00: // Control/Status
	65	case 0x10: // AFSR
	66	case 0x18: // AFAR
	67	case 0x20: // Diagnostic
	68	case 0x28: // Target address space
f930d07e	69	// XXX
502a5395	70	default:
f930d07e	71	break;
502a5395 PB	72	}
	73	}
	74
	75	static uint32_t apb_config_readl (void *opaque,
c227f099	76	target_phys_addr_t addr)
502a5395 PB	77	{
	78	//PCIBus *s = opaque;
	79	uint32_t val;
	80
	81	switch (addr & 0x3f) {
	82	case 0x00: // Control/Status
	83	case 0x10: // AFSR
	84	case 0x18: // AFAR
	85	case 0x20: // Diagnostic
	86	case 0x28: // Target address space
f930d07e	87	// XXX
502a5395	88	default:
f930d07e BS	89	val = 0;
f930d07e BS	90	break;
502a5395 PB	91	}
	92	return val;
	93	}
	94
d60efc6b	95	static CPUWriteMemoryFunc * const apb_config_write[] = {
502a5395 PB	96	&apb_config_writel,
	97	&apb_config_writel,
	98	&apb_config_writel,
	99	};
	100
d60efc6b	101	static CPUReadMemoryFunc * const apb_config_read[] = {
502a5395 PB	102	&apb_config_readl,
	103	&apb_config_readl,
	104	&apb_config_readl,
	105	};
	106
c227f099	107	static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
502a5395 PB	108	uint32_t val)
502a5395 PB	109	{
afcea8cb	110	cpu_outb(addr & IOPORTS_MASK, val);
502a5395 PB	111	}
502a5395 PB	112
c227f099	113	static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
502a5395 PB	114	uint32_t val)
502a5395 PB	115	{
afcea8cb	116	cpu_outw(addr & IOPORTS_MASK, val);
502a5395 PB	117	}
502a5395 PB	118
c227f099	119	static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
502a5395 PB	120	uint32_t val)
502a5395 PB	121	{
afcea8cb	122	cpu_outl(addr & IOPORTS_MASK, val);
502a5395 PB	123	}
502a5395 PB	124
c227f099	125	static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
502a5395 PB	126	{
	127	uint32_t val;
	128
afcea8cb	129	val = cpu_inb(addr & IOPORTS_MASK);
502a5395 PB	130	return val;
	131	}
	132
c227f099	133	static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
502a5395 PB	134	{
	135	uint32_t val;
	136
afcea8cb	137	val = cpu_inw(addr & IOPORTS_MASK);
502a5395 PB	138	return val;
	139	}
	140
c227f099	141	static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
502a5395 PB	142	{
	143	uint32_t val;
	144
afcea8cb	145	val = cpu_inl(addr & IOPORTS_MASK);
502a5395 PB	146	return val;
	147	}
	148
d60efc6b	149	static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
502a5395 PB	150	&pci_apb_iowriteb,
	151	&pci_apb_iowritew,
	152	&pci_apb_iowritel,
	153	};
	154
d60efc6b	155	static CPUReadMemoryFunc * const pci_apb_ioread[] = {
502a5395 PB	156	&pci_apb_ioreadb,
	157	&pci_apb_ioreadw,
	158	&pci_apb_ioreadl,
	159	};
	160
80b3ada7	161	/* The APB host has an IRQ line for each IRQ line of each slot. */
d2b59317	162	static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	163	{
80b3ada7 PB	164	return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
	165	}
	166
	167	static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
	168	{
	169	int bus_offset;
	170	if (pci_dev->devfn & 1)
	171	bus_offset = 16;
	172	else
	173	bus_offset = 0;
	174	return bus_offset + irq_num;
d2b59317 PB	175	}
d2b59317 PB	176
5d4e84c8	177	static void pci_apb_set_irq(void *opaque, int irq_num, int level)
d2b59317	178	{
5d4e84c8 JQ	179	qemu_irq *pic = opaque;
5d4e84c8 JQ	180
80b3ada7	181	/* PCI IRQ map onto the first 32 INO. */
d537cf6c	182	qemu_set_irq(pic[irq_num], level);
502a5395 PB	183	}
502a5395 PB	184
d6318738 MT	185	static void apb_pci_bridge_init(PCIBus *b)
	186	{
	187	PCIDevice *dev = pci_bridge_get_device(b);
	188
	189	/*
	190	* command register:
	191	* According to PCI bridge spec, after reset
	192	* bus master bit is off
	193	* memory space enable bit is off
	194	* According to manual (805-1251.pdf).
	195	* the reset value should be zero unless the boot pin is tied high
	196	* (which is true) and thus it should be PCI_COMMAND_MEMORY.
	197	*/
	198	pci_set_word(dev->config + PCI_COMMAND,
	199	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	200	dev->config[PCI_LATENCY_TIMER] = 0x10;
	201	dev->config[PCI_HEADER_TYPE] \|= PCI_HEADER_TYPE_MULTI_FUNCTION;
	202	}
	203
c227f099 AL	204	PCIBus *pci_apb_init(target_phys_addr_t special_base,
c227f099 AL	205	target_phys_addr_t mem_base,
c190ea07	206	qemu_irq pic, PCIBus bus2, PCIBus *bus3)
502a5395	207	{
72f44c8c BS	208	DeviceState *dev;
	209	SysBusDevice *s;
	210	APBState *d;
502a5395	211
80b3ada7	212	/* Ultrasparc PBM main bus */
72f44c8c	213	dev = qdev_create(NULL, "pbm");
e23a1b33	214	qdev_init_nofail(dev);
72f44c8c BS	215	s = sysbus_from_qdev(dev);
	216	/* apb_config */
	217	sysbus_mmio_map(s, 0, special_base + 0x2000ULL);
	218	/* pci_ioport */
	219	sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
	220	/* mem_config: XXX size should be 4G-prom */
	221	sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
	222	/* mem_data */
	223	sysbus_mmio_map(s, 3, mem_base);
	224	d = FROM_SYSBUS(APBState, s);
c5ff6d54	225	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
72f44c8c BS	226	pci_apb_set_irq, pci_pbm_map_irq, pic,
	227	0, 32);
	228	pci_create_simple(d->host_state.bus, 0, "pbm");
	229	/* APB secondary busses */
2217dcff IY	230	*bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
	231	PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
	232	pci_apb_map_irq,
72f44c8c	233	"Advanced PCI Bus secondary bridge 1");
d6318738 MT	234	apb_pci_bridge_init(*bus2);
d6318738 MT	235
2217dcff IY	236	*bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
	237	PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
	238	pci_apb_map_irq,
72f44c8c	239	"Advanced PCI Bus secondary bridge 2");
d6318738	240	apb_pci_bridge_init(*bus3);
502a5395	241
72f44c8c BS	242	return d->host_state.bus;
	243	}
	244
81a322d4	245	static int pci_pbm_init_device(SysBusDevice *dev)
72f44c8c BS	246	{
	247
	248	APBState *s;
	249	int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
	250
	251	s = FROM_SYSBUS(APBState, dev);
	252	/* apb_config */
1eed09cb	253	apb_config = cpu_register_io_memory(apb_config_read,
f930d07e	254	apb_config_write, s);
72f44c8c BS	255	sysbus_init_mmio(dev, 0x40ULL, apb_config);
72f44c8c BS	256	/* pci_ioport */
1eed09cb	257	pci_ioport = cpu_register_io_memory(pci_apb_ioread,
502a5395	258	pci_apb_iowrite, s);
72f44c8c BS	259	sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
72f44c8c BS	260	/* mem_config */
f08b32fe	261	pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
72f44c8c BS	262	sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
72f44c8c BS	263	/* mem_data */
f08b32fe	264	pci_mem_data = pci_host_data_register_mmio(&s->host_state);
72f44c8c	265	sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
81a322d4	266	return 0;
72f44c8c	267	}
502a5395	268
81a322d4	269	static int pbm_pci_host_init(PCIDevice *d)
72f44c8c	270	{
deb54399 AL	271	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
deb54399 AL	272	pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
502a5395 PB	273	d->config[0x04] = 0x06; // command = bus master, pci mem
	274	d->config[0x05] = 0x00;
	275	d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
	276	d->config[0x07] = 0x03; // status = medium devsel
	277	d->config[0x08] = 0x00; // revision
	278	d->config[0x09] = 0x00; // programming i/f
173a543b	279	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395	280	d->config[0x0D] = 0x10; // latency_timer
110c50fd	281	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
81a322d4	282	return 0;
72f44c8c	283	}
80b3ada7	284
72f44c8c BS	285	static PCIDeviceInfo pbm_pci_host_info = {
	286	.qdev.name = "pbm",
	287	.qdev.size = sizeof(PCIDevice),
	288	.init = pbm_pci_host_init,
	289	};
	290
	291	static void pbm_register_devices(void)
	292	{
	293	sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device);
	294	pci_qdev_register(&pbm_pci_host_info);
502a5395	295	}
72f44c8c BS	296
72f44c8c BS	297	device_init(pbm_register_devices)