[qemu.git] / hw / apb_pci.c

/*
 * QEMU Ultrasparc APB PCI host
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* XXX This file and most of its contents are somewhat misnamed.  The
   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
   the secondary PCI bridge.  */

#include "sysbus.h"
#include "pci.h"
#include "pci_host.h"
#include "apb_pci.h"

/* debug APB */
//#define DEBUG_APB

#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, ...) \
do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#else
#define APB_DPRINTF(fmt, ...)
#endif

/*
 * Chipset docs:
 * PBM: "UltraSPARC IIi User's Manual",
 * http://www.sun.com/processors/manuals/805-0087.pdf
 *
 * APB: "Advanced PCI Bridge (APB) User's Manual",
 * http://www.sun.com/processors/manuals/805-1251.pdf
 */

typedef struct APBState {
    SysBusDevice busdev;
    PCIHostState host_state;
} APBState;

static void apb_config_writel (void *opaque, target_phys_addr_t addr,
                               uint32_t val)
{
    //PCIBus *s = opaque;

    switch (addr & 0x3f) {
    case 0x00: // Control/Status
    case 0x10: // AFSR
    case 0x18: // AFAR
    case 0x20: // Diagnostic
    case 0x28: // Target address space
        // XXX
    default:
        break;
    }
}

static uint32_t apb_config_readl (void *opaque,
                                  target_phys_addr_t addr)
{
    //PCIBus *s = opaque;
    uint32_t val;

    switch (addr & 0x3f) {
    case 0x00: // Control/Status
    case 0x10: // AFSR
    case 0x18: // AFAR
    case 0x20: // Diagnostic
    case 0x28: // Target address space
        // XXX
    default:
        val = 0;
        break;
    }
    return val;
}

static CPUWriteMemoryFunc * const apb_config_write[] = {
    &apb_config_writel,
    &apb_config_writel,
    &apb_config_writel,
};

static CPUReadMemoryFunc * const apb_config_read[] = {
    &apb_config_readl,
    &apb_config_readl,
    &apb_config_readl,
};

static void apb_pci_config_write(APBState *s, target_phys_addr_t addr,
                                 uint32_t val, int size)
{
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
    pci_data_write(s->host_state.bus, (addr & 0x00ffffff) | (1u << 31), val,
                   size);
}

static uint32_t apb_pci_config_read(APBState *s, target_phys_addr_t addr,
                                    int size)
{
    uint32_t ret;

    ret = pci_data_read(s->host_state.bus, (addr & 0x00ffffff) | (1u << 31),
                        size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
    return ret;
}

static void apb_pci_config_writel(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    APBState *s = opaque;

    apb_pci_config_write(s, addr, bswap32(val), 4);
}

static void apb_pci_config_writew(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    APBState *s = opaque;

    apb_pci_config_write(s, addr, bswap16(val), 2);
}

static void apb_pci_config_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    APBState *s = opaque;

    apb_pci_config_write(s, addr, val, 1);
}

static uint32_t apb_pci_config_readl(void *opaque, target_phys_addr_t addr)
{
    APBState *s = opaque;

    return bswap32(apb_pci_config_read(s, addr, 4));
}

static uint32_t apb_pci_config_readw(void *opaque, target_phys_addr_t addr)
{
    APBState *s = opaque;

    return bswap16(apb_pci_config_read(s, addr, 2));
}

static uint32_t apb_pci_config_readb(void *opaque, target_phys_addr_t addr)
{
    APBState *s = opaque;

    return apb_pci_config_read(s, addr, 1);
}

static CPUWriteMemoryFunc * const apb_pci_config_writes[] = {
    &apb_pci_config_writeb,
    &apb_pci_config_writew,
    &apb_pci_config_writel,
};

static CPUReadMemoryFunc * const apb_pci_config_reads[] = {
    &apb_pci_config_readb,
    &apb_pci_config_readw,
    &apb_pci_config_readl,
};

static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outb(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outw(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    cpu_outl(addr & IOPORTS_MASK, val);
}

static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inb(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inw(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inl(addr & IOPORTS_MASK);
    return val;
}

static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
    &pci_apb_iowriteb,
    &pci_apb_iowritew,
    &pci_apb_iowritel,
};

static CPUReadMemoryFunc * const pci_apb_ioread[] = {
    &pci_apb_ioreadb,
    &pci_apb_ioreadw,
    &pci_apb_ioreadl,
};

/* The APB host has an IRQ line for each IRQ line of each slot.  */
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}

static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int bus_offset;
    if (pci_dev->devfn & 1)
        bus_offset = 16;
    else
        bus_offset = 0;
    return bus_offset + irq_num;
}

static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    /* PCI IRQ map onto the first 32 INO.  */
    qemu_set_irq(pic[irq_num], level);
}

static void apb_pci_bridge_init(PCIBus *b)
{
    PCIDevice *dev = pci_bridge_get_device(b);

    /*
     * command register:
     * According to PCI bridge spec, after reset
     *   bus master bit is off
     *   memory space enable bit is off
     * According to manual (805-1251.pdf).
     *   the reset value should be zero unless the boot pin is tied high
     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
     */
    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    dev->config[PCI_LATENCY_TIMER] = 0x10;
    dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
}

PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
    DeviceState *dev;
    SysBusDevice *s;
    APBState *d;

    /* Ultrasparc PBM main bus */
    dev = qdev_create(NULL, "pbm");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    /* apb_config */
    sysbus_mmio_map(s, 0, special_base);
    /* pci_ioport */
    sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
    /* pci_config */
    sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
    /* mem_data */
    sysbus_mmio_map(s, 3, mem_base);
    d = FROM_SYSBUS(APBState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_apb_set_irq, pci_pbm_map_irq, pic,
                                         0, 32);
    pci_bus_set_mem_base(d->host_state.bus, mem_base);

    pci_create_simple(d->host_state.bus, 0, "pbm");
    /* APB secondary busses */
    *bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                            pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 1");
    apb_pci_bridge_init(*bus2);

    *bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                            pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 2");
    apb_pci_bridge_init(*bus3);

    return d->host_state.bus;
}

static int pci_pbm_init_device(SysBusDevice *dev)
{

    APBState *s;
    int pci_mem_data, apb_config, pci_ioport, pci_config;

    s = FROM_SYSBUS(APBState, dev);
    /* apb_config */
    apb_config = cpu_register_io_memory(apb_config_read,
                                        apb_config_write, s);
    sysbus_init_mmio(dev, 0x10000ULL, apb_config);
    /* pci_ioport */
    pci_ioport = cpu_register_io_memory(pci_apb_ioread,
                                          pci_apb_iowrite, s);
    sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
    /* pci_config */
    pci_config = cpu_register_io_memory(apb_pci_config_reads,
                                        apb_pci_config_writes, s);
    sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
    /* mem_data */
    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
    sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
    return 0;
}

static int pbm_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
    d->config[0x04] = 0x06; // command = bus master, pci mem
    d->config[0x05] = 0x00;
    d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
    d->config[0x07] = 0x03; // status = medium devsel
    d->config[0x08] = 0x00; // revision
    d->config[0x09] = 0x00; // programming i/f
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    return 0;
}

static PCIDeviceInfo pbm_pci_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(PCIDevice),
    .init      = pbm_pci_host_init,
};

static void pbm_register_devices(void)
{
    sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device);
    pci_qdev_register(&pbm_pci_host_info);
}

device_init(pbm_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Ultrasparc APB PCI host
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80b3ada7	24
a94fd955	25	/* XXX This file and most of its contents are somewhat misnamed. The
80b3ada7 PB	26	Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
	27	the secondary PCI bridge. */
	28
72f44c8c	29	#include "sysbus.h"
87ecb68b	30	#include "pci.h"
4f5e19e6	31	#include "pci_host.h"
18e08a55	32	#include "apb_pci.h"
a94fd955 BS	33
	34	/* debug APB */
	35	//#define DEBUG_APB
	36
	37	#ifdef DEBUG_APB
001faf32 BS	38	#define APB_DPRINTF(fmt, ...) \
001faf32 BS	39	do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
a94fd955	40	#else
001faf32	41	#define APB_DPRINTF(fmt, ...)
a94fd955 BS	42	#endif
a94fd955 BS	43
930f3fe1 BS	44	/*
	45	* Chipset docs:
	46	* PBM: "UltraSPARC IIi User's Manual",
	47	* http://www.sun.com/processors/manuals/805-0087.pdf
	48	*
	49	* APB: "Advanced PCI Bridge (APB) User's Manual",
	50	* http://www.sun.com/processors/manuals/805-1251.pdf
	51	*/
	52
72f44c8c BS	53	typedef struct APBState {
	54	SysBusDevice busdev;
	55	PCIHostState host_state;
	56	} APBState;
502a5395	57
c227f099	58	static void apb_config_writel (void *opaque, target_phys_addr_t addr,
f930d07e	59	uint32_t val)
502a5395 PB	60	{
	61	//PCIBus *s = opaque;
	62
	63	switch (addr & 0x3f) {
	64	case 0x00: // Control/Status
	65	case 0x10: // AFSR
	66	case 0x18: // AFAR
	67	case 0x20: // Diagnostic
	68	case 0x28: // Target address space
f930d07e	69	// XXX
502a5395	70	default:
f930d07e	71	break;
502a5395 PB	72	}
	73	}
	74
	75	static uint32_t apb_config_readl (void *opaque,
c227f099	76	target_phys_addr_t addr)
502a5395 PB	77	{
	78	//PCIBus *s = opaque;
	79	uint32_t val;
	80
	81	switch (addr & 0x3f) {
	82	case 0x00: // Control/Status
	83	case 0x10: // AFSR
	84	case 0x18: // AFAR
	85	case 0x20: // Diagnostic
	86	case 0x28: // Target address space
f930d07e	87	// XXX
502a5395	88	default:
f930d07e BS	89	val = 0;
f930d07e BS	90	break;
502a5395 PB	91	}
	92	return val;
	93	}
	94
d60efc6b	95	static CPUWriteMemoryFunc * const apb_config_write[] = {
502a5395 PB	96	&apb_config_writel,
	97	&apb_config_writel,
	98	&apb_config_writel,
	99	};
	100
d60efc6b	101	static CPUReadMemoryFunc * const apb_config_read[] = {
502a5395 PB	102	&apb_config_readl,
	103	&apb_config_readl,
	104	&apb_config_readl,
	105	};
	106
5a5d4a76 BS	107	static void apb_pci_config_write(APBState *s, target_phys_addr_t addr,
	108	uint32_t val, int size)
	109	{
	110	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
	111	pci_data_write(s->host_state.bus, (addr & 0x00ffffff) \| (1u << 31), val,
	112	size);
	113	}
	114
	115	static uint32_t apb_pci_config_read(APBState *s, target_phys_addr_t addr,
	116	int size)
	117	{
	118	uint32_t ret;
	119
	120	ret = pci_data_read(s->host_state.bus, (addr & 0x00ffffff) \| (1u << 31),
	121	size);
	122	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
	123	return ret;
	124	}
	125
	126	static void apb_pci_config_writel(void *opaque, target_phys_addr_t addr,
	127	uint32_t val)
	128	{
	129	APBState *s = opaque;
	130
204c7a39	131	apb_pci_config_write(s, addr, bswap32(val), 4);
5a5d4a76 BS	132	}
	133
	134	static void apb_pci_config_writew(void *opaque, target_phys_addr_t addr,
	135	uint32_t val)
	136	{
	137	APBState *s = opaque;
	138
204c7a39	139	apb_pci_config_write(s, addr, bswap16(val), 2);
5a5d4a76 BS	140	}
	141
	142	static void apb_pci_config_writeb(void *opaque, target_phys_addr_t addr,
	143	uint32_t val)
	144	{
	145	APBState *s = opaque;
	146
	147	apb_pci_config_write(s, addr, val, 1);
	148	}
	149
	150	static uint32_t apb_pci_config_readl(void *opaque, target_phys_addr_t addr)
	151	{
	152	APBState *s = opaque;
	153
204c7a39	154	return bswap32(apb_pci_config_read(s, addr, 4));
5a5d4a76 BS	155	}
	156
	157	static uint32_t apb_pci_config_readw(void *opaque, target_phys_addr_t addr)
	158	{
	159	APBState *s = opaque;
	160
204c7a39	161	return bswap16(apb_pci_config_read(s, addr, 2));
5a5d4a76 BS	162	}
	163
	164	static uint32_t apb_pci_config_readb(void *opaque, target_phys_addr_t addr)
	165	{
	166	APBState *s = opaque;
	167
	168	return apb_pci_config_read(s, addr, 1);
	169	}
	170
	171	static CPUWriteMemoryFunc * const apb_pci_config_writes[] = {
5a5d4a76	172	&apb_pci_config_writeb,
3eb26cc2 BS	173	&apb_pci_config_writew,
3eb26cc2 BS	174	&apb_pci_config_writel,
5a5d4a76 BS	175	};
	176
	177	static CPUReadMemoryFunc * const apb_pci_config_reads[] = {
5a5d4a76	178	&apb_pci_config_readb,
3eb26cc2 BS	179	&apb_pci_config_readw,
3eb26cc2 BS	180	&apb_pci_config_readl,
5a5d4a76 BS	181	};
5a5d4a76 BS	182
c227f099	183	static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
502a5395 PB	184	uint32_t val)
502a5395 PB	185	{
afcea8cb	186	cpu_outb(addr & IOPORTS_MASK, val);
502a5395 PB	187	}
502a5395 PB	188
c227f099	189	static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
502a5395 PB	190	uint32_t val)
502a5395 PB	191	{
afcea8cb	192	cpu_outw(addr & IOPORTS_MASK, val);
502a5395 PB	193	}
502a5395 PB	194
c227f099	195	static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
502a5395 PB	196	uint32_t val)
502a5395 PB	197	{
afcea8cb	198	cpu_outl(addr & IOPORTS_MASK, val);
502a5395 PB	199	}
502a5395 PB	200
c227f099	201	static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
502a5395 PB	202	{
	203	uint32_t val;
	204
afcea8cb	205	val = cpu_inb(addr & IOPORTS_MASK);
502a5395 PB	206	return val;
	207	}
	208
c227f099	209	static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
502a5395 PB	210	{
	211	uint32_t val;
	212
afcea8cb	213	val = cpu_inw(addr & IOPORTS_MASK);
502a5395 PB	214	return val;
	215	}
	216
c227f099	217	static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
502a5395 PB	218	{
	219	uint32_t val;
	220
afcea8cb	221	val = cpu_inl(addr & IOPORTS_MASK);
502a5395 PB	222	return val;
	223	}
	224
d60efc6b	225	static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
502a5395 PB	226	&pci_apb_iowriteb,
	227	&pci_apb_iowritew,
	228	&pci_apb_iowritel,
	229	};
	230
d60efc6b	231	static CPUReadMemoryFunc * const pci_apb_ioread[] = {
502a5395 PB	232	&pci_apb_ioreadb,
	233	&pci_apb_ioreadw,
	234	&pci_apb_ioreadl,
	235	};
	236
80b3ada7	237	/* The APB host has an IRQ line for each IRQ line of each slot. */
d2b59317	238	static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	239	{
80b3ada7 PB	240	return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
	241	}
	242
	243	static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
	244	{
	245	int bus_offset;
	246	if (pci_dev->devfn & 1)
	247	bus_offset = 16;
	248	else
	249	bus_offset = 0;
	250	return bus_offset + irq_num;
d2b59317 PB	251	}
d2b59317 PB	252
5d4e84c8	253	static void pci_apb_set_irq(void *opaque, int irq_num, int level)
d2b59317	254	{
5d4e84c8 JQ	255	qemu_irq *pic = opaque;
5d4e84c8 JQ	256
80b3ada7	257	/* PCI IRQ map onto the first 32 INO. */
d537cf6c	258	qemu_set_irq(pic[irq_num], level);
502a5395 PB	259	}
502a5395 PB	260
d6318738 MT	261	static void apb_pci_bridge_init(PCIBus *b)
	262	{
	263	PCIDevice *dev = pci_bridge_get_device(b);
	264
	265	/*
	266	* command register:
	267	* According to PCI bridge spec, after reset
	268	* bus master bit is off
	269	* memory space enable bit is off
	270	* According to manual (805-1251.pdf).
	271	* the reset value should be zero unless the boot pin is tied high
	272	* (which is true) and thus it should be PCI_COMMAND_MEMORY.
	273	*/
	274	pci_set_word(dev->config + PCI_COMMAND,
	275	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	276	dev->config[PCI_LATENCY_TIMER] = 0x10;
	277	dev->config[PCI_HEADER_TYPE] \|= PCI_HEADER_TYPE_MULTI_FUNCTION;
	278	}
	279
c227f099 AL	280	PCIBus *pci_apb_init(target_phys_addr_t special_base,
c227f099 AL	281	target_phys_addr_t mem_base,
c190ea07	282	qemu_irq pic, PCIBus bus2, PCIBus *bus3)
502a5395	283	{
72f44c8c BS	284	DeviceState *dev;
	285	SysBusDevice *s;
	286	APBState *d;
502a5395	287
80b3ada7	288	/* Ultrasparc PBM main bus */
72f44c8c	289	dev = qdev_create(NULL, "pbm");
e23a1b33	290	qdev_init_nofail(dev);
72f44c8c BS	291	s = sysbus_from_qdev(dev);
72f44c8c BS	292	/* apb_config */
bae7b517	293	sysbus_mmio_map(s, 0, special_base);
72f44c8c BS	294	/* pci_ioport */
72f44c8c BS	295	sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
204c7a39	296	/* pci_config */
72f44c8c BS	297	sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
72f44c8c BS	298	/* mem_data */
204c7a39	299	sysbus_mmio_map(s, 3, mem_base);
72f44c8c	300	d = FROM_SYSBUS(APBState, s);
c5ff6d54	301	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
72f44c8c BS	302	pci_apb_set_irq, pci_pbm_map_irq, pic,
72f44c8c BS	303	0, 32);
f6b6f1bc BS	304	pci_bus_set_mem_base(d->host_state.bus, mem_base);
f6b6f1bc BS	305
72f44c8c BS	306	pci_create_simple(d->host_state.bus, 0, "pbm");
72f44c8c BS	307	/* APB secondary busses */
2217dcff IY	308	*bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
	309	PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
	310	pci_apb_map_irq,
72f44c8c	311	"Advanced PCI Bus secondary bridge 1");
d6318738 MT	312	apb_pci_bridge_init(*bus2);
d6318738 MT	313
2217dcff IY	314	*bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
	315	PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
	316	pci_apb_map_irq,
72f44c8c	317	"Advanced PCI Bus secondary bridge 2");
d6318738	318	apb_pci_bridge_init(*bus3);
502a5395	319
72f44c8c BS	320	return d->host_state.bus;
	321	}
	322
81a322d4	323	static int pci_pbm_init_device(SysBusDevice *dev)
72f44c8c BS	324	{
	325
	326	APBState *s;
204c7a39	327	int pci_mem_data, apb_config, pci_ioport, pci_config;
72f44c8c BS	328
	329	s = FROM_SYSBUS(APBState, dev);
	330	/* apb_config */
1eed09cb	331	apb_config = cpu_register_io_memory(apb_config_read,
f930d07e	332	apb_config_write, s);
bae7b517	333	sysbus_init_mmio(dev, 0x10000ULL, apb_config);
72f44c8c	334	/* pci_ioport */
1eed09cb	335	pci_ioport = cpu_register_io_memory(pci_apb_ioread,
502a5395	336	pci_apb_iowrite, s);
72f44c8c	337	sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
5a5d4a76 BS	338	/* pci_config */
	339	pci_config = cpu_register_io_memory(apb_pci_config_reads,
	340	apb_pci_config_writes, s);
	341	sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
72f44c8c	342	/* mem_data */
f08b32fe	343	pci_mem_data = pci_host_data_register_mmio(&s->host_state);
72f44c8c	344	sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
81a322d4	345	return 0;
72f44c8c	346	}
502a5395	347
81a322d4	348	static int pbm_pci_host_init(PCIDevice *d)
72f44c8c	349	{
deb54399 AL	350	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
deb54399 AL	351	pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
502a5395 PB	352	d->config[0x04] = 0x06; // command = bus master, pci mem
	353	d->config[0x05] = 0x00;
	354	d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
	355	d->config[0x07] = 0x03; // status = medium devsel
	356	d->config[0x08] = 0x00; // revision
	357	d->config[0x09] = 0x00; // programming i/f
173a543b	358	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395	359	d->config[0x0D] = 0x10; // latency_timer
110c50fd	360	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
81a322d4	361	return 0;
72f44c8c	362	}
80b3ada7	363
72f44c8c BS	364	static PCIDeviceInfo pbm_pci_host_info = {
	365	.qdev.name = "pbm",
	366	.qdev.size = sizeof(PCIDevice),
	367	.init = pbm_pci_host_init,
	368	};
	369
	370	static void pbm_register_devices(void)
	371	{
	372	sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device);
	373	pci_qdev_register(&pbm_pci_host_info);
502a5395	374	}
72f44c8c BS	375
72f44c8c BS	376	device_init(pbm_register_devices)