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Commit | Line | Data |
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574bbf7b FB |
1 | /* |
2 | * APIC support | |
5fafdf24 | 3 | * |
574bbf7b FB |
4 | * Copyright (c) 2004-2005 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
574bbf7b | 18 | */ |
5d62c43a | 19 | #include "qemu-thread.h" |
dae01685 | 20 | #include "apic_internal.h" |
aa28b9bf | 21 | #include "apic.h" |
0280b571 | 22 | #include "ioapic.h" |
08a82ac0 | 23 | #include "msi.h" |
bb7e7293 | 24 | #include "host-utils.h" |
d8023f31 | 25 | #include "trace.h" |
d96e1737 | 26 | #include "pc.h" |
9886c23a | 27 | #include "apic-msidef.h" |
574bbf7b | 28 | |
d3e9db93 FB |
29 | #define MAX_APIC_WORDS 8 |
30 | ||
e5ad936b JK |
31 | #define SYNC_FROM_VAPIC 0x1 |
32 | #define SYNC_TO_VAPIC 0x2 | |
33 | #define SYNC_ISR_IRR_TO_VAPIC 0x4 | |
34 | ||
dae01685 | 35 | static APICCommonState *local_apics[MAX_APICS + 1]; |
73822ec8 | 36 | |
dae01685 JK |
37 | static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); |
38 | static void apic_update_irq(APICCommonState *s); | |
610626af AL |
39 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
40 | uint8_t dest, uint8_t dest_mode); | |
d592d303 | 41 | |
3b63c04e AJ |
42 | /* Find first bit starting from msb */ |
43 | static int fls_bit(uint32_t value) | |
44 | { | |
45 | return 31 - clz32(value); | |
46 | } | |
47 | ||
e95f5491 | 48 | /* Find first bit starting from lsb */ |
d3e9db93 FB |
49 | static int ffs_bit(uint32_t value) |
50 | { | |
bb7e7293 | 51 | return ctz32(value); |
d3e9db93 FB |
52 | } |
53 | ||
54 | static inline void set_bit(uint32_t *tab, int index) | |
55 | { | |
56 | int i, mask; | |
57 | i = index >> 5; | |
58 | mask = 1 << (index & 0x1f); | |
59 | tab[i] |= mask; | |
60 | } | |
61 | ||
62 | static inline void reset_bit(uint32_t *tab, int index) | |
63 | { | |
64 | int i, mask; | |
65 | i = index >> 5; | |
66 | mask = 1 << (index & 0x1f); | |
67 | tab[i] &= ~mask; | |
68 | } | |
69 | ||
73822ec8 AL |
70 | static inline int get_bit(uint32_t *tab, int index) |
71 | { | |
72 | int i, mask; | |
73 | i = index >> 5; | |
74 | mask = 1 << (index & 0x1f); | |
75 | return !!(tab[i] & mask); | |
76 | } | |
77 | ||
e5ad936b JK |
78 | /* return -1 if no bit is set */ |
79 | static int get_highest_priority_int(uint32_t *tab) | |
80 | { | |
81 | int i; | |
82 | for (i = 7; i >= 0; i--) { | |
83 | if (tab[i] != 0) { | |
84 | return i * 32 + fls_bit(tab[i]); | |
85 | } | |
86 | } | |
87 | return -1; | |
88 | } | |
89 | ||
90 | static void apic_sync_vapic(APICCommonState *s, int sync_type) | |
91 | { | |
92 | VAPICState vapic_state; | |
93 | size_t length; | |
94 | off_t start; | |
95 | int vector; | |
96 | ||
97 | if (!s->vapic_paddr) { | |
98 | return; | |
99 | } | |
100 | if (sync_type & SYNC_FROM_VAPIC) { | |
101 | cpu_physical_memory_rw(s->vapic_paddr, (void *)&vapic_state, | |
102 | sizeof(vapic_state), 0); | |
103 | s->tpr = vapic_state.tpr; | |
104 | } | |
105 | if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) { | |
106 | start = offsetof(VAPICState, isr); | |
107 | length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); | |
108 | ||
109 | if (sync_type & SYNC_TO_VAPIC) { | |
110 | assert(qemu_cpu_is_self(s->cpu_env)); | |
111 | ||
112 | vapic_state.tpr = s->tpr; | |
113 | vapic_state.enabled = 1; | |
114 | start = 0; | |
115 | length = sizeof(VAPICState); | |
116 | } | |
117 | ||
118 | vector = get_highest_priority_int(s->isr); | |
119 | if (vector < 0) { | |
120 | vector = 0; | |
121 | } | |
122 | vapic_state.isr = vector & 0xf0; | |
123 | ||
124 | vapic_state.zero = 0; | |
125 | ||
126 | vector = get_highest_priority_int(s->irr); | |
127 | if (vector < 0) { | |
128 | vector = 0; | |
129 | } | |
130 | vapic_state.irr = vector & 0xff; | |
131 | ||
132 | cpu_physical_memory_write_rom(s->vapic_paddr + start, | |
133 | ((void *)&vapic_state) + start, length); | |
134 | } | |
135 | } | |
136 | ||
137 | static void apic_vapic_base_update(APICCommonState *s) | |
138 | { | |
139 | apic_sync_vapic(s, SYNC_TO_VAPIC); | |
140 | } | |
141 | ||
dae01685 | 142 | static void apic_local_deliver(APICCommonState *s, int vector) |
a5b38b51 | 143 | { |
a5b38b51 AJ |
144 | uint32_t lvt = s->lvt[vector]; |
145 | int trigger_mode; | |
146 | ||
d8023f31 BS |
147 | trace_apic_local_deliver(vector, (lvt >> 8) & 7); |
148 | ||
a5b38b51 AJ |
149 | if (lvt & APIC_LVT_MASKED) |
150 | return; | |
151 | ||
152 | switch ((lvt >> 8) & 7) { | |
153 | case APIC_DM_SMI: | |
cf6d64bf | 154 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); |
a5b38b51 AJ |
155 | break; |
156 | ||
157 | case APIC_DM_NMI: | |
cf6d64bf | 158 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); |
a5b38b51 AJ |
159 | break; |
160 | ||
161 | case APIC_DM_EXTINT: | |
cf6d64bf | 162 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
a5b38b51 AJ |
163 | break; |
164 | ||
165 | case APIC_DM_FIXED: | |
166 | trigger_mode = APIC_TRIGGER_EDGE; | |
167 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && | |
168 | (lvt & APIC_LVT_LEVEL_TRIGGER)) | |
169 | trigger_mode = APIC_TRIGGER_LEVEL; | |
170 | apic_set_irq(s, lvt & 0xff, trigger_mode); | |
171 | } | |
172 | } | |
173 | ||
92a16d7a | 174 | void apic_deliver_pic_intr(DeviceState *d, int level) |
1a7de94a | 175 | { |
dae01685 | 176 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
92a16d7a | 177 | |
cf6d64bf BS |
178 | if (level) { |
179 | apic_local_deliver(s, APIC_LVT_LINT0); | |
180 | } else { | |
1a7de94a AJ |
181 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
182 | ||
183 | switch ((lvt >> 8) & 7) { | |
184 | case APIC_DM_FIXED: | |
185 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) | |
186 | break; | |
187 | reset_bit(s->irr, lvt & 0xff); | |
188 | /* fall through */ | |
189 | case APIC_DM_EXTINT: | |
cf6d64bf | 190 | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
1a7de94a AJ |
191 | break; |
192 | } | |
193 | } | |
194 | } | |
195 | ||
dae01685 | 196 | static void apic_external_nmi(APICCommonState *s) |
02c09195 | 197 | { |
02c09195 JK |
198 | apic_local_deliver(s, APIC_LVT_LINT1); |
199 | } | |
200 | ||
d3e9db93 FB |
201 | #define foreach_apic(apic, deliver_bitmask, code) \ |
202 | {\ | |
203 | int __i, __j, __mask;\ | |
204 | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ | |
205 | __mask = deliver_bitmask[__i];\ | |
206 | if (__mask) {\ | |
207 | for(__j = 0; __j < 32; __j++) {\ | |
208 | if (__mask & (1 << __j)) {\ | |
209 | apic = local_apics[__i * 32 + __j];\ | |
210 | if (apic) {\ | |
211 | code;\ | |
212 | }\ | |
213 | }\ | |
214 | }\ | |
215 | }\ | |
216 | }\ | |
217 | } | |
218 | ||
5fafdf24 | 219 | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
1f6f408c | 220 | uint8_t delivery_mode, uint8_t vector_num, |
d592d303 FB |
221 | uint8_t trigger_mode) |
222 | { | |
dae01685 | 223 | APICCommonState *apic_iter; |
d592d303 FB |
224 | |
225 | switch (delivery_mode) { | |
226 | case APIC_DM_LOWPRI: | |
8dd69b8f | 227 | /* XXX: search for focus processor, arbitration */ |
d3e9db93 FB |
228 | { |
229 | int i, d; | |
230 | d = -1; | |
231 | for(i = 0; i < MAX_APIC_WORDS; i++) { | |
232 | if (deliver_bitmask[i]) { | |
233 | d = i * 32 + ffs_bit(deliver_bitmask[i]); | |
234 | break; | |
235 | } | |
236 | } | |
237 | if (d >= 0) { | |
238 | apic_iter = local_apics[d]; | |
239 | if (apic_iter) { | |
240 | apic_set_irq(apic_iter, vector_num, trigger_mode); | |
241 | } | |
242 | } | |
8dd69b8f | 243 | } |
d3e9db93 | 244 | return; |
8dd69b8f | 245 | |
d592d303 | 246 | case APIC_DM_FIXED: |
d592d303 FB |
247 | break; |
248 | ||
249 | case APIC_DM_SMI: | |
e2eb9d3e AJ |
250 | foreach_apic(apic_iter, deliver_bitmask, |
251 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); | |
252 | return; | |
253 | ||
d592d303 | 254 | case APIC_DM_NMI: |
e2eb9d3e AJ |
255 | foreach_apic(apic_iter, deliver_bitmask, |
256 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); | |
257 | return; | |
d592d303 FB |
258 | |
259 | case APIC_DM_INIT: | |
260 | /* normal INIT IPI sent to processors */ | |
5fafdf24 | 261 | foreach_apic(apic_iter, deliver_bitmask, |
b09ea7d5 | 262 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
d592d303 | 263 | return; |
3b46e624 | 264 | |
d592d303 | 265 | case APIC_DM_EXTINT: |
b1fc0348 | 266 | /* handled in I/O APIC code */ |
d592d303 FB |
267 | break; |
268 | ||
269 | default: | |
270 | return; | |
271 | } | |
272 | ||
5fafdf24 | 273 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 274 | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
d592d303 | 275 | } |
574bbf7b | 276 | |
1f6f408c JK |
277 | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, |
278 | uint8_t vector_num, uint8_t trigger_mode) | |
610626af AL |
279 | { |
280 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; | |
281 | ||
d8023f31 | 282 | trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
1f6f408c | 283 | trigger_mode); |
d8023f31 | 284 | |
610626af | 285 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
1f6f408c | 286 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
610626af AL |
287 | } |
288 | ||
dae01685 | 289 | static void apic_set_base(APICCommonState *s, uint64_t val) |
574bbf7b | 290 | { |
5fafdf24 | 291 | s->apicbase = (val & 0xfffff000) | |
574bbf7b FB |
292 | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
293 | /* if disabled, cannot be enabled again */ | |
294 | if (!(val & MSR_IA32_APICBASE_ENABLE)) { | |
295 | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; | |
0e26b7b8 | 296 | cpu_clear_apic_feature(s->cpu_env); |
574bbf7b FB |
297 | s->spurious_vec &= ~APIC_SV_ENABLE; |
298 | } | |
299 | } | |
300 | ||
dae01685 | 301 | static void apic_set_tpr(APICCommonState *s, uint8_t val) |
574bbf7b | 302 | { |
e5ad936b JK |
303 | /* Updates from cr8 are ignored while the VAPIC is active */ |
304 | if (!s->vapic_paddr) { | |
305 | s->tpr = val << 4; | |
306 | apic_update_irq(s); | |
307 | } | |
9230e66e FB |
308 | } |
309 | ||
e5ad936b | 310 | static uint8_t apic_get_tpr(APICCommonState *s) |
d592d303 | 311 | { |
e5ad936b JK |
312 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
313 | return s->tpr >> 4; | |
d592d303 FB |
314 | } |
315 | ||
dae01685 | 316 | static int apic_get_ppr(APICCommonState *s) |
574bbf7b FB |
317 | { |
318 | int tpr, isrv, ppr; | |
319 | ||
320 | tpr = (s->tpr >> 4); | |
321 | isrv = get_highest_priority_int(s->isr); | |
322 | if (isrv < 0) | |
323 | isrv = 0; | |
324 | isrv >>= 4; | |
325 | if (tpr >= isrv) | |
326 | ppr = s->tpr; | |
327 | else | |
328 | ppr = isrv << 4; | |
329 | return ppr; | |
330 | } | |
331 | ||
dae01685 | 332 | static int apic_get_arb_pri(APICCommonState *s) |
d592d303 FB |
333 | { |
334 | /* XXX: arbitration */ | |
335 | return 0; | |
336 | } | |
337 | ||
0fbfbb59 GN |
338 | |
339 | /* | |
340 | * <0 - low prio interrupt, | |
341 | * 0 - no interrupt, | |
342 | * >0 - interrupt number | |
343 | */ | |
dae01685 | 344 | static int apic_irq_pending(APICCommonState *s) |
574bbf7b | 345 | { |
d592d303 | 346 | int irrv, ppr; |
574bbf7b | 347 | irrv = get_highest_priority_int(s->irr); |
0fbfbb59 GN |
348 | if (irrv < 0) { |
349 | return 0; | |
350 | } | |
d592d303 | 351 | ppr = apic_get_ppr(s); |
0fbfbb59 GN |
352 | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { |
353 | return -1; | |
354 | } | |
355 | ||
356 | return irrv; | |
357 | } | |
358 | ||
359 | /* signal the CPU if an irq is pending */ | |
dae01685 | 360 | static void apic_update_irq(APICCommonState *s) |
0fbfbb59 GN |
361 | { |
362 | if (!(s->spurious_vec & APIC_SV_ENABLE)) { | |
574bbf7b | 363 | return; |
0fbfbb59 | 364 | } |
5d62c43a JK |
365 | if (!qemu_cpu_is_self(s->cpu_env)) { |
366 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_POLL); | |
367 | } else if (apic_irq_pending(s) > 0) { | |
0fbfbb59 GN |
368 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
369 | } | |
574bbf7b FB |
370 | } |
371 | ||
e5ad936b JK |
372 | void apic_poll_irq(DeviceState *d) |
373 | { | |
374 | APICCommonState *s = APIC_COMMON(d); | |
375 | ||
376 | apic_sync_vapic(s, SYNC_FROM_VAPIC); | |
377 | apic_update_irq(s); | |
378 | } | |
379 | ||
dae01685 | 380 | static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) |
574bbf7b | 381 | { |
343270ea | 382 | apic_report_irq_delivered(!get_bit(s->irr, vector_num)); |
73822ec8 | 383 | |
574bbf7b FB |
384 | set_bit(s->irr, vector_num); |
385 | if (trigger_mode) | |
386 | set_bit(s->tmr, vector_num); | |
387 | else | |
388 | reset_bit(s->tmr, vector_num); | |
e5ad936b JK |
389 | if (s->vapic_paddr) { |
390 | apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); | |
391 | /* | |
392 | * The vcpu thread needs to see the new IRR before we pull its current | |
393 | * TPR value. That way, if we miss a lowering of the TRP, the guest | |
394 | * has the chance to notice the new IRR and poll for IRQs on its own. | |
395 | */ | |
396 | smp_wmb(); | |
397 | apic_sync_vapic(s, SYNC_FROM_VAPIC); | |
398 | } | |
574bbf7b FB |
399 | apic_update_irq(s); |
400 | } | |
401 | ||
dae01685 | 402 | static void apic_eoi(APICCommonState *s) |
574bbf7b FB |
403 | { |
404 | int isrv; | |
405 | isrv = get_highest_priority_int(s->isr); | |
406 | if (isrv < 0) | |
407 | return; | |
408 | reset_bit(s->isr, isrv); | |
0280b571 JK |
409 | if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) { |
410 | ioapic_eoi_broadcast(isrv); | |
411 | } | |
e5ad936b | 412 | apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); |
574bbf7b FB |
413 | apic_update_irq(s); |
414 | } | |
415 | ||
678e12cc GN |
416 | static int apic_find_dest(uint8_t dest) |
417 | { | |
dae01685 | 418 | APICCommonState *apic = local_apics[dest]; |
678e12cc GN |
419 | int i; |
420 | ||
421 | if (apic && apic->id == dest) | |
422 | return dest; /* shortcut in case apic->id == apic->idx */ | |
423 | ||
424 | for (i = 0; i < MAX_APICS; i++) { | |
425 | apic = local_apics[i]; | |
426 | if (apic && apic->id == dest) | |
427 | return i; | |
b538e53e AW |
428 | if (!apic) |
429 | break; | |
678e12cc GN |
430 | } |
431 | ||
432 | return -1; | |
433 | } | |
434 | ||
d3e9db93 FB |
435 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
436 | uint8_t dest, uint8_t dest_mode) | |
d592d303 | 437 | { |
dae01685 | 438 | APICCommonState *apic_iter; |
d3e9db93 | 439 | int i; |
d592d303 FB |
440 | |
441 | if (dest_mode == 0) { | |
d3e9db93 FB |
442 | if (dest == 0xff) { |
443 | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); | |
444 | } else { | |
678e12cc | 445 | int idx = apic_find_dest(dest); |
d3e9db93 | 446 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
678e12cc GN |
447 | if (idx >= 0) |
448 | set_bit(deliver_bitmask, idx); | |
d3e9db93 | 449 | } |
d592d303 FB |
450 | } else { |
451 | /* XXX: cluster mode */ | |
d3e9db93 FB |
452 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
453 | for(i = 0; i < MAX_APICS; i++) { | |
454 | apic_iter = local_apics[i]; | |
455 | if (apic_iter) { | |
456 | if (apic_iter->dest_mode == 0xf) { | |
457 | if (dest & apic_iter->log_dest) | |
458 | set_bit(deliver_bitmask, i); | |
459 | } else if (apic_iter->dest_mode == 0x0) { | |
460 | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && | |
461 | (dest & apic_iter->log_dest & 0x0f)) { | |
462 | set_bit(deliver_bitmask, i); | |
463 | } | |
464 | } | |
b538e53e AW |
465 | } else { |
466 | break; | |
d3e9db93 | 467 | } |
d592d303 FB |
468 | } |
469 | } | |
d592d303 FB |
470 | } |
471 | ||
dae01685 | 472 | static void apic_startup(APICCommonState *s, int vector_num) |
e0fd8781 | 473 | { |
b09ea7d5 GN |
474 | s->sipi_vector = vector_num; |
475 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); | |
476 | } | |
477 | ||
92a16d7a | 478 | void apic_sipi(DeviceState *d) |
b09ea7d5 | 479 | { |
dae01685 | 480 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
92a16d7a | 481 | |
4a942cea | 482 | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
b09ea7d5 GN |
483 | |
484 | if (!s->wait_for_sipi) | |
e0fd8781 | 485 | return; |
0e26b7b8 | 486 | cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); |
b09ea7d5 | 487 | s->wait_for_sipi = 0; |
e0fd8781 FB |
488 | } |
489 | ||
92a16d7a | 490 | static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, |
d592d303 | 491 | uint8_t delivery_mode, uint8_t vector_num, |
1f6f408c | 492 | uint8_t trigger_mode) |
d592d303 | 493 | { |
dae01685 | 494 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
d3e9db93 | 495 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
d592d303 | 496 | int dest_shorthand = (s->icr[0] >> 18) & 3; |
dae01685 | 497 | APICCommonState *apic_iter; |
d592d303 | 498 | |
e0fd8781 | 499 | switch (dest_shorthand) { |
d3e9db93 FB |
500 | case 0: |
501 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); | |
502 | break; | |
503 | case 1: | |
504 | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); | |
678e12cc | 505 | set_bit(deliver_bitmask, s->idx); |
d3e9db93 FB |
506 | break; |
507 | case 2: | |
508 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
509 | break; | |
510 | case 3: | |
511 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
678e12cc | 512 | reset_bit(deliver_bitmask, s->idx); |
d3e9db93 | 513 | break; |
e0fd8781 FB |
514 | } |
515 | ||
d592d303 | 516 | switch (delivery_mode) { |
d592d303 FB |
517 | case APIC_DM_INIT: |
518 | { | |
519 | int trig_mode = (s->icr[0] >> 15) & 1; | |
520 | int level = (s->icr[0] >> 14) & 1; | |
521 | if (level == 0 && trig_mode == 1) { | |
5fafdf24 | 522 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 523 | apic_iter->arb_id = apic_iter->id ); |
d592d303 FB |
524 | return; |
525 | } | |
526 | } | |
527 | break; | |
528 | ||
529 | case APIC_DM_SIPI: | |
5fafdf24 | 530 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 531 | apic_startup(apic_iter, vector_num) ); |
d592d303 FB |
532 | return; |
533 | } | |
534 | ||
1f6f408c | 535 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
d592d303 FB |
536 | } |
537 | ||
a94820dd JK |
538 | static bool apic_check_pic(APICCommonState *s) |
539 | { | |
540 | if (!apic_accept_pic_intr(&s->busdev.qdev) || !pic_get_output(isa_pic)) { | |
541 | return false; | |
542 | } | |
543 | apic_deliver_pic_intr(&s->busdev.qdev, 1); | |
544 | return true; | |
545 | } | |
546 | ||
92a16d7a | 547 | int apic_get_interrupt(DeviceState *d) |
574bbf7b | 548 | { |
dae01685 | 549 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
574bbf7b FB |
550 | int intno; |
551 | ||
552 | /* if the APIC is installed or enabled, we let the 8259 handle the | |
553 | IRQs */ | |
554 | if (!s) | |
555 | return -1; | |
556 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
557 | return -1; | |
3b46e624 | 558 | |
e5ad936b | 559 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
0fbfbb59 GN |
560 | intno = apic_irq_pending(s); |
561 | ||
562 | if (intno == 0) { | |
e5ad936b | 563 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
574bbf7b | 564 | return -1; |
0fbfbb59 | 565 | } else if (intno < 0) { |
e5ad936b | 566 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
d592d303 | 567 | return s->spurious_vec & 0xff; |
0fbfbb59 | 568 | } |
b4511723 | 569 | reset_bit(s->irr, intno); |
574bbf7b | 570 | set_bit(s->isr, intno); |
e5ad936b | 571 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
3db3659b JK |
572 | |
573 | /* re-inject if there is still a pending PIC interrupt */ | |
a94820dd | 574 | apic_check_pic(s); |
3db3659b | 575 | |
574bbf7b | 576 | apic_update_irq(s); |
3db3659b | 577 | |
574bbf7b FB |
578 | return intno; |
579 | } | |
580 | ||
92a16d7a | 581 | int apic_accept_pic_intr(DeviceState *d) |
0e21e12b | 582 | { |
dae01685 | 583 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
0e21e12b TS |
584 | uint32_t lvt0; |
585 | ||
586 | if (!s) | |
587 | return -1; | |
588 | ||
589 | lvt0 = s->lvt[APIC_LVT_LINT0]; | |
590 | ||
a5b38b51 AJ |
591 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
592 | (lvt0 & APIC_LVT_MASKED) == 0) | |
0e21e12b TS |
593 | return 1; |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
dae01685 | 598 | static uint32_t apic_get_current_count(APICCommonState *s) |
574bbf7b FB |
599 | { |
600 | int64_t d; | |
601 | uint32_t val; | |
74475455 | 602 | d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >> |
574bbf7b FB |
603 | s->count_shift; |
604 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
605 | /* periodic */ | |
d592d303 | 606 | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); |
574bbf7b FB |
607 | } else { |
608 | if (d >= s->initial_count) | |
609 | val = 0; | |
610 | else | |
611 | val = s->initial_count - d; | |
612 | } | |
613 | return val; | |
614 | } | |
615 | ||
dae01685 | 616 | static void apic_timer_update(APICCommonState *s, int64_t current_time) |
574bbf7b | 617 | { |
7a380ca3 JK |
618 | if (apic_next_timer(s, current_time)) { |
619 | qemu_mod_timer(s->timer, s->next_time); | |
574bbf7b | 620 | } else { |
574bbf7b FB |
621 | qemu_del_timer(s->timer); |
622 | } | |
623 | } | |
624 | ||
625 | static void apic_timer(void *opaque) | |
626 | { | |
dae01685 | 627 | APICCommonState *s = opaque; |
574bbf7b | 628 | |
cf6d64bf | 629 | apic_local_deliver(s, APIC_LVT_TIMER); |
574bbf7b FB |
630 | apic_timer_update(s, s->next_time); |
631 | } | |
632 | ||
c227f099 | 633 | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
634 | { |
635 | return 0; | |
636 | } | |
637 | ||
c227f099 | 638 | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
639 | { |
640 | return 0; | |
641 | } | |
642 | ||
c227f099 | 643 | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
644 | { |
645 | } | |
646 | ||
c227f099 | 647 | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
648 | { |
649 | } | |
650 | ||
c227f099 | 651 | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
574bbf7b | 652 | { |
92a16d7a | 653 | DeviceState *d; |
dae01685 | 654 | APICCommonState *s; |
574bbf7b FB |
655 | uint32_t val; |
656 | int index; | |
657 | ||
92a16d7a BS |
658 | d = cpu_get_current_apic(); |
659 | if (!d) { | |
574bbf7b | 660 | return 0; |
0e26b7b8 | 661 | } |
dae01685 | 662 | s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
574bbf7b FB |
663 | |
664 | index = (addr >> 4) & 0xff; | |
665 | switch(index) { | |
666 | case 0x02: /* id */ | |
667 | val = s->id << 24; | |
668 | break; | |
669 | case 0x03: /* version */ | |
670 | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ | |
671 | break; | |
672 | case 0x08: | |
e5ad936b JK |
673 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
674 | if (apic_report_tpr_access) { | |
675 | cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ); | |
676 | } | |
574bbf7b FB |
677 | val = s->tpr; |
678 | break; | |
d592d303 FB |
679 | case 0x09: |
680 | val = apic_get_arb_pri(s); | |
681 | break; | |
574bbf7b FB |
682 | case 0x0a: |
683 | /* ppr */ | |
684 | val = apic_get_ppr(s); | |
685 | break; | |
b237db36 AJ |
686 | case 0x0b: |
687 | val = 0; | |
688 | break; | |
d592d303 FB |
689 | case 0x0d: |
690 | val = s->log_dest << 24; | |
691 | break; | |
692 | case 0x0e: | |
693 | val = s->dest_mode << 28; | |
694 | break; | |
574bbf7b FB |
695 | case 0x0f: |
696 | val = s->spurious_vec; | |
697 | break; | |
698 | case 0x10 ... 0x17: | |
699 | val = s->isr[index & 7]; | |
700 | break; | |
701 | case 0x18 ... 0x1f: | |
702 | val = s->tmr[index & 7]; | |
703 | break; | |
704 | case 0x20 ... 0x27: | |
705 | val = s->irr[index & 7]; | |
706 | break; | |
707 | case 0x28: | |
708 | val = s->esr; | |
709 | break; | |
574bbf7b FB |
710 | case 0x30: |
711 | case 0x31: | |
712 | val = s->icr[index & 1]; | |
713 | break; | |
e0fd8781 FB |
714 | case 0x32 ... 0x37: |
715 | val = s->lvt[index - 0x32]; | |
716 | break; | |
574bbf7b FB |
717 | case 0x38: |
718 | val = s->initial_count; | |
719 | break; | |
720 | case 0x39: | |
721 | val = apic_get_current_count(s); | |
722 | break; | |
723 | case 0x3e: | |
724 | val = s->divide_conf; | |
725 | break; | |
726 | default: | |
727 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
728 | val = 0; | |
729 | break; | |
730 | } | |
d8023f31 | 731 | trace_apic_mem_readl(addr, val); |
574bbf7b FB |
732 | return val; |
733 | } | |
734 | ||
f5095c63 | 735 | static void apic_send_msi(target_phys_addr_t addr, uint32_t data) |
54c96da7 MT |
736 | { |
737 | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; | |
738 | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
739 | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; | |
740 | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; | |
741 | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; | |
742 | /* XXX: Ignore redirection hint. */ | |
1f6f408c | 743 | apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); |
54c96da7 MT |
744 | } |
745 | ||
c227f099 | 746 | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b | 747 | { |
92a16d7a | 748 | DeviceState *d; |
dae01685 | 749 | APICCommonState *s; |
54c96da7 MT |
750 | int index = (addr >> 4) & 0xff; |
751 | if (addr > 0xfff || !index) { | |
752 | /* MSI and MMIO APIC are at the same memory location, | |
753 | * but actually not on the global bus: MSI is on PCI bus | |
754 | * APIC is connected directly to the CPU. | |
755 | * Mapping them on the global bus happens to work because | |
756 | * MSI registers are reserved in APIC MMIO and vice versa. */ | |
757 | apic_send_msi(addr, val); | |
758 | return; | |
759 | } | |
574bbf7b | 760 | |
92a16d7a BS |
761 | d = cpu_get_current_apic(); |
762 | if (!d) { | |
574bbf7b | 763 | return; |
0e26b7b8 | 764 | } |
dae01685 | 765 | s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
574bbf7b | 766 | |
d8023f31 | 767 | trace_apic_mem_writel(addr, val); |
574bbf7b | 768 | |
574bbf7b FB |
769 | switch(index) { |
770 | case 0x02: | |
771 | s->id = (val >> 24); | |
772 | break; | |
e0fd8781 FB |
773 | case 0x03: |
774 | break; | |
574bbf7b | 775 | case 0x08: |
e5ad936b JK |
776 | if (apic_report_tpr_access) { |
777 | cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE); | |
778 | } | |
574bbf7b | 779 | s->tpr = val; |
e5ad936b | 780 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
d592d303 | 781 | apic_update_irq(s); |
574bbf7b | 782 | break; |
e0fd8781 FB |
783 | case 0x09: |
784 | case 0x0a: | |
785 | break; | |
574bbf7b FB |
786 | case 0x0b: /* EOI */ |
787 | apic_eoi(s); | |
788 | break; | |
d592d303 FB |
789 | case 0x0d: |
790 | s->log_dest = val >> 24; | |
791 | break; | |
792 | case 0x0e: | |
793 | s->dest_mode = val >> 28; | |
794 | break; | |
574bbf7b FB |
795 | case 0x0f: |
796 | s->spurious_vec = val & 0x1ff; | |
d592d303 | 797 | apic_update_irq(s); |
574bbf7b | 798 | break; |
e0fd8781 FB |
799 | case 0x10 ... 0x17: |
800 | case 0x18 ... 0x1f: | |
801 | case 0x20 ... 0x27: | |
802 | case 0x28: | |
803 | break; | |
574bbf7b | 804 | case 0x30: |
d592d303 | 805 | s->icr[0] = val; |
92a16d7a | 806 | apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
d592d303 | 807 | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
1f6f408c | 808 | (s->icr[0] >> 15) & 1); |
d592d303 | 809 | break; |
574bbf7b | 810 | case 0x31: |
d592d303 | 811 | s->icr[1] = val; |
574bbf7b FB |
812 | break; |
813 | case 0x32 ... 0x37: | |
814 | { | |
815 | int n = index - 0x32; | |
816 | s->lvt[n] = val; | |
a94820dd | 817 | if (n == APIC_LVT_TIMER) { |
74475455 | 818 | apic_timer_update(s, qemu_get_clock_ns(vm_clock)); |
a94820dd JK |
819 | } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) { |
820 | apic_update_irq(s); | |
821 | } | |
574bbf7b FB |
822 | } |
823 | break; | |
824 | case 0x38: | |
825 | s->initial_count = val; | |
74475455 | 826 | s->initial_count_load_time = qemu_get_clock_ns(vm_clock); |
574bbf7b FB |
827 | apic_timer_update(s, s->initial_count_load_time); |
828 | break; | |
e0fd8781 FB |
829 | case 0x39: |
830 | break; | |
574bbf7b FB |
831 | case 0x3e: |
832 | { | |
833 | int v; | |
834 | s->divide_conf = val & 0xb; | |
835 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); | |
836 | s->count_shift = (v + 1) & 7; | |
837 | } | |
838 | break; | |
839 | default: | |
840 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
841 | break; | |
842 | } | |
843 | } | |
844 | ||
e5ad936b JK |
845 | static void apic_pre_save(APICCommonState *s) |
846 | { | |
847 | apic_sync_vapic(s, SYNC_FROM_VAPIC); | |
848 | } | |
849 | ||
7a380ca3 JK |
850 | static void apic_post_load(APICCommonState *s) |
851 | { | |
852 | if (s->timer_expiry != -1) { | |
853 | qemu_mod_timer(s->timer, s->timer_expiry); | |
854 | } else { | |
855 | qemu_del_timer(s->timer); | |
856 | } | |
857 | } | |
858 | ||
312b4234 AK |
859 | static const MemoryRegionOps apic_io_ops = { |
860 | .old_mmio = { | |
861 | .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, | |
862 | .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, | |
863 | }, | |
864 | .endianness = DEVICE_NATIVE_ENDIAN, | |
574bbf7b FB |
865 | }; |
866 | ||
dae01685 | 867 | static void apic_init(APICCommonState *s) |
8546b099 | 868 | { |
dae01685 JK |
869 | memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic-msi", |
870 | MSI_SPACE_SIZE); | |
8546b099 | 871 | |
74475455 | 872 | s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); |
8546b099 | 873 | local_apics[s->idx] = s; |
08a82ac0 JK |
874 | |
875 | msi_supported = true; | |
8546b099 BS |
876 | } |
877 | ||
999e12bb AL |
878 | static void apic_class_init(ObjectClass *klass, void *data) |
879 | { | |
880 | APICCommonClass *k = APIC_COMMON_CLASS(klass); | |
881 | ||
882 | k->init = apic_init; | |
883 | k->set_base = apic_set_base; | |
884 | k->set_tpr = apic_set_tpr; | |
e5ad936b JK |
885 | k->get_tpr = apic_get_tpr; |
886 | k->vapic_base_update = apic_vapic_base_update; | |
999e12bb | 887 | k->external_nmi = apic_external_nmi; |
e5ad936b | 888 | k->pre_save = apic_pre_save; |
999e12bb AL |
889 | k->post_load = apic_post_load; |
890 | } | |
891 | ||
39bffca2 AL |
892 | static TypeInfo apic_info = { |
893 | .name = "apic", | |
894 | .instance_size = sizeof(APICCommonState), | |
895 | .parent = TYPE_APIC_COMMON, | |
896 | .class_init = apic_class_init, | |
8546b099 BS |
897 | }; |
898 | ||
83f7d43a | 899 | static void apic_register_types(void) |
8546b099 | 900 | { |
39bffca2 | 901 | type_register_static(&apic_info); |
8546b099 BS |
902 | } |
903 | ||
83f7d43a | 904 | type_init(apic_register_types) |