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Commit | Line | Data |
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574bbf7b FB |
1 | /* |
2 | * APIC support | |
5fafdf24 | 3 | * |
574bbf7b FB |
4 | * Copyright (c) 2004-2005 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
574bbf7b | 18 | */ |
87ecb68b | 19 | #include "hw.h" |
aa28b9bf | 20 | #include "apic.h" |
87ecb68b | 21 | #include "qemu-timer.h" |
bb7e7293 | 22 | #include "host-utils.h" |
8546b099 | 23 | #include "sysbus.h" |
574bbf7b FB |
24 | |
25 | //#define DEBUG_APIC | |
0a3c5921 BS |
26 | //#define DEBUG_COALESCING |
27 | ||
28 | #ifdef DEBUG_APIC | |
29 | #define DPRINTF(fmt, ...) \ | |
30 | do { printf("apic: " fmt , ## __VA_ARGS__); } while (0) | |
31 | #else | |
32 | #define DPRINTF(fmt, ...) | |
33 | #endif | |
34 | ||
35 | #ifdef DEBUG_COALESCING | |
36 | #define DPRINTF_C(fmt, ...) \ | |
37 | do { printf("apic: " fmt , ## __VA_ARGS__); } while (0) | |
38 | #else | |
39 | #define DPRINTF_C(fmt, ...) | |
40 | #endif | |
574bbf7b FB |
41 | |
42 | /* APIC Local Vector Table */ | |
43 | #define APIC_LVT_TIMER 0 | |
44 | #define APIC_LVT_THERMAL 1 | |
45 | #define APIC_LVT_PERFORM 2 | |
46 | #define APIC_LVT_LINT0 3 | |
47 | #define APIC_LVT_LINT1 4 | |
48 | #define APIC_LVT_ERROR 5 | |
49 | #define APIC_LVT_NB 6 | |
50 | ||
51 | /* APIC delivery modes */ | |
52 | #define APIC_DM_FIXED 0 | |
53 | #define APIC_DM_LOWPRI 1 | |
54 | #define APIC_DM_SMI 2 | |
55 | #define APIC_DM_NMI 4 | |
56 | #define APIC_DM_INIT 5 | |
57 | #define APIC_DM_SIPI 6 | |
58 | #define APIC_DM_EXTINT 7 | |
59 | ||
d592d303 FB |
60 | /* APIC destination mode */ |
61 | #define APIC_DESTMODE_FLAT 0xf | |
62 | #define APIC_DESTMODE_CLUSTER 1 | |
63 | ||
574bbf7b FB |
64 | #define APIC_TRIGGER_EDGE 0 |
65 | #define APIC_TRIGGER_LEVEL 1 | |
66 | ||
67 | #define APIC_LVT_TIMER_PERIODIC (1<<17) | |
68 | #define APIC_LVT_MASKED (1<<16) | |
69 | #define APIC_LVT_LEVEL_TRIGGER (1<<15) | |
70 | #define APIC_LVT_REMOTE_IRR (1<<14) | |
71 | #define APIC_INPUT_POLARITY (1<<13) | |
72 | #define APIC_SEND_PENDING (1<<12) | |
73 | ||
74 | #define ESR_ILLEGAL_ADDRESS (1 << 7) | |
75 | ||
76 | #define APIC_SV_ENABLE (1 << 8) | |
77 | ||
d3e9db93 FB |
78 | #define MAX_APICS 255 |
79 | #define MAX_APIC_WORDS 8 | |
80 | ||
54c96da7 MT |
81 | /* Intel APIC constants: from include/asm/msidef.h */ |
82 | #define MSI_DATA_VECTOR_SHIFT 0 | |
83 | #define MSI_DATA_VECTOR_MASK 0x000000ff | |
84 | #define MSI_DATA_DELIVERY_MODE_SHIFT 8 | |
85 | #define MSI_DATA_TRIGGER_SHIFT 15 | |
86 | #define MSI_DATA_LEVEL_SHIFT 14 | |
87 | #define MSI_ADDR_DEST_MODE_SHIFT 2 | |
88 | #define MSI_ADDR_DEST_ID_SHIFT 12 | |
89 | #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 | |
90 | ||
54c96da7 MT |
91 | #define MSI_ADDR_SIZE 0x100000 |
92 | ||
92a16d7a BS |
93 | typedef struct APICState APICState; |
94 | ||
cf6d64bf | 95 | struct APICState { |
8546b099 BS |
96 | SysBusDevice busdev; |
97 | void *cpu_env; | |
574bbf7b FB |
98 | uint32_t apicbase; |
99 | uint8_t id; | |
d592d303 | 100 | uint8_t arb_id; |
574bbf7b FB |
101 | uint8_t tpr; |
102 | uint32_t spurious_vec; | |
d592d303 FB |
103 | uint8_t log_dest; |
104 | uint8_t dest_mode; | |
574bbf7b FB |
105 | uint32_t isr[8]; /* in service register */ |
106 | uint32_t tmr[8]; /* trigger mode register */ | |
107 | uint32_t irr[8]; /* interrupt request register */ | |
108 | uint32_t lvt[APIC_LVT_NB]; | |
109 | uint32_t esr; /* error register */ | |
110 | uint32_t icr[2]; | |
111 | ||
112 | uint32_t divide_conf; | |
113 | int count_shift; | |
114 | uint32_t initial_count; | |
115 | int64_t initial_count_load_time, next_time; | |
678e12cc | 116 | uint32_t idx; |
574bbf7b | 117 | QEMUTimer *timer; |
b09ea7d5 GN |
118 | int sipi_vector; |
119 | int wait_for_sipi; | |
cf6d64bf | 120 | }; |
574bbf7b | 121 | |
d3e9db93 | 122 | static APICState *local_apics[MAX_APICS + 1]; |
73822ec8 AL |
123 | static int apic_irq_delivered; |
124 | ||
d592d303 FB |
125 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
126 | static void apic_update_irq(APICState *s); | |
610626af AL |
127 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
128 | uint8_t dest, uint8_t dest_mode); | |
d592d303 | 129 | |
3b63c04e AJ |
130 | /* Find first bit starting from msb */ |
131 | static int fls_bit(uint32_t value) | |
132 | { | |
133 | return 31 - clz32(value); | |
134 | } | |
135 | ||
e95f5491 | 136 | /* Find first bit starting from lsb */ |
d3e9db93 FB |
137 | static int ffs_bit(uint32_t value) |
138 | { | |
bb7e7293 | 139 | return ctz32(value); |
d3e9db93 FB |
140 | } |
141 | ||
142 | static inline void set_bit(uint32_t *tab, int index) | |
143 | { | |
144 | int i, mask; | |
145 | i = index >> 5; | |
146 | mask = 1 << (index & 0x1f); | |
147 | tab[i] |= mask; | |
148 | } | |
149 | ||
150 | static inline void reset_bit(uint32_t *tab, int index) | |
151 | { | |
152 | int i, mask; | |
153 | i = index >> 5; | |
154 | mask = 1 << (index & 0x1f); | |
155 | tab[i] &= ~mask; | |
156 | } | |
157 | ||
73822ec8 AL |
158 | static inline int get_bit(uint32_t *tab, int index) |
159 | { | |
160 | int i, mask; | |
161 | i = index >> 5; | |
162 | mask = 1 << (index & 0x1f); | |
163 | return !!(tab[i] & mask); | |
164 | } | |
165 | ||
cf6d64bf | 166 | static void apic_local_deliver(APICState *s, int vector) |
a5b38b51 | 167 | { |
a5b38b51 AJ |
168 | uint32_t lvt = s->lvt[vector]; |
169 | int trigger_mode; | |
170 | ||
0a3c5921 BS |
171 | DPRINTF("%s: vector %d delivery mode %d\n", __func__, vector, |
172 | (lvt >> 8) & 7); | |
a5b38b51 AJ |
173 | if (lvt & APIC_LVT_MASKED) |
174 | return; | |
175 | ||
176 | switch ((lvt >> 8) & 7) { | |
177 | case APIC_DM_SMI: | |
cf6d64bf | 178 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); |
a5b38b51 AJ |
179 | break; |
180 | ||
181 | case APIC_DM_NMI: | |
cf6d64bf | 182 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); |
a5b38b51 AJ |
183 | break; |
184 | ||
185 | case APIC_DM_EXTINT: | |
cf6d64bf | 186 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
a5b38b51 AJ |
187 | break; |
188 | ||
189 | case APIC_DM_FIXED: | |
190 | trigger_mode = APIC_TRIGGER_EDGE; | |
191 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && | |
192 | (lvt & APIC_LVT_LEVEL_TRIGGER)) | |
193 | trigger_mode = APIC_TRIGGER_LEVEL; | |
194 | apic_set_irq(s, lvt & 0xff, trigger_mode); | |
195 | } | |
196 | } | |
197 | ||
92a16d7a | 198 | void apic_deliver_pic_intr(DeviceState *d, int level) |
1a7de94a | 199 | { |
92a16d7a BS |
200 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
201 | ||
cf6d64bf BS |
202 | if (level) { |
203 | apic_local_deliver(s, APIC_LVT_LINT0); | |
204 | } else { | |
1a7de94a AJ |
205 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
206 | ||
207 | switch ((lvt >> 8) & 7) { | |
208 | case APIC_DM_FIXED: | |
209 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) | |
210 | break; | |
211 | reset_bit(s->irr, lvt & 0xff); | |
212 | /* fall through */ | |
213 | case APIC_DM_EXTINT: | |
cf6d64bf | 214 | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
1a7de94a AJ |
215 | break; |
216 | } | |
217 | } | |
218 | } | |
219 | ||
d3e9db93 FB |
220 | #define foreach_apic(apic, deliver_bitmask, code) \ |
221 | {\ | |
222 | int __i, __j, __mask;\ | |
223 | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ | |
224 | __mask = deliver_bitmask[__i];\ | |
225 | if (__mask) {\ | |
226 | for(__j = 0; __j < 32; __j++) {\ | |
227 | if (__mask & (1 << __j)) {\ | |
228 | apic = local_apics[__i * 32 + __j];\ | |
229 | if (apic) {\ | |
230 | code;\ | |
231 | }\ | |
232 | }\ | |
233 | }\ | |
234 | }\ | |
235 | }\ | |
236 | } | |
237 | ||
5fafdf24 | 238 | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
d3e9db93 | 239 | uint8_t delivery_mode, |
d592d303 FB |
240 | uint8_t vector_num, uint8_t polarity, |
241 | uint8_t trigger_mode) | |
242 | { | |
243 | APICState *apic_iter; | |
244 | ||
245 | switch (delivery_mode) { | |
246 | case APIC_DM_LOWPRI: | |
8dd69b8f | 247 | /* XXX: search for focus processor, arbitration */ |
d3e9db93 FB |
248 | { |
249 | int i, d; | |
250 | d = -1; | |
251 | for(i = 0; i < MAX_APIC_WORDS; i++) { | |
252 | if (deliver_bitmask[i]) { | |
253 | d = i * 32 + ffs_bit(deliver_bitmask[i]); | |
254 | break; | |
255 | } | |
256 | } | |
257 | if (d >= 0) { | |
258 | apic_iter = local_apics[d]; | |
259 | if (apic_iter) { | |
260 | apic_set_irq(apic_iter, vector_num, trigger_mode); | |
261 | } | |
262 | } | |
8dd69b8f | 263 | } |
d3e9db93 | 264 | return; |
8dd69b8f | 265 | |
d592d303 | 266 | case APIC_DM_FIXED: |
d592d303 FB |
267 | break; |
268 | ||
269 | case APIC_DM_SMI: | |
e2eb9d3e AJ |
270 | foreach_apic(apic_iter, deliver_bitmask, |
271 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); | |
272 | return; | |
273 | ||
d592d303 | 274 | case APIC_DM_NMI: |
e2eb9d3e AJ |
275 | foreach_apic(apic_iter, deliver_bitmask, |
276 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); | |
277 | return; | |
d592d303 FB |
278 | |
279 | case APIC_DM_INIT: | |
280 | /* normal INIT IPI sent to processors */ | |
5fafdf24 | 281 | foreach_apic(apic_iter, deliver_bitmask, |
b09ea7d5 | 282 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
d592d303 | 283 | return; |
3b46e624 | 284 | |
d592d303 | 285 | case APIC_DM_EXTINT: |
b1fc0348 | 286 | /* handled in I/O APIC code */ |
d592d303 FB |
287 | break; |
288 | ||
289 | default: | |
290 | return; | |
291 | } | |
292 | ||
5fafdf24 | 293 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 294 | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
d592d303 | 295 | } |
574bbf7b | 296 | |
610626af AL |
297 | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, |
298 | uint8_t delivery_mode, uint8_t vector_num, | |
299 | uint8_t polarity, uint8_t trigger_mode) | |
300 | { | |
301 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; | |
302 | ||
0a3c5921 BS |
303 | DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d" |
304 | " polarity %d trigger_mode %d\n", __func__, dest, dest_mode, | |
305 | delivery_mode, vector_num, polarity, trigger_mode); | |
610626af AL |
306 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
307 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, | |
308 | trigger_mode); | |
309 | } | |
310 | ||
92a16d7a | 311 | void cpu_set_apic_base(DeviceState *d, uint64_t val) |
574bbf7b | 312 | { |
92a16d7a BS |
313 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
314 | ||
0a3c5921 | 315 | DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val); |
2c7c13d4 AJ |
316 | if (!s) |
317 | return; | |
5fafdf24 | 318 | s->apicbase = (val & 0xfffff000) | |
574bbf7b FB |
319 | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
320 | /* if disabled, cannot be enabled again */ | |
321 | if (!(val & MSR_IA32_APICBASE_ENABLE)) { | |
322 | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; | |
0e26b7b8 | 323 | cpu_clear_apic_feature(s->cpu_env); |
574bbf7b FB |
324 | s->spurious_vec &= ~APIC_SV_ENABLE; |
325 | } | |
326 | } | |
327 | ||
92a16d7a | 328 | uint64_t cpu_get_apic_base(DeviceState *d) |
574bbf7b | 329 | { |
92a16d7a BS |
330 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
331 | ||
0a3c5921 BS |
332 | DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n", |
333 | s ? (uint64_t)s->apicbase: 0); | |
2c7c13d4 | 334 | return s ? s->apicbase : 0; |
574bbf7b FB |
335 | } |
336 | ||
92a16d7a | 337 | void cpu_set_apic_tpr(DeviceState *d, uint8_t val) |
9230e66e | 338 | { |
92a16d7a BS |
339 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
340 | ||
2c7c13d4 AJ |
341 | if (!s) |
342 | return; | |
9230e66e | 343 | s->tpr = (val & 0x0f) << 4; |
d592d303 | 344 | apic_update_irq(s); |
9230e66e FB |
345 | } |
346 | ||
92a16d7a | 347 | uint8_t cpu_get_apic_tpr(DeviceState *d) |
9230e66e | 348 | { |
92a16d7a BS |
349 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
350 | ||
2c7c13d4 | 351 | return s ? s->tpr >> 4 : 0; |
9230e66e FB |
352 | } |
353 | ||
d592d303 FB |
354 | /* return -1 if no bit is set */ |
355 | static int get_highest_priority_int(uint32_t *tab) | |
356 | { | |
357 | int i; | |
358 | for(i = 7; i >= 0; i--) { | |
359 | if (tab[i] != 0) { | |
3b63c04e | 360 | return i * 32 + fls_bit(tab[i]); |
d592d303 FB |
361 | } |
362 | } | |
363 | return -1; | |
364 | } | |
365 | ||
574bbf7b FB |
366 | static int apic_get_ppr(APICState *s) |
367 | { | |
368 | int tpr, isrv, ppr; | |
369 | ||
370 | tpr = (s->tpr >> 4); | |
371 | isrv = get_highest_priority_int(s->isr); | |
372 | if (isrv < 0) | |
373 | isrv = 0; | |
374 | isrv >>= 4; | |
375 | if (tpr >= isrv) | |
376 | ppr = s->tpr; | |
377 | else | |
378 | ppr = isrv << 4; | |
379 | return ppr; | |
380 | } | |
381 | ||
d592d303 FB |
382 | static int apic_get_arb_pri(APICState *s) |
383 | { | |
384 | /* XXX: arbitration */ | |
385 | return 0; | |
386 | } | |
387 | ||
574bbf7b FB |
388 | /* signal the CPU if an irq is pending */ |
389 | static void apic_update_irq(APICState *s) | |
390 | { | |
d592d303 FB |
391 | int irrv, ppr; |
392 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
393 | return; | |
574bbf7b FB |
394 | irrv = get_highest_priority_int(s->irr); |
395 | if (irrv < 0) | |
396 | return; | |
d592d303 FB |
397 | ppr = apic_get_ppr(s); |
398 | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) | |
574bbf7b FB |
399 | return; |
400 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); | |
401 | } | |
402 | ||
73822ec8 AL |
403 | void apic_reset_irq_delivered(void) |
404 | { | |
0a3c5921 | 405 | DPRINTF_C("%s: old coalescing %d\n", __func__, apic_irq_delivered); |
73822ec8 AL |
406 | apic_irq_delivered = 0; |
407 | } | |
408 | ||
409 | int apic_get_irq_delivered(void) | |
410 | { | |
0a3c5921 | 411 | DPRINTF_C("%s: returning coalescing %d\n", __func__, apic_irq_delivered); |
73822ec8 AL |
412 | return apic_irq_delivered; |
413 | } | |
414 | ||
574bbf7b FB |
415 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
416 | { | |
73822ec8 | 417 | apic_irq_delivered += !get_bit(s->irr, vector_num); |
0a3c5921 | 418 | DPRINTF_C("%s: coalescing %d\n", __func__, apic_irq_delivered); |
73822ec8 | 419 | |
574bbf7b FB |
420 | set_bit(s->irr, vector_num); |
421 | if (trigger_mode) | |
422 | set_bit(s->tmr, vector_num); | |
423 | else | |
424 | reset_bit(s->tmr, vector_num); | |
425 | apic_update_irq(s); | |
426 | } | |
427 | ||
428 | static void apic_eoi(APICState *s) | |
429 | { | |
430 | int isrv; | |
431 | isrv = get_highest_priority_int(s->isr); | |
432 | if (isrv < 0) | |
433 | return; | |
434 | reset_bit(s->isr, isrv); | |
d592d303 FB |
435 | /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to |
436 | set the remote IRR bit for level triggered interrupts. */ | |
574bbf7b FB |
437 | apic_update_irq(s); |
438 | } | |
439 | ||
678e12cc GN |
440 | static int apic_find_dest(uint8_t dest) |
441 | { | |
442 | APICState *apic = local_apics[dest]; | |
443 | int i; | |
444 | ||
445 | if (apic && apic->id == dest) | |
446 | return dest; /* shortcut in case apic->id == apic->idx */ | |
447 | ||
448 | for (i = 0; i < MAX_APICS; i++) { | |
449 | apic = local_apics[i]; | |
450 | if (apic && apic->id == dest) | |
451 | return i; | |
452 | } | |
453 | ||
454 | return -1; | |
455 | } | |
456 | ||
d3e9db93 FB |
457 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
458 | uint8_t dest, uint8_t dest_mode) | |
d592d303 | 459 | { |
d592d303 | 460 | APICState *apic_iter; |
d3e9db93 | 461 | int i; |
d592d303 FB |
462 | |
463 | if (dest_mode == 0) { | |
d3e9db93 FB |
464 | if (dest == 0xff) { |
465 | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); | |
466 | } else { | |
678e12cc | 467 | int idx = apic_find_dest(dest); |
d3e9db93 | 468 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
678e12cc GN |
469 | if (idx >= 0) |
470 | set_bit(deliver_bitmask, idx); | |
d3e9db93 | 471 | } |
d592d303 FB |
472 | } else { |
473 | /* XXX: cluster mode */ | |
d3e9db93 FB |
474 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
475 | for(i = 0; i < MAX_APICS; i++) { | |
476 | apic_iter = local_apics[i]; | |
477 | if (apic_iter) { | |
478 | if (apic_iter->dest_mode == 0xf) { | |
479 | if (dest & apic_iter->log_dest) | |
480 | set_bit(deliver_bitmask, i); | |
481 | } else if (apic_iter->dest_mode == 0x0) { | |
482 | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && | |
483 | (dest & apic_iter->log_dest & 0x0f)) { | |
484 | set_bit(deliver_bitmask, i); | |
485 | } | |
486 | } | |
487 | } | |
d592d303 FB |
488 | } |
489 | } | |
d592d303 FB |
490 | } |
491 | ||
92a16d7a | 492 | void apic_init_reset(DeviceState *d) |
d592d303 | 493 | { |
92a16d7a | 494 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
d592d303 FB |
495 | int i; |
496 | ||
b09ea7d5 GN |
497 | if (!s) |
498 | return; | |
499 | ||
d592d303 FB |
500 | s->tpr = 0; |
501 | s->spurious_vec = 0xff; | |
502 | s->log_dest = 0; | |
e0fd8781 | 503 | s->dest_mode = 0xf; |
d592d303 FB |
504 | memset(s->isr, 0, sizeof(s->isr)); |
505 | memset(s->tmr, 0, sizeof(s->tmr)); | |
506 | memset(s->irr, 0, sizeof(s->irr)); | |
b4511723 FB |
507 | for(i = 0; i < APIC_LVT_NB; i++) |
508 | s->lvt[i] = 1 << 16; /* mask LVT */ | |
d592d303 FB |
509 | s->esr = 0; |
510 | memset(s->icr, 0, sizeof(s->icr)); | |
511 | s->divide_conf = 0; | |
512 | s->count_shift = 0; | |
513 | s->initial_count = 0; | |
514 | s->initial_count_load_time = 0; | |
515 | s->next_time = 0; | |
b09ea7d5 | 516 | s->wait_for_sipi = 1; |
d592d303 FB |
517 | } |
518 | ||
e0fd8781 FB |
519 | static void apic_startup(APICState *s, int vector_num) |
520 | { | |
b09ea7d5 GN |
521 | s->sipi_vector = vector_num; |
522 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); | |
523 | } | |
524 | ||
92a16d7a | 525 | void apic_sipi(DeviceState *d) |
b09ea7d5 | 526 | { |
92a16d7a BS |
527 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
528 | ||
4a942cea | 529 | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
b09ea7d5 GN |
530 | |
531 | if (!s->wait_for_sipi) | |
e0fd8781 | 532 | return; |
0e26b7b8 | 533 | cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); |
b09ea7d5 | 534 | s->wait_for_sipi = 0; |
e0fd8781 FB |
535 | } |
536 | ||
92a16d7a | 537 | static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, |
d592d303 FB |
538 | uint8_t delivery_mode, uint8_t vector_num, |
539 | uint8_t polarity, uint8_t trigger_mode) | |
540 | { | |
92a16d7a | 541 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
d3e9db93 | 542 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
d592d303 FB |
543 | int dest_shorthand = (s->icr[0] >> 18) & 3; |
544 | APICState *apic_iter; | |
545 | ||
e0fd8781 | 546 | switch (dest_shorthand) { |
d3e9db93 FB |
547 | case 0: |
548 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); | |
549 | break; | |
550 | case 1: | |
551 | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); | |
678e12cc | 552 | set_bit(deliver_bitmask, s->idx); |
d3e9db93 FB |
553 | break; |
554 | case 2: | |
555 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
556 | break; | |
557 | case 3: | |
558 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
678e12cc | 559 | reset_bit(deliver_bitmask, s->idx); |
d3e9db93 | 560 | break; |
e0fd8781 FB |
561 | } |
562 | ||
d592d303 | 563 | switch (delivery_mode) { |
d592d303 FB |
564 | case APIC_DM_INIT: |
565 | { | |
566 | int trig_mode = (s->icr[0] >> 15) & 1; | |
567 | int level = (s->icr[0] >> 14) & 1; | |
568 | if (level == 0 && trig_mode == 1) { | |
5fafdf24 | 569 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 570 | apic_iter->arb_id = apic_iter->id ); |
d592d303 FB |
571 | return; |
572 | } | |
573 | } | |
574 | break; | |
575 | ||
576 | case APIC_DM_SIPI: | |
5fafdf24 | 577 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 578 | apic_startup(apic_iter, vector_num) ); |
d592d303 FB |
579 | return; |
580 | } | |
581 | ||
d592d303 FB |
582 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
583 | trigger_mode); | |
584 | } | |
585 | ||
92a16d7a | 586 | int apic_get_interrupt(DeviceState *d) |
574bbf7b | 587 | { |
92a16d7a | 588 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
574bbf7b FB |
589 | int intno; |
590 | ||
591 | /* if the APIC is installed or enabled, we let the 8259 handle the | |
592 | IRQs */ | |
593 | if (!s) | |
594 | return -1; | |
595 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
596 | return -1; | |
3b46e624 | 597 | |
574bbf7b FB |
598 | /* XXX: spurious IRQ handling */ |
599 | intno = get_highest_priority_int(s->irr); | |
600 | if (intno < 0) | |
601 | return -1; | |
d592d303 FB |
602 | if (s->tpr && intno <= s->tpr) |
603 | return s->spurious_vec & 0xff; | |
b4511723 | 604 | reset_bit(s->irr, intno); |
574bbf7b FB |
605 | set_bit(s->isr, intno); |
606 | apic_update_irq(s); | |
607 | return intno; | |
608 | } | |
609 | ||
92a16d7a | 610 | int apic_accept_pic_intr(DeviceState *d) |
0e21e12b | 611 | { |
92a16d7a | 612 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
0e21e12b TS |
613 | uint32_t lvt0; |
614 | ||
615 | if (!s) | |
616 | return -1; | |
617 | ||
618 | lvt0 = s->lvt[APIC_LVT_LINT0]; | |
619 | ||
a5b38b51 AJ |
620 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
621 | (lvt0 & APIC_LVT_MASKED) == 0) | |
0e21e12b TS |
622 | return 1; |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
574bbf7b FB |
627 | static uint32_t apic_get_current_count(APICState *s) |
628 | { | |
629 | int64_t d; | |
630 | uint32_t val; | |
5fafdf24 | 631 | d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
574bbf7b FB |
632 | s->count_shift; |
633 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
634 | /* periodic */ | |
d592d303 | 635 | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); |
574bbf7b FB |
636 | } else { |
637 | if (d >= s->initial_count) | |
638 | val = 0; | |
639 | else | |
640 | val = s->initial_count - d; | |
641 | } | |
642 | return val; | |
643 | } | |
644 | ||
645 | static void apic_timer_update(APICState *s, int64_t current_time) | |
646 | { | |
647 | int64_t next_time, d; | |
3b46e624 | 648 | |
574bbf7b | 649 | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { |
5fafdf24 | 650 | d = (current_time - s->initial_count_load_time) >> |
574bbf7b FB |
651 | s->count_shift; |
652 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
681f8c29 AL |
653 | if (!s->initial_count) |
654 | goto no_timer; | |
d592d303 | 655 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
574bbf7b FB |
656 | } else { |
657 | if (d >= s->initial_count) | |
658 | goto no_timer; | |
d592d303 | 659 | d = (uint64_t)s->initial_count + 1; |
574bbf7b FB |
660 | } |
661 | next_time = s->initial_count_load_time + (d << s->count_shift); | |
662 | qemu_mod_timer(s->timer, next_time); | |
663 | s->next_time = next_time; | |
664 | } else { | |
665 | no_timer: | |
666 | qemu_del_timer(s->timer); | |
667 | } | |
668 | } | |
669 | ||
670 | static void apic_timer(void *opaque) | |
671 | { | |
672 | APICState *s = opaque; | |
673 | ||
cf6d64bf | 674 | apic_local_deliver(s, APIC_LVT_TIMER); |
574bbf7b FB |
675 | apic_timer_update(s, s->next_time); |
676 | } | |
677 | ||
c227f099 | 678 | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
679 | { |
680 | return 0; | |
681 | } | |
682 | ||
c227f099 | 683 | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
684 | { |
685 | return 0; | |
686 | } | |
687 | ||
c227f099 | 688 | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
689 | { |
690 | } | |
691 | ||
c227f099 | 692 | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
693 | { |
694 | } | |
695 | ||
c227f099 | 696 | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
574bbf7b | 697 | { |
92a16d7a | 698 | DeviceState *d; |
574bbf7b FB |
699 | APICState *s; |
700 | uint32_t val; | |
701 | int index; | |
702 | ||
92a16d7a BS |
703 | d = cpu_get_current_apic(); |
704 | if (!d) { | |
574bbf7b | 705 | return 0; |
0e26b7b8 | 706 | } |
92a16d7a | 707 | s = DO_UPCAST(APICState, busdev.qdev, d); |
574bbf7b FB |
708 | |
709 | index = (addr >> 4) & 0xff; | |
710 | switch(index) { | |
711 | case 0x02: /* id */ | |
712 | val = s->id << 24; | |
713 | break; | |
714 | case 0x03: /* version */ | |
715 | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ | |
716 | break; | |
717 | case 0x08: | |
718 | val = s->tpr; | |
719 | break; | |
d592d303 FB |
720 | case 0x09: |
721 | val = apic_get_arb_pri(s); | |
722 | break; | |
574bbf7b FB |
723 | case 0x0a: |
724 | /* ppr */ | |
725 | val = apic_get_ppr(s); | |
726 | break; | |
b237db36 AJ |
727 | case 0x0b: |
728 | val = 0; | |
729 | break; | |
d592d303 FB |
730 | case 0x0d: |
731 | val = s->log_dest << 24; | |
732 | break; | |
733 | case 0x0e: | |
734 | val = s->dest_mode << 28; | |
735 | break; | |
574bbf7b FB |
736 | case 0x0f: |
737 | val = s->spurious_vec; | |
738 | break; | |
739 | case 0x10 ... 0x17: | |
740 | val = s->isr[index & 7]; | |
741 | break; | |
742 | case 0x18 ... 0x1f: | |
743 | val = s->tmr[index & 7]; | |
744 | break; | |
745 | case 0x20 ... 0x27: | |
746 | val = s->irr[index & 7]; | |
747 | break; | |
748 | case 0x28: | |
749 | val = s->esr; | |
750 | break; | |
574bbf7b FB |
751 | case 0x30: |
752 | case 0x31: | |
753 | val = s->icr[index & 1]; | |
754 | break; | |
e0fd8781 FB |
755 | case 0x32 ... 0x37: |
756 | val = s->lvt[index - 0x32]; | |
757 | break; | |
574bbf7b FB |
758 | case 0x38: |
759 | val = s->initial_count; | |
760 | break; | |
761 | case 0x39: | |
762 | val = apic_get_current_count(s); | |
763 | break; | |
764 | case 0x3e: | |
765 | val = s->divide_conf; | |
766 | break; | |
767 | default: | |
768 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
769 | val = 0; | |
770 | break; | |
771 | } | |
0a3c5921 | 772 | DPRINTF("read: " TARGET_FMT_plx " = %08x\n", addr, val); |
574bbf7b FB |
773 | return val; |
774 | } | |
775 | ||
c227f099 | 776 | static void apic_send_msi(target_phys_addr_t addr, uint32 data) |
54c96da7 MT |
777 | { |
778 | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; | |
779 | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
780 | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; | |
781 | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; | |
782 | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; | |
783 | /* XXX: Ignore redirection hint. */ | |
784 | apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode); | |
785 | } | |
786 | ||
c227f099 | 787 | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b | 788 | { |
92a16d7a | 789 | DeviceState *d; |
574bbf7b | 790 | APICState *s; |
54c96da7 MT |
791 | int index = (addr >> 4) & 0xff; |
792 | if (addr > 0xfff || !index) { | |
793 | /* MSI and MMIO APIC are at the same memory location, | |
794 | * but actually not on the global bus: MSI is on PCI bus | |
795 | * APIC is connected directly to the CPU. | |
796 | * Mapping them on the global bus happens to work because | |
797 | * MSI registers are reserved in APIC MMIO and vice versa. */ | |
798 | apic_send_msi(addr, val); | |
799 | return; | |
800 | } | |
574bbf7b | 801 | |
92a16d7a BS |
802 | d = cpu_get_current_apic(); |
803 | if (!d) { | |
574bbf7b | 804 | return; |
0e26b7b8 | 805 | } |
92a16d7a | 806 | s = DO_UPCAST(APICState, busdev.qdev, d); |
574bbf7b | 807 | |
0a3c5921 | 808 | DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val); |
574bbf7b | 809 | |
574bbf7b FB |
810 | switch(index) { |
811 | case 0x02: | |
812 | s->id = (val >> 24); | |
813 | break; | |
e0fd8781 FB |
814 | case 0x03: |
815 | break; | |
574bbf7b FB |
816 | case 0x08: |
817 | s->tpr = val; | |
d592d303 | 818 | apic_update_irq(s); |
574bbf7b | 819 | break; |
e0fd8781 FB |
820 | case 0x09: |
821 | case 0x0a: | |
822 | break; | |
574bbf7b FB |
823 | case 0x0b: /* EOI */ |
824 | apic_eoi(s); | |
825 | break; | |
d592d303 FB |
826 | case 0x0d: |
827 | s->log_dest = val >> 24; | |
828 | break; | |
829 | case 0x0e: | |
830 | s->dest_mode = val >> 28; | |
831 | break; | |
574bbf7b FB |
832 | case 0x0f: |
833 | s->spurious_vec = val & 0x1ff; | |
d592d303 | 834 | apic_update_irq(s); |
574bbf7b | 835 | break; |
e0fd8781 FB |
836 | case 0x10 ... 0x17: |
837 | case 0x18 ... 0x1f: | |
838 | case 0x20 ... 0x27: | |
839 | case 0x28: | |
840 | break; | |
574bbf7b | 841 | case 0x30: |
d592d303 | 842 | s->icr[0] = val; |
92a16d7a | 843 | apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
d592d303 FB |
844 | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
845 | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); | |
846 | break; | |
574bbf7b | 847 | case 0x31: |
d592d303 | 848 | s->icr[1] = val; |
574bbf7b FB |
849 | break; |
850 | case 0x32 ... 0x37: | |
851 | { | |
852 | int n = index - 0x32; | |
853 | s->lvt[n] = val; | |
854 | if (n == APIC_LVT_TIMER) | |
855 | apic_timer_update(s, qemu_get_clock(vm_clock)); | |
856 | } | |
857 | break; | |
858 | case 0x38: | |
859 | s->initial_count = val; | |
860 | s->initial_count_load_time = qemu_get_clock(vm_clock); | |
861 | apic_timer_update(s, s->initial_count_load_time); | |
862 | break; | |
e0fd8781 FB |
863 | case 0x39: |
864 | break; | |
574bbf7b FB |
865 | case 0x3e: |
866 | { | |
867 | int v; | |
868 | s->divide_conf = val & 0xb; | |
869 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); | |
870 | s->count_shift = (v + 1) & 7; | |
871 | } | |
872 | break; | |
873 | default: | |
874 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
875 | break; | |
876 | } | |
877 | } | |
878 | ||
695dcf71 JQ |
879 | /* This function is only used for old state version 1 and 2 */ |
880 | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) | |
d592d303 FB |
881 | { |
882 | APICState *s = opaque; | |
883 | int i; | |
884 | ||
e6cf6a8c | 885 | if (version_id > 2) |
d592d303 FB |
886 | return -EINVAL; |
887 | ||
888 | /* XXX: what if the base changes? (registered memory regions) */ | |
889 | qemu_get_be32s(f, &s->apicbase); | |
890 | qemu_get_8s(f, &s->id); | |
891 | qemu_get_8s(f, &s->arb_id); | |
892 | qemu_get_8s(f, &s->tpr); | |
893 | qemu_get_be32s(f, &s->spurious_vec); | |
894 | qemu_get_8s(f, &s->log_dest); | |
895 | qemu_get_8s(f, &s->dest_mode); | |
896 | for (i = 0; i < 8; i++) { | |
897 | qemu_get_be32s(f, &s->isr[i]); | |
898 | qemu_get_be32s(f, &s->tmr[i]); | |
899 | qemu_get_be32s(f, &s->irr[i]); | |
900 | } | |
901 | for (i = 0; i < APIC_LVT_NB; i++) { | |
902 | qemu_get_be32s(f, &s->lvt[i]); | |
903 | } | |
904 | qemu_get_be32s(f, &s->esr); | |
905 | qemu_get_be32s(f, &s->icr[0]); | |
906 | qemu_get_be32s(f, &s->icr[1]); | |
907 | qemu_get_be32s(f, &s->divide_conf); | |
bee8d684 | 908 | s->count_shift=qemu_get_be32(f); |
d592d303 | 909 | qemu_get_be32s(f, &s->initial_count); |
bee8d684 TS |
910 | s->initial_count_load_time=qemu_get_be64(f); |
911 | s->next_time=qemu_get_be64(f); | |
e6cf6a8c FB |
912 | |
913 | if (version_id >= 2) | |
914 | qemu_get_timer(f, s->timer); | |
d592d303 FB |
915 | return 0; |
916 | } | |
574bbf7b | 917 | |
695dcf71 JQ |
918 | static const VMStateDescription vmstate_apic = { |
919 | .name = "apic", | |
920 | .version_id = 3, | |
921 | .minimum_version_id = 3, | |
922 | .minimum_version_id_old = 1, | |
923 | .load_state_old = apic_load_old, | |
924 | .fields = (VMStateField []) { | |
925 | VMSTATE_UINT32(apicbase, APICState), | |
926 | VMSTATE_UINT8(id, APICState), | |
927 | VMSTATE_UINT8(arb_id, APICState), | |
928 | VMSTATE_UINT8(tpr, APICState), | |
929 | VMSTATE_UINT32(spurious_vec, APICState), | |
930 | VMSTATE_UINT8(log_dest, APICState), | |
931 | VMSTATE_UINT8(dest_mode, APICState), | |
932 | VMSTATE_UINT32_ARRAY(isr, APICState, 8), | |
933 | VMSTATE_UINT32_ARRAY(tmr, APICState, 8), | |
934 | VMSTATE_UINT32_ARRAY(irr, APICState, 8), | |
935 | VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), | |
936 | VMSTATE_UINT32(esr, APICState), | |
937 | VMSTATE_UINT32_ARRAY(icr, APICState, 2), | |
938 | VMSTATE_UINT32(divide_conf, APICState), | |
939 | VMSTATE_INT32(count_shift, APICState), | |
940 | VMSTATE_UINT32(initial_count, APICState), | |
941 | VMSTATE_INT64(initial_count_load_time, APICState), | |
942 | VMSTATE_INT64(next_time, APICState), | |
943 | VMSTATE_TIMER(timer, APICState), | |
944 | VMSTATE_END_OF_LIST() | |
945 | } | |
946 | }; | |
947 | ||
8546b099 | 948 | static void apic_reset(DeviceState *d) |
d592d303 | 949 | { |
8546b099 | 950 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
4c0960c0 | 951 | int bsp; |
fec5fa02 | 952 | |
4c0960c0 | 953 | bsp = cpu_is_bsp(s->cpu_env); |
fec5fa02 | 954 | s->apicbase = 0xfee00000 | |
678e12cc | 955 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; |
fec5fa02 | 956 | |
92a16d7a | 957 | apic_init_reset(d); |
0e21e12b | 958 | |
678e12cc | 959 | if (bsp) { |
a5b38b51 AJ |
960 | /* |
961 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization | |
962 | * time typically by BIOS, so PIC interrupt can be delivered to the | |
963 | * processor when local APIC is enabled. | |
964 | */ | |
965 | s->lvt[APIC_LVT_LINT0] = 0x700; | |
966 | } | |
d592d303 | 967 | } |
574bbf7b | 968 | |
d60efc6b | 969 | static CPUReadMemoryFunc * const apic_mem_read[3] = { |
574bbf7b FB |
970 | apic_mem_readb, |
971 | apic_mem_readw, | |
972 | apic_mem_readl, | |
973 | }; | |
974 | ||
d60efc6b | 975 | static CPUWriteMemoryFunc * const apic_mem_write[3] = { |
574bbf7b FB |
976 | apic_mem_writeb, |
977 | apic_mem_writew, | |
978 | apic_mem_writel, | |
979 | }; | |
980 | ||
8546b099 BS |
981 | static int apic_init1(SysBusDevice *dev) |
982 | { | |
983 | APICState *s = FROM_SYSBUS(APICState, dev); | |
984 | int apic_io_memory; | |
985 | static int last_apic_idx; | |
986 | ||
987 | if (last_apic_idx >= MAX_APICS) { | |
988 | return -1; | |
989 | } | |
990 | apic_io_memory = cpu_register_io_memory(apic_mem_read, | |
991 | apic_mem_write, NULL); | |
992 | sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory); | |
993 | ||
994 | s->timer = qemu_new_timer(vm_clock, apic_timer, s); | |
995 | s->idx = last_apic_idx++; | |
996 | local_apics[s->idx] = s; | |
997 | return 0; | |
998 | } | |
999 | ||
1000 | static SysBusDeviceInfo apic_info = { | |
1001 | .init = apic_init1, | |
1002 | .qdev.name = "apic", | |
1003 | .qdev.size = sizeof(APICState), | |
1004 | .qdev.vmsd = &vmstate_apic, | |
1005 | .qdev.reset = apic_reset, | |
1006 | .qdev.no_user = 1, | |
1007 | .qdev.props = (Property[]) { | |
1008 | DEFINE_PROP_UINT8("id", APICState, id, -1), | |
1009 | DEFINE_PROP_PTR("cpu_env", APICState, cpu_env), | |
1010 | DEFINE_PROP_END_OF_LIST(), | |
1011 | } | |
1012 | }; | |
1013 | ||
1014 | static void apic_register_devices(void) | |
1015 | { | |
1016 | sysbus_register_withprop(&apic_info); | |
1017 | } | |
1018 | ||
1019 | device_init(apic_register_devices) |