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Commit | Line | Data |
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574bbf7b FB |
1 | /* |
2 | * APIC support | |
5fafdf24 | 3 | * |
574bbf7b FB |
4 | * Copyright (c) 2004-2005 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
574bbf7b | 18 | */ |
87ecb68b | 19 | #include "hw.h" |
aa28b9bf | 20 | #include "apic.h" |
0280b571 | 21 | #include "ioapic.h" |
87ecb68b | 22 | #include "qemu-timer.h" |
bb7e7293 | 23 | #include "host-utils.h" |
8546b099 | 24 | #include "sysbus.h" |
d8023f31 | 25 | #include "trace.h" |
574bbf7b FB |
26 | |
27 | /* APIC Local Vector Table */ | |
28 | #define APIC_LVT_TIMER 0 | |
29 | #define APIC_LVT_THERMAL 1 | |
30 | #define APIC_LVT_PERFORM 2 | |
31 | #define APIC_LVT_LINT0 3 | |
32 | #define APIC_LVT_LINT1 4 | |
33 | #define APIC_LVT_ERROR 5 | |
34 | #define APIC_LVT_NB 6 | |
35 | ||
36 | /* APIC delivery modes */ | |
37 | #define APIC_DM_FIXED 0 | |
38 | #define APIC_DM_LOWPRI 1 | |
39 | #define APIC_DM_SMI 2 | |
40 | #define APIC_DM_NMI 4 | |
41 | #define APIC_DM_INIT 5 | |
42 | #define APIC_DM_SIPI 6 | |
43 | #define APIC_DM_EXTINT 7 | |
44 | ||
d592d303 FB |
45 | /* APIC destination mode */ |
46 | #define APIC_DESTMODE_FLAT 0xf | |
47 | #define APIC_DESTMODE_CLUSTER 1 | |
48 | ||
574bbf7b FB |
49 | #define APIC_TRIGGER_EDGE 0 |
50 | #define APIC_TRIGGER_LEVEL 1 | |
51 | ||
52 | #define APIC_LVT_TIMER_PERIODIC (1<<17) | |
53 | #define APIC_LVT_MASKED (1<<16) | |
54 | #define APIC_LVT_LEVEL_TRIGGER (1<<15) | |
55 | #define APIC_LVT_REMOTE_IRR (1<<14) | |
56 | #define APIC_INPUT_POLARITY (1<<13) | |
57 | #define APIC_SEND_PENDING (1<<12) | |
58 | ||
59 | #define ESR_ILLEGAL_ADDRESS (1 << 7) | |
60 | ||
0280b571 JK |
61 | #define APIC_SV_DIRECTED_IO (1<<12) |
62 | #define APIC_SV_ENABLE (1<<8) | |
574bbf7b | 63 | |
d3e9db93 FB |
64 | #define MAX_APICS 255 |
65 | #define MAX_APIC_WORDS 8 | |
66 | ||
54c96da7 MT |
67 | /* Intel APIC constants: from include/asm/msidef.h */ |
68 | #define MSI_DATA_VECTOR_SHIFT 0 | |
69 | #define MSI_DATA_VECTOR_MASK 0x000000ff | |
70 | #define MSI_DATA_DELIVERY_MODE_SHIFT 8 | |
71 | #define MSI_DATA_TRIGGER_SHIFT 15 | |
72 | #define MSI_DATA_LEVEL_SHIFT 14 | |
73 | #define MSI_ADDR_DEST_MODE_SHIFT 2 | |
74 | #define MSI_ADDR_DEST_ID_SHIFT 12 | |
75 | #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 | |
76 | ||
54c96da7 MT |
77 | #define MSI_ADDR_SIZE 0x100000 |
78 | ||
92a16d7a BS |
79 | typedef struct APICState APICState; |
80 | ||
cf6d64bf | 81 | struct APICState { |
8546b099 | 82 | SysBusDevice busdev; |
312b4234 | 83 | MemoryRegion io_memory; |
8546b099 | 84 | void *cpu_env; |
574bbf7b FB |
85 | uint32_t apicbase; |
86 | uint8_t id; | |
d592d303 | 87 | uint8_t arb_id; |
574bbf7b FB |
88 | uint8_t tpr; |
89 | uint32_t spurious_vec; | |
d592d303 FB |
90 | uint8_t log_dest; |
91 | uint8_t dest_mode; | |
574bbf7b FB |
92 | uint32_t isr[8]; /* in service register */ |
93 | uint32_t tmr[8]; /* trigger mode register */ | |
94 | uint32_t irr[8]; /* interrupt request register */ | |
95 | uint32_t lvt[APIC_LVT_NB]; | |
96 | uint32_t esr; /* error register */ | |
97 | uint32_t icr[2]; | |
98 | ||
99 | uint32_t divide_conf; | |
100 | int count_shift; | |
101 | uint32_t initial_count; | |
102 | int64_t initial_count_load_time, next_time; | |
678e12cc | 103 | uint32_t idx; |
574bbf7b | 104 | QEMUTimer *timer; |
b09ea7d5 GN |
105 | int sipi_vector; |
106 | int wait_for_sipi; | |
cf6d64bf | 107 | }; |
574bbf7b | 108 | |
d3e9db93 | 109 | static APICState *local_apics[MAX_APICS + 1]; |
73822ec8 AL |
110 | static int apic_irq_delivered; |
111 | ||
d592d303 FB |
112 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
113 | static void apic_update_irq(APICState *s); | |
610626af AL |
114 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
115 | uint8_t dest, uint8_t dest_mode); | |
d592d303 | 116 | |
3b63c04e AJ |
117 | /* Find first bit starting from msb */ |
118 | static int fls_bit(uint32_t value) | |
119 | { | |
120 | return 31 - clz32(value); | |
121 | } | |
122 | ||
e95f5491 | 123 | /* Find first bit starting from lsb */ |
d3e9db93 FB |
124 | static int ffs_bit(uint32_t value) |
125 | { | |
bb7e7293 | 126 | return ctz32(value); |
d3e9db93 FB |
127 | } |
128 | ||
129 | static inline void set_bit(uint32_t *tab, int index) | |
130 | { | |
131 | int i, mask; | |
132 | i = index >> 5; | |
133 | mask = 1 << (index & 0x1f); | |
134 | tab[i] |= mask; | |
135 | } | |
136 | ||
137 | static inline void reset_bit(uint32_t *tab, int index) | |
138 | { | |
139 | int i, mask; | |
140 | i = index >> 5; | |
141 | mask = 1 << (index & 0x1f); | |
142 | tab[i] &= ~mask; | |
143 | } | |
144 | ||
73822ec8 AL |
145 | static inline int get_bit(uint32_t *tab, int index) |
146 | { | |
147 | int i, mask; | |
148 | i = index >> 5; | |
149 | mask = 1 << (index & 0x1f); | |
150 | return !!(tab[i] & mask); | |
151 | } | |
152 | ||
cf6d64bf | 153 | static void apic_local_deliver(APICState *s, int vector) |
a5b38b51 | 154 | { |
a5b38b51 AJ |
155 | uint32_t lvt = s->lvt[vector]; |
156 | int trigger_mode; | |
157 | ||
d8023f31 BS |
158 | trace_apic_local_deliver(vector, (lvt >> 8) & 7); |
159 | ||
a5b38b51 AJ |
160 | if (lvt & APIC_LVT_MASKED) |
161 | return; | |
162 | ||
163 | switch ((lvt >> 8) & 7) { | |
164 | case APIC_DM_SMI: | |
cf6d64bf | 165 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); |
a5b38b51 AJ |
166 | break; |
167 | ||
168 | case APIC_DM_NMI: | |
cf6d64bf | 169 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); |
a5b38b51 AJ |
170 | break; |
171 | ||
172 | case APIC_DM_EXTINT: | |
cf6d64bf | 173 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
a5b38b51 AJ |
174 | break; |
175 | ||
176 | case APIC_DM_FIXED: | |
177 | trigger_mode = APIC_TRIGGER_EDGE; | |
178 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && | |
179 | (lvt & APIC_LVT_LEVEL_TRIGGER)) | |
180 | trigger_mode = APIC_TRIGGER_LEVEL; | |
181 | apic_set_irq(s, lvt & 0xff, trigger_mode); | |
182 | } | |
183 | } | |
184 | ||
92a16d7a | 185 | void apic_deliver_pic_intr(DeviceState *d, int level) |
1a7de94a | 186 | { |
92a16d7a BS |
187 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
188 | ||
cf6d64bf BS |
189 | if (level) { |
190 | apic_local_deliver(s, APIC_LVT_LINT0); | |
191 | } else { | |
1a7de94a AJ |
192 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
193 | ||
194 | switch ((lvt >> 8) & 7) { | |
195 | case APIC_DM_FIXED: | |
196 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) | |
197 | break; | |
198 | reset_bit(s->irr, lvt & 0xff); | |
199 | /* fall through */ | |
200 | case APIC_DM_EXTINT: | |
cf6d64bf | 201 | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
1a7de94a AJ |
202 | break; |
203 | } | |
204 | } | |
205 | } | |
206 | ||
d3e9db93 FB |
207 | #define foreach_apic(apic, deliver_bitmask, code) \ |
208 | {\ | |
209 | int __i, __j, __mask;\ | |
210 | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ | |
211 | __mask = deliver_bitmask[__i];\ | |
212 | if (__mask) {\ | |
213 | for(__j = 0; __j < 32; __j++) {\ | |
214 | if (__mask & (1 << __j)) {\ | |
215 | apic = local_apics[__i * 32 + __j];\ | |
216 | if (apic) {\ | |
217 | code;\ | |
218 | }\ | |
219 | }\ | |
220 | }\ | |
221 | }\ | |
222 | }\ | |
223 | } | |
224 | ||
5fafdf24 | 225 | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
1f6f408c | 226 | uint8_t delivery_mode, uint8_t vector_num, |
d592d303 FB |
227 | uint8_t trigger_mode) |
228 | { | |
229 | APICState *apic_iter; | |
230 | ||
231 | switch (delivery_mode) { | |
232 | case APIC_DM_LOWPRI: | |
8dd69b8f | 233 | /* XXX: search for focus processor, arbitration */ |
d3e9db93 FB |
234 | { |
235 | int i, d; | |
236 | d = -1; | |
237 | for(i = 0; i < MAX_APIC_WORDS; i++) { | |
238 | if (deliver_bitmask[i]) { | |
239 | d = i * 32 + ffs_bit(deliver_bitmask[i]); | |
240 | break; | |
241 | } | |
242 | } | |
243 | if (d >= 0) { | |
244 | apic_iter = local_apics[d]; | |
245 | if (apic_iter) { | |
246 | apic_set_irq(apic_iter, vector_num, trigger_mode); | |
247 | } | |
248 | } | |
8dd69b8f | 249 | } |
d3e9db93 | 250 | return; |
8dd69b8f | 251 | |
d592d303 | 252 | case APIC_DM_FIXED: |
d592d303 FB |
253 | break; |
254 | ||
255 | case APIC_DM_SMI: | |
e2eb9d3e AJ |
256 | foreach_apic(apic_iter, deliver_bitmask, |
257 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); | |
258 | return; | |
259 | ||
d592d303 | 260 | case APIC_DM_NMI: |
e2eb9d3e AJ |
261 | foreach_apic(apic_iter, deliver_bitmask, |
262 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); | |
263 | return; | |
d592d303 FB |
264 | |
265 | case APIC_DM_INIT: | |
266 | /* normal INIT IPI sent to processors */ | |
5fafdf24 | 267 | foreach_apic(apic_iter, deliver_bitmask, |
b09ea7d5 | 268 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
d592d303 | 269 | return; |
3b46e624 | 270 | |
d592d303 | 271 | case APIC_DM_EXTINT: |
b1fc0348 | 272 | /* handled in I/O APIC code */ |
d592d303 FB |
273 | break; |
274 | ||
275 | default: | |
276 | return; | |
277 | } | |
278 | ||
5fafdf24 | 279 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 280 | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
d592d303 | 281 | } |
574bbf7b | 282 | |
1f6f408c JK |
283 | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, |
284 | uint8_t vector_num, uint8_t trigger_mode) | |
610626af AL |
285 | { |
286 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; | |
287 | ||
d8023f31 | 288 | trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
1f6f408c | 289 | trigger_mode); |
d8023f31 | 290 | |
610626af | 291 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
1f6f408c | 292 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
610626af AL |
293 | } |
294 | ||
92a16d7a | 295 | void cpu_set_apic_base(DeviceState *d, uint64_t val) |
574bbf7b | 296 | { |
92a16d7a BS |
297 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
298 | ||
d8023f31 BS |
299 | trace_cpu_set_apic_base(val); |
300 | ||
2c7c13d4 AJ |
301 | if (!s) |
302 | return; | |
5fafdf24 | 303 | s->apicbase = (val & 0xfffff000) | |
574bbf7b FB |
304 | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
305 | /* if disabled, cannot be enabled again */ | |
306 | if (!(val & MSR_IA32_APICBASE_ENABLE)) { | |
307 | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; | |
0e26b7b8 | 308 | cpu_clear_apic_feature(s->cpu_env); |
574bbf7b FB |
309 | s->spurious_vec &= ~APIC_SV_ENABLE; |
310 | } | |
311 | } | |
312 | ||
92a16d7a | 313 | uint64_t cpu_get_apic_base(DeviceState *d) |
574bbf7b | 314 | { |
92a16d7a BS |
315 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
316 | ||
d8023f31 BS |
317 | trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0); |
318 | ||
2c7c13d4 | 319 | return s ? s->apicbase : 0; |
574bbf7b FB |
320 | } |
321 | ||
92a16d7a | 322 | void cpu_set_apic_tpr(DeviceState *d, uint8_t val) |
9230e66e | 323 | { |
92a16d7a BS |
324 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
325 | ||
2c7c13d4 AJ |
326 | if (!s) |
327 | return; | |
9230e66e | 328 | s->tpr = (val & 0x0f) << 4; |
d592d303 | 329 | apic_update_irq(s); |
9230e66e FB |
330 | } |
331 | ||
92a16d7a | 332 | uint8_t cpu_get_apic_tpr(DeviceState *d) |
9230e66e | 333 | { |
92a16d7a BS |
334 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
335 | ||
2c7c13d4 | 336 | return s ? s->tpr >> 4 : 0; |
9230e66e FB |
337 | } |
338 | ||
d592d303 FB |
339 | /* return -1 if no bit is set */ |
340 | static int get_highest_priority_int(uint32_t *tab) | |
341 | { | |
342 | int i; | |
343 | for(i = 7; i >= 0; i--) { | |
344 | if (tab[i] != 0) { | |
3b63c04e | 345 | return i * 32 + fls_bit(tab[i]); |
d592d303 FB |
346 | } |
347 | } | |
348 | return -1; | |
349 | } | |
350 | ||
574bbf7b FB |
351 | static int apic_get_ppr(APICState *s) |
352 | { | |
353 | int tpr, isrv, ppr; | |
354 | ||
355 | tpr = (s->tpr >> 4); | |
356 | isrv = get_highest_priority_int(s->isr); | |
357 | if (isrv < 0) | |
358 | isrv = 0; | |
359 | isrv >>= 4; | |
360 | if (tpr >= isrv) | |
361 | ppr = s->tpr; | |
362 | else | |
363 | ppr = isrv << 4; | |
364 | return ppr; | |
365 | } | |
366 | ||
d592d303 FB |
367 | static int apic_get_arb_pri(APICState *s) |
368 | { | |
369 | /* XXX: arbitration */ | |
370 | return 0; | |
371 | } | |
372 | ||
0fbfbb59 GN |
373 | |
374 | /* | |
375 | * <0 - low prio interrupt, | |
376 | * 0 - no interrupt, | |
377 | * >0 - interrupt number | |
378 | */ | |
379 | static int apic_irq_pending(APICState *s) | |
574bbf7b | 380 | { |
d592d303 | 381 | int irrv, ppr; |
574bbf7b | 382 | irrv = get_highest_priority_int(s->irr); |
0fbfbb59 GN |
383 | if (irrv < 0) { |
384 | return 0; | |
385 | } | |
d592d303 | 386 | ppr = apic_get_ppr(s); |
0fbfbb59 GN |
387 | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { |
388 | return -1; | |
389 | } | |
390 | ||
391 | return irrv; | |
392 | } | |
393 | ||
394 | /* signal the CPU if an irq is pending */ | |
395 | static void apic_update_irq(APICState *s) | |
396 | { | |
397 | if (!(s->spurious_vec & APIC_SV_ENABLE)) { | |
574bbf7b | 398 | return; |
0fbfbb59 GN |
399 | } |
400 | if (apic_irq_pending(s) > 0) { | |
401 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); | |
402 | } | |
574bbf7b FB |
403 | } |
404 | ||
73822ec8 AL |
405 | void apic_reset_irq_delivered(void) |
406 | { | |
d8023f31 BS |
407 | trace_apic_reset_irq_delivered(apic_irq_delivered); |
408 | ||
73822ec8 AL |
409 | apic_irq_delivered = 0; |
410 | } | |
411 | ||
412 | int apic_get_irq_delivered(void) | |
413 | { | |
d8023f31 BS |
414 | trace_apic_get_irq_delivered(apic_irq_delivered); |
415 | ||
73822ec8 AL |
416 | return apic_irq_delivered; |
417 | } | |
418 | ||
574bbf7b FB |
419 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
420 | { | |
73822ec8 | 421 | apic_irq_delivered += !get_bit(s->irr, vector_num); |
d8023f31 BS |
422 | |
423 | trace_apic_set_irq(apic_irq_delivered); | |
73822ec8 | 424 | |
574bbf7b FB |
425 | set_bit(s->irr, vector_num); |
426 | if (trigger_mode) | |
427 | set_bit(s->tmr, vector_num); | |
428 | else | |
429 | reset_bit(s->tmr, vector_num); | |
430 | apic_update_irq(s); | |
431 | } | |
432 | ||
433 | static void apic_eoi(APICState *s) | |
434 | { | |
435 | int isrv; | |
436 | isrv = get_highest_priority_int(s->isr); | |
437 | if (isrv < 0) | |
438 | return; | |
439 | reset_bit(s->isr, isrv); | |
0280b571 JK |
440 | if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) { |
441 | ioapic_eoi_broadcast(isrv); | |
442 | } | |
574bbf7b FB |
443 | apic_update_irq(s); |
444 | } | |
445 | ||
678e12cc GN |
446 | static int apic_find_dest(uint8_t dest) |
447 | { | |
448 | APICState *apic = local_apics[dest]; | |
449 | int i; | |
450 | ||
451 | if (apic && apic->id == dest) | |
452 | return dest; /* shortcut in case apic->id == apic->idx */ | |
453 | ||
454 | for (i = 0; i < MAX_APICS; i++) { | |
455 | apic = local_apics[i]; | |
456 | if (apic && apic->id == dest) | |
457 | return i; | |
b538e53e AW |
458 | if (!apic) |
459 | break; | |
678e12cc GN |
460 | } |
461 | ||
462 | return -1; | |
463 | } | |
464 | ||
d3e9db93 FB |
465 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
466 | uint8_t dest, uint8_t dest_mode) | |
d592d303 | 467 | { |
d592d303 | 468 | APICState *apic_iter; |
d3e9db93 | 469 | int i; |
d592d303 FB |
470 | |
471 | if (dest_mode == 0) { | |
d3e9db93 FB |
472 | if (dest == 0xff) { |
473 | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); | |
474 | } else { | |
678e12cc | 475 | int idx = apic_find_dest(dest); |
d3e9db93 | 476 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
678e12cc GN |
477 | if (idx >= 0) |
478 | set_bit(deliver_bitmask, idx); | |
d3e9db93 | 479 | } |
d592d303 FB |
480 | } else { |
481 | /* XXX: cluster mode */ | |
d3e9db93 FB |
482 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
483 | for(i = 0; i < MAX_APICS; i++) { | |
484 | apic_iter = local_apics[i]; | |
485 | if (apic_iter) { | |
486 | if (apic_iter->dest_mode == 0xf) { | |
487 | if (dest & apic_iter->log_dest) | |
488 | set_bit(deliver_bitmask, i); | |
489 | } else if (apic_iter->dest_mode == 0x0) { | |
490 | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && | |
491 | (dest & apic_iter->log_dest & 0x0f)) { | |
492 | set_bit(deliver_bitmask, i); | |
493 | } | |
494 | } | |
b538e53e AW |
495 | } else { |
496 | break; | |
d3e9db93 | 497 | } |
d592d303 FB |
498 | } |
499 | } | |
d592d303 FB |
500 | } |
501 | ||
92a16d7a | 502 | void apic_init_reset(DeviceState *d) |
d592d303 | 503 | { |
92a16d7a | 504 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
d592d303 FB |
505 | int i; |
506 | ||
b09ea7d5 GN |
507 | if (!s) |
508 | return; | |
509 | ||
d592d303 FB |
510 | s->tpr = 0; |
511 | s->spurious_vec = 0xff; | |
512 | s->log_dest = 0; | |
e0fd8781 | 513 | s->dest_mode = 0xf; |
d592d303 FB |
514 | memset(s->isr, 0, sizeof(s->isr)); |
515 | memset(s->tmr, 0, sizeof(s->tmr)); | |
516 | memset(s->irr, 0, sizeof(s->irr)); | |
b4511723 FB |
517 | for(i = 0; i < APIC_LVT_NB; i++) |
518 | s->lvt[i] = 1 << 16; /* mask LVT */ | |
d592d303 FB |
519 | s->esr = 0; |
520 | memset(s->icr, 0, sizeof(s->icr)); | |
521 | s->divide_conf = 0; | |
522 | s->count_shift = 0; | |
523 | s->initial_count = 0; | |
524 | s->initial_count_load_time = 0; | |
525 | s->next_time = 0; | |
b09ea7d5 | 526 | s->wait_for_sipi = 1; |
d592d303 FB |
527 | } |
528 | ||
e0fd8781 FB |
529 | static void apic_startup(APICState *s, int vector_num) |
530 | { | |
b09ea7d5 GN |
531 | s->sipi_vector = vector_num; |
532 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); | |
533 | } | |
534 | ||
92a16d7a | 535 | void apic_sipi(DeviceState *d) |
b09ea7d5 | 536 | { |
92a16d7a BS |
537 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
538 | ||
4a942cea | 539 | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
b09ea7d5 GN |
540 | |
541 | if (!s->wait_for_sipi) | |
e0fd8781 | 542 | return; |
0e26b7b8 | 543 | cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); |
b09ea7d5 | 544 | s->wait_for_sipi = 0; |
e0fd8781 FB |
545 | } |
546 | ||
92a16d7a | 547 | static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, |
d592d303 | 548 | uint8_t delivery_mode, uint8_t vector_num, |
1f6f408c | 549 | uint8_t trigger_mode) |
d592d303 | 550 | { |
92a16d7a | 551 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
d3e9db93 | 552 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
d592d303 FB |
553 | int dest_shorthand = (s->icr[0] >> 18) & 3; |
554 | APICState *apic_iter; | |
555 | ||
e0fd8781 | 556 | switch (dest_shorthand) { |
d3e9db93 FB |
557 | case 0: |
558 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); | |
559 | break; | |
560 | case 1: | |
561 | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); | |
678e12cc | 562 | set_bit(deliver_bitmask, s->idx); |
d3e9db93 FB |
563 | break; |
564 | case 2: | |
565 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
566 | break; | |
567 | case 3: | |
568 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
678e12cc | 569 | reset_bit(deliver_bitmask, s->idx); |
d3e9db93 | 570 | break; |
e0fd8781 FB |
571 | } |
572 | ||
d592d303 | 573 | switch (delivery_mode) { |
d592d303 FB |
574 | case APIC_DM_INIT: |
575 | { | |
576 | int trig_mode = (s->icr[0] >> 15) & 1; | |
577 | int level = (s->icr[0] >> 14) & 1; | |
578 | if (level == 0 && trig_mode == 1) { | |
5fafdf24 | 579 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 580 | apic_iter->arb_id = apic_iter->id ); |
d592d303 FB |
581 | return; |
582 | } | |
583 | } | |
584 | break; | |
585 | ||
586 | case APIC_DM_SIPI: | |
5fafdf24 | 587 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 588 | apic_startup(apic_iter, vector_num) ); |
d592d303 FB |
589 | return; |
590 | } | |
591 | ||
1f6f408c | 592 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
d592d303 FB |
593 | } |
594 | ||
92a16d7a | 595 | int apic_get_interrupt(DeviceState *d) |
574bbf7b | 596 | { |
92a16d7a | 597 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
574bbf7b FB |
598 | int intno; |
599 | ||
600 | /* if the APIC is installed or enabled, we let the 8259 handle the | |
601 | IRQs */ | |
602 | if (!s) | |
603 | return -1; | |
604 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
605 | return -1; | |
3b46e624 | 606 | |
0fbfbb59 GN |
607 | intno = apic_irq_pending(s); |
608 | ||
609 | if (intno == 0) { | |
574bbf7b | 610 | return -1; |
0fbfbb59 | 611 | } else if (intno < 0) { |
d592d303 | 612 | return s->spurious_vec & 0xff; |
0fbfbb59 | 613 | } |
b4511723 | 614 | reset_bit(s->irr, intno); |
574bbf7b FB |
615 | set_bit(s->isr, intno); |
616 | apic_update_irq(s); | |
617 | return intno; | |
618 | } | |
619 | ||
92a16d7a | 620 | int apic_accept_pic_intr(DeviceState *d) |
0e21e12b | 621 | { |
92a16d7a | 622 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
0e21e12b TS |
623 | uint32_t lvt0; |
624 | ||
625 | if (!s) | |
626 | return -1; | |
627 | ||
628 | lvt0 = s->lvt[APIC_LVT_LINT0]; | |
629 | ||
a5b38b51 AJ |
630 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
631 | (lvt0 & APIC_LVT_MASKED) == 0) | |
0e21e12b TS |
632 | return 1; |
633 | ||
634 | return 0; | |
635 | } | |
636 | ||
574bbf7b FB |
637 | static uint32_t apic_get_current_count(APICState *s) |
638 | { | |
639 | int64_t d; | |
640 | uint32_t val; | |
74475455 | 641 | d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >> |
574bbf7b FB |
642 | s->count_shift; |
643 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
644 | /* periodic */ | |
d592d303 | 645 | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); |
574bbf7b FB |
646 | } else { |
647 | if (d >= s->initial_count) | |
648 | val = 0; | |
649 | else | |
650 | val = s->initial_count - d; | |
651 | } | |
652 | return val; | |
653 | } | |
654 | ||
655 | static void apic_timer_update(APICState *s, int64_t current_time) | |
656 | { | |
657 | int64_t next_time, d; | |
3b46e624 | 658 | |
574bbf7b | 659 | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { |
5fafdf24 | 660 | d = (current_time - s->initial_count_load_time) >> |
574bbf7b FB |
661 | s->count_shift; |
662 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
681f8c29 AL |
663 | if (!s->initial_count) |
664 | goto no_timer; | |
d592d303 | 665 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
574bbf7b FB |
666 | } else { |
667 | if (d >= s->initial_count) | |
668 | goto no_timer; | |
d592d303 | 669 | d = (uint64_t)s->initial_count + 1; |
574bbf7b FB |
670 | } |
671 | next_time = s->initial_count_load_time + (d << s->count_shift); | |
672 | qemu_mod_timer(s->timer, next_time); | |
673 | s->next_time = next_time; | |
674 | } else { | |
675 | no_timer: | |
676 | qemu_del_timer(s->timer); | |
677 | } | |
678 | } | |
679 | ||
680 | static void apic_timer(void *opaque) | |
681 | { | |
682 | APICState *s = opaque; | |
683 | ||
cf6d64bf | 684 | apic_local_deliver(s, APIC_LVT_TIMER); |
574bbf7b FB |
685 | apic_timer_update(s, s->next_time); |
686 | } | |
687 | ||
c227f099 | 688 | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
689 | { |
690 | return 0; | |
691 | } | |
692 | ||
c227f099 | 693 | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
694 | { |
695 | return 0; | |
696 | } | |
697 | ||
c227f099 | 698 | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
699 | { |
700 | } | |
701 | ||
c227f099 | 702 | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
703 | { |
704 | } | |
705 | ||
c227f099 | 706 | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
574bbf7b | 707 | { |
92a16d7a | 708 | DeviceState *d; |
574bbf7b FB |
709 | APICState *s; |
710 | uint32_t val; | |
711 | int index; | |
712 | ||
92a16d7a BS |
713 | d = cpu_get_current_apic(); |
714 | if (!d) { | |
574bbf7b | 715 | return 0; |
0e26b7b8 | 716 | } |
92a16d7a | 717 | s = DO_UPCAST(APICState, busdev.qdev, d); |
574bbf7b FB |
718 | |
719 | index = (addr >> 4) & 0xff; | |
720 | switch(index) { | |
721 | case 0x02: /* id */ | |
722 | val = s->id << 24; | |
723 | break; | |
724 | case 0x03: /* version */ | |
725 | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ | |
726 | break; | |
727 | case 0x08: | |
728 | val = s->tpr; | |
729 | break; | |
d592d303 FB |
730 | case 0x09: |
731 | val = apic_get_arb_pri(s); | |
732 | break; | |
574bbf7b FB |
733 | case 0x0a: |
734 | /* ppr */ | |
735 | val = apic_get_ppr(s); | |
736 | break; | |
b237db36 AJ |
737 | case 0x0b: |
738 | val = 0; | |
739 | break; | |
d592d303 FB |
740 | case 0x0d: |
741 | val = s->log_dest << 24; | |
742 | break; | |
743 | case 0x0e: | |
744 | val = s->dest_mode << 28; | |
745 | break; | |
574bbf7b FB |
746 | case 0x0f: |
747 | val = s->spurious_vec; | |
748 | break; | |
749 | case 0x10 ... 0x17: | |
750 | val = s->isr[index & 7]; | |
751 | break; | |
752 | case 0x18 ... 0x1f: | |
753 | val = s->tmr[index & 7]; | |
754 | break; | |
755 | case 0x20 ... 0x27: | |
756 | val = s->irr[index & 7]; | |
757 | break; | |
758 | case 0x28: | |
759 | val = s->esr; | |
760 | break; | |
574bbf7b FB |
761 | case 0x30: |
762 | case 0x31: | |
763 | val = s->icr[index & 1]; | |
764 | break; | |
e0fd8781 FB |
765 | case 0x32 ... 0x37: |
766 | val = s->lvt[index - 0x32]; | |
767 | break; | |
574bbf7b FB |
768 | case 0x38: |
769 | val = s->initial_count; | |
770 | break; | |
771 | case 0x39: | |
772 | val = apic_get_current_count(s); | |
773 | break; | |
774 | case 0x3e: | |
775 | val = s->divide_conf; | |
776 | break; | |
777 | default: | |
778 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
779 | val = 0; | |
780 | break; | |
781 | } | |
d8023f31 | 782 | trace_apic_mem_readl(addr, val); |
574bbf7b FB |
783 | return val; |
784 | } | |
785 | ||
f5095c63 | 786 | static void apic_send_msi(target_phys_addr_t addr, uint32_t data) |
54c96da7 MT |
787 | { |
788 | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; | |
789 | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
790 | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; | |
791 | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; | |
792 | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; | |
793 | /* XXX: Ignore redirection hint. */ | |
1f6f408c | 794 | apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); |
54c96da7 MT |
795 | } |
796 | ||
c227f099 | 797 | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b | 798 | { |
92a16d7a | 799 | DeviceState *d; |
574bbf7b | 800 | APICState *s; |
54c96da7 MT |
801 | int index = (addr >> 4) & 0xff; |
802 | if (addr > 0xfff || !index) { | |
803 | /* MSI and MMIO APIC are at the same memory location, | |
804 | * but actually not on the global bus: MSI is on PCI bus | |
805 | * APIC is connected directly to the CPU. | |
806 | * Mapping them on the global bus happens to work because | |
807 | * MSI registers are reserved in APIC MMIO and vice versa. */ | |
808 | apic_send_msi(addr, val); | |
809 | return; | |
810 | } | |
574bbf7b | 811 | |
92a16d7a BS |
812 | d = cpu_get_current_apic(); |
813 | if (!d) { | |
574bbf7b | 814 | return; |
0e26b7b8 | 815 | } |
92a16d7a | 816 | s = DO_UPCAST(APICState, busdev.qdev, d); |
574bbf7b | 817 | |
d8023f31 | 818 | trace_apic_mem_writel(addr, val); |
574bbf7b | 819 | |
574bbf7b FB |
820 | switch(index) { |
821 | case 0x02: | |
822 | s->id = (val >> 24); | |
823 | break; | |
e0fd8781 FB |
824 | case 0x03: |
825 | break; | |
574bbf7b FB |
826 | case 0x08: |
827 | s->tpr = val; | |
d592d303 | 828 | apic_update_irq(s); |
574bbf7b | 829 | break; |
e0fd8781 FB |
830 | case 0x09: |
831 | case 0x0a: | |
832 | break; | |
574bbf7b FB |
833 | case 0x0b: /* EOI */ |
834 | apic_eoi(s); | |
835 | break; | |
d592d303 FB |
836 | case 0x0d: |
837 | s->log_dest = val >> 24; | |
838 | break; | |
839 | case 0x0e: | |
840 | s->dest_mode = val >> 28; | |
841 | break; | |
574bbf7b FB |
842 | case 0x0f: |
843 | s->spurious_vec = val & 0x1ff; | |
d592d303 | 844 | apic_update_irq(s); |
574bbf7b | 845 | break; |
e0fd8781 FB |
846 | case 0x10 ... 0x17: |
847 | case 0x18 ... 0x1f: | |
848 | case 0x20 ... 0x27: | |
849 | case 0x28: | |
850 | break; | |
574bbf7b | 851 | case 0x30: |
d592d303 | 852 | s->icr[0] = val; |
92a16d7a | 853 | apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
d592d303 | 854 | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
1f6f408c | 855 | (s->icr[0] >> 15) & 1); |
d592d303 | 856 | break; |
574bbf7b | 857 | case 0x31: |
d592d303 | 858 | s->icr[1] = val; |
574bbf7b FB |
859 | break; |
860 | case 0x32 ... 0x37: | |
861 | { | |
862 | int n = index - 0x32; | |
863 | s->lvt[n] = val; | |
864 | if (n == APIC_LVT_TIMER) | |
74475455 | 865 | apic_timer_update(s, qemu_get_clock_ns(vm_clock)); |
574bbf7b FB |
866 | } |
867 | break; | |
868 | case 0x38: | |
869 | s->initial_count = val; | |
74475455 | 870 | s->initial_count_load_time = qemu_get_clock_ns(vm_clock); |
574bbf7b FB |
871 | apic_timer_update(s, s->initial_count_load_time); |
872 | break; | |
e0fd8781 FB |
873 | case 0x39: |
874 | break; | |
574bbf7b FB |
875 | case 0x3e: |
876 | { | |
877 | int v; | |
878 | s->divide_conf = val & 0xb; | |
879 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); | |
880 | s->count_shift = (v + 1) & 7; | |
881 | } | |
882 | break; | |
883 | default: | |
884 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
885 | break; | |
886 | } | |
887 | } | |
888 | ||
695dcf71 JQ |
889 | /* This function is only used for old state version 1 and 2 */ |
890 | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) | |
d592d303 FB |
891 | { |
892 | APICState *s = opaque; | |
893 | int i; | |
894 | ||
e6cf6a8c | 895 | if (version_id > 2) |
d592d303 FB |
896 | return -EINVAL; |
897 | ||
898 | /* XXX: what if the base changes? (registered memory regions) */ | |
899 | qemu_get_be32s(f, &s->apicbase); | |
900 | qemu_get_8s(f, &s->id); | |
901 | qemu_get_8s(f, &s->arb_id); | |
902 | qemu_get_8s(f, &s->tpr); | |
903 | qemu_get_be32s(f, &s->spurious_vec); | |
904 | qemu_get_8s(f, &s->log_dest); | |
905 | qemu_get_8s(f, &s->dest_mode); | |
906 | for (i = 0; i < 8; i++) { | |
907 | qemu_get_be32s(f, &s->isr[i]); | |
908 | qemu_get_be32s(f, &s->tmr[i]); | |
909 | qemu_get_be32s(f, &s->irr[i]); | |
910 | } | |
911 | for (i = 0; i < APIC_LVT_NB; i++) { | |
912 | qemu_get_be32s(f, &s->lvt[i]); | |
913 | } | |
914 | qemu_get_be32s(f, &s->esr); | |
915 | qemu_get_be32s(f, &s->icr[0]); | |
916 | qemu_get_be32s(f, &s->icr[1]); | |
917 | qemu_get_be32s(f, &s->divide_conf); | |
bee8d684 | 918 | s->count_shift=qemu_get_be32(f); |
d592d303 | 919 | qemu_get_be32s(f, &s->initial_count); |
bee8d684 TS |
920 | s->initial_count_load_time=qemu_get_be64(f); |
921 | s->next_time=qemu_get_be64(f); | |
e6cf6a8c FB |
922 | |
923 | if (version_id >= 2) | |
924 | qemu_get_timer(f, s->timer); | |
d592d303 FB |
925 | return 0; |
926 | } | |
574bbf7b | 927 | |
695dcf71 JQ |
928 | static const VMStateDescription vmstate_apic = { |
929 | .name = "apic", | |
930 | .version_id = 3, | |
931 | .minimum_version_id = 3, | |
932 | .minimum_version_id_old = 1, | |
933 | .load_state_old = apic_load_old, | |
934 | .fields = (VMStateField []) { | |
935 | VMSTATE_UINT32(apicbase, APICState), | |
936 | VMSTATE_UINT8(id, APICState), | |
937 | VMSTATE_UINT8(arb_id, APICState), | |
938 | VMSTATE_UINT8(tpr, APICState), | |
939 | VMSTATE_UINT32(spurious_vec, APICState), | |
940 | VMSTATE_UINT8(log_dest, APICState), | |
941 | VMSTATE_UINT8(dest_mode, APICState), | |
942 | VMSTATE_UINT32_ARRAY(isr, APICState, 8), | |
943 | VMSTATE_UINT32_ARRAY(tmr, APICState, 8), | |
944 | VMSTATE_UINT32_ARRAY(irr, APICState, 8), | |
945 | VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), | |
946 | VMSTATE_UINT32(esr, APICState), | |
947 | VMSTATE_UINT32_ARRAY(icr, APICState, 2), | |
948 | VMSTATE_UINT32(divide_conf, APICState), | |
949 | VMSTATE_INT32(count_shift, APICState), | |
950 | VMSTATE_UINT32(initial_count, APICState), | |
951 | VMSTATE_INT64(initial_count_load_time, APICState), | |
952 | VMSTATE_INT64(next_time, APICState), | |
953 | VMSTATE_TIMER(timer, APICState), | |
954 | VMSTATE_END_OF_LIST() | |
955 | } | |
956 | }; | |
957 | ||
8546b099 | 958 | static void apic_reset(DeviceState *d) |
d592d303 | 959 | { |
8546b099 | 960 | APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
4c0960c0 | 961 | int bsp; |
fec5fa02 | 962 | |
4c0960c0 | 963 | bsp = cpu_is_bsp(s->cpu_env); |
fec5fa02 | 964 | s->apicbase = 0xfee00000 | |
678e12cc | 965 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; |
fec5fa02 | 966 | |
92a16d7a | 967 | apic_init_reset(d); |
0e21e12b | 968 | |
678e12cc | 969 | if (bsp) { |
a5b38b51 AJ |
970 | /* |
971 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization | |
972 | * time typically by BIOS, so PIC interrupt can be delivered to the | |
973 | * processor when local APIC is enabled. | |
974 | */ | |
975 | s->lvt[APIC_LVT_LINT0] = 0x700; | |
976 | } | |
d592d303 | 977 | } |
574bbf7b | 978 | |
312b4234 AK |
979 | static const MemoryRegionOps apic_io_ops = { |
980 | .old_mmio = { | |
981 | .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, | |
982 | .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, | |
983 | }, | |
984 | .endianness = DEVICE_NATIVE_ENDIAN, | |
574bbf7b FB |
985 | }; |
986 | ||
8546b099 BS |
987 | static int apic_init1(SysBusDevice *dev) |
988 | { | |
989 | APICState *s = FROM_SYSBUS(APICState, dev); | |
8546b099 BS |
990 | static int last_apic_idx; |
991 | ||
992 | if (last_apic_idx >= MAX_APICS) { | |
993 | return -1; | |
994 | } | |
312b4234 AK |
995 | memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic", |
996 | MSI_ADDR_SIZE); | |
997 | sysbus_init_mmio_region(dev, &s->io_memory); | |
8546b099 | 998 | |
74475455 | 999 | s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); |
8546b099 BS |
1000 | s->idx = last_apic_idx++; |
1001 | local_apics[s->idx] = s; | |
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static SysBusDeviceInfo apic_info = { | |
1006 | .init = apic_init1, | |
1007 | .qdev.name = "apic", | |
1008 | .qdev.size = sizeof(APICState), | |
1009 | .qdev.vmsd = &vmstate_apic, | |
1010 | .qdev.reset = apic_reset, | |
1011 | .qdev.no_user = 1, | |
1012 | .qdev.props = (Property[]) { | |
1013 | DEFINE_PROP_UINT8("id", APICState, id, -1), | |
1014 | DEFINE_PROP_PTR("cpu_env", APICState, cpu_env), | |
1015 | DEFINE_PROP_END_OF_LIST(), | |
1016 | } | |
1017 | }; | |
1018 | ||
1019 | static void apic_register_devices(void) | |
1020 | { | |
1021 | sysbus_register_withprop(&apic_info); | |
1022 | } | |
1023 | ||
1024 | device_init(apic_register_devices) |