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Commit | Line | Data |
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574bbf7b FB |
1 | /* |
2 | * APIC support | |
5fafdf24 | 3 | * |
574bbf7b FB |
4 | * Copyright (c) 2004-2005 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
574bbf7b | 18 | */ |
87ecb68b PB |
19 | #include "hw.h" |
20 | #include "pc.h" | |
aa28b9bf | 21 | #include "apic.h" |
54c96da7 MT |
22 | #include "pci.h" |
23 | #include "msix.h" | |
87ecb68b | 24 | #include "qemu-timer.h" |
bb7e7293 | 25 | #include "host-utils.h" |
8d2ba1fb | 26 | #include "kvm.h" |
574bbf7b FB |
27 | |
28 | //#define DEBUG_APIC | |
0a3c5921 BS |
29 | //#define DEBUG_COALESCING |
30 | ||
31 | #ifdef DEBUG_APIC | |
32 | #define DPRINTF(fmt, ...) \ | |
33 | do { printf("apic: " fmt , ## __VA_ARGS__); } while (0) | |
34 | #else | |
35 | #define DPRINTF(fmt, ...) | |
36 | #endif | |
37 | ||
38 | #ifdef DEBUG_COALESCING | |
39 | #define DPRINTF_C(fmt, ...) \ | |
40 | do { printf("apic: " fmt , ## __VA_ARGS__); } while (0) | |
41 | #else | |
42 | #define DPRINTF_C(fmt, ...) | |
43 | #endif | |
574bbf7b FB |
44 | |
45 | /* APIC Local Vector Table */ | |
46 | #define APIC_LVT_TIMER 0 | |
47 | #define APIC_LVT_THERMAL 1 | |
48 | #define APIC_LVT_PERFORM 2 | |
49 | #define APIC_LVT_LINT0 3 | |
50 | #define APIC_LVT_LINT1 4 | |
51 | #define APIC_LVT_ERROR 5 | |
52 | #define APIC_LVT_NB 6 | |
53 | ||
54 | /* APIC delivery modes */ | |
55 | #define APIC_DM_FIXED 0 | |
56 | #define APIC_DM_LOWPRI 1 | |
57 | #define APIC_DM_SMI 2 | |
58 | #define APIC_DM_NMI 4 | |
59 | #define APIC_DM_INIT 5 | |
60 | #define APIC_DM_SIPI 6 | |
61 | #define APIC_DM_EXTINT 7 | |
62 | ||
d592d303 FB |
63 | /* APIC destination mode */ |
64 | #define APIC_DESTMODE_FLAT 0xf | |
65 | #define APIC_DESTMODE_CLUSTER 1 | |
66 | ||
574bbf7b FB |
67 | #define APIC_TRIGGER_EDGE 0 |
68 | #define APIC_TRIGGER_LEVEL 1 | |
69 | ||
70 | #define APIC_LVT_TIMER_PERIODIC (1<<17) | |
71 | #define APIC_LVT_MASKED (1<<16) | |
72 | #define APIC_LVT_LEVEL_TRIGGER (1<<15) | |
73 | #define APIC_LVT_REMOTE_IRR (1<<14) | |
74 | #define APIC_INPUT_POLARITY (1<<13) | |
75 | #define APIC_SEND_PENDING (1<<12) | |
76 | ||
77 | #define ESR_ILLEGAL_ADDRESS (1 << 7) | |
78 | ||
79 | #define APIC_SV_ENABLE (1 << 8) | |
80 | ||
d3e9db93 FB |
81 | #define MAX_APICS 255 |
82 | #define MAX_APIC_WORDS 8 | |
83 | ||
54c96da7 MT |
84 | /* Intel APIC constants: from include/asm/msidef.h */ |
85 | #define MSI_DATA_VECTOR_SHIFT 0 | |
86 | #define MSI_DATA_VECTOR_MASK 0x000000ff | |
87 | #define MSI_DATA_DELIVERY_MODE_SHIFT 8 | |
88 | #define MSI_DATA_TRIGGER_SHIFT 15 | |
89 | #define MSI_DATA_LEVEL_SHIFT 14 | |
90 | #define MSI_ADDR_DEST_MODE_SHIFT 2 | |
91 | #define MSI_ADDR_DEST_ID_SHIFT 12 | |
92 | #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 | |
93 | ||
94 | #define MSI_ADDR_BASE 0xfee00000 | |
95 | #define MSI_ADDR_SIZE 0x100000 | |
96 | ||
574bbf7b FB |
97 | typedef struct APICState { |
98 | CPUState *cpu_env; | |
99 | uint32_t apicbase; | |
100 | uint8_t id; | |
d592d303 | 101 | uint8_t arb_id; |
574bbf7b FB |
102 | uint8_t tpr; |
103 | uint32_t spurious_vec; | |
d592d303 FB |
104 | uint8_t log_dest; |
105 | uint8_t dest_mode; | |
574bbf7b FB |
106 | uint32_t isr[8]; /* in service register */ |
107 | uint32_t tmr[8]; /* trigger mode register */ | |
108 | uint32_t irr[8]; /* interrupt request register */ | |
109 | uint32_t lvt[APIC_LVT_NB]; | |
110 | uint32_t esr; /* error register */ | |
111 | uint32_t icr[2]; | |
112 | ||
113 | uint32_t divide_conf; | |
114 | int count_shift; | |
115 | uint32_t initial_count; | |
116 | int64_t initial_count_load_time, next_time; | |
678e12cc | 117 | uint32_t idx; |
574bbf7b | 118 | QEMUTimer *timer; |
b09ea7d5 GN |
119 | int sipi_vector; |
120 | int wait_for_sipi; | |
574bbf7b FB |
121 | } APICState; |
122 | ||
123 | static int apic_io_memory; | |
d3e9db93 | 124 | static APICState *local_apics[MAX_APICS + 1]; |
678e12cc | 125 | static int last_apic_idx = 0; |
73822ec8 AL |
126 | static int apic_irq_delivered; |
127 | ||
d592d303 | 128 | |
d592d303 FB |
129 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
130 | static void apic_update_irq(APICState *s); | |
610626af AL |
131 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
132 | uint8_t dest, uint8_t dest_mode); | |
d592d303 | 133 | |
3b63c04e AJ |
134 | /* Find first bit starting from msb */ |
135 | static int fls_bit(uint32_t value) | |
136 | { | |
137 | return 31 - clz32(value); | |
138 | } | |
139 | ||
e95f5491 | 140 | /* Find first bit starting from lsb */ |
d3e9db93 FB |
141 | static int ffs_bit(uint32_t value) |
142 | { | |
bb7e7293 | 143 | return ctz32(value); |
d3e9db93 FB |
144 | } |
145 | ||
146 | static inline void set_bit(uint32_t *tab, int index) | |
147 | { | |
148 | int i, mask; | |
149 | i = index >> 5; | |
150 | mask = 1 << (index & 0x1f); | |
151 | tab[i] |= mask; | |
152 | } | |
153 | ||
154 | static inline void reset_bit(uint32_t *tab, int index) | |
155 | { | |
156 | int i, mask; | |
157 | i = index >> 5; | |
158 | mask = 1 << (index & 0x1f); | |
159 | tab[i] &= ~mask; | |
160 | } | |
161 | ||
73822ec8 AL |
162 | static inline int get_bit(uint32_t *tab, int index) |
163 | { | |
164 | int i, mask; | |
165 | i = index >> 5; | |
166 | mask = 1 << (index & 0x1f); | |
167 | return !!(tab[i] & mask); | |
168 | } | |
169 | ||
1a7de94a | 170 | static void apic_local_deliver(CPUState *env, int vector) |
a5b38b51 AJ |
171 | { |
172 | APICState *s = env->apic_state; | |
173 | uint32_t lvt = s->lvt[vector]; | |
174 | int trigger_mode; | |
175 | ||
0a3c5921 BS |
176 | DPRINTF("%s: vector %d delivery mode %d\n", __func__, vector, |
177 | (lvt >> 8) & 7); | |
a5b38b51 AJ |
178 | if (lvt & APIC_LVT_MASKED) |
179 | return; | |
180 | ||
181 | switch ((lvt >> 8) & 7) { | |
182 | case APIC_DM_SMI: | |
183 | cpu_interrupt(env, CPU_INTERRUPT_SMI); | |
184 | break; | |
185 | ||
186 | case APIC_DM_NMI: | |
187 | cpu_interrupt(env, CPU_INTERRUPT_NMI); | |
188 | break; | |
189 | ||
190 | case APIC_DM_EXTINT: | |
191 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
192 | break; | |
193 | ||
194 | case APIC_DM_FIXED: | |
195 | trigger_mode = APIC_TRIGGER_EDGE; | |
196 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && | |
197 | (lvt & APIC_LVT_LEVEL_TRIGGER)) | |
198 | trigger_mode = APIC_TRIGGER_LEVEL; | |
199 | apic_set_irq(s, lvt & 0xff, trigger_mode); | |
200 | } | |
201 | } | |
202 | ||
1a7de94a AJ |
203 | void apic_deliver_pic_intr(CPUState *env, int level) |
204 | { | |
205 | if (level) | |
206 | apic_local_deliver(env, APIC_LVT_LINT0); | |
207 | else { | |
208 | APICState *s = env->apic_state; | |
209 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; | |
210 | ||
211 | switch ((lvt >> 8) & 7) { | |
212 | case APIC_DM_FIXED: | |
213 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) | |
214 | break; | |
215 | reset_bit(s->irr, lvt & 0xff); | |
216 | /* fall through */ | |
217 | case APIC_DM_EXTINT: | |
218 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
219 | break; | |
220 | } | |
221 | } | |
222 | } | |
223 | ||
d3e9db93 FB |
224 | #define foreach_apic(apic, deliver_bitmask, code) \ |
225 | {\ | |
226 | int __i, __j, __mask;\ | |
227 | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ | |
228 | __mask = deliver_bitmask[__i];\ | |
229 | if (__mask) {\ | |
230 | for(__j = 0; __j < 32; __j++) {\ | |
231 | if (__mask & (1 << __j)) {\ | |
232 | apic = local_apics[__i * 32 + __j];\ | |
233 | if (apic) {\ | |
234 | code;\ | |
235 | }\ | |
236 | }\ | |
237 | }\ | |
238 | }\ | |
239 | }\ | |
240 | } | |
241 | ||
5fafdf24 | 242 | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
d3e9db93 | 243 | uint8_t delivery_mode, |
d592d303 FB |
244 | uint8_t vector_num, uint8_t polarity, |
245 | uint8_t trigger_mode) | |
246 | { | |
247 | APICState *apic_iter; | |
248 | ||
249 | switch (delivery_mode) { | |
250 | case APIC_DM_LOWPRI: | |
8dd69b8f | 251 | /* XXX: search for focus processor, arbitration */ |
d3e9db93 FB |
252 | { |
253 | int i, d; | |
254 | d = -1; | |
255 | for(i = 0; i < MAX_APIC_WORDS; i++) { | |
256 | if (deliver_bitmask[i]) { | |
257 | d = i * 32 + ffs_bit(deliver_bitmask[i]); | |
258 | break; | |
259 | } | |
260 | } | |
261 | if (d >= 0) { | |
262 | apic_iter = local_apics[d]; | |
263 | if (apic_iter) { | |
264 | apic_set_irq(apic_iter, vector_num, trigger_mode); | |
265 | } | |
266 | } | |
8dd69b8f | 267 | } |
d3e9db93 | 268 | return; |
8dd69b8f | 269 | |
d592d303 | 270 | case APIC_DM_FIXED: |
d592d303 FB |
271 | break; |
272 | ||
273 | case APIC_DM_SMI: | |
e2eb9d3e AJ |
274 | foreach_apic(apic_iter, deliver_bitmask, |
275 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); | |
276 | return; | |
277 | ||
d592d303 | 278 | case APIC_DM_NMI: |
e2eb9d3e AJ |
279 | foreach_apic(apic_iter, deliver_bitmask, |
280 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); | |
281 | return; | |
d592d303 FB |
282 | |
283 | case APIC_DM_INIT: | |
284 | /* normal INIT IPI sent to processors */ | |
5fafdf24 | 285 | foreach_apic(apic_iter, deliver_bitmask, |
b09ea7d5 | 286 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
d592d303 | 287 | return; |
3b46e624 | 288 | |
d592d303 | 289 | case APIC_DM_EXTINT: |
b1fc0348 | 290 | /* handled in I/O APIC code */ |
d592d303 FB |
291 | break; |
292 | ||
293 | default: | |
294 | return; | |
295 | } | |
296 | ||
5fafdf24 | 297 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 298 | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
d592d303 | 299 | } |
574bbf7b | 300 | |
610626af AL |
301 | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, |
302 | uint8_t delivery_mode, uint8_t vector_num, | |
303 | uint8_t polarity, uint8_t trigger_mode) | |
304 | { | |
305 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; | |
306 | ||
0a3c5921 BS |
307 | DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d" |
308 | " polarity %d trigger_mode %d\n", __func__, dest, dest_mode, | |
309 | delivery_mode, vector_num, polarity, trigger_mode); | |
610626af AL |
310 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
311 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, | |
312 | trigger_mode); | |
313 | } | |
314 | ||
574bbf7b FB |
315 | void cpu_set_apic_base(CPUState *env, uint64_t val) |
316 | { | |
317 | APICState *s = env->apic_state; | |
0a3c5921 BS |
318 | |
319 | DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val); | |
2c7c13d4 AJ |
320 | if (!s) |
321 | return; | |
5fafdf24 | 322 | s->apicbase = (val & 0xfffff000) | |
574bbf7b FB |
323 | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
324 | /* if disabled, cannot be enabled again */ | |
325 | if (!(val & MSR_IA32_APICBASE_ENABLE)) { | |
326 | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; | |
327 | env->cpuid_features &= ~CPUID_APIC; | |
328 | s->spurious_vec &= ~APIC_SV_ENABLE; | |
329 | } | |
330 | } | |
331 | ||
332 | uint64_t cpu_get_apic_base(CPUState *env) | |
333 | { | |
334 | APICState *s = env->apic_state; | |
0a3c5921 BS |
335 | |
336 | DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n", | |
337 | s ? (uint64_t)s->apicbase: 0); | |
2c7c13d4 | 338 | return s ? s->apicbase : 0; |
574bbf7b FB |
339 | } |
340 | ||
9230e66e FB |
341 | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val) |
342 | { | |
343 | APICState *s = env->apic_state; | |
2c7c13d4 AJ |
344 | if (!s) |
345 | return; | |
9230e66e | 346 | s->tpr = (val & 0x0f) << 4; |
d592d303 | 347 | apic_update_irq(s); |
9230e66e FB |
348 | } |
349 | ||
350 | uint8_t cpu_get_apic_tpr(CPUX86State *env) | |
351 | { | |
352 | APICState *s = env->apic_state; | |
2c7c13d4 | 353 | return s ? s->tpr >> 4 : 0; |
9230e66e FB |
354 | } |
355 | ||
d592d303 FB |
356 | /* return -1 if no bit is set */ |
357 | static int get_highest_priority_int(uint32_t *tab) | |
358 | { | |
359 | int i; | |
360 | for(i = 7; i >= 0; i--) { | |
361 | if (tab[i] != 0) { | |
3b63c04e | 362 | return i * 32 + fls_bit(tab[i]); |
d592d303 FB |
363 | } |
364 | } | |
365 | return -1; | |
366 | } | |
367 | ||
574bbf7b FB |
368 | static int apic_get_ppr(APICState *s) |
369 | { | |
370 | int tpr, isrv, ppr; | |
371 | ||
372 | tpr = (s->tpr >> 4); | |
373 | isrv = get_highest_priority_int(s->isr); | |
374 | if (isrv < 0) | |
375 | isrv = 0; | |
376 | isrv >>= 4; | |
377 | if (tpr >= isrv) | |
378 | ppr = s->tpr; | |
379 | else | |
380 | ppr = isrv << 4; | |
381 | return ppr; | |
382 | } | |
383 | ||
d592d303 FB |
384 | static int apic_get_arb_pri(APICState *s) |
385 | { | |
386 | /* XXX: arbitration */ | |
387 | return 0; | |
388 | } | |
389 | ||
574bbf7b FB |
390 | /* signal the CPU if an irq is pending */ |
391 | static void apic_update_irq(APICState *s) | |
392 | { | |
d592d303 FB |
393 | int irrv, ppr; |
394 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
395 | return; | |
574bbf7b FB |
396 | irrv = get_highest_priority_int(s->irr); |
397 | if (irrv < 0) | |
398 | return; | |
d592d303 FB |
399 | ppr = apic_get_ppr(s); |
400 | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) | |
574bbf7b FB |
401 | return; |
402 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); | |
403 | } | |
404 | ||
73822ec8 AL |
405 | void apic_reset_irq_delivered(void) |
406 | { | |
0a3c5921 | 407 | DPRINTF_C("%s: old coalescing %d\n", __func__, apic_irq_delivered); |
73822ec8 AL |
408 | apic_irq_delivered = 0; |
409 | } | |
410 | ||
411 | int apic_get_irq_delivered(void) | |
412 | { | |
0a3c5921 | 413 | DPRINTF_C("%s: returning coalescing %d\n", __func__, apic_irq_delivered); |
73822ec8 AL |
414 | return apic_irq_delivered; |
415 | } | |
416 | ||
574bbf7b FB |
417 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
418 | { | |
73822ec8 | 419 | apic_irq_delivered += !get_bit(s->irr, vector_num); |
0a3c5921 | 420 | DPRINTF_C("%s: coalescing %d\n", __func__, apic_irq_delivered); |
73822ec8 | 421 | |
574bbf7b FB |
422 | set_bit(s->irr, vector_num); |
423 | if (trigger_mode) | |
424 | set_bit(s->tmr, vector_num); | |
425 | else | |
426 | reset_bit(s->tmr, vector_num); | |
427 | apic_update_irq(s); | |
428 | } | |
429 | ||
430 | static void apic_eoi(APICState *s) | |
431 | { | |
432 | int isrv; | |
433 | isrv = get_highest_priority_int(s->isr); | |
434 | if (isrv < 0) | |
435 | return; | |
436 | reset_bit(s->isr, isrv); | |
d592d303 FB |
437 | /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to |
438 | set the remote IRR bit for level triggered interrupts. */ | |
574bbf7b FB |
439 | apic_update_irq(s); |
440 | } | |
441 | ||
678e12cc GN |
442 | static int apic_find_dest(uint8_t dest) |
443 | { | |
444 | APICState *apic = local_apics[dest]; | |
445 | int i; | |
446 | ||
447 | if (apic && apic->id == dest) | |
448 | return dest; /* shortcut in case apic->id == apic->idx */ | |
449 | ||
450 | for (i = 0; i < MAX_APICS; i++) { | |
451 | apic = local_apics[i]; | |
452 | if (apic && apic->id == dest) | |
453 | return i; | |
454 | } | |
455 | ||
456 | return -1; | |
457 | } | |
458 | ||
d3e9db93 FB |
459 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
460 | uint8_t dest, uint8_t dest_mode) | |
d592d303 | 461 | { |
d592d303 | 462 | APICState *apic_iter; |
d3e9db93 | 463 | int i; |
d592d303 FB |
464 | |
465 | if (dest_mode == 0) { | |
d3e9db93 FB |
466 | if (dest == 0xff) { |
467 | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); | |
468 | } else { | |
678e12cc | 469 | int idx = apic_find_dest(dest); |
d3e9db93 | 470 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
678e12cc GN |
471 | if (idx >= 0) |
472 | set_bit(deliver_bitmask, idx); | |
d3e9db93 | 473 | } |
d592d303 FB |
474 | } else { |
475 | /* XXX: cluster mode */ | |
d3e9db93 FB |
476 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
477 | for(i = 0; i < MAX_APICS; i++) { | |
478 | apic_iter = local_apics[i]; | |
479 | if (apic_iter) { | |
480 | if (apic_iter->dest_mode == 0xf) { | |
481 | if (dest & apic_iter->log_dest) | |
482 | set_bit(deliver_bitmask, i); | |
483 | } else if (apic_iter->dest_mode == 0x0) { | |
484 | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && | |
485 | (dest & apic_iter->log_dest & 0x0f)) { | |
486 | set_bit(deliver_bitmask, i); | |
487 | } | |
488 | } | |
489 | } | |
d592d303 FB |
490 | } |
491 | } | |
d592d303 FB |
492 | } |
493 | ||
494 | ||
b09ea7d5 | 495 | void apic_init_reset(CPUState *env) |
d592d303 | 496 | { |
b09ea7d5 | 497 | APICState *s = env->apic_state; |
d592d303 FB |
498 | int i; |
499 | ||
b09ea7d5 GN |
500 | if (!s) |
501 | return; | |
502 | ||
d592d303 FB |
503 | s->tpr = 0; |
504 | s->spurious_vec = 0xff; | |
505 | s->log_dest = 0; | |
e0fd8781 | 506 | s->dest_mode = 0xf; |
d592d303 FB |
507 | memset(s->isr, 0, sizeof(s->isr)); |
508 | memset(s->tmr, 0, sizeof(s->tmr)); | |
509 | memset(s->irr, 0, sizeof(s->irr)); | |
b4511723 FB |
510 | for(i = 0; i < APIC_LVT_NB; i++) |
511 | s->lvt[i] = 1 << 16; /* mask LVT */ | |
d592d303 FB |
512 | s->esr = 0; |
513 | memset(s->icr, 0, sizeof(s->icr)); | |
514 | s->divide_conf = 0; | |
515 | s->count_shift = 0; | |
516 | s->initial_count = 0; | |
517 | s->initial_count_load_time = 0; | |
518 | s->next_time = 0; | |
b09ea7d5 | 519 | s->wait_for_sipi = 1; |
3003b8bb | 520 | |
b09ea7d5 | 521 | env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP); |
d592d303 FB |
522 | } |
523 | ||
e0fd8781 FB |
524 | static void apic_startup(APICState *s, int vector_num) |
525 | { | |
b09ea7d5 GN |
526 | s->sipi_vector = vector_num; |
527 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); | |
528 | } | |
529 | ||
530 | void apic_sipi(CPUState *env) | |
531 | { | |
532 | APICState *s = env->apic_state; | |
533 | ||
534 | cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI); | |
535 | ||
536 | if (!s->wait_for_sipi) | |
e0fd8781 | 537 | return; |
b09ea7d5 | 538 | |
e0fd8781 | 539 | env->eip = 0; |
b09ea7d5 | 540 | cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12, |
19a2223f | 541 | env->segs[R_CS].limit, env->segs[R_CS].flags); |
ce5232c5 | 542 | env->halted = 0; |
b09ea7d5 | 543 | s->wait_for_sipi = 0; |
e0fd8781 FB |
544 | } |
545 | ||
d592d303 FB |
546 | static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
547 | uint8_t delivery_mode, uint8_t vector_num, | |
548 | uint8_t polarity, uint8_t trigger_mode) | |
549 | { | |
d3e9db93 | 550 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
d592d303 FB |
551 | int dest_shorthand = (s->icr[0] >> 18) & 3; |
552 | APICState *apic_iter; | |
553 | ||
e0fd8781 | 554 | switch (dest_shorthand) { |
d3e9db93 FB |
555 | case 0: |
556 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); | |
557 | break; | |
558 | case 1: | |
559 | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); | |
678e12cc | 560 | set_bit(deliver_bitmask, s->idx); |
d3e9db93 FB |
561 | break; |
562 | case 2: | |
563 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
564 | break; | |
565 | case 3: | |
566 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
678e12cc | 567 | reset_bit(deliver_bitmask, s->idx); |
d3e9db93 | 568 | break; |
e0fd8781 FB |
569 | } |
570 | ||
d592d303 | 571 | switch (delivery_mode) { |
d592d303 FB |
572 | case APIC_DM_INIT: |
573 | { | |
574 | int trig_mode = (s->icr[0] >> 15) & 1; | |
575 | int level = (s->icr[0] >> 14) & 1; | |
576 | if (level == 0 && trig_mode == 1) { | |
5fafdf24 | 577 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 578 | apic_iter->arb_id = apic_iter->id ); |
d592d303 FB |
579 | return; |
580 | } | |
581 | } | |
582 | break; | |
583 | ||
584 | case APIC_DM_SIPI: | |
5fafdf24 | 585 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 586 | apic_startup(apic_iter, vector_num) ); |
d592d303 FB |
587 | return; |
588 | } | |
589 | ||
d592d303 FB |
590 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
591 | trigger_mode); | |
592 | } | |
593 | ||
574bbf7b FB |
594 | int apic_get_interrupt(CPUState *env) |
595 | { | |
596 | APICState *s = env->apic_state; | |
597 | int intno; | |
598 | ||
599 | /* if the APIC is installed or enabled, we let the 8259 handle the | |
600 | IRQs */ | |
601 | if (!s) | |
602 | return -1; | |
603 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
604 | return -1; | |
3b46e624 | 605 | |
574bbf7b FB |
606 | /* XXX: spurious IRQ handling */ |
607 | intno = get_highest_priority_int(s->irr); | |
608 | if (intno < 0) | |
609 | return -1; | |
d592d303 FB |
610 | if (s->tpr && intno <= s->tpr) |
611 | return s->spurious_vec & 0xff; | |
b4511723 | 612 | reset_bit(s->irr, intno); |
574bbf7b FB |
613 | set_bit(s->isr, intno); |
614 | apic_update_irq(s); | |
615 | return intno; | |
616 | } | |
617 | ||
0e21e12b TS |
618 | int apic_accept_pic_intr(CPUState *env) |
619 | { | |
620 | APICState *s = env->apic_state; | |
621 | uint32_t lvt0; | |
622 | ||
623 | if (!s) | |
624 | return -1; | |
625 | ||
626 | lvt0 = s->lvt[APIC_LVT_LINT0]; | |
627 | ||
a5b38b51 AJ |
628 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
629 | (lvt0 & APIC_LVT_MASKED) == 0) | |
0e21e12b TS |
630 | return 1; |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
574bbf7b FB |
635 | static uint32_t apic_get_current_count(APICState *s) |
636 | { | |
637 | int64_t d; | |
638 | uint32_t val; | |
5fafdf24 | 639 | d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
574bbf7b FB |
640 | s->count_shift; |
641 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
642 | /* periodic */ | |
d592d303 | 643 | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); |
574bbf7b FB |
644 | } else { |
645 | if (d >= s->initial_count) | |
646 | val = 0; | |
647 | else | |
648 | val = s->initial_count - d; | |
649 | } | |
650 | return val; | |
651 | } | |
652 | ||
653 | static void apic_timer_update(APICState *s, int64_t current_time) | |
654 | { | |
655 | int64_t next_time, d; | |
3b46e624 | 656 | |
574bbf7b | 657 | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { |
5fafdf24 | 658 | d = (current_time - s->initial_count_load_time) >> |
574bbf7b FB |
659 | s->count_shift; |
660 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
681f8c29 AL |
661 | if (!s->initial_count) |
662 | goto no_timer; | |
d592d303 | 663 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
574bbf7b FB |
664 | } else { |
665 | if (d >= s->initial_count) | |
666 | goto no_timer; | |
d592d303 | 667 | d = (uint64_t)s->initial_count + 1; |
574bbf7b FB |
668 | } |
669 | next_time = s->initial_count_load_time + (d << s->count_shift); | |
670 | qemu_mod_timer(s->timer, next_time); | |
671 | s->next_time = next_time; | |
672 | } else { | |
673 | no_timer: | |
674 | qemu_del_timer(s->timer); | |
675 | } | |
676 | } | |
677 | ||
678 | static void apic_timer(void *opaque) | |
679 | { | |
680 | APICState *s = opaque; | |
681 | ||
a5b38b51 | 682 | apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); |
574bbf7b FB |
683 | apic_timer_update(s, s->next_time); |
684 | } | |
685 | ||
c227f099 | 686 | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
687 | { |
688 | return 0; | |
689 | } | |
690 | ||
c227f099 | 691 | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
692 | { |
693 | return 0; | |
694 | } | |
695 | ||
c227f099 | 696 | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
697 | { |
698 | } | |
699 | ||
c227f099 | 700 | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
701 | { |
702 | } | |
703 | ||
c227f099 | 704 | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
705 | { |
706 | CPUState *env; | |
707 | APICState *s; | |
708 | uint32_t val; | |
709 | int index; | |
710 | ||
711 | env = cpu_single_env; | |
712 | if (!env) | |
713 | return 0; | |
714 | s = env->apic_state; | |
715 | ||
716 | index = (addr >> 4) & 0xff; | |
717 | switch(index) { | |
718 | case 0x02: /* id */ | |
719 | val = s->id << 24; | |
720 | break; | |
721 | case 0x03: /* version */ | |
722 | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ | |
723 | break; | |
724 | case 0x08: | |
725 | val = s->tpr; | |
726 | break; | |
d592d303 FB |
727 | case 0x09: |
728 | val = apic_get_arb_pri(s); | |
729 | break; | |
574bbf7b FB |
730 | case 0x0a: |
731 | /* ppr */ | |
732 | val = apic_get_ppr(s); | |
733 | break; | |
b237db36 AJ |
734 | case 0x0b: |
735 | val = 0; | |
736 | break; | |
d592d303 FB |
737 | case 0x0d: |
738 | val = s->log_dest << 24; | |
739 | break; | |
740 | case 0x0e: | |
741 | val = s->dest_mode << 28; | |
742 | break; | |
574bbf7b FB |
743 | case 0x0f: |
744 | val = s->spurious_vec; | |
745 | break; | |
746 | case 0x10 ... 0x17: | |
747 | val = s->isr[index & 7]; | |
748 | break; | |
749 | case 0x18 ... 0x1f: | |
750 | val = s->tmr[index & 7]; | |
751 | break; | |
752 | case 0x20 ... 0x27: | |
753 | val = s->irr[index & 7]; | |
754 | break; | |
755 | case 0x28: | |
756 | val = s->esr; | |
757 | break; | |
574bbf7b FB |
758 | case 0x30: |
759 | case 0x31: | |
760 | val = s->icr[index & 1]; | |
761 | break; | |
e0fd8781 FB |
762 | case 0x32 ... 0x37: |
763 | val = s->lvt[index - 0x32]; | |
764 | break; | |
574bbf7b FB |
765 | case 0x38: |
766 | val = s->initial_count; | |
767 | break; | |
768 | case 0x39: | |
769 | val = apic_get_current_count(s); | |
770 | break; | |
771 | case 0x3e: | |
772 | val = s->divide_conf; | |
773 | break; | |
774 | default: | |
775 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
776 | val = 0; | |
777 | break; | |
778 | } | |
0a3c5921 | 779 | DPRINTF("read: " TARGET_FMT_plx " = %08x\n", addr, val); |
574bbf7b FB |
780 | return val; |
781 | } | |
782 | ||
c227f099 | 783 | static void apic_send_msi(target_phys_addr_t addr, uint32 data) |
54c96da7 MT |
784 | { |
785 | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; | |
786 | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
787 | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; | |
788 | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; | |
789 | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; | |
790 | /* XXX: Ignore redirection hint. */ | |
791 | apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode); | |
792 | } | |
793 | ||
c227f099 | 794 | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
795 | { |
796 | CPUState *env; | |
797 | APICState *s; | |
54c96da7 MT |
798 | int index = (addr >> 4) & 0xff; |
799 | if (addr > 0xfff || !index) { | |
800 | /* MSI and MMIO APIC are at the same memory location, | |
801 | * but actually not on the global bus: MSI is on PCI bus | |
802 | * APIC is connected directly to the CPU. | |
803 | * Mapping them on the global bus happens to work because | |
804 | * MSI registers are reserved in APIC MMIO and vice versa. */ | |
805 | apic_send_msi(addr, val); | |
806 | return; | |
807 | } | |
574bbf7b FB |
808 | |
809 | env = cpu_single_env; | |
810 | if (!env) | |
811 | return; | |
812 | s = env->apic_state; | |
813 | ||
0a3c5921 | 814 | DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val); |
574bbf7b | 815 | |
574bbf7b FB |
816 | switch(index) { |
817 | case 0x02: | |
818 | s->id = (val >> 24); | |
819 | break; | |
e0fd8781 FB |
820 | case 0x03: |
821 | break; | |
574bbf7b FB |
822 | case 0x08: |
823 | s->tpr = val; | |
d592d303 | 824 | apic_update_irq(s); |
574bbf7b | 825 | break; |
e0fd8781 FB |
826 | case 0x09: |
827 | case 0x0a: | |
828 | break; | |
574bbf7b FB |
829 | case 0x0b: /* EOI */ |
830 | apic_eoi(s); | |
831 | break; | |
d592d303 FB |
832 | case 0x0d: |
833 | s->log_dest = val >> 24; | |
834 | break; | |
835 | case 0x0e: | |
836 | s->dest_mode = val >> 28; | |
837 | break; | |
574bbf7b FB |
838 | case 0x0f: |
839 | s->spurious_vec = val & 0x1ff; | |
d592d303 | 840 | apic_update_irq(s); |
574bbf7b | 841 | break; |
e0fd8781 FB |
842 | case 0x10 ... 0x17: |
843 | case 0x18 ... 0x1f: | |
844 | case 0x20 ... 0x27: | |
845 | case 0x28: | |
846 | break; | |
574bbf7b | 847 | case 0x30: |
d592d303 FB |
848 | s->icr[0] = val; |
849 | apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, | |
850 | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), | |
851 | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); | |
852 | break; | |
574bbf7b | 853 | case 0x31: |
d592d303 | 854 | s->icr[1] = val; |
574bbf7b FB |
855 | break; |
856 | case 0x32 ... 0x37: | |
857 | { | |
858 | int n = index - 0x32; | |
859 | s->lvt[n] = val; | |
860 | if (n == APIC_LVT_TIMER) | |
861 | apic_timer_update(s, qemu_get_clock(vm_clock)); | |
862 | } | |
863 | break; | |
864 | case 0x38: | |
865 | s->initial_count = val; | |
866 | s->initial_count_load_time = qemu_get_clock(vm_clock); | |
867 | apic_timer_update(s, s->initial_count_load_time); | |
868 | break; | |
e0fd8781 FB |
869 | case 0x39: |
870 | break; | |
574bbf7b FB |
871 | case 0x3e: |
872 | { | |
873 | int v; | |
874 | s->divide_conf = val & 0xb; | |
875 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); | |
876 | s->count_shift = (v + 1) & 7; | |
877 | } | |
878 | break; | |
879 | default: | |
880 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
881 | break; | |
882 | } | |
883 | } | |
884 | ||
695dcf71 JQ |
885 | /* This function is only used for old state version 1 and 2 */ |
886 | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) | |
d592d303 FB |
887 | { |
888 | APICState *s = opaque; | |
889 | int i; | |
890 | ||
e6cf6a8c | 891 | if (version_id > 2) |
d592d303 FB |
892 | return -EINVAL; |
893 | ||
894 | /* XXX: what if the base changes? (registered memory regions) */ | |
895 | qemu_get_be32s(f, &s->apicbase); | |
896 | qemu_get_8s(f, &s->id); | |
897 | qemu_get_8s(f, &s->arb_id); | |
898 | qemu_get_8s(f, &s->tpr); | |
899 | qemu_get_be32s(f, &s->spurious_vec); | |
900 | qemu_get_8s(f, &s->log_dest); | |
901 | qemu_get_8s(f, &s->dest_mode); | |
902 | for (i = 0; i < 8; i++) { | |
903 | qemu_get_be32s(f, &s->isr[i]); | |
904 | qemu_get_be32s(f, &s->tmr[i]); | |
905 | qemu_get_be32s(f, &s->irr[i]); | |
906 | } | |
907 | for (i = 0; i < APIC_LVT_NB; i++) { | |
908 | qemu_get_be32s(f, &s->lvt[i]); | |
909 | } | |
910 | qemu_get_be32s(f, &s->esr); | |
911 | qemu_get_be32s(f, &s->icr[0]); | |
912 | qemu_get_be32s(f, &s->icr[1]); | |
913 | qemu_get_be32s(f, &s->divide_conf); | |
bee8d684 | 914 | s->count_shift=qemu_get_be32(f); |
d592d303 | 915 | qemu_get_be32s(f, &s->initial_count); |
bee8d684 TS |
916 | s->initial_count_load_time=qemu_get_be64(f); |
917 | s->next_time=qemu_get_be64(f); | |
e6cf6a8c FB |
918 | |
919 | if (version_id >= 2) | |
920 | qemu_get_timer(f, s->timer); | |
d592d303 FB |
921 | return 0; |
922 | } | |
574bbf7b | 923 | |
695dcf71 JQ |
924 | static const VMStateDescription vmstate_apic = { |
925 | .name = "apic", | |
926 | .version_id = 3, | |
927 | .minimum_version_id = 3, | |
928 | .minimum_version_id_old = 1, | |
929 | .load_state_old = apic_load_old, | |
930 | .fields = (VMStateField []) { | |
931 | VMSTATE_UINT32(apicbase, APICState), | |
932 | VMSTATE_UINT8(id, APICState), | |
933 | VMSTATE_UINT8(arb_id, APICState), | |
934 | VMSTATE_UINT8(tpr, APICState), | |
935 | VMSTATE_UINT32(spurious_vec, APICState), | |
936 | VMSTATE_UINT8(log_dest, APICState), | |
937 | VMSTATE_UINT8(dest_mode, APICState), | |
938 | VMSTATE_UINT32_ARRAY(isr, APICState, 8), | |
939 | VMSTATE_UINT32_ARRAY(tmr, APICState, 8), | |
940 | VMSTATE_UINT32_ARRAY(irr, APICState, 8), | |
941 | VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), | |
942 | VMSTATE_UINT32(esr, APICState), | |
943 | VMSTATE_UINT32_ARRAY(icr, APICState, 2), | |
944 | VMSTATE_UINT32(divide_conf, APICState), | |
945 | VMSTATE_INT32(count_shift, APICState), | |
946 | VMSTATE_UINT32(initial_count, APICState), | |
947 | VMSTATE_INT64(initial_count_load_time, APICState), | |
948 | VMSTATE_INT64(next_time, APICState), | |
949 | VMSTATE_TIMER(timer, APICState), | |
950 | VMSTATE_END_OF_LIST() | |
951 | } | |
952 | }; | |
953 | ||
d592d303 FB |
954 | static void apic_reset(void *opaque) |
955 | { | |
956 | APICState *s = opaque; | |
4c0960c0 | 957 | int bsp; |
fec5fa02 | 958 | |
4c0960c0 | 959 | bsp = cpu_is_bsp(s->cpu_env); |
fec5fa02 | 960 | s->apicbase = 0xfee00000 | |
678e12cc | 961 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; |
fec5fa02 | 962 | |
b09ea7d5 GN |
963 | cpu_reset(s->cpu_env); |
964 | apic_init_reset(s->cpu_env); | |
0e21e12b | 965 | |
678e12cc | 966 | if (bsp) { |
a5b38b51 AJ |
967 | /* |
968 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization | |
969 | * time typically by BIOS, so PIC interrupt can be delivered to the | |
970 | * processor when local APIC is enabled. | |
971 | */ | |
972 | s->lvt[APIC_LVT_LINT0] = 0x700; | |
973 | } | |
d592d303 | 974 | } |
574bbf7b | 975 | |
d60efc6b | 976 | static CPUReadMemoryFunc * const apic_mem_read[3] = { |
574bbf7b FB |
977 | apic_mem_readb, |
978 | apic_mem_readw, | |
979 | apic_mem_readl, | |
980 | }; | |
981 | ||
d60efc6b | 982 | static CPUWriteMemoryFunc * const apic_mem_write[3] = { |
574bbf7b FB |
983 | apic_mem_writeb, |
984 | apic_mem_writew, | |
985 | apic_mem_writel, | |
986 | }; | |
987 | ||
988 | int apic_init(CPUState *env) | |
989 | { | |
990 | APICState *s; | |
574bbf7b | 991 | |
678e12cc | 992 | if (last_apic_idx >= MAX_APICS) |
d3e9db93 | 993 | return -1; |
d592d303 | 994 | s = qemu_mallocz(sizeof(APICState)); |
574bbf7b | 995 | env->apic_state = s; |
678e12cc GN |
996 | s->idx = last_apic_idx++; |
997 | s->id = env->cpuid_apic_id; | |
574bbf7b | 998 | s->cpu_env = env; |
574bbf7b | 999 | |
54c96da7 | 1000 | msix_supported = 1; |
0e21e12b | 1001 | |
d592d303 | 1002 | /* XXX: mapping more APICs at the same memory location */ |
574bbf7b FB |
1003 | if (apic_io_memory == 0) { |
1004 | /* NOTE: the APIC is directly connected to the CPU - it is not | |
1005 | on the global memory bus. */ | |
1eed09cb | 1006 | apic_io_memory = cpu_register_io_memory(apic_mem_read, |
574bbf7b | 1007 | apic_mem_write, NULL); |
54c96da7 MT |
1008 | /* XXX: what if the base changes? */ |
1009 | cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE, | |
d592d303 | 1010 | apic_io_memory); |
574bbf7b FB |
1011 | } |
1012 | s->timer = qemu_new_timer(vm_clock, apic_timer, s); | |
d592d303 | 1013 | |
695dcf71 | 1014 | vmstate_register(s->idx, &vmstate_apic, s); |
a08d4367 | 1015 | qemu_register_reset(apic_reset, s); |
3b46e624 | 1016 | |
678e12cc | 1017 | local_apics[s->idx] = s; |
d592d303 FB |
1018 | return 0; |
1019 | } |