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574bbf7b FB |
1 | /* |
2 | * APIC support | |
5fafdf24 | 3 | * |
574bbf7b FB |
4 | * Copyright (c) 2004-2005 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
574bbf7b | 18 | */ |
dae01685 | 19 | #include "apic_internal.h" |
aa28b9bf | 20 | #include "apic.h" |
0280b571 | 21 | #include "ioapic.h" |
08a82ac0 | 22 | #include "msi.h" |
bb7e7293 | 23 | #include "host-utils.h" |
d8023f31 | 24 | #include "trace.h" |
d96e1737 | 25 | #include "pc.h" |
9886c23a | 26 | #include "apic-msidef.h" |
574bbf7b | 27 | |
d3e9db93 FB |
28 | #define MAX_APIC_WORDS 8 |
29 | ||
e5ad936b JK |
30 | #define SYNC_FROM_VAPIC 0x1 |
31 | #define SYNC_TO_VAPIC 0x2 | |
32 | #define SYNC_ISR_IRR_TO_VAPIC 0x4 | |
33 | ||
dae01685 | 34 | static APICCommonState *local_apics[MAX_APICS + 1]; |
73822ec8 | 35 | |
dae01685 JK |
36 | static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); |
37 | static void apic_update_irq(APICCommonState *s); | |
610626af AL |
38 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
39 | uint8_t dest, uint8_t dest_mode); | |
d592d303 | 40 | |
3b63c04e AJ |
41 | /* Find first bit starting from msb */ |
42 | static int fls_bit(uint32_t value) | |
43 | { | |
44 | return 31 - clz32(value); | |
45 | } | |
46 | ||
e95f5491 | 47 | /* Find first bit starting from lsb */ |
d3e9db93 FB |
48 | static int ffs_bit(uint32_t value) |
49 | { | |
bb7e7293 | 50 | return ctz32(value); |
d3e9db93 FB |
51 | } |
52 | ||
53 | static inline void set_bit(uint32_t *tab, int index) | |
54 | { | |
55 | int i, mask; | |
56 | i = index >> 5; | |
57 | mask = 1 << (index & 0x1f); | |
58 | tab[i] |= mask; | |
59 | } | |
60 | ||
61 | static inline void reset_bit(uint32_t *tab, int index) | |
62 | { | |
63 | int i, mask; | |
64 | i = index >> 5; | |
65 | mask = 1 << (index & 0x1f); | |
66 | tab[i] &= ~mask; | |
67 | } | |
68 | ||
73822ec8 AL |
69 | static inline int get_bit(uint32_t *tab, int index) |
70 | { | |
71 | int i, mask; | |
72 | i = index >> 5; | |
73 | mask = 1 << (index & 0x1f); | |
74 | return !!(tab[i] & mask); | |
75 | } | |
76 | ||
e5ad936b JK |
77 | /* return -1 if no bit is set */ |
78 | static int get_highest_priority_int(uint32_t *tab) | |
79 | { | |
80 | int i; | |
81 | for (i = 7; i >= 0; i--) { | |
82 | if (tab[i] != 0) { | |
83 | return i * 32 + fls_bit(tab[i]); | |
84 | } | |
85 | } | |
86 | return -1; | |
87 | } | |
88 | ||
89 | static void apic_sync_vapic(APICCommonState *s, int sync_type) | |
90 | { | |
91 | VAPICState vapic_state; | |
92 | size_t length; | |
93 | off_t start; | |
94 | int vector; | |
95 | ||
96 | if (!s->vapic_paddr) { | |
97 | return; | |
98 | } | |
99 | if (sync_type & SYNC_FROM_VAPIC) { | |
100 | cpu_physical_memory_rw(s->vapic_paddr, (void *)&vapic_state, | |
101 | sizeof(vapic_state), 0); | |
102 | s->tpr = vapic_state.tpr; | |
103 | } | |
104 | if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) { | |
105 | start = offsetof(VAPICState, isr); | |
106 | length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); | |
107 | ||
108 | if (sync_type & SYNC_TO_VAPIC) { | |
109 | assert(qemu_cpu_is_self(s->cpu_env)); | |
110 | ||
111 | vapic_state.tpr = s->tpr; | |
112 | vapic_state.enabled = 1; | |
113 | start = 0; | |
114 | length = sizeof(VAPICState); | |
115 | } | |
116 | ||
117 | vector = get_highest_priority_int(s->isr); | |
118 | if (vector < 0) { | |
119 | vector = 0; | |
120 | } | |
121 | vapic_state.isr = vector & 0xf0; | |
122 | ||
123 | vapic_state.zero = 0; | |
124 | ||
125 | vector = get_highest_priority_int(s->irr); | |
126 | if (vector < 0) { | |
127 | vector = 0; | |
128 | } | |
129 | vapic_state.irr = vector & 0xff; | |
130 | ||
131 | cpu_physical_memory_write_rom(s->vapic_paddr + start, | |
132 | ((void *)&vapic_state) + start, length); | |
133 | } | |
134 | } | |
135 | ||
136 | static void apic_vapic_base_update(APICCommonState *s) | |
137 | { | |
138 | apic_sync_vapic(s, SYNC_TO_VAPIC); | |
139 | } | |
140 | ||
dae01685 | 141 | static void apic_local_deliver(APICCommonState *s, int vector) |
a5b38b51 | 142 | { |
a5b38b51 AJ |
143 | uint32_t lvt = s->lvt[vector]; |
144 | int trigger_mode; | |
145 | ||
d8023f31 BS |
146 | trace_apic_local_deliver(vector, (lvt >> 8) & 7); |
147 | ||
a5b38b51 AJ |
148 | if (lvt & APIC_LVT_MASKED) |
149 | return; | |
150 | ||
151 | switch ((lvt >> 8) & 7) { | |
152 | case APIC_DM_SMI: | |
cf6d64bf | 153 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); |
a5b38b51 AJ |
154 | break; |
155 | ||
156 | case APIC_DM_NMI: | |
cf6d64bf | 157 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); |
a5b38b51 AJ |
158 | break; |
159 | ||
160 | case APIC_DM_EXTINT: | |
cf6d64bf | 161 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
a5b38b51 AJ |
162 | break; |
163 | ||
164 | case APIC_DM_FIXED: | |
165 | trigger_mode = APIC_TRIGGER_EDGE; | |
166 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && | |
167 | (lvt & APIC_LVT_LEVEL_TRIGGER)) | |
168 | trigger_mode = APIC_TRIGGER_LEVEL; | |
169 | apic_set_irq(s, lvt & 0xff, trigger_mode); | |
170 | } | |
171 | } | |
172 | ||
92a16d7a | 173 | void apic_deliver_pic_intr(DeviceState *d, int level) |
1a7de94a | 174 | { |
dae01685 | 175 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
92a16d7a | 176 | |
cf6d64bf BS |
177 | if (level) { |
178 | apic_local_deliver(s, APIC_LVT_LINT0); | |
179 | } else { | |
1a7de94a AJ |
180 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
181 | ||
182 | switch ((lvt >> 8) & 7) { | |
183 | case APIC_DM_FIXED: | |
184 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) | |
185 | break; | |
186 | reset_bit(s->irr, lvt & 0xff); | |
187 | /* fall through */ | |
188 | case APIC_DM_EXTINT: | |
cf6d64bf | 189 | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
1a7de94a AJ |
190 | break; |
191 | } | |
192 | } | |
193 | } | |
194 | ||
dae01685 | 195 | static void apic_external_nmi(APICCommonState *s) |
02c09195 | 196 | { |
02c09195 JK |
197 | apic_local_deliver(s, APIC_LVT_LINT1); |
198 | } | |
199 | ||
d3e9db93 FB |
200 | #define foreach_apic(apic, deliver_bitmask, code) \ |
201 | {\ | |
202 | int __i, __j, __mask;\ | |
203 | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ | |
204 | __mask = deliver_bitmask[__i];\ | |
205 | if (__mask) {\ | |
206 | for(__j = 0; __j < 32; __j++) {\ | |
207 | if (__mask & (1 << __j)) {\ | |
208 | apic = local_apics[__i * 32 + __j];\ | |
209 | if (apic) {\ | |
210 | code;\ | |
211 | }\ | |
212 | }\ | |
213 | }\ | |
214 | }\ | |
215 | }\ | |
216 | } | |
217 | ||
5fafdf24 | 218 | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
1f6f408c | 219 | uint8_t delivery_mode, uint8_t vector_num, |
d592d303 FB |
220 | uint8_t trigger_mode) |
221 | { | |
dae01685 | 222 | APICCommonState *apic_iter; |
d592d303 FB |
223 | |
224 | switch (delivery_mode) { | |
225 | case APIC_DM_LOWPRI: | |
8dd69b8f | 226 | /* XXX: search for focus processor, arbitration */ |
d3e9db93 FB |
227 | { |
228 | int i, d; | |
229 | d = -1; | |
230 | for(i = 0; i < MAX_APIC_WORDS; i++) { | |
231 | if (deliver_bitmask[i]) { | |
232 | d = i * 32 + ffs_bit(deliver_bitmask[i]); | |
233 | break; | |
234 | } | |
235 | } | |
236 | if (d >= 0) { | |
237 | apic_iter = local_apics[d]; | |
238 | if (apic_iter) { | |
239 | apic_set_irq(apic_iter, vector_num, trigger_mode); | |
240 | } | |
241 | } | |
8dd69b8f | 242 | } |
d3e9db93 | 243 | return; |
8dd69b8f | 244 | |
d592d303 | 245 | case APIC_DM_FIXED: |
d592d303 FB |
246 | break; |
247 | ||
248 | case APIC_DM_SMI: | |
e2eb9d3e AJ |
249 | foreach_apic(apic_iter, deliver_bitmask, |
250 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); | |
251 | return; | |
252 | ||
d592d303 | 253 | case APIC_DM_NMI: |
e2eb9d3e AJ |
254 | foreach_apic(apic_iter, deliver_bitmask, |
255 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); | |
256 | return; | |
d592d303 FB |
257 | |
258 | case APIC_DM_INIT: | |
259 | /* normal INIT IPI sent to processors */ | |
5fafdf24 | 260 | foreach_apic(apic_iter, deliver_bitmask, |
b09ea7d5 | 261 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
d592d303 | 262 | return; |
3b46e624 | 263 | |
d592d303 | 264 | case APIC_DM_EXTINT: |
b1fc0348 | 265 | /* handled in I/O APIC code */ |
d592d303 FB |
266 | break; |
267 | ||
268 | default: | |
269 | return; | |
270 | } | |
271 | ||
5fafdf24 | 272 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 273 | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
d592d303 | 274 | } |
574bbf7b | 275 | |
1f6f408c JK |
276 | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, |
277 | uint8_t vector_num, uint8_t trigger_mode) | |
610626af AL |
278 | { |
279 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; | |
280 | ||
d8023f31 | 281 | trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
1f6f408c | 282 | trigger_mode); |
d8023f31 | 283 | |
610626af | 284 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
1f6f408c | 285 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
610626af AL |
286 | } |
287 | ||
dae01685 | 288 | static void apic_set_base(APICCommonState *s, uint64_t val) |
574bbf7b | 289 | { |
5fafdf24 | 290 | s->apicbase = (val & 0xfffff000) | |
574bbf7b FB |
291 | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
292 | /* if disabled, cannot be enabled again */ | |
293 | if (!(val & MSR_IA32_APICBASE_ENABLE)) { | |
294 | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; | |
0e26b7b8 | 295 | cpu_clear_apic_feature(s->cpu_env); |
574bbf7b FB |
296 | s->spurious_vec &= ~APIC_SV_ENABLE; |
297 | } | |
298 | } | |
299 | ||
dae01685 | 300 | static void apic_set_tpr(APICCommonState *s, uint8_t val) |
574bbf7b | 301 | { |
e5ad936b JK |
302 | /* Updates from cr8 are ignored while the VAPIC is active */ |
303 | if (!s->vapic_paddr) { | |
304 | s->tpr = val << 4; | |
305 | apic_update_irq(s); | |
306 | } | |
9230e66e FB |
307 | } |
308 | ||
e5ad936b | 309 | static uint8_t apic_get_tpr(APICCommonState *s) |
d592d303 | 310 | { |
e5ad936b JK |
311 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
312 | return s->tpr >> 4; | |
d592d303 FB |
313 | } |
314 | ||
dae01685 | 315 | static int apic_get_ppr(APICCommonState *s) |
574bbf7b FB |
316 | { |
317 | int tpr, isrv, ppr; | |
318 | ||
319 | tpr = (s->tpr >> 4); | |
320 | isrv = get_highest_priority_int(s->isr); | |
321 | if (isrv < 0) | |
322 | isrv = 0; | |
323 | isrv >>= 4; | |
324 | if (tpr >= isrv) | |
325 | ppr = s->tpr; | |
326 | else | |
327 | ppr = isrv << 4; | |
328 | return ppr; | |
329 | } | |
330 | ||
dae01685 | 331 | static int apic_get_arb_pri(APICCommonState *s) |
d592d303 FB |
332 | { |
333 | /* XXX: arbitration */ | |
334 | return 0; | |
335 | } | |
336 | ||
0fbfbb59 GN |
337 | |
338 | /* | |
339 | * <0 - low prio interrupt, | |
340 | * 0 - no interrupt, | |
341 | * >0 - interrupt number | |
342 | */ | |
dae01685 | 343 | static int apic_irq_pending(APICCommonState *s) |
574bbf7b | 344 | { |
d592d303 | 345 | int irrv, ppr; |
574bbf7b | 346 | irrv = get_highest_priority_int(s->irr); |
0fbfbb59 GN |
347 | if (irrv < 0) { |
348 | return 0; | |
349 | } | |
d592d303 | 350 | ppr = apic_get_ppr(s); |
0fbfbb59 GN |
351 | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { |
352 | return -1; | |
353 | } | |
354 | ||
355 | return irrv; | |
356 | } | |
357 | ||
358 | /* signal the CPU if an irq is pending */ | |
dae01685 | 359 | static void apic_update_irq(APICCommonState *s) |
0fbfbb59 GN |
360 | { |
361 | if (!(s->spurious_vec & APIC_SV_ENABLE)) { | |
574bbf7b | 362 | return; |
0fbfbb59 GN |
363 | } |
364 | if (apic_irq_pending(s) > 0) { | |
365 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); | |
366 | } | |
574bbf7b FB |
367 | } |
368 | ||
e5ad936b JK |
369 | void apic_poll_irq(DeviceState *d) |
370 | { | |
371 | APICCommonState *s = APIC_COMMON(d); | |
372 | ||
373 | apic_sync_vapic(s, SYNC_FROM_VAPIC); | |
374 | apic_update_irq(s); | |
375 | } | |
376 | ||
dae01685 | 377 | static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) |
574bbf7b | 378 | { |
343270ea | 379 | apic_report_irq_delivered(!get_bit(s->irr, vector_num)); |
73822ec8 | 380 | |
574bbf7b FB |
381 | set_bit(s->irr, vector_num); |
382 | if (trigger_mode) | |
383 | set_bit(s->tmr, vector_num); | |
384 | else | |
385 | reset_bit(s->tmr, vector_num); | |
e5ad936b JK |
386 | if (s->vapic_paddr) { |
387 | apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); | |
388 | /* | |
389 | * The vcpu thread needs to see the new IRR before we pull its current | |
390 | * TPR value. That way, if we miss a lowering of the TRP, the guest | |
391 | * has the chance to notice the new IRR and poll for IRQs on its own. | |
392 | */ | |
393 | smp_wmb(); | |
394 | apic_sync_vapic(s, SYNC_FROM_VAPIC); | |
395 | } | |
574bbf7b FB |
396 | apic_update_irq(s); |
397 | } | |
398 | ||
dae01685 | 399 | static void apic_eoi(APICCommonState *s) |
574bbf7b FB |
400 | { |
401 | int isrv; | |
402 | isrv = get_highest_priority_int(s->isr); | |
403 | if (isrv < 0) | |
404 | return; | |
405 | reset_bit(s->isr, isrv); | |
0280b571 JK |
406 | if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) { |
407 | ioapic_eoi_broadcast(isrv); | |
408 | } | |
e5ad936b | 409 | apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); |
574bbf7b FB |
410 | apic_update_irq(s); |
411 | } | |
412 | ||
678e12cc GN |
413 | static int apic_find_dest(uint8_t dest) |
414 | { | |
dae01685 | 415 | APICCommonState *apic = local_apics[dest]; |
678e12cc GN |
416 | int i; |
417 | ||
418 | if (apic && apic->id == dest) | |
419 | return dest; /* shortcut in case apic->id == apic->idx */ | |
420 | ||
421 | for (i = 0; i < MAX_APICS; i++) { | |
422 | apic = local_apics[i]; | |
423 | if (apic && apic->id == dest) | |
424 | return i; | |
b538e53e AW |
425 | if (!apic) |
426 | break; | |
678e12cc GN |
427 | } |
428 | ||
429 | return -1; | |
430 | } | |
431 | ||
d3e9db93 FB |
432 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
433 | uint8_t dest, uint8_t dest_mode) | |
d592d303 | 434 | { |
dae01685 | 435 | APICCommonState *apic_iter; |
d3e9db93 | 436 | int i; |
d592d303 FB |
437 | |
438 | if (dest_mode == 0) { | |
d3e9db93 FB |
439 | if (dest == 0xff) { |
440 | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); | |
441 | } else { | |
678e12cc | 442 | int idx = apic_find_dest(dest); |
d3e9db93 | 443 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
678e12cc GN |
444 | if (idx >= 0) |
445 | set_bit(deliver_bitmask, idx); | |
d3e9db93 | 446 | } |
d592d303 FB |
447 | } else { |
448 | /* XXX: cluster mode */ | |
d3e9db93 FB |
449 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
450 | for(i = 0; i < MAX_APICS; i++) { | |
451 | apic_iter = local_apics[i]; | |
452 | if (apic_iter) { | |
453 | if (apic_iter->dest_mode == 0xf) { | |
454 | if (dest & apic_iter->log_dest) | |
455 | set_bit(deliver_bitmask, i); | |
456 | } else if (apic_iter->dest_mode == 0x0) { | |
457 | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && | |
458 | (dest & apic_iter->log_dest & 0x0f)) { | |
459 | set_bit(deliver_bitmask, i); | |
460 | } | |
461 | } | |
b538e53e AW |
462 | } else { |
463 | break; | |
d3e9db93 | 464 | } |
d592d303 FB |
465 | } |
466 | } | |
d592d303 FB |
467 | } |
468 | ||
dae01685 | 469 | static void apic_startup(APICCommonState *s, int vector_num) |
e0fd8781 | 470 | { |
b09ea7d5 GN |
471 | s->sipi_vector = vector_num; |
472 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); | |
473 | } | |
474 | ||
92a16d7a | 475 | void apic_sipi(DeviceState *d) |
b09ea7d5 | 476 | { |
dae01685 | 477 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
92a16d7a | 478 | |
4a942cea | 479 | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
b09ea7d5 GN |
480 | |
481 | if (!s->wait_for_sipi) | |
e0fd8781 | 482 | return; |
0e26b7b8 | 483 | cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); |
b09ea7d5 | 484 | s->wait_for_sipi = 0; |
e0fd8781 FB |
485 | } |
486 | ||
92a16d7a | 487 | static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, |
d592d303 | 488 | uint8_t delivery_mode, uint8_t vector_num, |
1f6f408c | 489 | uint8_t trigger_mode) |
d592d303 | 490 | { |
dae01685 | 491 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
d3e9db93 | 492 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
d592d303 | 493 | int dest_shorthand = (s->icr[0] >> 18) & 3; |
dae01685 | 494 | APICCommonState *apic_iter; |
d592d303 | 495 | |
e0fd8781 | 496 | switch (dest_shorthand) { |
d3e9db93 FB |
497 | case 0: |
498 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); | |
499 | break; | |
500 | case 1: | |
501 | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); | |
678e12cc | 502 | set_bit(deliver_bitmask, s->idx); |
d3e9db93 FB |
503 | break; |
504 | case 2: | |
505 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
506 | break; | |
507 | case 3: | |
508 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
678e12cc | 509 | reset_bit(deliver_bitmask, s->idx); |
d3e9db93 | 510 | break; |
e0fd8781 FB |
511 | } |
512 | ||
d592d303 | 513 | switch (delivery_mode) { |
d592d303 FB |
514 | case APIC_DM_INIT: |
515 | { | |
516 | int trig_mode = (s->icr[0] >> 15) & 1; | |
517 | int level = (s->icr[0] >> 14) & 1; | |
518 | if (level == 0 && trig_mode == 1) { | |
5fafdf24 | 519 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 520 | apic_iter->arb_id = apic_iter->id ); |
d592d303 FB |
521 | return; |
522 | } | |
523 | } | |
524 | break; | |
525 | ||
526 | case APIC_DM_SIPI: | |
5fafdf24 | 527 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 528 | apic_startup(apic_iter, vector_num) ); |
d592d303 FB |
529 | return; |
530 | } | |
531 | ||
1f6f408c | 532 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
d592d303 FB |
533 | } |
534 | ||
a94820dd JK |
535 | static bool apic_check_pic(APICCommonState *s) |
536 | { | |
537 | if (!apic_accept_pic_intr(&s->busdev.qdev) || !pic_get_output(isa_pic)) { | |
538 | return false; | |
539 | } | |
540 | apic_deliver_pic_intr(&s->busdev.qdev, 1); | |
541 | return true; | |
542 | } | |
543 | ||
92a16d7a | 544 | int apic_get_interrupt(DeviceState *d) |
574bbf7b | 545 | { |
dae01685 | 546 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
574bbf7b FB |
547 | int intno; |
548 | ||
549 | /* if the APIC is installed or enabled, we let the 8259 handle the | |
550 | IRQs */ | |
551 | if (!s) | |
552 | return -1; | |
553 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
554 | return -1; | |
3b46e624 | 555 | |
e5ad936b | 556 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
0fbfbb59 GN |
557 | intno = apic_irq_pending(s); |
558 | ||
559 | if (intno == 0) { | |
e5ad936b | 560 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
574bbf7b | 561 | return -1; |
0fbfbb59 | 562 | } else if (intno < 0) { |
e5ad936b | 563 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
d592d303 | 564 | return s->spurious_vec & 0xff; |
0fbfbb59 | 565 | } |
b4511723 | 566 | reset_bit(s->irr, intno); |
574bbf7b | 567 | set_bit(s->isr, intno); |
e5ad936b | 568 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
3db3659b JK |
569 | |
570 | /* re-inject if there is still a pending PIC interrupt */ | |
a94820dd | 571 | apic_check_pic(s); |
3db3659b | 572 | |
574bbf7b | 573 | apic_update_irq(s); |
3db3659b | 574 | |
574bbf7b FB |
575 | return intno; |
576 | } | |
577 | ||
92a16d7a | 578 | int apic_accept_pic_intr(DeviceState *d) |
0e21e12b | 579 | { |
dae01685 | 580 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
0e21e12b TS |
581 | uint32_t lvt0; |
582 | ||
583 | if (!s) | |
584 | return -1; | |
585 | ||
586 | lvt0 = s->lvt[APIC_LVT_LINT0]; | |
587 | ||
a5b38b51 AJ |
588 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
589 | (lvt0 & APIC_LVT_MASKED) == 0) | |
0e21e12b TS |
590 | return 1; |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
dae01685 | 595 | static uint32_t apic_get_current_count(APICCommonState *s) |
574bbf7b FB |
596 | { |
597 | int64_t d; | |
598 | uint32_t val; | |
74475455 | 599 | d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >> |
574bbf7b FB |
600 | s->count_shift; |
601 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
602 | /* periodic */ | |
d592d303 | 603 | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); |
574bbf7b FB |
604 | } else { |
605 | if (d >= s->initial_count) | |
606 | val = 0; | |
607 | else | |
608 | val = s->initial_count - d; | |
609 | } | |
610 | return val; | |
611 | } | |
612 | ||
dae01685 | 613 | static void apic_timer_update(APICCommonState *s, int64_t current_time) |
574bbf7b | 614 | { |
7a380ca3 JK |
615 | if (apic_next_timer(s, current_time)) { |
616 | qemu_mod_timer(s->timer, s->next_time); | |
574bbf7b | 617 | } else { |
574bbf7b FB |
618 | qemu_del_timer(s->timer); |
619 | } | |
620 | } | |
621 | ||
622 | static void apic_timer(void *opaque) | |
623 | { | |
dae01685 | 624 | APICCommonState *s = opaque; |
574bbf7b | 625 | |
cf6d64bf | 626 | apic_local_deliver(s, APIC_LVT_TIMER); |
574bbf7b FB |
627 | apic_timer_update(s, s->next_time); |
628 | } | |
629 | ||
c227f099 | 630 | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
631 | { |
632 | return 0; | |
633 | } | |
634 | ||
c227f099 | 635 | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
636 | { |
637 | return 0; | |
638 | } | |
639 | ||
c227f099 | 640 | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
641 | { |
642 | } | |
643 | ||
c227f099 | 644 | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
645 | { |
646 | } | |
647 | ||
c227f099 | 648 | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
574bbf7b | 649 | { |
92a16d7a | 650 | DeviceState *d; |
dae01685 | 651 | APICCommonState *s; |
574bbf7b FB |
652 | uint32_t val; |
653 | int index; | |
654 | ||
92a16d7a BS |
655 | d = cpu_get_current_apic(); |
656 | if (!d) { | |
574bbf7b | 657 | return 0; |
0e26b7b8 | 658 | } |
dae01685 | 659 | s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
574bbf7b FB |
660 | |
661 | index = (addr >> 4) & 0xff; | |
662 | switch(index) { | |
663 | case 0x02: /* id */ | |
664 | val = s->id << 24; | |
665 | break; | |
666 | case 0x03: /* version */ | |
667 | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ | |
668 | break; | |
669 | case 0x08: | |
e5ad936b JK |
670 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
671 | if (apic_report_tpr_access) { | |
672 | cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ); | |
673 | } | |
574bbf7b FB |
674 | val = s->tpr; |
675 | break; | |
d592d303 FB |
676 | case 0x09: |
677 | val = apic_get_arb_pri(s); | |
678 | break; | |
574bbf7b FB |
679 | case 0x0a: |
680 | /* ppr */ | |
681 | val = apic_get_ppr(s); | |
682 | break; | |
b237db36 AJ |
683 | case 0x0b: |
684 | val = 0; | |
685 | break; | |
d592d303 FB |
686 | case 0x0d: |
687 | val = s->log_dest << 24; | |
688 | break; | |
689 | case 0x0e: | |
690 | val = s->dest_mode << 28; | |
691 | break; | |
574bbf7b FB |
692 | case 0x0f: |
693 | val = s->spurious_vec; | |
694 | break; | |
695 | case 0x10 ... 0x17: | |
696 | val = s->isr[index & 7]; | |
697 | break; | |
698 | case 0x18 ... 0x1f: | |
699 | val = s->tmr[index & 7]; | |
700 | break; | |
701 | case 0x20 ... 0x27: | |
702 | val = s->irr[index & 7]; | |
703 | break; | |
704 | case 0x28: | |
705 | val = s->esr; | |
706 | break; | |
574bbf7b FB |
707 | case 0x30: |
708 | case 0x31: | |
709 | val = s->icr[index & 1]; | |
710 | break; | |
e0fd8781 FB |
711 | case 0x32 ... 0x37: |
712 | val = s->lvt[index - 0x32]; | |
713 | break; | |
574bbf7b FB |
714 | case 0x38: |
715 | val = s->initial_count; | |
716 | break; | |
717 | case 0x39: | |
718 | val = apic_get_current_count(s); | |
719 | break; | |
720 | case 0x3e: | |
721 | val = s->divide_conf; | |
722 | break; | |
723 | default: | |
724 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
725 | val = 0; | |
726 | break; | |
727 | } | |
d8023f31 | 728 | trace_apic_mem_readl(addr, val); |
574bbf7b FB |
729 | return val; |
730 | } | |
731 | ||
f5095c63 | 732 | static void apic_send_msi(target_phys_addr_t addr, uint32_t data) |
54c96da7 MT |
733 | { |
734 | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; | |
735 | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
736 | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; | |
737 | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; | |
738 | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; | |
739 | /* XXX: Ignore redirection hint. */ | |
1f6f408c | 740 | apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); |
54c96da7 MT |
741 | } |
742 | ||
c227f099 | 743 | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b | 744 | { |
92a16d7a | 745 | DeviceState *d; |
dae01685 | 746 | APICCommonState *s; |
54c96da7 MT |
747 | int index = (addr >> 4) & 0xff; |
748 | if (addr > 0xfff || !index) { | |
749 | /* MSI and MMIO APIC are at the same memory location, | |
750 | * but actually not on the global bus: MSI is on PCI bus | |
751 | * APIC is connected directly to the CPU. | |
752 | * Mapping them on the global bus happens to work because | |
753 | * MSI registers are reserved in APIC MMIO and vice versa. */ | |
754 | apic_send_msi(addr, val); | |
755 | return; | |
756 | } | |
574bbf7b | 757 | |
92a16d7a BS |
758 | d = cpu_get_current_apic(); |
759 | if (!d) { | |
574bbf7b | 760 | return; |
0e26b7b8 | 761 | } |
dae01685 | 762 | s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
574bbf7b | 763 | |
d8023f31 | 764 | trace_apic_mem_writel(addr, val); |
574bbf7b | 765 | |
574bbf7b FB |
766 | switch(index) { |
767 | case 0x02: | |
768 | s->id = (val >> 24); | |
769 | break; | |
e0fd8781 FB |
770 | case 0x03: |
771 | break; | |
574bbf7b | 772 | case 0x08: |
e5ad936b JK |
773 | if (apic_report_tpr_access) { |
774 | cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE); | |
775 | } | |
574bbf7b | 776 | s->tpr = val; |
e5ad936b | 777 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
d592d303 | 778 | apic_update_irq(s); |
574bbf7b | 779 | break; |
e0fd8781 FB |
780 | case 0x09: |
781 | case 0x0a: | |
782 | break; | |
574bbf7b FB |
783 | case 0x0b: /* EOI */ |
784 | apic_eoi(s); | |
785 | break; | |
d592d303 FB |
786 | case 0x0d: |
787 | s->log_dest = val >> 24; | |
788 | break; | |
789 | case 0x0e: | |
790 | s->dest_mode = val >> 28; | |
791 | break; | |
574bbf7b FB |
792 | case 0x0f: |
793 | s->spurious_vec = val & 0x1ff; | |
d592d303 | 794 | apic_update_irq(s); |
574bbf7b | 795 | break; |
e0fd8781 FB |
796 | case 0x10 ... 0x17: |
797 | case 0x18 ... 0x1f: | |
798 | case 0x20 ... 0x27: | |
799 | case 0x28: | |
800 | break; | |
574bbf7b | 801 | case 0x30: |
d592d303 | 802 | s->icr[0] = val; |
92a16d7a | 803 | apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
d592d303 | 804 | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
1f6f408c | 805 | (s->icr[0] >> 15) & 1); |
d592d303 | 806 | break; |
574bbf7b | 807 | case 0x31: |
d592d303 | 808 | s->icr[1] = val; |
574bbf7b FB |
809 | break; |
810 | case 0x32 ... 0x37: | |
811 | { | |
812 | int n = index - 0x32; | |
813 | s->lvt[n] = val; | |
a94820dd | 814 | if (n == APIC_LVT_TIMER) { |
74475455 | 815 | apic_timer_update(s, qemu_get_clock_ns(vm_clock)); |
a94820dd JK |
816 | } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) { |
817 | apic_update_irq(s); | |
818 | } | |
574bbf7b FB |
819 | } |
820 | break; | |
821 | case 0x38: | |
822 | s->initial_count = val; | |
74475455 | 823 | s->initial_count_load_time = qemu_get_clock_ns(vm_clock); |
574bbf7b FB |
824 | apic_timer_update(s, s->initial_count_load_time); |
825 | break; | |
e0fd8781 FB |
826 | case 0x39: |
827 | break; | |
574bbf7b FB |
828 | case 0x3e: |
829 | { | |
830 | int v; | |
831 | s->divide_conf = val & 0xb; | |
832 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); | |
833 | s->count_shift = (v + 1) & 7; | |
834 | } | |
835 | break; | |
836 | default: | |
837 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
838 | break; | |
839 | } | |
840 | } | |
841 | ||
e5ad936b JK |
842 | static void apic_pre_save(APICCommonState *s) |
843 | { | |
844 | apic_sync_vapic(s, SYNC_FROM_VAPIC); | |
845 | } | |
846 | ||
7a380ca3 JK |
847 | static void apic_post_load(APICCommonState *s) |
848 | { | |
849 | if (s->timer_expiry != -1) { | |
850 | qemu_mod_timer(s->timer, s->timer_expiry); | |
851 | } else { | |
852 | qemu_del_timer(s->timer); | |
853 | } | |
854 | } | |
855 | ||
312b4234 AK |
856 | static const MemoryRegionOps apic_io_ops = { |
857 | .old_mmio = { | |
858 | .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, | |
859 | .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, | |
860 | }, | |
861 | .endianness = DEVICE_NATIVE_ENDIAN, | |
574bbf7b FB |
862 | }; |
863 | ||
dae01685 | 864 | static void apic_init(APICCommonState *s) |
8546b099 | 865 | { |
dae01685 JK |
866 | memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic-msi", |
867 | MSI_SPACE_SIZE); | |
8546b099 | 868 | |
74475455 | 869 | s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); |
8546b099 | 870 | local_apics[s->idx] = s; |
08a82ac0 JK |
871 | |
872 | msi_supported = true; | |
8546b099 BS |
873 | } |
874 | ||
999e12bb AL |
875 | static void apic_class_init(ObjectClass *klass, void *data) |
876 | { | |
877 | APICCommonClass *k = APIC_COMMON_CLASS(klass); | |
878 | ||
879 | k->init = apic_init; | |
880 | k->set_base = apic_set_base; | |
881 | k->set_tpr = apic_set_tpr; | |
e5ad936b JK |
882 | k->get_tpr = apic_get_tpr; |
883 | k->vapic_base_update = apic_vapic_base_update; | |
999e12bb | 884 | k->external_nmi = apic_external_nmi; |
e5ad936b | 885 | k->pre_save = apic_pre_save; |
999e12bb AL |
886 | k->post_load = apic_post_load; |
887 | } | |
888 | ||
39bffca2 AL |
889 | static TypeInfo apic_info = { |
890 | .name = "apic", | |
891 | .instance_size = sizeof(APICCommonState), | |
892 | .parent = TYPE_APIC_COMMON, | |
893 | .class_init = apic_class_init, | |
8546b099 BS |
894 | }; |
895 | ||
83f7d43a | 896 | static void apic_register_types(void) |
8546b099 | 897 | { |
39bffca2 | 898 | type_register_static(&apic_info); |
8546b099 BS |
899 | } |
900 | ||
83f7d43a | 901 | type_init(apic_register_types) |