[qemu.git] / hw / apic.h

#ifndef APIC_H
#define APIC_H

typedef struct IOAPICState IOAPICState;
void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
                             uint8_t delivery_mode,
                             uint8_t vector_num, uint8_t polarity,
                             uint8_t trigger_mode);
int apic_init(CPUState *env);
int apic_accept_pic_intr(CPUState *env);
void apic_deliver_pic_intr(CPUState *env, int level);
int apic_get_interrupt(CPUState *env);
qemu_irq *ioapic_init(void);
void ioapic_set_irq(void *opaque, int vector, int level);
void apic_reset_irq_delivered(void);
int apic_get_irq_delivered(void);

int cpu_is_bsp(CPUState *env);

#endif
Commit	Line	Data
aa28b9bf BS	1	#ifndef APIC_H
	2	#define APIC_H
	3
	4	typedef struct IOAPICState IOAPICState;
	5	void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
	6	uint8_t delivery_mode,
	7	uint8_t vector_num, uint8_t polarity,
	8	uint8_t trigger_mode);
	9	int apic_init(CPUState *env);
	10	int apic_accept_pic_intr(CPUState *env);
	11	void apic_deliver_pic_intr(CPUState *env, int level);
	12	int apic_get_interrupt(CPUState *env);
	13	qemu_irq *ioapic_init(void);
	14	void ioapic_set_irq(void *opaque, int vector, int level);
	15	void apic_reset_irq_delivered(void);
	16	int apic_get_irq_delivered(void);
	17
	18	int cpu_is_bsp(CPUState *env);
	19
	20	#endif