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dae01685 JK |
1 | /* |
2 | * APIC support - common bits of emulated and KVM kernel model | |
3 | * | |
4 | * Copyright (c) 2004-2005 Fabrice Bellard | |
5 | * Copyright (c) 2011 Jan Kiszka, Siemens AG | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
19 | */ | |
20 | #include "apic.h" | |
21 | #include "apic_internal.h" | |
22 | #include "trace.h" | |
e5ad936b | 23 | #include "kvm.h" |
dae01685 JK |
24 | |
25 | static int apic_irq_delivered; | |
e5ad936b | 26 | bool apic_report_tpr_access; |
dae01685 JK |
27 | |
28 | void cpu_set_apic_base(DeviceState *d, uint64_t val) | |
29 | { | |
dae01685 JK |
30 | trace_cpu_set_apic_base(val); |
31 | ||
999e12bb AL |
32 | if (d) { |
33 | APICCommonState *s = APIC_COMMON(d); | |
34 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
dae01685 JK |
35 | info->set_base(s, val); |
36 | } | |
37 | } | |
38 | ||
39 | uint64_t cpu_get_apic_base(DeviceState *d) | |
40 | { | |
999e12bb AL |
41 | if (d) { |
42 | APICCommonState *s = APIC_COMMON(d); | |
43 | trace_cpu_get_apic_base((uint64_t)s->apicbase); | |
44 | return s->apicbase; | |
45 | } else { | |
dd673288 IM |
46 | trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); |
47 | return MSR_IA32_APICBASE_BSP; | |
999e12bb | 48 | } |
dae01685 JK |
49 | } |
50 | ||
51 | void cpu_set_apic_tpr(DeviceState *d, uint8_t val) | |
52 | { | |
999e12bb AL |
53 | APICCommonState *s; |
54 | APICCommonClass *info; | |
dae01685 | 55 | |
999e12bb AL |
56 | if (!d) { |
57 | return; | |
dae01685 | 58 | } |
999e12bb AL |
59 | |
60 | s = APIC_COMMON(d); | |
61 | info = APIC_COMMON_GET_CLASS(s); | |
62 | ||
63 | info->set_tpr(s, val); | |
dae01685 JK |
64 | } |
65 | ||
66 | uint8_t cpu_get_apic_tpr(DeviceState *d) | |
e5ad936b JK |
67 | { |
68 | APICCommonState *s; | |
69 | APICCommonClass *info; | |
70 | ||
71 | if (!d) { | |
72 | return 0; | |
73 | } | |
74 | ||
75 | s = APIC_COMMON(d); | |
76 | info = APIC_COMMON_GET_CLASS(s); | |
77 | ||
78 | return info->get_tpr(s); | |
79 | } | |
80 | ||
81 | void apic_enable_tpr_access_reporting(DeviceState *d, bool enable) | |
82 | { | |
83 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); | |
84 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
85 | ||
86 | apic_report_tpr_access = enable; | |
87 | if (info->enable_tpr_reporting) { | |
88 | info->enable_tpr_reporting(s, enable); | |
89 | } | |
90 | } | |
91 | ||
a8170e5e | 92 | void apic_enable_vapic(DeviceState *d, hwaddr paddr) |
dae01685 JK |
93 | { |
94 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); | |
e5ad936b | 95 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 | 96 | |
e5ad936b JK |
97 | s->vapic_paddr = paddr; |
98 | info->vapic_base_update(s); | |
dae01685 JK |
99 | } |
100 | ||
d362e757 JK |
101 | void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, |
102 | TPRAccess access) | |
103 | { | |
e5ad936b JK |
104 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
105 | ||
60671e58 | 106 | vapic_report_tpr_access(s->vapic, &s->cpu->env, ip, access); |
d362e757 JK |
107 | } |
108 | ||
dae01685 JK |
109 | void apic_report_irq_delivered(int delivered) |
110 | { | |
111 | apic_irq_delivered += delivered; | |
112 | ||
113 | trace_apic_report_irq_delivered(apic_irq_delivered); | |
114 | } | |
115 | ||
116 | void apic_reset_irq_delivered(void) | |
117 | { | |
118 | trace_apic_reset_irq_delivered(apic_irq_delivered); | |
119 | ||
120 | apic_irq_delivered = 0; | |
121 | } | |
122 | ||
123 | int apic_get_irq_delivered(void) | |
124 | { | |
125 | trace_apic_get_irq_delivered(apic_irq_delivered); | |
126 | ||
127 | return apic_irq_delivered; | |
128 | } | |
129 | ||
130 | void apic_deliver_nmi(DeviceState *d) | |
131 | { | |
999e12bb AL |
132 | APICCommonState *s = APIC_COMMON(d); |
133 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
dae01685 | 134 | |
dae01685 JK |
135 | info->external_nmi(s); |
136 | } | |
137 | ||
7a380ca3 JK |
138 | bool apic_next_timer(APICCommonState *s, int64_t current_time) |
139 | { | |
140 | int64_t d; | |
141 | ||
142 | /* We need to store the timer state separately to support APIC | |
143 | * implementations that maintain a non-QEMU timer, e.g. inside the | |
144 | * host kernel. This open-coded state allows us to migrate between | |
145 | * both models. */ | |
146 | s->timer_expiry = -1; | |
147 | ||
148 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { | |
149 | return false; | |
150 | } | |
151 | ||
152 | d = (current_time - s->initial_count_load_time) >> s->count_shift; | |
153 | ||
154 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
155 | if (!s->initial_count) { | |
156 | return false; | |
157 | } | |
158 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * | |
159 | ((uint64_t)s->initial_count + 1); | |
160 | } else { | |
161 | if (d >= s->initial_count) { | |
162 | return false; | |
163 | } | |
164 | d = (uint64_t)s->initial_count + 1; | |
165 | } | |
166 | s->next_time = s->initial_count_load_time + (d << s->count_shift); | |
167 | s->timer_expiry = s->next_time; | |
168 | return true; | |
169 | } | |
170 | ||
dae01685 JK |
171 | void apic_init_reset(DeviceState *d) |
172 | { | |
173 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); | |
174 | int i; | |
175 | ||
176 | if (!s) { | |
177 | return; | |
178 | } | |
179 | s->tpr = 0; | |
180 | s->spurious_vec = 0xff; | |
181 | s->log_dest = 0; | |
182 | s->dest_mode = 0xf; | |
183 | memset(s->isr, 0, sizeof(s->isr)); | |
184 | memset(s->tmr, 0, sizeof(s->tmr)); | |
185 | memset(s->irr, 0, sizeof(s->irr)); | |
186 | for (i = 0; i < APIC_LVT_NB; i++) { | |
187 | s->lvt[i] = APIC_LVT_MASKED; | |
188 | } | |
189 | s->esr = 0; | |
190 | memset(s->icr, 0, sizeof(s->icr)); | |
191 | s->divide_conf = 0; | |
192 | s->count_shift = 0; | |
193 | s->initial_count = 0; | |
194 | s->initial_count_load_time = 0; | |
195 | s->next_time = 0; | |
196 | s->wait_for_sipi = 1; | |
197 | ||
7a380ca3 JK |
198 | if (s->timer) { |
199 | qemu_del_timer(s->timer); | |
200 | } | |
201 | s->timer_expiry = -1; | |
dae01685 JK |
202 | } |
203 | ||
dd673288 IM |
204 | void apic_designate_bsp(DeviceState *d) |
205 | { | |
206 | if (d == NULL) { | |
207 | return; | |
208 | } | |
209 | ||
210 | APICCommonState *s = APIC_COMMON(d); | |
211 | s->apicbase |= MSR_IA32_APICBASE_BSP; | |
212 | } | |
213 | ||
dae01685 JK |
214 | static void apic_reset_common(DeviceState *d) |
215 | { | |
216 | APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); | |
e5ad936b | 217 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 JK |
218 | bool bsp; |
219 | ||
60671e58 | 220 | bsp = cpu_is_bsp(s->cpu); |
dae01685 JK |
221 | s->apicbase = 0xfee00000 | |
222 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; | |
223 | ||
e5ad936b JK |
224 | s->vapic_paddr = 0; |
225 | info->vapic_base_update(s); | |
226 | ||
dae01685 JK |
227 | apic_init_reset(d); |
228 | ||
229 | if (bsp) { | |
230 | /* | |
231 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization | |
232 | * time typically by BIOS, so PIC interrupt can be delivered to the | |
233 | * processor when local APIC is enabled. | |
234 | */ | |
235 | s->lvt[APIC_LVT_LINT0] = 0x700; | |
236 | } | |
237 | } | |
238 | ||
239 | /* This function is only used for old state version 1 and 2 */ | |
240 | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) | |
241 | { | |
242 | APICCommonState *s = opaque; | |
a4aecd28 | 243 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 JK |
244 | int i; |
245 | ||
246 | if (version_id > 2) { | |
247 | return -EINVAL; | |
248 | } | |
249 | ||
250 | /* XXX: what if the base changes? (registered memory regions) */ | |
251 | qemu_get_be32s(f, &s->apicbase); | |
252 | qemu_get_8s(f, &s->id); | |
253 | qemu_get_8s(f, &s->arb_id); | |
254 | qemu_get_8s(f, &s->tpr); | |
255 | qemu_get_be32s(f, &s->spurious_vec); | |
256 | qemu_get_8s(f, &s->log_dest); | |
257 | qemu_get_8s(f, &s->dest_mode); | |
258 | for (i = 0; i < 8; i++) { | |
259 | qemu_get_be32s(f, &s->isr[i]); | |
260 | qemu_get_be32s(f, &s->tmr[i]); | |
261 | qemu_get_be32s(f, &s->irr[i]); | |
262 | } | |
263 | for (i = 0; i < APIC_LVT_NB; i++) { | |
264 | qemu_get_be32s(f, &s->lvt[i]); | |
265 | } | |
266 | qemu_get_be32s(f, &s->esr); | |
267 | qemu_get_be32s(f, &s->icr[0]); | |
268 | qemu_get_be32s(f, &s->icr[1]); | |
269 | qemu_get_be32s(f, &s->divide_conf); | |
270 | s->count_shift = qemu_get_be32(f); | |
271 | qemu_get_be32s(f, &s->initial_count); | |
272 | s->initial_count_load_time = qemu_get_be64(f); | |
273 | s->next_time = qemu_get_be64(f); | |
274 | ||
275 | if (version_id >= 2) { | |
a4aecd28 JK |
276 | s->timer_expiry = qemu_get_be64(f); |
277 | } | |
278 | ||
279 | if (info->post_load) { | |
280 | info->post_load(s); | |
dae01685 JK |
281 | } |
282 | return 0; | |
283 | } | |
284 | ||
285 | static int apic_init_common(SysBusDevice *dev) | |
286 | { | |
999e12bb AL |
287 | APICCommonState *s = APIC_COMMON(dev); |
288 | APICCommonClass *info; | |
e5ad936b | 289 | static DeviceState *vapic; |
dae01685 JK |
290 | static int apic_no; |
291 | ||
292 | if (apic_no >= MAX_APICS) { | |
293 | return -1; | |
294 | } | |
295 | s->idx = apic_no++; | |
296 | ||
999e12bb | 297 | info = APIC_COMMON_GET_CLASS(s); |
dae01685 JK |
298 | info->init(s); |
299 | ||
e5ad936b JK |
300 | sysbus_init_mmio(dev, &s->io_memory); |
301 | ||
a9605e03 JK |
302 | /* Note: We need at least 1M to map the VAPIC option ROM */ |
303 | if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && | |
304 | ram_size >= 1024 * 1024) { | |
e5ad936b JK |
305 | vapic = sysbus_create_simple("kvmvapic", -1, NULL); |
306 | } | |
307 | s->vapic = vapic; | |
308 | if (apic_report_tpr_access && info->enable_tpr_reporting) { | |
309 | info->enable_tpr_reporting(s, true); | |
310 | } | |
311 | ||
dae01685 JK |
312 | return 0; |
313 | } | |
314 | ||
e5ad936b JK |
315 | static void apic_dispatch_pre_save(void *opaque) |
316 | { | |
317 | APICCommonState *s = APIC_COMMON(opaque); | |
318 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
319 | ||
320 | if (info->pre_save) { | |
321 | info->pre_save(s); | |
322 | } | |
323 | } | |
324 | ||
7a380ca3 JK |
325 | static int apic_dispatch_post_load(void *opaque, int version_id) |
326 | { | |
999e12bb AL |
327 | APICCommonState *s = APIC_COMMON(opaque); |
328 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
7a380ca3 JK |
329 | |
330 | if (info->post_load) { | |
331 | info->post_load(s); | |
332 | } | |
333 | return 0; | |
334 | } | |
335 | ||
dae01685 JK |
336 | static const VMStateDescription vmstate_apic_common = { |
337 | .name = "apic", | |
338 | .version_id = 3, | |
339 | .minimum_version_id = 3, | |
340 | .minimum_version_id_old = 1, | |
341 | .load_state_old = apic_load_old, | |
e5ad936b | 342 | .pre_save = apic_dispatch_pre_save, |
7a380ca3 | 343 | .post_load = apic_dispatch_post_load, |
dae01685 JK |
344 | .fields = (VMStateField[]) { |
345 | VMSTATE_UINT32(apicbase, APICCommonState), | |
346 | VMSTATE_UINT8(id, APICCommonState), | |
347 | VMSTATE_UINT8(arb_id, APICCommonState), | |
348 | VMSTATE_UINT8(tpr, APICCommonState), | |
349 | VMSTATE_UINT32(spurious_vec, APICCommonState), | |
350 | VMSTATE_UINT8(log_dest, APICCommonState), | |
351 | VMSTATE_UINT8(dest_mode, APICCommonState), | |
352 | VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), | |
353 | VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), | |
354 | VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), | |
355 | VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), | |
356 | VMSTATE_UINT32(esr, APICCommonState), | |
357 | VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), | |
358 | VMSTATE_UINT32(divide_conf, APICCommonState), | |
359 | VMSTATE_INT32(count_shift, APICCommonState), | |
360 | VMSTATE_UINT32(initial_count, APICCommonState), | |
361 | VMSTATE_INT64(initial_count_load_time, APICCommonState), | |
362 | VMSTATE_INT64(next_time, APICCommonState), | |
7a380ca3 JK |
363 | VMSTATE_INT64(timer_expiry, |
364 | APICCommonState), /* open-coded timer state */ | |
dae01685 JK |
365 | VMSTATE_END_OF_LIST() |
366 | } | |
367 | }; | |
368 | ||
369 | static Property apic_properties_common[] = { | |
370 | DEFINE_PROP_UINT8("id", APICCommonState, id, -1), | |
e5ad936b JK |
371 | DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, |
372 | true), | |
dae01685 JK |
373 | DEFINE_PROP_END_OF_LIST(), |
374 | }; | |
375 | ||
999e12bb AL |
376 | static void apic_common_class_init(ObjectClass *klass, void *data) |
377 | { | |
378 | SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass); | |
39bffca2 | 379 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 380 | |
39bffca2 AL |
381 | dc->vmsd = &vmstate_apic_common; |
382 | dc->reset = apic_reset_common; | |
383 | dc->no_user = 1; | |
384 | dc->props = apic_properties_common; | |
999e12bb AL |
385 | sc->init = apic_init_common; |
386 | } | |
dae01685 | 387 | |
999e12bb AL |
388 | static TypeInfo apic_common_type = { |
389 | .name = TYPE_APIC_COMMON, | |
390 | .parent = TYPE_SYS_BUS_DEVICE, | |
391 | .instance_size = sizeof(APICCommonState), | |
392 | .class_size = sizeof(APICCommonClass), | |
393 | .class_init = apic_common_class_init, | |
394 | .abstract = true, | |
395 | }; | |
396 | ||
83f7d43a | 397 | static void register_types(void) |
999e12bb AL |
398 | { |
399 | type_register_static(&apic_common_type); | |
400 | } | |
401 | ||
83f7d43a | 402 | type_init(register_types) |