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dae01685 JK |
1 | /* |
2 | * APIC support - internal interfaces | |
3 | * | |
4 | * Copyright (c) 2004-2005 Fabrice Bellard | |
5 | * Copyright (c) 2011 Jan Kiszka, Siemens AG | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
19 | */ | |
20 | #ifndef QEMU_APIC_INTERNAL_H | |
21 | #define QEMU_APIC_INTERNAL_H | |
22 | ||
23 | #include "memory.h" | |
24 | #include "sysbus.h" | |
25 | #include "qemu-timer.h" | |
26 | ||
27 | /* APIC Local Vector Table */ | |
28 | #define APIC_LVT_TIMER 0 | |
29 | #define APIC_LVT_THERMAL 1 | |
30 | #define APIC_LVT_PERFORM 2 | |
31 | #define APIC_LVT_LINT0 3 | |
32 | #define APIC_LVT_LINT1 4 | |
33 | #define APIC_LVT_ERROR 5 | |
34 | #define APIC_LVT_NB 6 | |
35 | ||
36 | /* APIC delivery modes */ | |
37 | #define APIC_DM_FIXED 0 | |
38 | #define APIC_DM_LOWPRI 1 | |
39 | #define APIC_DM_SMI 2 | |
40 | #define APIC_DM_NMI 4 | |
41 | #define APIC_DM_INIT 5 | |
42 | #define APIC_DM_SIPI 6 | |
43 | #define APIC_DM_EXTINT 7 | |
44 | ||
45 | /* APIC destination mode */ | |
46 | #define APIC_DESTMODE_FLAT 0xf | |
47 | #define APIC_DESTMODE_CLUSTER 1 | |
48 | ||
49 | #define APIC_TRIGGER_EDGE 0 | |
50 | #define APIC_TRIGGER_LEVEL 1 | |
51 | ||
52 | #define APIC_LVT_TIMER_PERIODIC (1<<17) | |
53 | #define APIC_LVT_MASKED (1<<16) | |
54 | #define APIC_LVT_LEVEL_TRIGGER (1<<15) | |
55 | #define APIC_LVT_REMOTE_IRR (1<<14) | |
56 | #define APIC_INPUT_POLARITY (1<<13) | |
57 | #define APIC_SEND_PENDING (1<<12) | |
58 | ||
59 | #define ESR_ILLEGAL_ADDRESS (1 << 7) | |
60 | ||
61 | #define APIC_SV_DIRECTED_IO (1<<12) | |
62 | #define APIC_SV_ENABLE (1<<8) | |
63 | ||
64 | #define MAX_APICS 255 | |
65 | ||
66 | #define MSI_SPACE_SIZE 0x100000 | |
67 | ||
68 | typedef struct APICCommonState APICCommonState; | |
69 | ||
70 | struct APICCommonState { | |
71 | SysBusDevice busdev; | |
72 | MemoryRegion io_memory; | |
73 | void *cpu_env; | |
74 | uint32_t apicbase; | |
75 | uint8_t id; | |
76 | uint8_t arb_id; | |
77 | uint8_t tpr; | |
78 | uint32_t spurious_vec; | |
79 | uint8_t log_dest; | |
80 | uint8_t dest_mode; | |
81 | uint32_t isr[8]; /* in service register */ | |
82 | uint32_t tmr[8]; /* trigger mode register */ | |
83 | uint32_t irr[8]; /* interrupt request register */ | |
84 | uint32_t lvt[APIC_LVT_NB]; | |
85 | uint32_t esr; /* error register */ | |
86 | uint32_t icr[2]; | |
87 | ||
88 | uint32_t divide_conf; | |
89 | int count_shift; | |
90 | uint32_t initial_count; | |
91 | int64_t initial_count_load_time; | |
92 | int64_t next_time; | |
93 | int idx; | |
94 | QEMUTimer *timer; | |
95 | int sipi_vector; | |
96 | int wait_for_sipi; | |
97 | }; | |
98 | ||
99 | typedef struct APICCommonInfo APICCommonInfo; | |
100 | ||
101 | struct APICCommonInfo { | |
102 | SysBusDeviceInfo busdev; | |
103 | void (*init)(APICCommonState *s); | |
104 | void (*set_base)(APICCommonState *s, uint64_t val); | |
105 | void (*set_tpr)(APICCommonState *s, uint8_t val); | |
106 | void (*external_nmi)(APICCommonState *s); | |
107 | }; | |
108 | ||
109 | void apic_report_irq_delivered(int delivered); | |
110 | void apic_qdev_register(APICCommonInfo *info); | |
111 | ||
112 | #endif /* !QEMU_APIC_INTERNAL_H */ |