[mirror_qemu.git] / hw / arm / aspeed_ast2600.c

/*
 * ASPEED SoC 2600 family
 *
 * Copyright (c) 2016-2019, IBM Corporation.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/char/serial.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
#include "hw/i2c/aspeed_i2c.h"
#include "net/net.h"
#include "sysemu/sysemu.h"

#define ASPEED_SOC_IOMEM_SIZE       0x00200000

static const hwaddr aspeed_soc_ast2600_memmap[] = {
    [ASPEED_SRAM]      = 0x10000000,
    /* 0x16000000     0x17FFFFFF : AHB BUS do LPC Bus bridge */
    [ASPEED_IOMEM]     = 0x1E600000,
    [ASPEED_PWM]       = 0x1E610000,
    [ASPEED_FMC]       = 0x1E620000,
    [ASPEED_SPI1]      = 0x1E630000,
    [ASPEED_SPI2]      = 0x1E641000,
    [ASPEED_EHCI1]     = 0x1E6A1000,
    [ASPEED_EHCI2]     = 0x1E6A3000,
    [ASPEED_MII1]      = 0x1E650000,
    [ASPEED_MII2]      = 0x1E650008,
    [ASPEED_MII3]      = 0x1E650010,
    [ASPEED_MII4]      = 0x1E650018,
    [ASPEED_ETH1]      = 0x1E660000,
    [ASPEED_ETH3]      = 0x1E670000,
    [ASPEED_ETH2]      = 0x1E680000,
    [ASPEED_ETH4]      = 0x1E690000,
    [ASPEED_VIC]       = 0x1E6C0000,
    [ASPEED_SDMC]      = 0x1E6E0000,
    [ASPEED_SCU]       = 0x1E6E2000,
    [ASPEED_XDMA]      = 0x1E6E7000,
    [ASPEED_ADC]       = 0x1E6E9000,
    [ASPEED_VIDEO]     = 0x1E700000,
    [ASPEED_SDHCI]     = 0x1E740000,
    [ASPEED_EMMC]      = 0x1E750000,
    [ASPEED_GPIO]      = 0x1E780000,
    [ASPEED_GPIO_1_8V] = 0x1E780800,
    [ASPEED_RTC]       = 0x1E781000,
    [ASPEED_TIMER1]    = 0x1E782000,
    [ASPEED_WDT]       = 0x1E785000,
    [ASPEED_LPC]       = 0x1E789000,
    [ASPEED_IBT]       = 0x1E789140,
    [ASPEED_I2C]       = 0x1E78A000,
    [ASPEED_UART1]     = 0x1E783000,
    [ASPEED_UART5]     = 0x1E784000,
    [ASPEED_VUART]     = 0x1E787000,
    [ASPEED_SDRAM]     = 0x80000000,
};

#define ASPEED_A7MPCORE_ADDR 0x40460000

#define ASPEED_SOC_AST2600_MAX_IRQ 128

/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2600_irqmap[] = {
    [ASPEED_UART1]     = 47,
    [ASPEED_UART2]     = 48,
    [ASPEED_UART3]     = 49,
    [ASPEED_UART4]     = 50,
    [ASPEED_UART5]     = 8,
    [ASPEED_VUART]     = 8,
    [ASPEED_FMC]       = 39,
    [ASPEED_SDMC]      = 0,
    [ASPEED_SCU]       = 12,
    [ASPEED_ADC]       = 78,
    [ASPEED_XDMA]      = 6,
    [ASPEED_SDHCI]     = 43,
    [ASPEED_EHCI1]     = 5,
    [ASPEED_EHCI2]     = 9,
    [ASPEED_EMMC]      = 15,
    [ASPEED_GPIO]      = 40,
    [ASPEED_GPIO_1_8V] = 11,
    [ASPEED_RTC]       = 13,
    [ASPEED_TIMER1]    = 16,
    [ASPEED_TIMER2]    = 17,
    [ASPEED_TIMER3]    = 18,
    [ASPEED_TIMER4]    = 19,
    [ASPEED_TIMER5]    = 20,
    [ASPEED_TIMER6]    = 21,
    [ASPEED_TIMER7]    = 22,
    [ASPEED_TIMER8]    = 23,
    [ASPEED_WDT]       = 24,
    [ASPEED_PWM]       = 44,
    [ASPEED_LPC]       = 35,
    [ASPEED_IBT]       = 35,    /* LPC */
    [ASPEED_I2C]       = 110,   /* 110 -> 125 */
    [ASPEED_ETH1]      = 2,
    [ASPEED_ETH2]      = 3,
    [ASPEED_ETH3]      = 32,
    [ASPEED_ETH4]      = 33,

};

static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
{
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
}

static void aspeed_soc_ast2600_init(Object *obj)
{
    AspeedSoCState *s = ASPEED_SOC(obj);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    int i;
    char socname[8];
    char typename[64];

    if (sscanf(sc->name, "%7s", socname) != 1) {
        g_assert_not_reached();
    }

    for (i = 0; i < sc->num_cpus; i++) {
        object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
                                sizeof(s->cpu[i]), sc->cpu_type,
                                &error_abort, NULL);
    }

    snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
    sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
                          typename);
    qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
                         sc->silicon_rev);
    object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
                              "hw-strap1", &error_abort);
    object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
                              "hw-strap2", &error_abort);
    object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                              "hw-prot-key", &error_abort);

    sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
                          sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);

    sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
                          TYPE_ASPEED_RTC);

    snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
    sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
                          sizeof(s->timerctrl), typename);

    snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
    sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
                          typename);

    snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
    sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
                          typename);
    object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
                              &error_abort);

    for (i = 0; i < sc->spis_num; i++) {
        snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
        sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
                              sizeof(s->spi[i]), typename);
    }

    for (i = 0; i < sc->ehcis_num; i++) {
        sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
                              sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
    }

    snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
    sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
                          typename);
    object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                              "ram-size", &error_abort);
    object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
                              "max-ram-size", &error_abort);

    for (i = 0; i < sc->wdts_num; i++) {
        snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
        sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
                              sizeof(s->wdt[i]), typename);
    }

    for (i = 0; i < sc->macs_num; i++) {
        sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
                              sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);

        sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
                              TYPE_ASPEED_MII);
    }

    sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
                          TYPE_ASPEED_XDMA);

    snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
    sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
                          typename);

    snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
    sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
                          sizeof(s->gpio_1_8v), typename);

    sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci),
                          sizeof(s->sdhci), TYPE_ASPEED_SDHCI);

    object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);

    /* Init sd card slot class here so that they're under the correct parent */
    for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
        sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
                              OBJECT(&s->sdhci.slots[i]),
                              sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
    }

    sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc),
                          sizeof(s->emmc), TYPE_ASPEED_SDHCI);

    object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);

    sysbus_init_child_obj(obj, "emmc-controller.sdhci",
                          OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]),
                          TYPE_SYSBUS_SDHCI);
}

/*
 * ASPEED ast2600 has 0xf as cluster ID
 *
 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
 */
static uint64_t aspeed_calc_affinity(int cpu)
{
    return (0xf << ARM_AFF1_SHIFT) | cpu;
}

static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
{
    int i;
    AspeedSoCState *s = ASPEED_SOC(dev);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    Error *err = NULL, *local_err = NULL;
    qemu_irq irq;

    /* IO space */
    create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
                                ASPEED_SOC_IOMEM_SIZE);

    /* Video engine stub */
    create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
                                0x1000);

    if (s->num_cpus > sc->num_cpus) {
        warn_report("%s: invalid number of CPUs %d, using default %d",
                    sc->name, s->num_cpus, sc->num_cpus);
        s->num_cpus = sc->num_cpus;
    }

    /* CPU */
    for (i = 0; i < s->num_cpus; i++) {
        object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
                                "psci-conduit", &error_abort);
        if (s->num_cpus > 1) {
            object_property_set_int(OBJECT(&s->cpu[i]),
                                    ASPEED_A7MPCORE_ADDR,
                                    "reset-cbar", &error_abort);
        }
        object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i),
                                "mp-affinity", &error_abort);

        object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq",
                                &error_abort);

        /*
         * TODO: the secondary CPUs are started and a boot helper
         * is needed when using -kernel
         */

        object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    /* A7MPCORE */
    object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu",
                            &error_abort);
    object_property_set_int(OBJECT(&s->a7mpcore),
                            ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
                            "num-irq", &error_abort);

    object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
                             &error_abort);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);

    for (i = 0; i < s->num_cpus; i++) {
        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
        DeviceState  *d   = DEVICE(qemu_get_cpu(i));

        irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
        sysbus_connect_irq(sbd, i, irq);
        irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
        sysbus_connect_irq(sbd, i + s->num_cpus, irq);
        irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
        sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq);
        irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
        sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq);
    }

    /* SRAM */
    memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
                           sc->sram_size, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(),
                                sc->memmap[ASPEED_SRAM], &s->sram);

    /* SCU */
    object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);

    /* RTC */
    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
                       aspeed_soc_get_irq(s, ASPEED_RTC));

    /* Timer */
    object_property_set_link(OBJECT(&s->timerctrl),
                             OBJECT(&s->scu), "scu", &error_abort);
    object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
                    sc->memmap[ASPEED_TIMER1]);
    for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
        qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
    }

    /* UART - attach an 8250 to the IO space as our UART5 */
    if (serial_hd(0)) {
        qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
        serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
                       uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
    }

    /* I2C */
    object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
    for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
                                        sc->irqmap[ASPEED_I2C] + i);
        /*
         * The AST2600 SoC has one IRQ per I2C bus. Skip the common
         * IRQ (AST2400 and AST2500) and connect all bussses.
         */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
    }

    /* FMC, The number of CS is set at the board level */
    object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
                            "sdram-base", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
                    s->fmc.ctrl->flash_window_base);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
                       aspeed_soc_get_irq(s, ASPEED_FMC));

    /* SPI */
    for (i = 0; i < sc->spis_num; i++) {
        object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
                                 &local_err);
        error_propagate(&err, local_err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
                        sc->memmap[ASPEED_SPI1 + i]);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
                        s->spi[i].ctrl->flash_window_base);
    }

    /* EHCI */
    for (i = 0; i < sc->ehcis_num; i++) {
        object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
                        sc->memmap[ASPEED_EHCI1 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
                           aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
    }

    /* SDMC - SDRAM Memory Controller */
    object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);

    /* Watch dog */
    for (i = 0; i < sc->wdts_num; i++) {
        AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);

        object_property_set_link(OBJECT(&s->wdt[i]),
                                 OBJECT(&s->scu), "scu", &error_abort);
        object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
                        sc->memmap[ASPEED_WDT] + i * awc->offset);
    }

    /* Net */
    for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
        qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
                                 &err);
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
                                 &local_err);
        error_propagate(&err, local_err);
        if (err) {
            error_propagate(errp, err);
           return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                        sc->memmap[ASPEED_ETH1 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                           aspeed_soc_get_irq(s, ASPEED_ETH1 + i));

        object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]),
                                 "nic", &error_abort);
        object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
                        sc->memmap[ASPEED_MII1 + i]);
    }

    /* XDMA */
    object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
                    sc->memmap[ASPEED_XDMA]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
                       aspeed_soc_get_irq(s, ASPEED_XDMA));

    /* GPIO */
    object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
                       aspeed_soc_get_irq(s, ASPEED_GPIO));

    object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
                    sc->memmap[ASPEED_GPIO_1_8V]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
                       aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));

    /* SDHCI */
    object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
                    sc->memmap[ASPEED_SDHCI]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
                       aspeed_soc_get_irq(s, ASPEED_SDHCI));

    /* eMMC */
    object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
                       aspeed_soc_get_irq(s, ASPEED_EMMC));
}

static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);

    dc->realize      = aspeed_soc_ast2600_realize;

    sc->name         = "ast2600-a0";
    sc->cpu_type     = ARM_CPU_TYPE_NAME("cortex-a7");
    sc->silicon_rev  = AST2600_A0_SILICON_REV;
    sc->sram_size    = 0x10000;
    sc->spis_num     = 2;
    sc->ehcis_num    = 2;
    sc->wdts_num     = 4;
    sc->macs_num     = 4;
    sc->irqmap       = aspeed_soc_ast2600_irqmap;
    sc->memmap       = aspeed_soc_ast2600_memmap;
    sc->num_cpus     = 2;
}

static const TypeInfo aspeed_soc_ast2600_type_info = {
    .name           = "ast2600-a0",
    .parent         = TYPE_ASPEED_SOC,
    .instance_size  = sizeof(AspeedSoCState),
    .instance_init  = aspeed_soc_ast2600_init,
    .class_init     = aspeed_soc_ast2600_class_init,
    .class_size     = sizeof(AspeedSoCClass),
};

static void aspeed_soc_register_types(void)
{
    type_register_static(&aspeed_soc_ast2600_type_info);
};

type_init(aspeed_soc_register_types)
Commit	Line	Data
f25c0ae1 CLG	1	/*
	2	* ASPEED SoC 2600 family
	3	*
	4	* Copyright (c) 2016-2019, IBM Corporation.
	5	*
	6	* This code is licensed under the GPL version 2 or later. See
	7	* the COPYING file in the top-level directory.
	8	*/
	9
	10	#include "qemu/osdep.h"
	11	#include "qapi/error.h"
	12	#include "cpu.h"
	13	#include "exec/address-spaces.h"
	14	#include "hw/misc/unimp.h"
	15	#include "hw/arm/aspeed_soc.h"
	16	#include "hw/char/serial.h"
	17	#include "qemu/log.h"
	18	#include "qemu/module.h"
	19	#include "qemu/error-report.h"
	20	#include "hw/i2c/aspeed_i2c.h"
	21	#include "net/net.h"
	22	#include "sysemu/sysemu.h"
	23
	24	#define ASPEED_SOC_IOMEM_SIZE 0x00200000
	25
	26	static const hwaddr aspeed_soc_ast2600_memmap[] = {
	27	[ASPEED_SRAM] = 0x10000000,
	28	/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
	29	[ASPEED_IOMEM] = 0x1E600000,
	30	[ASPEED_PWM] = 0x1E610000,
	31	[ASPEED_FMC] = 0x1E620000,
	32	[ASPEED_SPI1] = 0x1E630000,
	33	[ASPEED_SPI2] = 0x1E641000,
917940ce GR	34	[ASPEED_EHCI1] = 0x1E6A1000,
917940ce GR	35	[ASPEED_EHCI2] = 0x1E6A3000,
289251b0 CLG	36	[ASPEED_MII1] = 0x1E650000,
	37	[ASPEED_MII2] = 0x1E650008,
	38	[ASPEED_MII3] = 0x1E650010,
	39	[ASPEED_MII4] = 0x1E650018,
f25c0ae1	40	[ASPEED_ETH1] = 0x1E660000,
d300db02	41	[ASPEED_ETH3] = 0x1E670000,
f25c0ae1	42	[ASPEED_ETH2] = 0x1E680000,
d300db02	43	[ASPEED_ETH4] = 0x1E690000,
f25c0ae1 CLG	44	[ASPEED_VIC] = 0x1E6C0000,
	45	[ASPEED_SDMC] = 0x1E6E0000,
	46	[ASPEED_SCU] = 0x1E6E2000,
	47	[ASPEED_XDMA] = 0x1E6E7000,
	48	[ASPEED_ADC] = 0x1E6E9000,
514bcf6f	49	[ASPEED_VIDEO] = 0x1E700000,
f25c0ae1	50	[ASPEED_SDHCI] = 0x1E740000,
a29e3e12	51	[ASPEED_EMMC] = 0x1E750000,
f25c0ae1 CLG	52	[ASPEED_GPIO] = 0x1E780000,
	53	[ASPEED_GPIO_1_8V] = 0x1E780800,
	54	[ASPEED_RTC] = 0x1E781000,
	55	[ASPEED_TIMER1] = 0x1E782000,
	56	[ASPEED_WDT] = 0x1E785000,
	57	[ASPEED_LPC] = 0x1E789000,
	58	[ASPEED_IBT] = 0x1E789140,
	59	[ASPEED_I2C] = 0x1E78A000,
	60	[ASPEED_UART1] = 0x1E783000,
	61	[ASPEED_UART5] = 0x1E784000,
	62	[ASPEED_VUART] = 0x1E787000,
	63	[ASPEED_SDRAM] = 0x80000000,
	64	};
	65
	66	#define ASPEED_A7MPCORE_ADDR 0x40460000
	67
	68	#define ASPEED_SOC_AST2600_MAX_IRQ 128
	69
a29e3e12	70	/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
f25c0ae1 CLG	71	static const int aspeed_soc_ast2600_irqmap[] = {
	72	[ASPEED_UART1] = 47,
	73	[ASPEED_UART2] = 48,
	74	[ASPEED_UART3] = 49,
	75	[ASPEED_UART4] = 50,
	76	[ASPEED_UART5] = 8,
	77	[ASPEED_VUART] = 8,
	78	[ASPEED_FMC] = 39,
	79	[ASPEED_SDMC] = 0,
	80	[ASPEED_SCU] = 12,
	81	[ASPEED_ADC] = 78,
	82	[ASPEED_XDMA] = 6,
	83	[ASPEED_SDHCI] = 43,
917940ce GR	84	[ASPEED_EHCI1] = 5,
917940ce GR	85	[ASPEED_EHCI2] = 9,
a29e3e12	86	[ASPEED_EMMC] = 15,
f25c0ae1 CLG	87	[ASPEED_GPIO] = 40,
	88	[ASPEED_GPIO_1_8V] = 11,
	89	[ASPEED_RTC] = 13,
	90	[ASPEED_TIMER1] = 16,
	91	[ASPEED_TIMER2] = 17,
	92	[ASPEED_TIMER3] = 18,
	93	[ASPEED_TIMER4] = 19,
	94	[ASPEED_TIMER5] = 20,
	95	[ASPEED_TIMER6] = 21,
	96	[ASPEED_TIMER7] = 22,
	97	[ASPEED_TIMER8] = 23,
	98	[ASPEED_WDT] = 24,
	99	[ASPEED_PWM] = 44,
	100	[ASPEED_LPC] = 35,
	101	[ASPEED_IBT] = 35, /* LPC */
	102	[ASPEED_I2C] = 110, /* 110 -> 125 */
	103	[ASPEED_ETH1] = 2,
	104	[ASPEED_ETH2] = 3,
d300db02 JS	105	[ASPEED_ETH3] = 32,
	106	[ASPEED_ETH4] = 33,
	107
f25c0ae1 CLG	108	};
	109
	110	static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
	111	{
	112	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
	113
	114	return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
	115	}
	116
	117	static void aspeed_soc_ast2600_init(Object *obj)
	118	{
	119	AspeedSoCState *s = ASPEED_SOC(obj);
	120	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
	121	int i;
	122	char socname[8];
	123	char typename[64];
	124
	125	if (sscanf(sc->name, "%7s", socname) != 1) {
	126	g_assert_not_reached();
	127	}
	128
	129	for (i = 0; i < sc->num_cpus; i++) {
	130	object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
	131	sizeof(s->cpu[i]), sc->cpu_type,
	132	&error_abort, NULL);
	133	}
	134
	135	snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
	136	sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
	137	typename);
	138	qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
	139	sc->silicon_rev);
	140	object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
	141	"hw-strap1", &error_abort);
	142	object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
	143	"hw-strap2", &error_abort);
	144	object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
	145	"hw-prot-key", &error_abort);
	146
	147	sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
	148	sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
	149
	150	sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
	151	TYPE_ASPEED_RTC);
	152
	153	snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
	154	sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
	155	sizeof(s->timerctrl), typename);
f25c0ae1 CLG	156
	157	snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
	158	sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
	159	typename);
	160
	161	snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
	162	sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
	163	typename);
	164	object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
	165	&error_abort);
f25c0ae1 CLG	166
	167	for (i = 0; i < sc->spis_num; i++) {
	168	snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
	169	sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
	170	sizeof(s->spi[i]), typename);
	171	}
	172
917940ce GR	173	for (i = 0; i < sc->ehcis_num; i++) {
	174	sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
	175	sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
	176	}
	177
f25c0ae1 CLG	178	snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
	179	sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
	180	typename);
	181	object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
	182	"ram-size", &error_abort);
	183	object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
	184	"max-ram-size", &error_abort);
	185
	186	for (i = 0; i < sc->wdts_num; i++) {
	187	snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
	188	sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
	189	sizeof(s->wdt[i]), typename);
f25c0ae1 CLG	190	}
f25c0ae1 CLG	191
d300db02	192	for (i = 0; i < sc->macs_num; i++) {
f25c0ae1 CLG	193	sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
f25c0ae1 CLG	194	sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
289251b0 CLG	195
	196	sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
	197	TYPE_ASPEED_MII);
f25c0ae1 CLG	198	}
	199
	200	sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
	201	TYPE_ASPEED_XDMA);
	202
	203	snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
	204	sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
	205	typename);
	206
	207	snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
	208	sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
	209	sizeof(s->gpio_1_8v), typename);
	210
a29e3e12 AJ	211	sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci),
a29e3e12 AJ	212	sizeof(s->sdhci), TYPE_ASPEED_SDHCI);
f25c0ae1	213
0e2c24c6 AJ	214	object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
0e2c24c6 AJ	215
f25c0ae1 CLG	216	/* Init sd card slot class here so that they're under the correct parent */
f25c0ae1 CLG	217	for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
a29e3e12 AJ	218	sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
a29e3e12 AJ	219	OBJECT(&s->sdhci.slots[i]),
f25c0ae1 CLG	220	sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
f25c0ae1 CLG	221	}
a29e3e12 AJ	222
	223	sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc),
	224	sizeof(s->emmc), TYPE_ASPEED_SDHCI);
	225
	226	object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);
	227
	228	sysbus_init_child_obj(obj, "emmc-controller.sdhci",
	229	OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]),
	230	TYPE_SYSBUS_SDHCI);
f25c0ae1 CLG	231	}
	232
	233	/*
	234	* ASPEED ast2600 has 0xf as cluster ID
	235	*
	236	* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
	237	*/
	238	static uint64_t aspeed_calc_affinity(int cpu)
	239	{
	240	return (0xf << ARM_AFF1_SHIFT) \| cpu;
	241	}
	242
	243	static void aspeed_soc_ast2600_realize(DeviceState dev, Error *errp)
	244	{
	245	int i;
	246	AspeedSoCState *s = ASPEED_SOC(dev);
	247	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
	248	Error err = NULL, local_err = NULL;
	249	qemu_irq irq;
	250
	251	/* IO space */
	252	create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
	253	ASPEED_SOC_IOMEM_SIZE);
	254
514bcf6f JS	255	/* Video engine stub */
	256	create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
	257	0x1000);
	258
f25c0ae1 CLG	259	if (s->num_cpus > sc->num_cpus) {
	260	warn_report("%s: invalid number of CPUs %d, using default %d",
	261	sc->name, s->num_cpus, sc->num_cpus);
	262	s->num_cpus = sc->num_cpus;
	263	}
	264
	265	/* CPU */
	266	for (i = 0; i < s->num_cpus; i++) {
	267	object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
	268	"psci-conduit", &error_abort);
	269	if (s->num_cpus > 1) {
	270	object_property_set_int(OBJECT(&s->cpu[i]),
	271	ASPEED_A7MPCORE_ADDR,
	272	"reset-cbar", &error_abort);
	273	}
	274	object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i),
	275	"mp-affinity", &error_abort);
	276
058d0955 AJ	277	object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq",
	278	&error_abort);
	279
f25c0ae1 CLG	280	/*
	281	* TODO: the secondary CPUs are started and a boot helper
	282	* is needed when using -kernel
	283	*/
	284
	285	object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
	286	if (err) {
	287	error_propagate(errp, err);
	288	return;
	289	}
	290	}
	291
	292	/* A7MPCORE */
	293	object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu",
	294	&error_abort);
	295	object_property_set_int(OBJECT(&s->a7mpcore),
	296	ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
	297	"num-irq", &error_abort);
	298
	299	object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
	300	&error_abort);
	301	sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
	302
	303	for (i = 0; i < s->num_cpus; i++) {
	304	SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
	305	DeviceState *d = DEVICE(qemu_get_cpu(i));
	306
	307	irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
	308	sysbus_connect_irq(sbd, i, irq);
	309	irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
	310	sysbus_connect_irq(sbd, i + s->num_cpus, irq);
	311	irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
	312	sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq);
	313	irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
	314	sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq);
	315	}
	316
	317	/* SRAM */
	318	memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
	319	sc->sram_size, &err);
	320	if (err) {
	321	error_propagate(errp, err);
	322	return;
	323	}
	324	memory_region_add_subregion(get_system_memory(),
	325	sc->memmap[ASPEED_SRAM], &s->sram);
	326
	327	/* SCU */
	328	object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
	329	if (err) {
	330	error_propagate(errp, err);
	331	return;
	332	}
	333	sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
	334
	335	/* RTC */
	336	object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
	337	if (err) {
	338	error_propagate(errp, err);
	339	return;
	340	}
	341	sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
	342	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
	343	aspeed_soc_get_irq(s, ASPEED_RTC));
344
345	/* Timer */
2ec11f23 CLG	346	object_property_set_link(OBJECT(&s->timerctrl),
2ec11f23 CLG	347	OBJECT(&s->scu), "scu", &error_abort);
f25c0ae1 CLG	348	object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
	349	if (err) {
	350	error_propagate(errp, err);
	351	return;
	352	}
	353	sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
	354	sc->memmap[ASPEED_TIMER1]);
	355	for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
	356	qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
	357	sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
	358	}
	359
	360	/* UART - attach an 8250 to the IO space as our UART5 */
	361	if (serial_hd(0)) {
	362	qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
	363	serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
	364	uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
	365	}
	366
	367	/* I2C */
545d6bef CLG	368	object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
	369	if (err) {
	370	error_propagate(errp, err);
	371	return;
	372	}
f25c0ae1 CLG	373	object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
	374	if (err) {
	375	error_propagate(errp, err);
	376	return;
	377	}
	378	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
	379	for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
	380	qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
	381	sc->irqmap[ASPEED_I2C] + i);
	382	/*
	383	* The AST2600 SoC has one IRQ per I2C bus. Skip the common
	384	* IRQ (AST2400 and AST2500) and connect all bussses.
	385	*/
	386	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
	387	}
	388
	389	/* FMC, The number of CS is set at the board level */
95b56e17 CLG	390	object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
	391	if (err) {
	392	error_propagate(errp, err);
	393	return;
	394	}
f25c0ae1 CLG	395	object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
	396	"sdram-base", &err);
	397	if (err) {
	398	error_propagate(errp, err);
	399	return;
	400	}
	401	object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
	402	if (err) {
	403	error_propagate(errp, err);
	404	return;
	405	}
	406	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
	407	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
	408	s->fmc.ctrl->flash_window_base);
	409	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
	410	aspeed_soc_get_irq(s, ASPEED_FMC));
	411
	412	/* SPI */
	413	for (i = 0; i < sc->spis_num; i++) {
	414	object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
	415	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
	416	&local_err);
	417	error_propagate(&err, local_err);
	418	if (err) {
	419	error_propagate(errp, err);
	420	return;
	421	}
	422	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
	423	sc->memmap[ASPEED_SPI1 + i]);
	424	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
	425	s->spi[i].ctrl->flash_window_base);
	426	}
	427
917940ce GR	428	/* EHCI */
	429	for (i = 0; i < sc->ehcis_num; i++) {
	430	object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
	431	if (err) {
	432	error_propagate(errp, err);
	433	return;
	434	}
	435	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
	436	sc->memmap[ASPEED_EHCI1 + i]);
	437	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
	438	aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
	439	}
	440
f25c0ae1 CLG	441	/* SDMC - SDRAM Memory Controller */
	442	object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
	443	if (err) {
	444	error_propagate(errp, err);
	445	return;
	446	}
	447	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
	448
	449	/* Watch dog */
	450	for (i = 0; i < sc->wdts_num; i++) {
	451	AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
	452
2ec11f23 CLG	453	object_property_set_link(OBJECT(&s->wdt[i]),
2ec11f23 CLG	454	OBJECT(&s->scu), "scu", &error_abort);
f25c0ae1 CLG	455	object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
	456	if (err) {
	457	error_propagate(errp, err);
	458	return;
	459	}
	460	sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
	461	sc->memmap[ASPEED_WDT] + i * awc->offset);
	462	}
	463
	464	/* Net */
d300db02	465	for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
f25c0ae1 CLG	466	qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
	467	object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
	468	&err);
	469	object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
	470	&local_err);
	471	error_propagate(&err, local_err);
	472	if (err) {
	473	error_propagate(errp, err);
	474	return;
	475	}
	476	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
	477	sc->memmap[ASPEED_ETH1 + i]);
	478	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
	479	aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
289251b0	480
ccb88bf2 CLG	481	object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]),
ccb88bf2 CLG	482	"nic", &error_abort);
289251b0 CLG	483	object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
	484	&err);
	485	if (err) {
	486	error_propagate(errp, err);
	487	return;
	488	}
	489
	490	sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
	491	sc->memmap[ASPEED_MII1 + i]);
f25c0ae1 CLG	492	}
	493
	494	/* XDMA */
	495	object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
	496	if (err) {
	497	error_propagate(errp, err);
	498	return;
	499	}
	500	sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
	501	sc->memmap[ASPEED_XDMA]);
	502	sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
	503	aspeed_soc_get_irq(s, ASPEED_XDMA));
	504
	505	/* GPIO */
	506	object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
	507	if (err) {
	508	error_propagate(errp, err);
	509	return;
	510	}
	511	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
	512	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
	513	aspeed_soc_get_irq(s, ASPEED_GPIO));
	514
	515	object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
	516	if (err) {
	517	error_propagate(errp, err);
	518	return;
	519	}
	520	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
	521	sc->memmap[ASPEED_GPIO_1_8V]);
	522	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
	523	aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
	524
	525	/* SDHCI */
	526	object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
	527	if (err) {
	528	error_propagate(errp, err);
	529	return;
	530	}
	531	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
	532	sc->memmap[ASPEED_SDHCI]);
	533	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
	534	aspeed_soc_get_irq(s, ASPEED_SDHCI));
a29e3e12 AJ	535
	536	/* eMMC */
	537	object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
	538	if (err) {
	539	error_propagate(errp, err);
	540	return;
	541	}
	542	sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]);
	543	sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
	544	aspeed_soc_get_irq(s, ASPEED_EMMC));
f25c0ae1 CLG	545	}
	546
	547	static void aspeed_soc_ast2600_class_init(ObjectClass oc, void data)
	548	{
	549	DeviceClass *dc = DEVICE_CLASS(oc);
	550	AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
	551
	552	dc->realize = aspeed_soc_ast2600_realize;
	553
	554	sc->name = "ast2600-a0";
	555	sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
	556	sc->silicon_rev = AST2600_A0_SILICON_REV;
	557	sc->sram_size = 0x10000;
	558	sc->spis_num = 2;
917940ce	559	sc->ehcis_num = 2;
f25c0ae1	560	sc->wdts_num = 4;
d300db02	561	sc->macs_num = 4;
f25c0ae1 CLG	562	sc->irqmap = aspeed_soc_ast2600_irqmap;
	563	sc->memmap = aspeed_soc_ast2600_memmap;
	564	sc->num_cpus = 2;
	565	}
	566
	567	static const TypeInfo aspeed_soc_ast2600_type_info = {
	568	.name = "ast2600-a0",
	569	.parent = TYPE_ASPEED_SOC,
	570	.instance_size = sizeof(AspeedSoCState),
	571	.instance_init = aspeed_soc_ast2600_init,
	572	.class_init = aspeed_soc_ast2600_class_init,
	573	.class_size = sizeof(AspeedSoCClass),
	574	};
	575
	576	static void aspeed_soc_register_types(void)
	577	{
	578	type_register_static(&aspeed_soc_ast2600_type_info);
	579	};
	580
	581	type_init(aspeed_soc_register_types)