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5fafdf24 1/*
16406950
PB
2 * ARM kernel loader.
3 *
9ee6e8bb 4 * Copyright (c) 2006-2007 CodeSourcery.
16406950
PB
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the GPL.
16406950
PB
8 */
9
412beee6 10#include "config.h"
83c9f4ca 11#include "hw/hw.h"
bd2be150 12#include "hw/arm/arm.h"
9c17d615 13#include "sysemu/sysemu.h"
83c9f4ca
PB
14#include "hw/boards.h"
15#include "hw/loader.h"
ca20cf32 16#include "elf.h"
9c17d615 17#include "sysemu/device_tree.h"
1de7afc9 18#include "qemu/config-file.h"
16406950
PB
19
20#define KERNEL_ARGS_ADDR 0x100
21#define KERNEL_LOAD_ADDR 0x00010000
16406950
PB
22
23/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
24static uint32_t bootloader[] = {
25 0xe3a00000, /* mov r0, #0 */
f8414cb5
PM
26 0xe59f1004, /* ldr r1, [pc, #4] */
27 0xe59f2004, /* ldr r2, [pc, #4] */
28 0xe59ff004, /* ldr pc, [pc, #4] */
29 0, /* Board ID */
16406950
PB
30 0, /* Address of kernel args. Set by integratorcp_init. */
31 0 /* Kernel entry point. Set by integratorcp_init. */
32};
33
9d5ba9bf
ML
34/* Handling for secondary CPU boot in a multicore system.
35 * Unlike the uniprocessor/primary CPU boot, this is platform
36 * dependent. The default code here is based on the secondary
37 * CPU boot protocol used on realview/vexpress boards, with
38 * some parameterisation to increase its flexibility.
39 * QEMU platform models for which this code is not appropriate
40 * should override write_secondary_boot and secondary_cpu_reset_hook
41 * instead.
42 *
43 * This code enables the interrupt controllers for the secondary
44 * CPUs and then puts all the secondary CPUs into a loop waiting
45 * for an interprocessor interrupt and polling a configurable
46 * location for the kernel secondary CPU entry point.
47 */
bf471f79
PM
48#define DSB_INSN 0xf57ff04f
49#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
50
9ee6e8bb 51static uint32_t smpboot[] = {
bf471f79
PM
52 0xe59f2028, /* ldr r2, gic_cpu_if */
53 0xe59f0028, /* ldr r0, startaddr */
078758d0 54 0xe3a01001, /* mov r1, #1 */
bf471f79
PM
55 0xe5821000, /* str r1, [r2] - set GICC_CTLR.Enable */
56 0xe3a010ff, /* mov r1, #0xff */
57 0xe5821004, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
58 DSB_INSN, /* dsb */
9ee6e8bb
PB
59 0xe320f003, /* wfi */
60 0xe5901000, /* ldr r1, [r0] */
be0f204a
PB
61 0xe1110001, /* tst r1, r1 */
62 0x0afffffb, /* beq <wfi> */
f7c70325 63 0xe12fff11, /* bx r1 */
96eacf64 64 0, /* gic_cpu_if: base address of GIC CPU interface */
078758d0 65 0 /* bootreg: Boot register address is held here */
9ee6e8bb
PB
66};
67
9543b0cd 68static void default_write_secondary(ARMCPU *cpu,
9d5ba9bf
ML
69 const struct arm_boot_info *info)
70{
71 int n;
72 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
96eacf64 73 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
9d5ba9bf 74 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
bf471f79
PM
75 /* Replace DSB with the pre-v7 DSB if necessary. */
76 if (!arm_feature(&cpu->env, ARM_FEATURE_V7) &&
77 smpboot[n] == DSB_INSN) {
78 smpboot[n] = CP15_DSB_INSN;
79 }
9d5ba9bf
ML
80 smpboot[n] = tswap32(smpboot[n]);
81 }
82 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
83 info->smp_loader_start);
84}
85
5d309320 86static void default_reset_secondary(ARMCPU *cpu,
9d5ba9bf
ML
87 const struct arm_boot_info *info)
88{
5d309320
AF
89 CPUARMState *env = &cpu->env;
90
9d5ba9bf
ML
91 stl_phys_notdirty(info->smp_bootreg_addr, 0);
92 env->regs[15] = info->smp_loader_start;
93}
94
52b43737
PB
95#define WRITE_WORD(p, value) do { \
96 stl_phys_notdirty(p, value); \
97 p += 4; \
98} while (0)
99
761c9eb0 100static void set_kernel_args(const struct arm_boot_info *info)
16406950 101{
761c9eb0 102 int initrd_size = info->initrd_size;
a8170e5e
AK
103 hwaddr base = info->loader_start;
104 hwaddr p;
16406950 105
52b43737 106 p = base + KERNEL_ARGS_ADDR;
16406950 107 /* ATAG_CORE */
52b43737
PB
108 WRITE_WORD(p, 5);
109 WRITE_WORD(p, 0x54410001);
110 WRITE_WORD(p, 1);
111 WRITE_WORD(p, 0x1000);
112 WRITE_WORD(p, 0);
16406950 113 /* ATAG_MEM */
f93eb9ff 114 /* TODO: handle multiple chips on one ATAG list */
52b43737
PB
115 WRITE_WORD(p, 4);
116 WRITE_WORD(p, 0x54410002);
117 WRITE_WORD(p, info->ram_size);
118 WRITE_WORD(p, info->loader_start);
16406950
PB
119 if (initrd_size) {
120 /* ATAG_INITRD2 */
52b43737
PB
121 WRITE_WORD(p, 4);
122 WRITE_WORD(p, 0x54420005);
fc53b7d4 123 WRITE_WORD(p, info->initrd_start);
52b43737 124 WRITE_WORD(p, initrd_size);
16406950 125 }
f93eb9ff 126 if (info->kernel_cmdline && *info->kernel_cmdline) {
16406950
PB
127 /* ATAG_CMDLINE */
128 int cmdline_size;
129
f93eb9ff 130 cmdline_size = strlen(info->kernel_cmdline);
e1fe50dc 131 cpu_physical_memory_write(p + 8, info->kernel_cmdline,
52b43737 132 cmdline_size + 1);
16406950 133 cmdline_size = (cmdline_size >> 2) + 1;
52b43737
PB
134 WRITE_WORD(p, cmdline_size + 2);
135 WRITE_WORD(p, 0x54410009);
136 p += cmdline_size * 4;
16406950 137 }
f93eb9ff
AZ
138 if (info->atag_board) {
139 /* ATAG_BOARD */
140 int atag_board_len;
52b43737 141 uint8_t atag_board_buf[0x1000];
f93eb9ff 142
52b43737
PB
143 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
144 WRITE_WORD(p, (atag_board_len + 8) >> 2);
145 WRITE_WORD(p, 0x414f4d50);
146 cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
f93eb9ff
AZ
147 p += atag_board_len;
148 }
16406950 149 /* ATAG_END */
52b43737
PB
150 WRITE_WORD(p, 0);
151 WRITE_WORD(p, 0);
16406950
PB
152}
153
761c9eb0 154static void set_kernel_args_old(const struct arm_boot_info *info)
2b8f2d41 155{
a8170e5e 156 hwaddr p;
52b43737 157 const char *s;
761c9eb0 158 int initrd_size = info->initrd_size;
a8170e5e 159 hwaddr base = info->loader_start;
2b8f2d41
AZ
160
161 /* see linux/include/asm-arm/setup.h */
52b43737 162 p = base + KERNEL_ARGS_ADDR;
2b8f2d41 163 /* page_size */
52b43737 164 WRITE_WORD(p, 4096);
2b8f2d41 165 /* nr_pages */
52b43737 166 WRITE_WORD(p, info->ram_size / 4096);
2b8f2d41 167 /* ramdisk_size */
52b43737 168 WRITE_WORD(p, 0);
2b8f2d41
AZ
169#define FLAG_READONLY 1
170#define FLAG_RDLOAD 4
171#define FLAG_RDPROMPT 8
172 /* flags */
52b43737 173 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
2b8f2d41 174 /* rootdev */
52b43737 175 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */
2b8f2d41 176 /* video_num_cols */
52b43737 177 WRITE_WORD(p, 0);
2b8f2d41 178 /* video_num_rows */
52b43737 179 WRITE_WORD(p, 0);
2b8f2d41 180 /* video_x */
52b43737 181 WRITE_WORD(p, 0);
2b8f2d41 182 /* video_y */
52b43737 183 WRITE_WORD(p, 0);
2b8f2d41 184 /* memc_control_reg */
52b43737 185 WRITE_WORD(p, 0);
2b8f2d41
AZ
186 /* unsigned char sounddefault */
187 /* unsigned char adfsdrives */
188 /* unsigned char bytes_per_char_h */
189 /* unsigned char bytes_per_char_v */
52b43737 190 WRITE_WORD(p, 0);
2b8f2d41 191 /* pages_in_bank[4] */
52b43737
PB
192 WRITE_WORD(p, 0);
193 WRITE_WORD(p, 0);
194 WRITE_WORD(p, 0);
195 WRITE_WORD(p, 0);
2b8f2d41 196 /* pages_in_vram */
52b43737 197 WRITE_WORD(p, 0);
2b8f2d41 198 /* initrd_start */
fc53b7d4
PM
199 if (initrd_size) {
200 WRITE_WORD(p, info->initrd_start);
201 } else {
52b43737 202 WRITE_WORD(p, 0);
fc53b7d4 203 }
2b8f2d41 204 /* initrd_size */
52b43737 205 WRITE_WORD(p, initrd_size);
2b8f2d41 206 /* rd_start */
52b43737 207 WRITE_WORD(p, 0);
2b8f2d41 208 /* system_rev */
52b43737 209 WRITE_WORD(p, 0);
2b8f2d41 210 /* system_serial_low */
52b43737 211 WRITE_WORD(p, 0);
2b8f2d41 212 /* system_serial_high */
52b43737 213 WRITE_WORD(p, 0);
2b8f2d41 214 /* mem_fclk_21285 */
52b43737 215 WRITE_WORD(p, 0);
2b8f2d41 216 /* zero unused fields */
52b43737
PB
217 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
218 WRITE_WORD(p, 0);
219 }
220 s = info->kernel_cmdline;
221 if (s) {
e1fe50dc 222 cpu_physical_memory_write(p, s, strlen(s) + 1);
52b43737
PB
223 } else {
224 WRITE_WORD(p, 0);
225 }
2b8f2d41
AZ
226}
227
a8170e5e 228static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo)
412beee6 229{
9bfa659e
PM
230 uint32_t *mem_reg_property;
231 uint32_t mem_reg_propsize;
412beee6
GL
232 void *fdt = NULL;
233 char *filename;
234 int size, rc;
9bfa659e 235 uint32_t acells, scells, hival;
412beee6
GL
236
237 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
238 if (!filename) {
239 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
c23045de 240 goto fail;
412beee6
GL
241 }
242
243 fdt = load_device_tree(filename, &size);
244 if (!fdt) {
245 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
246 g_free(filename);
c23045de 247 goto fail;
412beee6
GL
248 }
249 g_free(filename);
250
9bfa659e
PM
251 acells = qemu_devtree_getprop_cell(fdt, "/", "#address-cells");
252 scells = qemu_devtree_getprop_cell(fdt, "/", "#size-cells");
253 if (acells == 0 || scells == 0) {
254 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
c23045de 255 goto fail;
9bfa659e
PM
256 }
257
258 mem_reg_propsize = acells + scells;
259 mem_reg_property = g_new0(uint32_t, mem_reg_propsize);
260 mem_reg_property[acells - 1] = cpu_to_be32(binfo->loader_start);
261 hival = cpu_to_be32(binfo->loader_start >> 32);
262 if (acells > 1) {
263 mem_reg_property[acells - 2] = hival;
264 } else if (hival != 0) {
265 fprintf(stderr, "qemu: dtb file not compatible with "
266 "RAM start address > 4GB\n");
c23045de 267 goto fail;
9bfa659e
PM
268 }
269 mem_reg_property[acells + scells - 1] = cpu_to_be32(binfo->ram_size);
270 hival = cpu_to_be32(binfo->ram_size >> 32);
271 if (scells > 1) {
272 mem_reg_property[acells + scells - 2] = hival;
273 } else if (hival != 0) {
274 fprintf(stderr, "qemu: dtb file not compatible with "
275 "RAM size > 4GB\n");
c23045de 276 goto fail;
9bfa659e
PM
277 }
278
412beee6 279 rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
9bfa659e 280 mem_reg_propsize * sizeof(uint32_t));
412beee6
GL
281 if (rc < 0) {
282 fprintf(stderr, "couldn't set /memory/reg\n");
c23045de 283 goto fail;
412beee6
GL
284 }
285
5e87975c
PC
286 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
287 rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
288 binfo->kernel_cmdline);
289 if (rc < 0) {
290 fprintf(stderr, "couldn't set /chosen/bootargs\n");
c23045de 291 goto fail;
5e87975c 292 }
412beee6
GL
293 }
294
295 if (binfo->initrd_size) {
296 rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
fc53b7d4 297 binfo->initrd_start);
412beee6
GL
298 if (rc < 0) {
299 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
c23045de 300 goto fail;
412beee6
GL
301 }
302
303 rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
fc53b7d4 304 binfo->initrd_start + binfo->initrd_size);
412beee6
GL
305 if (rc < 0) {
306 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
c23045de 307 goto fail;
412beee6
GL
308 }
309 }
2acafb1a 310 qemu_devtree_dumpdtb(fdt, size);
412beee6
GL
311
312 cpu_physical_memory_write(addr, fdt, size);
313
c23045de
PM
314 g_free(fdt);
315
412beee6 316 return 0;
c23045de
PM
317
318fail:
319 g_free(fdt);
320 return -1;
412beee6
GL
321}
322
6ed221b6 323static void do_cpu_reset(void *opaque)
f2d74978 324{
351d5666
AF
325 ARMCPU *cpu = opaque;
326 CPUARMState *env = &cpu->env;
462a8bc6 327 const struct arm_boot_info *info = env->boot_info;
f2d74978 328
351d5666 329 cpu_reset(CPU(cpu));
f2d74978
PB
330 if (info) {
331 if (!info->is_linux) {
332 /* Jump to the entry point. */
333 env->regs[15] = info->entry & 0xfffffffe;
334 env->thumb = info->entry & 1;
335 } else {
6ed221b6
AL
336 if (env == first_cpu) {
337 env->regs[15] = info->loader_start;
412beee6
GL
338 if (!info->dtb_filename) {
339 if (old_param) {
340 set_kernel_args_old(info);
341 } else {
342 set_kernel_args(info);
343 }
6ed221b6 344 }
f2d74978 345 } else {
5d309320 346 info->secondary_cpu_reset_hook(cpu, info);
f2d74978
PB
347 }
348 }
349 }
f2d74978
PB
350}
351
3aaa8dfa 352void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
16406950 353{
3aaa8dfa 354 CPUARMState *env = &cpu->env;
16406950
PB
355 int kernel_size;
356 int initrd_size;
357 int n;
1c7b3754
PB
358 int is_linux = 0;
359 uint64_t elf_entry;
a8170e5e 360 hwaddr entry;
ca20cf32 361 int big_endian;
412beee6 362 QemuOpts *machine_opts;
16406950
PB
363
364 /* Load the kernel. */
f93eb9ff 365 if (!info->kernel_filename) {
16406950
PB
366 fprintf(stderr, "Kernel image must be specified\n");
367 exit(1);
368 }
daf90626 369
412beee6
GL
370 machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
371 if (machine_opts) {
372 info->dtb_filename = qemu_opt_get(machine_opts, "dtb");
373 } else {
374 info->dtb_filename = NULL;
375 }
376
9d5ba9bf
ML
377 if (!info->secondary_cpu_reset_hook) {
378 info->secondary_cpu_reset_hook = default_reset_secondary;
379 }
380 if (!info->write_secondary_boot) {
381 info->write_secondary_boot = default_write_secondary;
382 }
383
f2d74978
PB
384 if (info->nb_cpus == 0)
385 info->nb_cpus = 1;
f93eb9ff 386
ca20cf32
BS
387#ifdef TARGET_WORDS_BIGENDIAN
388 big_endian = 1;
389#else
390 big_endian = 0;
391#endif
392
fc53b7d4
PM
393 /* We want to put the initrd far enough into RAM that when the
394 * kernel is uncompressed it will not clobber the initrd. However
395 * on boards without much RAM we must ensure that we still leave
396 * enough room for a decent sized initrd, and on boards with large
397 * amounts of RAM we must avoid the initrd being so far up in RAM
398 * that it is outside lowmem and inaccessible to the kernel.
399 * So for boards with less than 256MB of RAM we put the initrd
400 * halfway into RAM, and for boards with 256MB of RAM or more we put
401 * the initrd at 128MB.
402 */
403 info->initrd_start = info->loader_start +
404 MIN(info->ram_size / 2, 128 * 1024 * 1024);
405
1c7b3754 406 /* Assume that raw images are linux kernels, and ELF images are not. */
409dbce5
AJ
407 kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
408 NULL, NULL, big_endian, ELF_MACHINE, 1);
1c7b3754
PB
409 entry = elf_entry;
410 if (kernel_size < 0) {
5a9154e0
AL
411 kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
412 &is_linux);
1c7b3754
PB
413 }
414 if (kernel_size < 0) {
f93eb9ff 415 entry = info->loader_start + KERNEL_LOAD_ADDR;
3b760e04 416 kernel_size = load_image_targphys(info->kernel_filename, entry,
0b944384 417 info->ram_size - KERNEL_LOAD_ADDR);
1c7b3754
PB
418 is_linux = 1;
419 }
420 if (kernel_size < 0) {
f93eb9ff
AZ
421 fprintf(stderr, "qemu: could not load kernel '%s'\n",
422 info->kernel_filename);
1c7b3754
PB
423 exit(1);
424 }
f2d74978
PB
425 info->entry = entry;
426 if (is_linux) {
f93eb9ff 427 if (info->initrd_filename) {
3b760e04 428 initrd_size = load_image_targphys(info->initrd_filename,
fc53b7d4
PM
429 info->initrd_start,
430 info->ram_size -
431 info->initrd_start);
daf90626
PB
432 if (initrd_size < 0) {
433 fprintf(stderr, "qemu: could not load initrd '%s'\n",
f93eb9ff 434 info->initrd_filename);
daf90626
PB
435 exit(1);
436 }
437 } else {
438 initrd_size = 0;
439 }
412beee6
GL
440 info->initrd_size = initrd_size;
441
f8414cb5 442 bootloader[4] = info->board_id;
412beee6
GL
443
444 /* for device tree boot, we pass the DTB directly in r2. Otherwise
445 * we point to the kernel args.
446 */
447 if (info->dtb_filename) {
98ed805c
PM
448 /* Place the DTB after the initrd in memory. Note that some
449 * kernels will trash anything in the 4K page the initrd
450 * ends in, so make sure the DTB isn't caught up in that.
451 */
452 hwaddr dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
453 4096);
412beee6
GL
454 if (load_dtb(dtb_start, info)) {
455 exit(1);
456 }
457 bootloader[5] = dtb_start;
458 } else {
459 bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR;
3871481c
PM
460 if (info->ram_size >= (1ULL << 32)) {
461 fprintf(stderr, "qemu: RAM size must be less than 4GB to boot"
462 " Linux kernel using ATAGS (try passing a device tree"
463 " using -dtb)\n");
464 exit(1);
465 }
412beee6 466 }
1c7b3754 467 bootloader[6] = entry;
52b43737 468 for (n = 0; n < sizeof(bootloader) / 4; n++) {
f2d74978 469 bootloader[n] = tswap32(bootloader[n]);
52b43737 470 }
f2d74978
PB
471 rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader),
472 info->loader_start);
52b43737 473 if (info->nb_cpus > 1) {
9543b0cd 474 info->write_secondary_boot(cpu, info);
52b43737 475 }
16406950 476 }
f2d74978 477 info->is_linux = is_linux;
6ed221b6
AL
478
479 for (; env; env = env->next_cpu) {
351d5666 480 cpu = arm_env_get_cpu(env);
6ed221b6 481 env->boot_info = info;
351d5666 482 qemu_register_reset(do_cpu_reset, cpu);
6ed221b6 483 }
16406950 484}