[qemu.git] / hw / arm / highbank.c

/*
 * Calxeda Highbank SoC emulation
 *
 * Copyright (c) 2010-2012 Calxeda
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/devices.h"
#include "hw/loader.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"

#define SMP_BOOT_ADDR 0x100
#define SMP_BOOT_REG  0x40
#define GIC_BASE_ADDR 0xfff10000

#define NIRQ_GIC      160

/* Board init.  */

static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
    int n;
    uint32_t smpboot[] = {
        0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
        0xe210000f, /* ands r0, r0, #0x0f */
        0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
        0xe0830200, /* add r0, r3, r0, lsl #4 */
        0xe59f2024, /* ldr r2, privbase */
        0xe3a01001, /* mov r1, #1 */
        0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
        0xe3a010ff, /* mov r1, #0xff */
        0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
        0xf57ff04f, /* dsb */
        0xe320f003, /* wfi */
        0xe5901000, /* ldr     r1, [r0] */
        0xe1110001, /* tst     r1, r1 */
        0x0afffffb, /* beq     <wfi> */
        0xe12fff11, /* bx      r1 */
        GIC_BASE_ADDR      /* privbase: gic address.  */
    };
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
        smpboot[n] = tswap32(smpboot[n]);
    }
    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
}

static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
    CPUARMState *env = &cpu->env;

    switch (info->nb_cpus) {
    case 4:
        stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
    case 3:
        stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
    case 2:
        stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
        env->regs[15] = SMP_BOOT_ADDR;
        break;
    default:
        break;
    }
}

#define NUM_REGS      0x200
static void hb_regs_write(void *opaque, hwaddr offset,
                          uint64_t value, unsigned size)
{
    uint32_t *regs = opaque;

    if (offset == 0xf00) {
        if (value == 1 || value == 2) {
            qemu_system_reset_request();
        } else if (value == 3) {
            qemu_system_shutdown_request();
        }
    }

    regs[offset/4] = value;
}

static uint64_t hb_regs_read(void *opaque, hwaddr offset,
                             unsigned size)
{
    uint32_t *regs = opaque;
    uint32_t value = regs[offset/4];

    if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
        value |= 0x30000000;
    }

    return value;
}

static const MemoryRegionOps hb_mem_ops = {
    .read = hb_regs_read,
    .write = hb_regs_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
#define HIGHBANK_REGISTERS(obj) \
    OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)

typedef struct {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion *iomem;
    uint32_t regs[NUM_REGS];
} HighbankRegsState;

static VMStateDescription vmstate_highbank_regs = {
    .name = "highbank-regs",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
        VMSTATE_END_OF_LIST(),
    },
};

static void highbank_regs_reset(DeviceState *dev)
{
    HighbankRegsState *s = HIGHBANK_REGISTERS(dev);

    s->regs[0x40] = 0x05F20121;
    s->regs[0x41] = 0x2;
    s->regs[0x42] = 0x05F30121;
    s->regs[0x43] = 0x05F40121;
}

static int highbank_regs_init(SysBusDevice *dev)
{
    HighbankRegsState *s = HIGHBANK_REGISTERS(dev);

    s->iomem = g_new(MemoryRegion, 1);
    memory_region_init_io(s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
                          "highbank_regs", 0x1000);
    sysbus_init_mmio(dev, s->iomem);

    return 0;
}

static void highbank_regs_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = highbank_regs_init;
    dc->desc = "Calxeda Highbank registers";
    dc->vmsd = &vmstate_highbank_regs;
    dc->reset = highbank_regs_reset;
}

static const TypeInfo highbank_regs_info = {
    .name          = TYPE_HIGHBANK_REGISTERS,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(HighbankRegsState),
    .class_init    = highbank_regs_class_init,
};

static void highbank_regs_register_types(void)
{
    type_register_static(&highbank_regs_info);
}

type_init(highbank_regs_register_types)

static struct arm_boot_info highbank_binfo;

enum cxmachines {
    CALXEDA_HIGHBANK,
    CALXEDA_MIDWAY,
};

/* ram_size must be set to match the upper bound of memory in the
 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 * normally 0xff900000 or -m 4089. When running this board on a
 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 * device tree and pass -m 2047 to QEMU.
 */
static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    const char *initrd_filename = args->initrd_filename;
    DeviceState *dev = NULL;
    SysBusDevice *busdev;
    qemu_irq pic[128];
    int n;
    qemu_irq cpu_irq[4];
    MemoryRegion *sysram;
    MemoryRegion *dram;
    MemoryRegion *sysmem;
    char *sysboot_filename;

    if (!cpu_model) {
        switch (machine) {
        case CALXEDA_HIGHBANK:
            cpu_model = "cortex-a9";
            break;
        case CALXEDA_MIDWAY:
            cpu_model = "cortex-a15";
            break;
        }
    }

    for (n = 0; n < smp_cpus; n++) {
        ARMCPU *cpu;
        cpu = cpu_arm_init(cpu_model);
        if (cpu == NULL) {
            fprintf(stderr, "Unable to find CPU definition\n");
            exit(1);
        }

        /* This will become a QOM property eventually */
        cpu->reset_cbar = GIC_BASE_ADDR;
        cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
    }

    sysmem = get_system_memory();
    dram = g_new(MemoryRegion, 1);
    memory_region_init_ram(dram, NULL, "highbank.dram", ram_size);
    /* SDRAM at address zero.  */
    memory_region_add_subregion(sysmem, 0, dram);

    sysram = g_new(MemoryRegion, 1);
    memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000);
    memory_region_add_subregion(sysmem, 0xfff88000, sysram);
    if (bios_name != NULL) {
        sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
        if (sysboot_filename != NULL) {
            uint32_t filesize = get_image_size(sysboot_filename);
            if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
                hw_error("Unable to load %s\n", bios_name);
            }
        } else {
           hw_error("Unable to find %s\n", bios_name);
        }
    }

    switch (machine) {
    case CALXEDA_HIGHBANK:
        dev = qdev_create(NULL, "l2x0");
        qdev_init_nofail(dev);
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, 0xfff12000);

        dev = qdev_create(NULL, "a9mpcore_priv");
        break;
    case CALXEDA_MIDWAY:
        dev = qdev_create(NULL, "a15mpcore_priv");
        break;
    }
    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
    qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
    for (n = 0; n < smp_cpus; n++) {
        sysbus_connect_irq(busdev, n, cpu_irq[n]);
    }

    for (n = 0; n < 128; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    dev = qdev_create(NULL, "sp804");
    qdev_prop_set_uint32(dev, "freq0", 150000000);
    qdev_prop_set_uint32(dev, "freq1", 150000000);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0xfff34000);
    sysbus_connect_irq(busdev, 0, pic[18]);
    sysbus_create_simple("pl011", 0xfff36000, pic[20]);

    dev = qdev_create(NULL, "highbank-regs");
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0xfff3c000);

    sysbus_create_simple("pl061", 0xfff30000, pic[14]);
    sysbus_create_simple("pl061", 0xfff31000, pic[15]);
    sysbus_create_simple("pl061", 0xfff32000, pic[16]);
    sysbus_create_simple("pl061", 0xfff33000, pic[17]);
    sysbus_create_simple("pl031", 0xfff35000, pic[19]);
    sysbus_create_simple("pl022", 0xfff39000, pic[23]);

    sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);

    if (nd_table[0].used) {
        qemu_check_nic_model(&nd_table[0], "xgmac");
        dev = qdev_create(NULL, "xgmac");
        qdev_set_nic_properties(dev, &nd_table[0]);
        qdev_init_nofail(dev);
        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);

        qemu_check_nic_model(&nd_table[1], "xgmac");
        dev = qdev_create(NULL, "xgmac");
        qdev_set_nic_properties(dev, &nd_table[1]);
        qdev_init_nofail(dev);
        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
    }

    highbank_binfo.ram_size = ram_size;
    highbank_binfo.kernel_filename = kernel_filename;
    highbank_binfo.kernel_cmdline = kernel_cmdline;
    highbank_binfo.initrd_filename = initrd_filename;
    /* highbank requires a dtb in order to boot, and the dtb will override
     * the board ID. The following value is ignored, so set it to -1 to be
     * clear that the value is meaningless.
     */
    highbank_binfo.board_id = -1;
    highbank_binfo.nb_cpus = smp_cpus;
    highbank_binfo.loader_start = 0;
    highbank_binfo.write_secondary_boot = hb_write_secondary;
    highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
    arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
}

static void highbank_init(QEMUMachineInitArgs *args)
{
    calxeda_init(args, CALXEDA_HIGHBANK);
}

static void midway_init(QEMUMachineInitArgs *args)
{
    calxeda_init(args, CALXEDA_MIDWAY);
}

static QEMUMachine highbank_machine = {
    .name = "highbank",
    .desc = "Calxeda Highbank (ECX-1000)",
    .init = highbank_init,
    .block_default_type = IF_SCSI,
    .max_cpus = 4,
};

static QEMUMachine midway_machine = {
    .name = "midway",
    .desc = "Calxeda Midway (ECX-2000)",
    .init = midway_init,
    .block_default_type = IF_SCSI,
    .max_cpus = 4,
};

static void calxeda_machines_init(void)
{
    qemu_register_machine(&highbank_machine);
    qemu_register_machine(&midway_machine);
}

machine_init(calxeda_machines_init);
Commit	Line	Data
2488514c RH	1	/*
	2	* Calxeda Highbank SoC emulation
	3	*
	4	* Copyright (c) 2010-2012 Calxeda
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	*/
	19
83c9f4ca	20	#include "hw/sysbus.h"
bd2be150 PM	21	#include "hw/arm/arm.h"
bd2be150 PM	22	#include "hw/devices.h"
83c9f4ca	23	#include "hw/loader.h"
1422e32d	24	#include "net/net.h"
9c17d615	25	#include "sysemu/sysemu.h"
83c9f4ca	26	#include "hw/boards.h"
9c17d615	27	#include "sysemu/blockdev.h"
022c62cb	28	#include "exec/address-spaces.h"
2488514c RH	29
	30	#define SMP_BOOT_ADDR 0x100
	31	#define SMP_BOOT_REG 0x40
	32	#define GIC_BASE_ADDR 0xfff10000
	33
	34	#define NIRQ_GIC 160
	35
	36	/* Board init. */
2488514c	37
9543b0cd	38	static void hb_write_secondary(ARMCPU cpu, const struct arm_boot_info info)
2488514c RH	39	{
	40	int n;
	41	uint32_t smpboot[] = {
	42	0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
	43	0xe210000f, /* ands r0, r0, #0x0f */
	44	0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
	45	0xe0830200, /* add r0, r3, r0, lsl #4 */
bf471f79	46	0xe59f2024, /* ldr r2, privbase */
2488514c	47	0xe3a01001, /* mov r1, #1 */
bf471f79 PM	48	0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
	49	0xe3a010ff, /* mov r1, #0xff */
	50	0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
	51	0xf57ff04f, /* dsb */
2488514c RH	52	0xe320f003, /* wfi */
	53	0xe5901000, /* ldr r1, [r0] */
	54	0xe1110001, /* tst r1, r1 */
	55	0x0afffffb, /* beq <wfi> */
	56	0xe12fff11, /* bx r1 */
	57	GIC_BASE_ADDR /* privbase: gic address. */
	58	};
	59	for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
	60	smpboot[n] = tswap32(smpboot[n]);
	61	}
	62	rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
	63	}
	64
5d309320	65	static void hb_reset_secondary(ARMCPU cpu, const struct arm_boot_info info)
2488514c	66	{
5d309320 AF	67	CPUARMState *env = &cpu->env;
5d309320 AF	68
2488514c RH	69	switch (info->nb_cpus) {
	70	case 4:
	71	stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
	72	case 3:
	73	stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
	74	case 2:
	75	stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
	76	env->regs[15] = SMP_BOOT_ADDR;
	77	break;
	78	default:
	79	break;
	80	}
	81	}
	82
	83	#define NUM_REGS 0x200
a8170e5e	84	static void hb_regs_write(void *opaque, hwaddr offset,
2488514c RH	85	uint64_t value, unsigned size)
	86	{
	87	uint32_t *regs = opaque;
	88
	89	if (offset == 0xf00) {
	90	if (value == 1 \|\| value == 2) {
	91	qemu_system_reset_request();
	92	} else if (value == 3) {
	93	qemu_system_shutdown_request();
	94	}
	95	}
	96
	97	regs[offset/4] = value;
	98	}
	99
a8170e5e	100	static uint64_t hb_regs_read(void *opaque, hwaddr offset,
2488514c RH	101	unsigned size)
	102	{
	103	uint32_t *regs = opaque;
	104	uint32_t value = regs[offset/4];
	105
	106	if ((offset == 0x100) \|\| (offset == 0x108) \|\| (offset == 0x10C)) {
	107	value \|= 0x30000000;
	108	}
	109
	110	return value;
	111	}
	112
	113	static const MemoryRegionOps hb_mem_ops = {
	114	.read = hb_regs_read,
	115	.write = hb_regs_write,
	116	.endianness = DEVICE_NATIVE_ENDIAN,
	117	};
	118
426533fa AF	119	#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
	120	#define HIGHBANK_REGISTERS(obj) \
	121	OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
	122
2488514c	123	typedef struct {
426533fa AF	124	/< private >/
	125	SysBusDevice parent_obj;
	126	/< public >/
	127
2488514c RH	128	MemoryRegion *iomem;
	129	uint32_t regs[NUM_REGS];
	130	} HighbankRegsState;
	131
	132	static VMStateDescription vmstate_highbank_regs = {
	133	.name = "highbank-regs",
	134	.version_id = 0,
	135	.minimum_version_id = 0,
	136	.minimum_version_id_old = 0,
	137	.fields = (VMStateField[]) {
	138	VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
	139	VMSTATE_END_OF_LIST(),
	140	},
	141	};
	142
	143	static void highbank_regs_reset(DeviceState *dev)
	144	{
426533fa	145	HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
2488514c RH	146
	147	s->regs[0x40] = 0x05F20121;
	148	s->regs[0x41] = 0x2;
	149	s->regs[0x42] = 0x05F30121;
	150	s->regs[0x43] = 0x05F40121;
	151	}
	152
	153	static int highbank_regs_init(SysBusDevice *dev)
	154	{
426533fa	155	HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
2488514c RH	156
2488514c RH	157	s->iomem = g_new(MemoryRegion, 1);
64bde0f3 PB	158	memory_region_init_io(s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
64bde0f3 PB	159	"highbank_regs", 0x1000);
2488514c RH	160	sysbus_init_mmio(dev, s->iomem);
	161
	162	return 0;
	163	}
	164
999e12bb AL	165	static void highbank_regs_class_init(ObjectClass klass, void data)
	166	{
	167	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
39bffca2	168	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	169
999e12bb AL	170	sbc->init = highbank_regs_init;
39bffca2 AL	171	dc->desc = "Calxeda Highbank registers";
	172	dc->vmsd = &vmstate_highbank_regs;
	173	dc->reset = highbank_regs_reset;
999e12bb AL	174	}
999e12bb AL	175
8c43a6f0	176	static const TypeInfo highbank_regs_info = {
426533fa	177	.name = TYPE_HIGHBANK_REGISTERS,
39bffca2 AL	178	.parent = TYPE_SYS_BUS_DEVICE,
	179	.instance_size = sizeof(HighbankRegsState),
	180	.class_init = highbank_regs_class_init,
2488514c RH	181	};
2488514c RH	182
83f7d43a	183	static void highbank_regs_register_types(void)
2488514c	184	{
39bffca2	185	type_register_static(&highbank_regs_info);
2488514c RH	186	}
2488514c RH	187
83f7d43a	188	type_init(highbank_regs_register_types)
2488514c RH	189
	190	static struct arm_boot_info highbank_binfo;
	191
574f66bc AP	192	enum cxmachines {
574f66bc AP	193	CALXEDA_HIGHBANK,
b25a83f0	194	CALXEDA_MIDWAY,
574f66bc AP	195	};
574f66bc AP	196
2488514c RH	197	/* ram_size must be set to match the upper bound of memory in the
	198	* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
	199	* normally 0xff900000 or -m 4089. When running this board on a
	200	* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
	201	* device tree and pass -m 2047 to QEMU.
	202	*/
574f66bc	203	static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
2488514c	204	{
5f072e1f EH	205	ram_addr_t ram_size = args->ram_size;
	206	const char *cpu_model = args->cpu_model;
	207	const char *kernel_filename = args->kernel_filename;
	208	const char *kernel_cmdline = args->kernel_cmdline;
	209	const char *initrd_filename = args->initrd_filename;
574f66bc	210	DeviceState *dev = NULL;
2488514c	211	SysBusDevice *busdev;
2488514c RH	212	qemu_irq pic[128];
	213	int n;
	214	qemu_irq cpu_irq[4];
	215	MemoryRegion *sysram;
	216	MemoryRegion *dram;
	217	MemoryRegion *sysmem;
	218	char *sysboot_filename;
	219
	220	if (!cpu_model) {
574f66bc AP	221	switch (machine) {
	222	case CALXEDA_HIGHBANK:
	223	cpu_model = "cortex-a9";
	224	break;
b25a83f0 AP	225	case CALXEDA_MIDWAY:
	226	cpu_model = "cortex-a15";
	227	break;
574f66bc	228	}
2488514c RH	229	}
	230
	231	for (n = 0; n < smp_cpus; n++) {
c5fad12f PM	232	ARMCPU *cpu;
	233	cpu = cpu_arm_init(cpu_model);
	234	if (cpu == NULL) {
2488514c RH	235	fprintf(stderr, "Unable to find CPU definition\n");
	236	exit(1);
	237	}
4bd74661	238
c5fad12f PM	239	/* This will become a QOM property eventually */
c5fad12f PM	240	cpu->reset_cbar = GIC_BASE_ADDR;
9188dbf7	241	cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
2488514c RH	242	}
	243
	244	sysmem = get_system_memory();
	245	dram = g_new(MemoryRegion, 1);
2c9b15ca	246	memory_region_init_ram(dram, NULL, "highbank.dram", ram_size);
2488514c RH	247	/* SDRAM at address zero. */
	248	memory_region_add_subregion(sysmem, 0, dram);
	249
	250	sysram = g_new(MemoryRegion, 1);
2c9b15ca	251	memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000);
2488514c RH	252	memory_region_add_subregion(sysmem, 0xfff88000, sysram);
	253	if (bios_name != NULL) {
	254	sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	255	if (sysboot_filename != NULL) {
	256	uint32_t filesize = get_image_size(sysboot_filename);
	257	if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
	258	hw_error("Unable to load %s\n", bios_name);
	259	}
	260	} else {
	261	hw_error("Unable to find %s\n", bios_name);
	262	}
	263	}
	264
574f66bc AP	265	switch (machine) {
574f66bc AP	266	case CALXEDA_HIGHBANK:
b25a83f0 AP	267	dev = qdev_create(NULL, "l2x0");
	268	qdev_init_nofail(dev);
	269	busdev = SYS_BUS_DEVICE(dev);
	270	sysbus_mmio_map(busdev, 0, 0xfff12000);
	271
574f66bc AP	272	dev = qdev_create(NULL, "a9mpcore_priv");
574f66bc AP	273	break;
b25a83f0 AP	274	case CALXEDA_MIDWAY:
	275	dev = qdev_create(NULL, "a15mpcore_priv");
	276	break;
574f66bc	277	}
2488514c RH	278	qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
	279	qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
	280	qdev_init_nofail(dev);
1356b98d	281	busdev = SYS_BUS_DEVICE(dev);
2488514c RH	282	sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
	283	for (n = 0; n < smp_cpus; n++) {
	284	sysbus_connect_irq(busdev, n, cpu_irq[n]);
	285	}
	286
	287	for (n = 0; n < 128; n++) {
	288	pic[n] = qdev_get_gpio_in(dev, n);
	289	}
	290
2488514c RH	291	dev = qdev_create(NULL, "sp804");
	292	qdev_prop_set_uint32(dev, "freq0", 150000000);
	293	qdev_prop_set_uint32(dev, "freq1", 150000000);
	294	qdev_init_nofail(dev);
1356b98d	295	busdev = SYS_BUS_DEVICE(dev);
2488514c RH	296	sysbus_mmio_map(busdev, 0, 0xfff34000);
	297	sysbus_connect_irq(busdev, 0, pic[18]);
	298	sysbus_create_simple("pl011", 0xfff36000, pic[20]);
	299
	300	dev = qdev_create(NULL, "highbank-regs");
	301	qdev_init_nofail(dev);
1356b98d	302	busdev = SYS_BUS_DEVICE(dev);
2488514c RH	303	sysbus_mmio_map(busdev, 0, 0xfff3c000);
	304
	305	sysbus_create_simple("pl061", 0xfff30000, pic[14]);
	306	sysbus_create_simple("pl061", 0xfff31000, pic[15]);
	307	sysbus_create_simple("pl061", 0xfff32000, pic[16]);
	308	sysbus_create_simple("pl061", 0xfff33000, pic[17]);
	309	sysbus_create_simple("pl031", 0xfff35000, pic[19]);
	310	sysbus_create_simple("pl022", 0xfff39000, pic[23]);
	311
	312	sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
	313
a005d073	314	if (nd_table[0].used) {
2488514c RH	315	qemu_check_nic_model(&nd_table[0], "xgmac");
	316	dev = qdev_create(NULL, "xgmac");
	317	qdev_set_nic_properties(dev, &nd_table[0]);
	318	qdev_init_nofail(dev);
1356b98d AF	319	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
	320	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
	321	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
	322	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
2488514c RH	323
	324	qemu_check_nic_model(&nd_table[1], "xgmac");
	325	dev = qdev_create(NULL, "xgmac");
	326	qdev_set_nic_properties(dev, &nd_table[1]);
	327	qdev_init_nofail(dev);
1356b98d AF	328	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
	329	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
	330	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
	331	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
2488514c RH	332	}
	333
	334	highbank_binfo.ram_size = ram_size;
	335	highbank_binfo.kernel_filename = kernel_filename;
	336	highbank_binfo.kernel_cmdline = kernel_cmdline;
	337	highbank_binfo.initrd_filename = initrd_filename;
	338	/* highbank requires a dtb in order to boot, and the dtb will override
	339	* the board ID. The following value is ignored, so set it to -1 to be
	340	* clear that the value is meaningless.
	341	*/
	342	highbank_binfo.board_id = -1;
	343	highbank_binfo.nb_cpus = smp_cpus;
	344	highbank_binfo.loader_start = 0;
	345	highbank_binfo.write_secondary_boot = hb_write_secondary;
	346	highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
182735ef	347	arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
2488514c RH	348	}
2488514c RH	349
574f66bc AP	350	static void highbank_init(QEMUMachineInitArgs *args)
	351	{
	352	calxeda_init(args, CALXEDA_HIGHBANK);
	353	}
	354
b25a83f0 AP	355	static void midway_init(QEMUMachineInitArgs *args)
	356	{
	357	calxeda_init(args, CALXEDA_MIDWAY);
	358	}
	359
2488514c RH	360	static QEMUMachine highbank_machine = {
	361	.name = "highbank",
	362	.desc = "Calxeda Highbank (ECX-1000)",
	363	.init = highbank_init,
2d0d2837	364	.block_default_type = IF_SCSI,
2488514c RH	365	.max_cpus = 4,
	366	};
	367
b25a83f0 AP	368	static QEMUMachine midway_machine = {
	369	.name = "midway",
	370	.desc = "Calxeda Midway (ECX-2000)",
	371	.init = midway_init,
	372	.block_default_type = IF_SCSI,
	373	.max_cpus = 4,
b25a83f0 AP	374	};
b25a83f0 AP	375
574f66bc	376	static void calxeda_machines_init(void)
2488514c RH	377	{
2488514c RH	378	qemu_register_machine(&highbank_machine);
b25a83f0	379	qemu_register_machine(&midway_machine);
2488514c RH	380	}
2488514c RH	381
574f66bc	382	machine_init(calxeda_machines_init);