[mirror_qemu.git] / hw / arm / raspi.c

/*
 * Raspberry Pi emulation (c) 2012 Gregory Estrade
 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
 *
 * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft
 * Written by Andrew Baumann
 *
 * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti
 * Upstream code cleanup (c) 2018 Pekka Enberg
 *
 * This code is licensed under the GNU GPLv2 and later.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/arm/bcm2836.h"
#include "hw/registerfields.h"
#include "qemu/error-report.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/arm/boot.h"
#include "sysemu/sysemu.h"

#define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
#define MVBAR_ADDR      0x400 /* secure vectors */
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */

/* Registered machine type (matches RPi Foundation bootloader and U-Boot) */
#define MACH_TYPE_BCM2708   3138

typedef struct RaspiMachineState {
    /*< private >*/
    MachineState parent_obj;
    /*< public >*/
    BCM283XState soc;
} RaspiMachineState;

typedef struct RaspiMachineClass {
    /*< private >*/
    MachineClass parent_obj;
    /*< public >*/
    uint32_t board_rev;
} RaspiMachineClass;

#define TYPE_RASPI_MACHINE       MACHINE_TYPE_NAME("raspi-common")
#define RASPI_MACHINE(obj) \
    OBJECT_CHECK(RaspiMachineState, (obj), TYPE_RASPI_MACHINE)

#define RASPI_MACHINE_CLASS(klass) \
     OBJECT_CLASS_CHECK(RaspiMachineClass, (klass), TYPE_RASPI_MACHINE)
#define RASPI_MACHINE_GET_CLASS(obj) \
     OBJECT_GET_CLASS(RaspiMachineClass, (obj), TYPE_RASPI_MACHINE)

/*
 * Board revision codes:
 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/
 */
FIELD(REV_CODE, REVISION,           0, 4);
FIELD(REV_CODE, TYPE,               4, 8);
FIELD(REV_CODE, PROCESSOR,         12, 4);
FIELD(REV_CODE, MANUFACTURER,      16, 4);
FIELD(REV_CODE, MEMORY_SIZE,       20, 3);
FIELD(REV_CODE, STYLE,             23, 1);

static uint64_t board_ram_size(uint32_t board_rev)
{
    assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
    return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
}

static int board_processor_id(uint32_t board_rev)
{
    assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
    return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
}

static int board_version(uint32_t board_rev)
{
    return board_processor_id(board_rev) + 1;
}

static const char *board_soc_type(uint32_t board_rev)
{
    static const char *soc_types[] = {
        NULL, TYPE_BCM2836, TYPE_BCM2837,
    };
    int proc_id = board_processor_id(board_rev);

    if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
        error_report("Unsupported processor id '%d' (board revision: 0x%x)",
                     proc_id, board_rev);
        exit(1);
    }
    return soc_types[proc_id];
}

static int cores_count(uint32_t board_rev)
{
    static const int soc_cores_count[] = {
        0, BCM283X_NCPUS, BCM283X_NCPUS,
    };
    int proc_id = board_processor_id(board_rev);

    if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) {
        error_report("Unsupported processor id '%d' (board revision: 0x%x)",
                     proc_id, board_rev);
        exit(1);
    }
    return soc_cores_count[proc_id];
}

static const char *board_type(uint32_t board_rev)
{
    static const char *types[] = {
        "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero",
        "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B",
    };
    assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
    int bt = FIELD_EX32(board_rev, REV_CODE, TYPE);
    if (bt >= ARRAY_SIZE(types) || !types[bt]) {
        return "Unknown";
    }
    return types[bt];
}

static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
{
    static const uint32_t smpboot[] = {
        0xe1a0e00f, /*    mov     lr, pc */
        0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */
        0xee100fb0, /*    mrc     p15, 0, r0, c0, c0, 5;get core ID */
        0xe7e10050, /*    ubfx    r0, r0, #0, #2       ;extract LSB */
        0xe59f5014, /*    ldr     r5, =0x400000CC      ;load mbox base */
        0xe320f001, /* 1: yield */
        0xe7953200, /*    ldr     r3, [r5, r0, lsl #4] ;read mbox for our core*/
        0xe3530000, /*    cmp     r3, #0               ;spin while zero */
        0x0afffffb, /*    beq     1b */
        0xe7853200, /*    str     r3, [r5, r0, lsl #4] ;clear mbox */
        0xe12fff13, /*    bx      r3                   ;jump to target */
        0x400000cc, /* (constant: mailbox 3 read/clear base) */
    };

    /* check that we don't overrun board setup vectors */
    QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR);
    /* check that board setup address is correctly relocated */
    QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0
                      || (BOARDSETUP_ADDR >> 4) >= 0x100);

    rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
                          info->smp_loader_start,
                          arm_boot_address_space(cpu, info));
}

static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
{
    AddressSpace *as = arm_boot_address_space(cpu, info);
    /* Unlike the AArch32 version we don't need to call the board setup hook.
     * The mechanism for doing the spin-table is also entirely different.
     * We must have four 64-bit fields at absolute addresses
     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
     * our CPUs, and which we must ensure are zero initialized before
     * the primary CPU goes into the kernel. We put these variables inside
     * a rom blob, so that the reset for ROM contents zeroes them for us.
     */
    static const uint32_t smpboot[] = {
        0xd2801b05, /*        mov     x5, 0xd8 */
        0xd53800a6, /*        mrs     x6, mpidr_el1 */
        0x924004c6, /*        and     x6, x6, #0x3 */
        0xd503205f, /* spin:  wfe */
        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
        0xb4ffffc4, /*        cbz     x4, spin */
        0xd2800000, /*        mov     x0, #0x0 */
        0xd2800001, /*        mov     x1, #0x0 */
        0xd2800002, /*        mov     x2, #0x0 */
        0xd2800003, /*        mov     x3, #0x0 */
        0xd61f0080, /*        br      x4 */
    };

    static const uint64_t spintables[] = {
        0, 0, 0, 0
    };

    rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
                          info->smp_loader_start, as);
    rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables),
                          SPINTABLE_ADDR, as);
}

static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
{
    arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
}

static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
    CPUState *cs = CPU(cpu);
    cpu_set_pc(cs, info->smp_loader_start);
}

static void setup_boot(MachineState *machine, int version, size_t ram_size)
{
    static struct arm_boot_info binfo;
    int r;

    binfo.board_id = MACH_TYPE_BCM2708;
    binfo.ram_size = ram_size;
    binfo.nb_cpus = machine->smp.cpus;

    if (version <= 2) {
        /* The rpi1 and 2 require some custom setup code to run in Secure
         * mode before booting a kernel (to set up the SMC vectors so
         * that we get a no-op SMC; this is used by Linux to call the
         * firmware for some cache maintenance operations.
         * The rpi3 doesn't need this.
         */
        binfo.board_setup_addr = BOARDSETUP_ADDR;
        binfo.write_board_setup = write_board_setup;
        binfo.secure_board_setup = true;
        binfo.secure_boot = true;
    }

    /* Pi2 and Pi3 requires SMP setup */
    if (version >= 2) {
        binfo.smp_loader_start = SMPBOOT_ADDR;
        if (version == 2) {
            binfo.write_secondary_boot = write_smpboot;
        } else {
            binfo.write_secondary_boot = write_smpboot64;
        }
        binfo.secondary_cpu_reset_hook = reset_secondary;
    }

    /* If the user specified a "firmware" image (e.g. UEFI), we bypass
     * the normal Linux boot process
     */
    if (machine->firmware) {
        hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
        /* load the firmware image (typically kernel.img) */
        r = load_image_targphys(machine->firmware, firmware_addr,
                                ram_size - firmware_addr);
        if (r < 0) {
            error_report("Failed to load firmware from %s", machine->firmware);
            exit(1);
        }

        binfo.entry = firmware_addr;
        binfo.firmware_loaded = true;
    }

    arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
}

static void raspi_machine_init(MachineState *machine)
{
    RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
    RaspiMachineState *s = RASPI_MACHINE(machine);
    uint32_t board_rev = mc->board_rev;
    int version = board_version(board_rev);
    uint64_t ram_size = board_ram_size(board_rev);
    uint32_t vcram_size;
    DriveInfo *di;
    BlockBackend *blk;
    BusState *bus;
    DeviceState *carddev;

    if (machine->ram_size != ram_size) {
        char *size_str = size_to_str(ram_size);
        error_report("Invalid RAM size, should be %s", size_str);
        g_free(size_str);
        exit(1);
    }

    /* FIXME: Remove when we have custom CPU address space support */
    memory_region_add_subregion_overlap(get_system_memory(), 0,
                                        machine->ram, 0);

    /* Setup the SOC */
    object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
                            board_soc_type(board_rev), &error_abort, NULL);
    object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram),
                                   &error_abort);
    object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort);

    /* Create and plug in the SD cards */
    di = drive_get_next(IF_SD);
    blk = di ? blk_by_legacy_dinfo(di) : NULL;
    bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus");
    if (bus == NULL) {
        error_report("No SD bus found in SOC object");
        exit(1);
    }
    carddev = qdev_create(bus, TYPE_SD_CARD);
    qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
    object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);

    vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
                                          &error_abort);
    setup_boot(machine, version, machine->ram_size - vcram_size);
}

static void raspi_machine_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);
    RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
    uint32_t board_rev = (uint32_t)(uintptr_t)data;

    rmc->board_rev = board_rev;
    mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev));
    mc->init = raspi_machine_init;
    mc->block_default_type = IF_SD;
    mc->no_parallel = 1;
    mc->no_floppy = 1;
    mc->no_cdrom = 1;
    mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
    mc->default_ram_size = board_ram_size(board_rev);
    mc->default_ram_id = "ram";
    if (board_version(board_rev) == 2) {
        mc->ignore_memory_transaction_failures = true;
    }
};

static const TypeInfo raspi_machine_types[] = {
    {
        .name           = MACHINE_TYPE_NAME("raspi2"),
        .parent         = TYPE_RASPI_MACHINE,
        .class_init     = raspi_machine_class_init,
        .class_data     = (void *)0xa21041,
#ifdef TARGET_AARCH64
    }, {
        .name           = MACHINE_TYPE_NAME("raspi3"),
        .parent         = TYPE_RASPI_MACHINE,
        .class_init     = raspi_machine_class_init,
        .class_data     = (void *)0xa02082,
#endif
    }, {
        .name           = TYPE_RASPI_MACHINE,
        .parent         = TYPE_MACHINE,
        .instance_size  = sizeof(RaspiMachineState),
        .class_size     = sizeof(RaspiMachineClass),
        .abstract       = true,
    }
};

DEFINE_TYPES(raspi_machine_types)
Commit	Line	Data
1df7d1f9 AB	1	/*
	2	* Raspberry Pi emulation (c) 2012 Gregory Estrade
	3	* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
	4	*
	5	* Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft
	6	* Written by Andrew Baumann
	7	*
bade5816 PE	8	* Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti
	9	* Upstream code cleanup (c) 2018 Pekka Enberg
	10	*
1df7d1f9 AB	11	* This code is licensed under the GNU GPLv2 and later.
	12	*/
	13
c964b660	14	#include "qemu/osdep.h"
ff3dcf28	15	#include "qemu/units.h"
f5bb124e	16	#include "qemu/cutils.h"
da34e65c	17	#include "qapi/error.h"
4771d756	18	#include "cpu.h"
1df7d1f9	19	#include "hw/arm/bcm2836.h"
cd6c9977	20	#include "hw/registerfields.h"
1df7d1f9 AB	21	#include "qemu/error-report.h"
	22	#include "hw/boards.h"
	23	#include "hw/loader.h"
12ec8bd5	24	#include "hw/arm/boot.h"
1df7d1f9 AB	25	#include "sysemu/sysemu.h"
	26
	27	#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
	28	#define MVBAR_ADDR 0x400 /* secure vectors */
	29	#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
bade5816 PE	30	#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
bade5816 PE	31	#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
ff72cb6b	32	#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
1df7d1f9	33
918c81a5 PMD	34	/* Registered machine type (matches RPi Foundation bootloader and U-Boot) */
918c81a5 PMD	35	#define MACH_TYPE_BCM2708 3138
1df7d1f9	36
cb57df6f PMD	37	typedef struct RaspiMachineState {
	38	/< private >/
	39	MachineState parent_obj;
	40	/< public >/
926dcdf0	41	BCM283XState soc;
cb57df6f PMD	42	} RaspiMachineState;
	43
	44	typedef struct RaspiMachineClass {
	45	/< private >/
	46	MachineClass parent_obj;
	47	/< public >/
c318c66c	48	uint32_t board_rev;
cb57df6f PMD	49	} RaspiMachineClass;
	50
	51	#define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
	52	#define RASPI_MACHINE(obj) \
	53	OBJECT_CHECK(RaspiMachineState, (obj), TYPE_RASPI_MACHINE)
	54
	55	#define RASPI_MACHINE_CLASS(klass) \
	56	OBJECT_CLASS_CHECK(RaspiMachineClass, (klass), TYPE_RASPI_MACHINE)
	57	#define RASPI_MACHINE_GET_CLASS(obj) \
	58	OBJECT_GET_CLASS(RaspiMachineClass, (obj), TYPE_RASPI_MACHINE)
1df7d1f9	59
cd6c9977 PMD	60	/*
	61	* Board revision codes:
	62	* www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/
	63	*/
	64	FIELD(REV_CODE, REVISION, 0, 4);
	65	FIELD(REV_CODE, TYPE, 4, 8);
	66	FIELD(REV_CODE, PROCESSOR, 12, 4);
	67	FIELD(REV_CODE, MANUFACTURER, 16, 4);
	68	FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
	69	FIELD(REV_CODE, STYLE, 23, 1);
	70
f5bb124e PMD	71	static uint64_t board_ram_size(uint32_t board_rev)
	72	{
	73	assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
	74	return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
	75	}
	76
cd6c9977 PMD	77	static int board_processor_id(uint32_t board_rev)
	78	{
	79	assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
	80	return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
	81	}
	82
	83	static int board_version(uint32_t board_rev)
	84	{
	85	return board_processor_id(board_rev) + 1;
	86	}
	87
2e664b45 PMD	88	static const char *board_soc_type(uint32_t board_rev)
	89	{
	90	static const char *soc_types[] = {
	91	NULL, TYPE_BCM2836, TYPE_BCM2837,
	92	};
	93	int proc_id = board_processor_id(board_rev);
	94
	95	if (proc_id >= ARRAY_SIZE(soc_types) \|\| !soc_types[proc_id]) {
	96	error_report("Unsupported processor id '%d' (board revision: 0x%x)",
	97	proc_id, board_rev);
	98	exit(1);
	99	}
	100	return soc_types[proc_id];
	101	}
	102
759f0f87 PMD	103	static int cores_count(uint32_t board_rev)
	104	{
	105	static const int soc_cores_count[] = {
	106	0, BCM283X_NCPUS, BCM283X_NCPUS,
	107	};
	108	int proc_id = board_processor_id(board_rev);
	109
	110	if (proc_id >= ARRAY_SIZE(soc_cores_count) \|\| !soc_cores_count[proc_id]) {
	111	error_report("Unsupported processor id '%d' (board revision: 0x%x)",
	112	proc_id, board_rev);
	113	exit(1);
	114	}
	115	return soc_cores_count[proc_id];
	116	}
	117
98b541e1 PMD	118	static const char *board_type(uint32_t board_rev)
	119	{
	120	static const char *types[] = {
	121	"A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero",
	122	"CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B",
	123	};
	124	assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
	125	int bt = FIELD_EX32(board_rev, REV_CODE, TYPE);
	126	if (bt >= ARRAY_SIZE(types) \|\| !types[bt]) {
	127	return "Unknown";
	128	}
	129	return types[bt];
	130	}
	131
1df7d1f9 AB	132	static void write_smpboot(ARMCPU cpu, const struct arm_boot_info info)
	133	{
	134	static const uint32_t smpboot[] = {
	135	0xe1a0e00f, /* mov lr, pc */
	136	0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */
	137	0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */
	138	0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */
	139	0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */
	140	0xe320f001, /* 1: yield */
	141	0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/
	142	0xe3530000, /* cmp r3, #0 ;spin while zero */
	143	0x0afffffb, /* beq 1b */
	144	0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */
	145	0xe12fff13, /* bx r3 ;jump to target */
	146	0x400000cc, /* (constant: mailbox 3 read/clear base) */
	147	};
	148
	149	/* check that we don't overrun board setup vectors */
	150	QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR);
	151	/* check that board setup address is correctly relocated */
	152	QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0
	153	\|\| (BOARDSETUP_ADDR >> 4) >= 0x100);
	154
0f073693 PMD	155	rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
	156	info->smp_loader_start,
	157	arm_boot_address_space(cpu, info));
1df7d1f9 AB	158	}
1df7d1f9 AB	159
ff72cb6b PM	160	static void write_smpboot64(ARMCPU cpu, const struct arm_boot_info info)
ff72cb6b PM	161	{
0f073693	162	AddressSpace *as = arm_boot_address_space(cpu, info);
ff72cb6b PM	163	/* Unlike the AArch32 version we don't need to call the board setup hook.
	164	* The mechanism for doing the spin-table is also entirely different.
	165	* We must have four 64-bit fields at absolute addresses
	166	* 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
	167	* our CPUs, and which we must ensure are zero initialized before
	168	* the primary CPU goes into the kernel. We put these variables inside
	169	* a rom blob, so that the reset for ROM contents zeroes them for us.
	170	*/
	171	static const uint32_t smpboot[] = {
	172	0xd2801b05, /* mov x5, 0xd8 */
	173	0xd53800a6, /* mrs x6, mpidr_el1 */
	174	0x924004c6, /* and x6, x6, #0x3 */
	175	0xd503205f, /* spin: wfe */
	176	0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
	177	0xb4ffffc4, /* cbz x4, spin */
	178	0xd2800000, /* mov x0, #0x0 */
	179	0xd2800001, /* mov x1, #0x0 */
	180	0xd2800002, /* mov x2, #0x0 */
	181	0xd2800003, /* mov x3, #0x0 */
	182	0xd61f0080, /* br x4 */
	183	};
	184
	185	static const uint64_t spintables[] = {
	186	0, 0, 0, 0
	187	};
	188
0f073693 PMD	189	rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
	190	info->smp_loader_start, as);
	191	rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables),
	192	SPINTABLE_ADDR, as);
ff72cb6b PM	193	}
ff72cb6b PM	194
1df7d1f9 AB	195	static void write_board_setup(ARMCPU cpu, const struct arm_boot_info info)
	196	{
	197	arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
	198	}
	199
	200	static void reset_secondary(ARMCPU cpu, const struct arm_boot_info info)
	201	{
	202	CPUState *cs = CPU(cpu);
	203	cpu_set_pc(cs, info->smp_loader_start);
	204	}
	205
	206	static void setup_boot(MachineState *machine, int version, size_t ram_size)
	207	{
	208	static struct arm_boot_info binfo;
	209	int r;
	210
918c81a5	211	binfo.board_id = MACH_TYPE_BCM2708;
1df7d1f9	212	binfo.ram_size = ram_size;
cc7d44c2	213	binfo.nb_cpus = machine->smp.cpus;
01e02f5a PM	214
	215	if (version <= 2) {
	216	/* The rpi1 and 2 require some custom setup code to run in Secure
	217	* mode before booting a kernel (to set up the SMC vectors so
	218	* that we get a no-op SMC; this is used by Linux to call the
	219	* firmware for some cache maintenance operations.
	220	* The rpi3 doesn't need this.
	221	*/
	222	binfo.board_setup_addr = BOARDSETUP_ADDR;
	223	binfo.write_board_setup = write_board_setup;
	224	binfo.secure_board_setup = true;
	225	binfo.secure_boot = true;
	226	}
1df7d1f9	227
bade5816 PE	228	/* Pi2 and Pi3 requires SMP setup */
bade5816 PE	229	if (version >= 2) {
1df7d1f9	230	binfo.smp_loader_start = SMPBOOT_ADDR;
ff72cb6b PM	231	if (version == 2) {
	232	binfo.write_secondary_boot = write_smpboot;
	233	} else {
	234	binfo.write_secondary_boot = write_smpboot64;
	235	}
1df7d1f9 AB	236	binfo.secondary_cpu_reset_hook = reset_secondary;
	237	}
	238
	239	/* If the user specified a "firmware" image (e.g. UEFI), we bypass
	240	* the normal Linux boot process
	241	*/
	242	if (machine->firmware) {
bade5816	243	hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
1df7d1f9	244	/* load the firmware image (typically kernel.img) */
bade5816 PE	245	r = load_image_targphys(machine->firmware, firmware_addr,
bade5816 PE	246	ram_size - firmware_addr);
1df7d1f9 AB	247	if (r < 0) {
	248	error_report("Failed to load firmware from %s", machine->firmware);
	249	exit(1);
	250	}
	251
bade5816	252	binfo.entry = firmware_addr;
1df7d1f9	253	binfo.firmware_loaded = true;
1df7d1f9 AB	254	}
1df7d1f9 AB	255
2744ece8	256	arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
1df7d1f9 AB	257	}
1df7d1f9 AB	258
13c4e2c0	259	static void raspi_machine_init(MachineState *machine)
1df7d1f9	260	{
c318c66c	261	RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
cb57df6f	262	RaspiMachineState *s = RASPI_MACHINE(machine);
c318c66c	263	uint32_t board_rev = mc->board_rev;
cd6c9977	264	int version = board_version(board_rev);
f5bb124e	265	uint64_t ram_size = board_ram_size(board_rev);
5e9c2a8d	266	uint32_t vcram_size;
a55b53a2 AB	267	DriveInfo *di;
	268	BlockBackend *blk;
	269	BusState *bus;
	270	DeviceState *carddev;
1df7d1f9	271
f5bb124e PMD	272	if (machine->ram_size != ram_size) {
	273	char *size_str = size_to_str(ram_size);
	274	error_report("Invalid RAM size, should be %s", size_str);
	275	g_free(size_str);
ff3dcf28 PM	276	exit(1);
	277	}
	278
1df7d1f9	279	/* FIXME: Remove when we have custom CPU address space support */
a4317ae8 IM	280	memory_region_add_subregion_overlap(get_system_memory(), 0,
a4317ae8 IM	281	machine->ram, 0);
1df7d1f9 AB	282
1df7d1f9 AB	283	/* Setup the SOC */
cc360632 PMD	284	object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
cc360632 PMD	285	board_soc_type(board_rev), &error_abort, NULL);
a4317ae8	286	object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram),
1df7d1f9	287	&error_abort);
bade5816	288	object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
f0afa731	289	&error_abort);
1df7d1f9 AB	290	object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort);
1df7d1f9 AB	291
a55b53a2 AB	292	/* Create and plug in the SD cards */
	293	di = drive_get_next(IF_SD);
	294	blk = di ? blk_by_legacy_dinfo(di) : NULL;
	295	bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus");
	296	if (bus == NULL) {
	297	error_report("No SD bus found in SOC object");
	298	exit(1);
	299	}
	300	carddev = qdev_create(bus, TYPE_SD_CARD);
	301	qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
	302	object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
	303
c5c6c47c MAL	304	vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
c5c6c47c MAL	305	&error_abort);
bade5816 PE	306	setup_boot(machine, version, machine->ram_size - vcram_size);
	307	}
	308
a03bde36	309	static void raspi_machine_class_init(ObjectClass oc, void data)
1df7d1f9	310	{
cb57df6f	311	MachineClass *mc = MACHINE_CLASS(oc);
c318c66c PMD	312	RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
c318c66c PMD	313	uint32_t board_rev = (uint32_t)(uintptr_t)data;
cb57df6f	314
c318c66c	315	rmc->board_rev = board_rev;
98b541e1	316	mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev));
13c4e2c0	317	mc->init = raspi_machine_init;
1df7d1f9 AB	318	mc->block_default_type = IF_SD;
	319	mc->no_parallel = 1;
	320	mc->no_floppy = 1;
	321	mc->no_cdrom = 1;
759f0f87	322	mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
975f3402	323	mc->default_ram_size = board_ram_size(board_rev);
a4317ae8	324	mc->default_ram_id = "ram";
a03bde36 PMD	325	if (board_version(board_rev) == 2) {
	326	mc->ignore_memory_transaction_failures = true;
	327	}
1df7d1f9	328	};
1c3db49d	329
cb57df6f PMD	330	static const TypeInfo raspi_machine_types[] = {
	331	{
	332	.name = MACHINE_TYPE_NAME("raspi2"),
	333	.parent = TYPE_RASPI_MACHINE,
a03bde36	334	.class_init = raspi_machine_class_init,
c318c66c	335	.class_data = (void *)0xa21041,
cb57df6f PMD	336	#ifdef TARGET_AARCH64
	337	}, {
	338	.name = MACHINE_TYPE_NAME("raspi3"),
	339	.parent = TYPE_RASPI_MACHINE,
a03bde36	340	.class_init = raspi_machine_class_init,
c318c66c	341	.class_data = (void *)0xa02082,
cb57df6f PMD	342	#endif
	343	}, {
	344	.name = TYPE_RASPI_MACHINE,
	345	.parent = TYPE_MACHINE,
	346	.instance_size = sizeof(RaspiMachineState),
	347	.class_size = sizeof(RaspiMachineClass),
	348	.abstract = true,
	349	}
	350	};
	351
	352	DEFINE_TYPES(raspi_machine_types)