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2055283b PM |
1 | /* |
2 | * ARM Versatile Express emulation. | |
3 | * | |
4 | * Copyright (c) 2010 - 2011 B Labs Ltd. | |
5 | * Copyright (c) 2011 Linaro Limited | |
6 | * Written by Bahadir Balban, Amit Mahajan, Peter Maydell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
6b620ca3 PB |
19 | * |
20 | * Contributions after 2012-01-13 are licensed under the terms of the | |
21 | * GNU GPL, version 2 or (at your option) any later version. | |
2055283b PM |
22 | */ |
23 | ||
83c9f4ca | 24 | #include "hw/sysbus.h" |
bd2be150 | 25 | #include "hw/arm/arm.h" |
0d09e41a | 26 | #include "hw/arm/primecell.h" |
bd2be150 | 27 | #include "hw/devices.h" |
1422e32d | 28 | #include "net/net.h" |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
83c9f4ca | 30 | #include "hw/boards.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
9c17d615 | 32 | #include "sysemu/blockdev.h" |
0d09e41a | 33 | #include "hw/block/flash.h" |
2055283b | 34 | |
2055283b | 35 | #define VEXPRESS_BOARD_ID 0x8e0 |
3dc3e7dd FL |
36 | #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) |
37 | #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) | |
2055283b | 38 | |
2558e0a6 PM |
39 | /* Address maps for peripherals: |
40 | * the Versatile Express motherboard has two possible maps, | |
41 | * the "legacy" one (used for A9) and the "Cortex-A Series" | |
42 | * map (used for newer cores). | |
43 | * Individual daughterboards can also have different maps for | |
44 | * their peripherals. | |
45 | */ | |
46 | ||
47 | enum { | |
48 | VE_SYSREGS, | |
49 | VE_SP810, | |
50 | VE_SERIALPCI, | |
51 | VE_PL041, | |
52 | VE_MMCI, | |
53 | VE_KMI0, | |
54 | VE_KMI1, | |
55 | VE_UART0, | |
56 | VE_UART1, | |
57 | VE_UART2, | |
58 | VE_UART3, | |
59 | VE_WDT, | |
60 | VE_TIMER01, | |
61 | VE_TIMER23, | |
62 | VE_SERIALDVI, | |
63 | VE_RTC, | |
64 | VE_COMPACTFLASH, | |
65 | VE_CLCD, | |
66 | VE_NORFLASH0, | |
2558e0a6 | 67 | VE_NORFLASH1, |
8941d6ce | 68 | VE_NORFLASHALIAS, |
2558e0a6 PM |
69 | VE_SRAM, |
70 | VE_VIDEORAM, | |
71 | VE_ETHERNET, | |
72 | VE_USB, | |
73 | VE_DAPROM, | |
74 | }; | |
75 | ||
a8170e5e | 76 | static hwaddr motherboard_legacy_map[] = { |
2558e0a6 PM |
77 | /* CS7: 0x10000000 .. 0x10020000 */ |
78 | [VE_SYSREGS] = 0x10000000, | |
79 | [VE_SP810] = 0x10001000, | |
80 | [VE_SERIALPCI] = 0x10002000, | |
81 | [VE_PL041] = 0x10004000, | |
82 | [VE_MMCI] = 0x10005000, | |
83 | [VE_KMI0] = 0x10006000, | |
84 | [VE_KMI1] = 0x10007000, | |
85 | [VE_UART0] = 0x10009000, | |
86 | [VE_UART1] = 0x1000a000, | |
87 | [VE_UART2] = 0x1000b000, | |
88 | [VE_UART3] = 0x1000c000, | |
89 | [VE_WDT] = 0x1000f000, | |
90 | [VE_TIMER01] = 0x10011000, | |
91 | [VE_TIMER23] = 0x10012000, | |
92 | [VE_SERIALDVI] = 0x10016000, | |
93 | [VE_RTC] = 0x10017000, | |
94 | [VE_COMPACTFLASH] = 0x1001a000, | |
95 | [VE_CLCD] = 0x1001f000, | |
96 | /* CS0: 0x40000000 .. 0x44000000 */ | |
97 | [VE_NORFLASH0] = 0x40000000, | |
98 | /* CS1: 0x44000000 .. 0x48000000 */ | |
99 | [VE_NORFLASH1] = 0x44000000, | |
100 | /* CS2: 0x48000000 .. 0x4a000000 */ | |
101 | [VE_SRAM] = 0x48000000, | |
102 | /* CS3: 0x4c000000 .. 0x50000000 */ | |
103 | [VE_VIDEORAM] = 0x4c000000, | |
104 | [VE_ETHERNET] = 0x4e000000, | |
105 | [VE_USB] = 0x4f000000, | |
8941d6ce | 106 | [VE_NORFLASHALIAS] = -1, /* not present */ |
2055283b PM |
107 | }; |
108 | ||
a8170e5e | 109 | static hwaddr motherboard_aseries_map[] = { |
8941d6ce | 110 | [VE_NORFLASHALIAS] = 0, |
661bafb3 FL |
111 | /* CS0: 0x08000000 .. 0x0c000000 */ |
112 | [VE_NORFLASH0] = 0x08000000, | |
961f195e PM |
113 | /* CS4: 0x0c000000 .. 0x10000000 */ |
114 | [VE_NORFLASH1] = 0x0c000000, | |
115 | /* CS5: 0x10000000 .. 0x14000000 */ | |
116 | /* CS1: 0x14000000 .. 0x18000000 */ | |
117 | [VE_SRAM] = 0x14000000, | |
118 | /* CS2: 0x18000000 .. 0x1c000000 */ | |
119 | [VE_VIDEORAM] = 0x18000000, | |
120 | [VE_ETHERNET] = 0x1a000000, | |
121 | [VE_USB] = 0x1b000000, | |
122 | /* CS3: 0x1c000000 .. 0x20000000 */ | |
123 | [VE_DAPROM] = 0x1c000000, | |
124 | [VE_SYSREGS] = 0x1c010000, | |
125 | [VE_SP810] = 0x1c020000, | |
126 | [VE_SERIALPCI] = 0x1c030000, | |
127 | [VE_PL041] = 0x1c040000, | |
128 | [VE_MMCI] = 0x1c050000, | |
129 | [VE_KMI0] = 0x1c060000, | |
130 | [VE_KMI1] = 0x1c070000, | |
131 | [VE_UART0] = 0x1c090000, | |
132 | [VE_UART1] = 0x1c0a0000, | |
133 | [VE_UART2] = 0x1c0b0000, | |
134 | [VE_UART3] = 0x1c0c0000, | |
135 | [VE_WDT] = 0x1c0f0000, | |
136 | [VE_TIMER01] = 0x1c110000, | |
137 | [VE_TIMER23] = 0x1c120000, | |
138 | [VE_SERIALDVI] = 0x1c160000, | |
139 | [VE_RTC] = 0x1c170000, | |
140 | [VE_COMPACTFLASH] = 0x1c1a0000, | |
141 | [VE_CLCD] = 0x1c1f0000, | |
142 | }; | |
143 | ||
4c3b29b8 PM |
144 | /* Structure defining the peculiarities of a specific daughterboard */ |
145 | ||
146 | typedef struct VEDBoardInfo VEDBoardInfo; | |
147 | ||
148 | typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, | |
149 | ram_addr_t ram_size, | |
150 | const char *cpu_model, | |
cdef10bb | 151 | qemu_irq *pic); |
4c3b29b8 PM |
152 | |
153 | struct VEDBoardInfo { | |
cef04a26 | 154 | struct arm_boot_info bootinfo; |
a8170e5e AK |
155 | const hwaddr *motherboard_map; |
156 | hwaddr loader_start; | |
157 | const hwaddr gic_cpu_if_addr; | |
cdef10bb | 158 | uint32_t proc_id; |
31410948 PM |
159 | uint32_t num_voltage_sensors; |
160 | const uint32_t *voltages; | |
9c7d4893 PM |
161 | uint32_t num_clocks; |
162 | const uint32_t *clocks; | |
4c3b29b8 PM |
163 | DBoardInitFn *init; |
164 | }; | |
165 | ||
166 | static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, | |
167 | ram_addr_t ram_size, | |
168 | const char *cpu_model, | |
cdef10bb | 169 | qemu_irq *pic) |
2055283b | 170 | { |
e6d17b05 AK |
171 | MemoryRegion *sysmem = get_system_memory(); |
172 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
173 | MemoryRegion *lowram = g_new(MemoryRegion, 1); | |
4c3b29b8 | 174 | DeviceState *dev; |
2055283b PM |
175 | SysBusDevice *busdev; |
176 | qemu_irq *irqp; | |
2055283b PM |
177 | int n; |
178 | qemu_irq cpu_irq[4]; | |
4c3b29b8 | 179 | ram_addr_t low_ram_size; |
2055283b PM |
180 | |
181 | if (!cpu_model) { | |
182 | cpu_model = "cortex-a9"; | |
183 | } | |
184 | ||
185 | for (n = 0; n < smp_cpus; n++) { | |
64c9e297 AF |
186 | ARMCPU *cpu = cpu_arm_init(cpu_model); |
187 | if (!cpu) { | |
2055283b PM |
188 | fprintf(stderr, "Unable to find CPU definition\n"); |
189 | exit(1); | |
190 | } | |
4bd74661 | 191 | irqp = arm_pic_init_cpu(cpu); |
2055283b PM |
192 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
193 | } | |
194 | ||
195 | if (ram_size > 0x40000000) { | |
196 | /* 1GB is the maximum the address space permits */ | |
4c3b29b8 | 197 | fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); |
2055283b PM |
198 | exit(1); |
199 | } | |
200 | ||
2c9b15ca | 201 | memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); |
c5705a77 | 202 | vmstate_register_ram_global(ram); |
2055283b PM |
203 | low_ram_size = ram_size; |
204 | if (low_ram_size > 0x4000000) { | |
205 | low_ram_size = 0x4000000; | |
206 | } | |
207 | /* RAM is from 0x60000000 upwards. The bottom 64MB of the | |
208 | * address space should in theory be remappable to various | |
209 | * things including ROM or RAM; we always map the RAM there. | |
210 | */ | |
2c9b15ca | 211 | memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); |
e6d17b05 AK |
212 | memory_region_add_subregion(sysmem, 0x0, lowram); |
213 | memory_region_add_subregion(sysmem, 0x60000000, ram); | |
2055283b PM |
214 | |
215 | /* 0x1e000000 A9MPCore (SCU) private memory region */ | |
216 | dev = qdev_create(NULL, "a9mpcore_priv"); | |
217 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); | |
218 | qdev_init_nofail(dev); | |
1356b98d | 219 | busdev = SYS_BUS_DEVICE(dev); |
96eacf64 | 220 | sysbus_mmio_map(busdev, 0, 0x1e000000); |
2055283b PM |
221 | for (n = 0; n < smp_cpus; n++) { |
222 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
223 | } | |
224 | /* Interrupts [42:0] are from the motherboard; | |
225 | * [47:43] are reserved; [63:48] are daughterboard | |
226 | * peripherals. Note that some documentation numbers | |
227 | * external interrupts starting from 32 (because the | |
228 | * A9MP has internal interrupts 0..31). | |
229 | */ | |
230 | for (n = 0; n < 64; n++) { | |
231 | pic[n] = qdev_get_gpio_in(dev, n); | |
232 | } | |
233 | ||
4c3b29b8 PM |
234 | /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ |
235 | ||
236 | /* 0x10020000 PL111 CLCD (daughterboard) */ | |
237 | sysbus_create_simple("pl111", 0x10020000, pic[44]); | |
238 | ||
239 | /* 0x10060000 AXI RAM */ | |
240 | /* 0x100e0000 PL341 Dynamic Memory Controller */ | |
241 | /* 0x100e1000 PL354 Static Memory Controller */ | |
242 | /* 0x100e2000 System Configuration Controller */ | |
243 | ||
244 | sysbus_create_simple("sp804", 0x100e4000, pic[48]); | |
245 | /* 0x100e5000 SP805 Watchdog module */ | |
246 | /* 0x100e6000 BP147 TrustZone Protection Controller */ | |
247 | /* 0x100e9000 PL301 'Fast' AXI matrix */ | |
248 | /* 0x100ea000 PL301 'Slow' AXI matrix */ | |
249 | /* 0x100ec000 TrustZone Address Space Controller */ | |
250 | /* 0x10200000 CoreSight debug APB */ | |
251 | /* 0x1e00a000 PL310 L2 Cache Controller */ | |
252 | sysbus_create_varargs("l2x0", 0x1e00a000, NULL); | |
253 | } | |
254 | ||
31410948 PM |
255 | /* Voltage values for SYS_CFG_VOLT daughterboard registers; |
256 | * values are in microvolts. | |
257 | */ | |
258 | static const uint32_t a9_voltages[] = { | |
259 | 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ | |
260 | 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ | |
261 | 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ | |
262 | 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ | |
263 | 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ | |
264 | 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ | |
265 | }; | |
266 | ||
9c7d4893 PM |
267 | /* Reset values for daughterboard oscillators (in Hz) */ |
268 | static const uint32_t a9_clocks[] = { | |
269 | 45000000, /* AMBA AXI ACLK: 45MHz */ | |
270 | 23750000, /* daughterboard CLCD clock: 23.75MHz */ | |
271 | 66670000, /* Test chip reference clock: 66.67MHz */ | |
272 | }; | |
273 | ||
cef04a26 | 274 | static VEDBoardInfo a9_daughterboard = { |
4c3b29b8 PM |
275 | .motherboard_map = motherboard_legacy_map, |
276 | .loader_start = 0x60000000, | |
96eacf64 | 277 | .gic_cpu_if_addr = 0x1e000100, |
cdef10bb | 278 | .proc_id = 0x0c000191, |
31410948 PM |
279 | .num_voltage_sensors = ARRAY_SIZE(a9_voltages), |
280 | .voltages = a9_voltages, | |
9c7d4893 PM |
281 | .num_clocks = ARRAY_SIZE(a9_clocks), |
282 | .clocks = a9_clocks, | |
4c3b29b8 PM |
283 | .init = a9_daughterboard_init, |
284 | }; | |
285 | ||
961f195e PM |
286 | static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, |
287 | ram_addr_t ram_size, | |
288 | const char *cpu_model, | |
cdef10bb | 289 | qemu_irq *pic) |
961f195e PM |
290 | { |
291 | int n; | |
961f195e PM |
292 | MemoryRegion *sysmem = get_system_memory(); |
293 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
294 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
295 | qemu_irq cpu_irq[4]; | |
296 | DeviceState *dev; | |
297 | SysBusDevice *busdev; | |
298 | ||
299 | if (!cpu_model) { | |
300 | cpu_model = "cortex-a15"; | |
301 | } | |
302 | ||
961f195e | 303 | for (n = 0; n < smp_cpus; n++) { |
64c9e297 | 304 | ARMCPU *cpu; |
961f195e | 305 | qemu_irq *irqp; |
64c9e297 AF |
306 | |
307 | cpu = cpu_arm_init(cpu_model); | |
308 | if (!cpu) { | |
961f195e PM |
309 | fprintf(stderr, "Unable to find CPU definition\n"); |
310 | exit(1); | |
311 | } | |
4bd74661 | 312 | irqp = arm_pic_init_cpu(cpu); |
961f195e PM |
313 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
314 | } | |
315 | ||
25d71699 PM |
316 | { |
317 | /* We have to use a separate 64 bit variable here to avoid the gcc | |
318 | * "comparison is always false due to limited range of data type" | |
319 | * warning if we are on a host where ram_addr_t is 32 bits. | |
320 | */ | |
321 | uint64_t rsz = ram_size; | |
322 | if (rsz > (30ULL * 1024 * 1024 * 1024)) { | |
323 | fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); | |
324 | exit(1); | |
325 | } | |
961f195e PM |
326 | } |
327 | ||
2c9b15ca | 328 | memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); |
961f195e PM |
329 | vmstate_register_ram_global(ram); |
330 | /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ | |
331 | memory_region_add_subregion(sysmem, 0x80000000, ram); | |
332 | ||
333 | /* 0x2c000000 A15MPCore private memory region (GIC) */ | |
334 | dev = qdev_create(NULL, "a15mpcore_priv"); | |
335 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); | |
336 | qdev_init_nofail(dev); | |
1356b98d | 337 | busdev = SYS_BUS_DEVICE(dev); |
961f195e PM |
338 | sysbus_mmio_map(busdev, 0, 0x2c000000); |
339 | for (n = 0; n < smp_cpus; n++) { | |
340 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
341 | } | |
342 | /* Interrupts [42:0] are from the motherboard; | |
343 | * [47:43] are reserved; [63:48] are daughterboard | |
344 | * peripherals. Note that some documentation numbers | |
345 | * external interrupts starting from 32 (because there | |
346 | * are internal interrupts 0..31). | |
347 | */ | |
348 | for (n = 0; n < 64; n++) { | |
349 | pic[n] = qdev_get_gpio_in(dev, n); | |
350 | } | |
351 | ||
352 | /* A15 daughterboard peripherals: */ | |
353 | ||
354 | /* 0x20000000: CoreSight interfaces: not modelled */ | |
355 | /* 0x2a000000: PL301 AXI interconnect: not modelled */ | |
356 | /* 0x2a420000: SCC: not modelled */ | |
357 | /* 0x2a430000: system counter: not modelled */ | |
358 | /* 0x2b000000: HDLCD controller: not modelled */ | |
359 | /* 0x2b060000: SP805 watchdog: not modelled */ | |
360 | /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ | |
361 | /* 0x2e000000: system SRAM */ | |
2c9b15ca | 362 | memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000); |
961f195e PM |
363 | vmstate_register_ram_global(sram); |
364 | memory_region_add_subregion(sysmem, 0x2e000000, sram); | |
365 | ||
366 | /* 0x7ffb0000: DMA330 DMA controller: not modelled */ | |
367 | /* 0x7ffd0000: PL354 static memory controller: not modelled */ | |
368 | } | |
369 | ||
31410948 PM |
370 | static const uint32_t a15_voltages[] = { |
371 | 900000, /* Vcore: 0.9V : CPU core voltage */ | |
372 | }; | |
373 | ||
9c7d4893 PM |
374 | static const uint32_t a15_clocks[] = { |
375 | 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ | |
376 | 0, /* OSCCLK1: reserved */ | |
377 | 0, /* OSCCLK2: reserved */ | |
378 | 0, /* OSCCLK3: reserved */ | |
379 | 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ | |
380 | 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ | |
381 | 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ | |
382 | 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ | |
383 | 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ | |
384 | }; | |
385 | ||
cef04a26 | 386 | static VEDBoardInfo a15_daughterboard = { |
961f195e PM |
387 | .motherboard_map = motherboard_aseries_map, |
388 | .loader_start = 0x80000000, | |
389 | .gic_cpu_if_addr = 0x2c002000, | |
cdef10bb | 390 | .proc_id = 0x14000237, |
31410948 PM |
391 | .num_voltage_sensors = ARRAY_SIZE(a15_voltages), |
392 | .voltages = a15_voltages, | |
9c7d4893 PM |
393 | .num_clocks = ARRAY_SIZE(a15_clocks), |
394 | .clocks = a15_clocks, | |
961f195e PM |
395 | .init = a15_daughterboard_init, |
396 | }; | |
397 | ||
cef04a26 | 398 | static void vexpress_common_init(VEDBoardInfo *daughterboard, |
f3cdbc32 | 399 | QEMUMachineInitArgs *args) |
4c3b29b8 PM |
400 | { |
401 | DeviceState *dev, *sysctl, *pl041; | |
402 | qemu_irq pic[64]; | |
4c3b29b8 | 403 | uint32_t sys_id; |
3dc3e7dd | 404 | DriveInfo *dinfo; |
8941d6ce | 405 | pflash_t *pflash0; |
4c3b29b8 PM |
406 | ram_addr_t vram_size, sram_size; |
407 | MemoryRegion *sysmem = get_system_memory(); | |
408 | MemoryRegion *vram = g_new(MemoryRegion, 1); | |
409 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
8941d6ce PM |
410 | MemoryRegion *flashalias = g_new(MemoryRegion, 1); |
411 | MemoryRegion *flash0mem; | |
a8170e5e | 412 | const hwaddr *map = daughterboard->motherboard_map; |
31410948 | 413 | int i; |
4c3b29b8 | 414 | |
cdef10bb | 415 | daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic); |
4c3b29b8 | 416 | |
2558e0a6 PM |
417 | /* Motherboard peripherals: the wiring is the same but the |
418 | * addresses vary between the legacy and A-Series memory maps. | |
419 | */ | |
420 | ||
2055283b | 421 | sys_id = 0x1190f500; |
2055283b | 422 | |
2055283b PM |
423 | sysctl = qdev_create(NULL, "realview_sysctl"); |
424 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); | |
cdef10bb | 425 | qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); |
31410948 PM |
426 | qdev_prop_set_uint32(sysctl, "len-db-voltage", |
427 | daughterboard->num_voltage_sensors); | |
428 | for (i = 0; i < daughterboard->num_voltage_sensors; i++) { | |
429 | char *propname = g_strdup_printf("db-voltage[%d]", i); | |
430 | qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); | |
431 | g_free(propname); | |
432 | } | |
9c7d4893 PM |
433 | qdev_prop_set_uint32(sysctl, "len-db-clock", |
434 | daughterboard->num_clocks); | |
435 | for (i = 0; i < daughterboard->num_clocks; i++) { | |
436 | char *propname = g_strdup_printf("db-clock[%d]", i); | |
437 | qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); | |
438 | g_free(propname); | |
439 | } | |
7a65c8cc | 440 | qdev_init_nofail(sysctl); |
1356b98d | 441 | sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); |
2558e0a6 PM |
442 | |
443 | /* VE_SP810: not modelled */ | |
444 | /* VE_SERIALPCI: not modelled */ | |
2055283b | 445 | |
03a0e944 PM |
446 | pl041 = qdev_create(NULL, "pl041"); |
447 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); | |
448 | qdev_init_nofail(pl041); | |
1356b98d AF |
449 | sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); |
450 | sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); | |
2055283b | 451 | |
2558e0a6 | 452 | dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); |
2055283b PM |
453 | /* Wire up MMC card detect and read-only signals */ |
454 | qdev_connect_gpio_out(dev, 0, | |
455 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); | |
456 | qdev_connect_gpio_out(dev, 1, | |
457 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); | |
458 | ||
2558e0a6 PM |
459 | sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); |
460 | sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); | |
2055283b | 461 | |
2558e0a6 PM |
462 | sysbus_create_simple("pl011", map[VE_UART0], pic[5]); |
463 | sysbus_create_simple("pl011", map[VE_UART1], pic[6]); | |
464 | sysbus_create_simple("pl011", map[VE_UART2], pic[7]); | |
465 | sysbus_create_simple("pl011", map[VE_UART3], pic[8]); | |
2055283b | 466 | |
2558e0a6 PM |
467 | sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); |
468 | sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); | |
2055283b | 469 | |
2558e0a6 | 470 | /* VE_SERIALDVI: not modelled */ |
2055283b | 471 | |
2558e0a6 | 472 | sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ |
2055283b | 473 | |
2558e0a6 | 474 | /* VE_COMPACTFLASH: not modelled */ |
2055283b | 475 | |
b7206878 | 476 | sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); |
2055283b | 477 | |
3dc3e7dd | 478 | dinfo = drive_get_next(IF_PFLASH); |
8941d6ce | 479 | pflash0 = pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0", |
3dc3e7dd FL |
480 | VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL, |
481 | VEXPRESS_FLASH_SECT_SIZE, | |
482 | VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4, | |
8941d6ce PM |
483 | 0x00, 0x89, 0x00, 0x18, 0); |
484 | if (!pflash0) { | |
3dc3e7dd FL |
485 | fprintf(stderr, "vexpress: error registering flash 0.\n"); |
486 | exit(1); | |
487 | } | |
488 | ||
8941d6ce PM |
489 | if (map[VE_NORFLASHALIAS] != -1) { |
490 | /* Map flash 0 as an alias into low memory */ | |
491 | flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); | |
492 | memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", | |
493 | flash0mem, 0, VEXPRESS_FLASH_SIZE); | |
494 | memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); | |
495 | } | |
496 | ||
3dc3e7dd FL |
497 | dinfo = drive_get_next(IF_PFLASH); |
498 | if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1", | |
499 | VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL, | |
500 | VEXPRESS_FLASH_SECT_SIZE, | |
501 | VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4, | |
502 | 0x00, 0x89, 0x00, 0x18, 0)) { | |
503 | fprintf(stderr, "vexpress: error registering flash 1.\n"); | |
504 | exit(1); | |
505 | } | |
2558e0a6 | 506 | |
2055283b | 507 | sram_size = 0x2000000; |
2c9b15ca | 508 | memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size); |
c5705a77 | 509 | vmstate_register_ram_global(sram); |
2558e0a6 | 510 | memory_region_add_subregion(sysmem, map[VE_SRAM], sram); |
2055283b | 511 | |
2055283b | 512 | vram_size = 0x800000; |
2c9b15ca | 513 | memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size); |
c5705a77 | 514 | vmstate_register_ram_global(vram); |
2558e0a6 | 515 | memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); |
2055283b PM |
516 | |
517 | /* 0x4e000000 LAN9118 Ethernet */ | |
a005d073 | 518 | if (nd_table[0].used) { |
2558e0a6 | 519 | lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); |
2055283b PM |
520 | } |
521 | ||
2558e0a6 PM |
522 | /* VE_USB: not modelled */ |
523 | ||
524 | /* VE_DAPROM: not modelled */ | |
2055283b | 525 | |
cef04a26 PM |
526 | daughterboard->bootinfo.ram_size = args->ram_size; |
527 | daughterboard->bootinfo.kernel_filename = args->kernel_filename; | |
528 | daughterboard->bootinfo.kernel_cmdline = args->kernel_cmdline; | |
529 | daughterboard->bootinfo.initrd_filename = args->initrd_filename; | |
530 | daughterboard->bootinfo.nb_cpus = smp_cpus; | |
531 | daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; | |
532 | daughterboard->bootinfo.loader_start = daughterboard->loader_start; | |
533 | daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; | |
534 | daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; | |
535 | daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; | |
536 | arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); | |
2055283b PM |
537 | } |
538 | ||
5f072e1f | 539 | static void vexpress_a9_init(QEMUMachineInitArgs *args) |
4c3b29b8 | 540 | { |
f3cdbc32 | 541 | vexpress_common_init(&a9_daughterboard, args); |
4c3b29b8 | 542 | } |
2055283b | 543 | |
5f072e1f | 544 | static void vexpress_a15_init(QEMUMachineInitArgs *args) |
961f195e | 545 | { |
f3cdbc32 | 546 | vexpress_common_init(&a15_daughterboard, args); |
961f195e PM |
547 | } |
548 | ||
2055283b PM |
549 | static QEMUMachine vexpress_a9_machine = { |
550 | .name = "vexpress-a9", | |
551 | .desc = "ARM Versatile Express for Cortex-A9", | |
552 | .init = vexpress_a9_init, | |
2d0d2837 | 553 | .block_default_type = IF_SCSI, |
2055283b | 554 | .max_cpus = 4, |
e4ada29e | 555 | DEFAULT_MACHINE_OPTIONS, |
2055283b PM |
556 | }; |
557 | ||
961f195e PM |
558 | static QEMUMachine vexpress_a15_machine = { |
559 | .name = "vexpress-a15", | |
560 | .desc = "ARM Versatile Express for Cortex-A15", | |
561 | .init = vexpress_a15_init, | |
2d0d2837 | 562 | .block_default_type = IF_SCSI, |
961f195e | 563 | .max_cpus = 4, |
e4ada29e | 564 | DEFAULT_MACHINE_OPTIONS, |
961f195e PM |
565 | }; |
566 | ||
2055283b PM |
567 | static void vexpress_machine_init(void) |
568 | { | |
569 | qemu_register_machine(&vexpress_a9_machine); | |
961f195e | 570 | qemu_register_machine(&vexpress_a15_machine); |
2055283b PM |
571 | } |
572 | ||
573 | machine_init(vexpress_machine_init); |